SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 Gigabit 4x4 CROSSPOINT SWITCH The SN65LVCP404 is a 4x4 non-blocking crosspoint switch in a flow-through pin-out allowing for ease in PCB layout. VML signaling is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVCP404 incorporates 100-Ω termination resistors for those applications where board space is a premium. Built-in transmit pre-emphasis and receive equalization for superior signal integrity performance. VCC 2DE 3DE 37 40 38 1Z 41 39 GND 1Y 42 P12 P11 45 44 1DE 46 43 S10 VCC 7 30 3Z VCC 8 29 VCC 3A 9 28 4Y 3B 10 27 4Z EQ 11 26 GND VBB 12 25 4DE GND 24 3Y 2B P32 2A 23 GND 31 22 32 6 P31 5 P42 GND 21 2Z P41 1B S41 2Y 33 19 34 4 20 3 S40 1A 17 P21 4B S21 VCC 18 P22 35 16 36 2 15 1 4A S20 14 Clock Buffering/Clock MUXing Wireless Base Stations High-Speed Network Routing Telecom/Datacom XAUI 802.3ae Protocol Backplane Redundancy S31 • • • • • 47 APPLICATIONS S11 The SN65LVCP404 is characterized for operation from -40°C to 85°C. 48 • • • • DESCRIPTION 13 • • • • • • Up to 4.25 Gbps Operation Non-blocking Architecture Allows Each Output to be Connected to Any Input 30 ps of Deterministic Jitter Selectable Transmit Pre-Emphasis Per Lane Selectable Receive Equalization Available Packaging 48 Pin QFN Propagation Delay Times: 500 ps Typical Inputs Electrically Compatible With CML Signal Levels Operates From a Single 3.3-V Supply Ability to 3-STATE ouputs Low Power: 560 mW Integrated Termination Resistors S30 FEATURES • • Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. LOGIC DIAGRAM TERMINAL FUNCTIONS TERMINAL NAME NO. TYPE DESCRIPTION Differential Inputs (with 50-Ω termination to Vbb) xA=P; xB=N Line Side Differential Inputs CML compatible High Speed I/O xA xB 3, 6, 9, 16 4, 7, 10, 17 xY xZ 41, 34, 31, 28 40, 33, 30, 27 Differential Output xY=P; xZ=N Switch Side Differential Outputs. VML 45, 38, 37, 25 Input Data Enable; Active Low; LVTTL; When not enabled the ouput is in 3-STATE mode for power savings Control Signals xDE S10 - S41 1, 2, 13, 14, 19, 20, 47, 48 Input; S1x = Channel 1 bit one Switching Selection; LVTTL P11-P42 43, 44, 35, 36, 23, 24, 21, 22 Input; P1x- Channel 1 bit one Output Preemphasis Control; LVTTL Input; Selection for receive equalization setting EQ = 1 (default) is for the 5 dB setting, EQ = 0 is for the 12 dB setting Power Power Supply 3.3v ±5% EQ 11 Power Supply VCC 8, 18, 29, 39, 46 GND 5, 15, 26, 32, 42 The ground center pad of the package must be connected to GND plane. Power Pad VBB 2 12 Input Receiver input biasing voltage Submit Documentation Feedback SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC IN+ RT(SE) = 50 W Gain Stage + EQ VCC RBBDC RT(SE) = 50 W IN− VBB ESD LineEndTermination Self−Biasing Network Figure 1. Equivalent Input Circuit Design OUT+ 49.9 W OUT− 49.9 W VOCM 1 pF Figure 2. Common-Mode Output Voltage Test Circuit Table 1. CROSSPOINT LOGIC TABLES OUTPUT CHANNEL 1 CONTROL PINS INPUT SELECTED OUTPUT CHANNEL 2 CONTROL PINS INPUT SELECTED OUTPUT CHANNEL 3 CONTROL PINS INPUT SELECTED OUTPUT CHANNEL 4 CONTROL PINS INPUT SELECTED S10 S11 1Y/1Z S20 S21 2Y/2Z S30 S31 3Y/3Z S40 S41 4Y/4Z 0 0 1A/1B 0 0 1A/1B 0 0 1A/1B 0 0 1A/1B 0 1 2A/2B 0 1 2A/2B 0 1 2A/2B 0 1 2A/2B 1 0 3A/3B 1 0 3A/3B 1 0 3A/3B 1 0 3A/3B 1 1 4A/4B 1 1 4A/4B 1 1 4A/4B 1 1 4A/4B AVAILABLE OPTIONS (1) TA DESCRIPTION -40°C to 85°C Serial multiplexer PACKAGED DEVICE (1) RGZ (48 pin) SN65LVCP404 The package is available taped and reeled. Add an R suffix to device types (e.g., SN65LVCP404RGZR). Submit Documentation Feedback 3 SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 PACKAGE THERMAL CHARACTERISTICS PACKAGE THERMAL CHARACTERISTICS (1) NOM UNIT θJA (junction-to-ambient) 33 °C/W θJB (junction-to-board) 20 °C/W 23.6 °C/W θJC (junction-to-case) PSI-jt (junction-to-top pseudo) PSI-jb (junction-to-board pseudo) 4-layer JEDEC Board (JESD51-7) using eight GND-vias θ-0.2 on the center pad as shown in the section: Recommended PCB footprint with boundary and environment conditions of JEDEC Board (JESD51-2) 0.6 °C/W 19.4 °C/W 5.4 °C/W θJP (junction-to-pad) (1) See application note SPRA953 for a detailed explanation of thermal parameters (http://www-s.ti.com/sc/psheets/spra953/spra953.pdf). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage range (2) –0.5 V to 6 V Control inputs, all outputs Voltage range ESD TJ Receiver inputs Human Body Model (3) Charged-Device Model (4) 3 kV All pins 500 V See Package Thermal Characteristics Table Maximum junction temperature 2 Reflow temperature package soldering, 4 seconds (2) (3) (4) 4 –0.5 V to 4 V All pins Moisture sensitivity level (1) –0.5 V to (VCC + 0.5 V) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 RECOMMENDED OPERATING CONDITIONS dR Operating data rate VCC Supply voltage VCC(N) Supply voltage noise amplitude TJ Junction temperature TA Operating free-air temperature (1) MIN NOM MAX UNIT 4.25 Gbps 3.135 3.3 3.465 10 Hz to 2.125 GHz V 20 mV 125 °C -40 85 °C dR(in) ≤ 4.25 Gbps 100 1750 mVPP 1.25 Gbps < dR(in) ≤ 4.25 Gbps 100 1560 mVPP dR(in) > 4.25 Gbps 100 1000 mVPP Note: for best jitter performance ac coupling is recommended. 1.5 DIFFERENTIAL INPUTS Receiver peak-to-peak differential input voltage (2) VID VICM Receiver common-mode input voltage |V 1.6 VCC * | ID 2 V CONTROL INPUTS VIH High-level input voltage 2 VCC + 0.3 V VIL Low-level input voltage –0.3 0.8 V 120 Ω DIFFERENTIAL OUTPUTS RL (1) (2) Differential load resistance 80 100 Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded. Differential input voltage VID is defined as | IN+ – IN– |. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DIFFERENTIAL INPUTS VIT+ Positive going differential input high threshold VIT– Negative going differential input low threshold A(EQ) Equalizer gain RT(D) Termination resistance, differential VBB Open-circuit Input voltage (input self-bias voltage) R(BBDC) Biasing network dc impedance R(BBAC) Biasing network ac impedance 50 mV –50 at 1.875 GHz (EQ=0) mV 12 80 AC-coupled inputs 100 dB Ω 120 1.6 V 30 kΩ 375 MHz 42 2.125 GHz 8.4 Ω DIFFERENTIAL OUTPUTS VODH High-level output voltage VODL Low-level output voltage VODB(PP) Output differential voltage without preemphasis (2) VOCM Output common mode voltage ∆VOC(SS) Change in steady-state See Figure 2 common-mode output voltage between logic states (1) (2) RL = 100 Ω±1%, Px_2 = Px_1=0; 4 Gbps alternating 1010-pattern; Figure 3 1000 650 mVPP –650 mVPP 1300 1500 mVPP 1.65 1 V mV All typical values are at TA = 25°C and VCC = 3.3 V supply unless otherwise noted. They are for reference purposes and are not production tested. Differential output voltage V(ODB) is defined as | OUT+ – OUT– |. Submit Documentation Feedback 5 SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER Output preemphasis voltage ratio, V(PE) V ODB(PP) TEST CONDITIONS RL = 100 Ω± 1%; x = L or S; See Figure 3 VODPE(PP) MIN TYP (1) Px_2:Px_1 = 00 0 Px_2:Px_1 = 01 3 Px_2:Px_1 = 10 6 Px_2:Px_1 = 11 9 MAX UNIT dB t(PRE) Preemphasis duration measurement Output preemphasis is set to 9 dB during test Px_x = 1; Measured with a 100-MHz clock signal; RL = 100 Ω± 1%, See Figure 4 175 ps ro Output resistance Differential on-chip termination between OUT+ and OUT– 100 Ω CONTROL INPUTS IIH High-level Input current VIN = VCC IIL Low-level Input current VIN = GND R(PU) Pullup resistance 5 -125 µA -90 µA 35 kΩ POWER CONSUMPTION PD Device power dissipation All outputs terminated 100 Ω PZ Device power dissipation in 3-State All outputs in 3-state ICC Device current consumption All outputs terminated 100 Ω PRBS Gbps 27-1 560 750 mW 600 mW 220 mA TYP (1) MAX UNIT 3 6 ns 0.5 0.7 ns 0.5 0.7 ns pattern at 4.25 SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MULTIPLEXER t(SM) Multiplexer switch time Multiplexer to valid output DIFFERENTIAL OUTPUTS tPLH Low-to-high propagation delay tPHL High-to-low propagation delay tr Rise time tf Fall time tsk(p) Pulse skew, | tPHL– tPLH | (2) tsk(o) Output skew (3) 20% to 80% of VO(DB); Test Pattern: 100-MHz clock signal; See Figure 5 and Figure 8 All outputs terminated with 100 Ω 80 ps 80 25 skew (4) ps 20 ps 100 ps tsk(pp) Part-to-part 300 ps tzd 3-State switch time to Disable Assumes 50 Ohm to Vcm and 150 pF load on each output 20 ns tze 3-State switch time to Enable Assumes 50 Ohm to Vcm and 150 pF load on each output 10 ns RJ Device random jitter, rms 2 ps-rms (1) (2) (3) (4) 6 Propagation delay input to output See Figure 6 See Figure 8 for test circuit. BERT setting 10–15 Alternating 10-pattern. 0.8 All typical values are at 25°C and with 3.3 V supply unless otherwise noted. tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 SWITCHING CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Intrinsic deterministic device jitter (5) (6), peak-to-peak DJ (5) (6) (7) 0 dB preemphasis (PREx_x = 0); See Figure 8 for the test circuit. 0 dB preemphasis Absolute deterministic (PREx_x = 0); output jitter (7), peak-to-peak See Figure 8 for the test circuit. PRBS 27-1 pattern MIN TYP (1) 4.25 Gbps UNIT 30 1.25Gbps; EQ=1 Over 25-inch FR4 trace PRBS 27-1 pattern MAX ps 7 4.25 Gbps; EQ=0 Over FR4 trace 2-inch to 43 inches long ps 20 Intrinsic deterministic device jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJ(OUT)– DJ(IN) ), where DJ(OUT) is the total peak-to-peak deterministic jitter measured at the output of the device in PSPP. DJ(IN) is the peak-to-peak deterministic jitter of the pattern generator driving the device. The SN65LVCP404 built-in passive input equalizer compensates for ISI. For a 25-inch FR4 transmission line with 8-mil trace width, the LVCP404 typically reduces jitter by 60 ps from the device input to the device output. Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP404 output. The value is a real measured value with a Bit error tester as described in Figure 8. The absolute DJ reflects the sum of all deterministic jitter components accumulated over the link: DJ(absolute) = DJ(Signal generator) + DJ(transmission line) + DJ(intrinsic(LVCP404)). Table 2. Preemphasis Controls PL_2, PL_1, PS_2, and PS_1 (1) Px_2 (1) Px_1 (1) OUTPUT PREEMPHASIS LEVEL IN dB OUTPUT LEVEL IN mVpp DE-EMPHASIZED PRE-EMPHASIZED TYPICAL FR4 TRACE LENGTH 0 0 0 dB 1200 1200 10 inches of FR4 trace 0 1 3 dB 850 1200 20 inches of FR4 trace 1 0 6 dB 600 1200 30 inches of FR4 trace 1 1 9 dB 425 1200 40 inches of FR4 trace x = L or S Table 3. Receive Equalization Settings EQ EQUALIZATION TYPICAL TRACE 1 5 dB 25 inches of FR4 0 12 dB 43 inches of FR4 Submit Documentation Feedback 7 SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 PARAMETER MEASUREMENT INFORMATION 1−bit 1 to N bit 3−dB Preemphasis VODPE3(pp) 9−dB Preemphasis VOCM VODB(PP) VODPE2(pp) 6−dB Preemphasis VODPE1(pp) 0−dB Preemphasis VOH VOL Figure 3. Preemphasis and Output Voltage Waveforms and Definitions 1−bit VODPE3(pp) 9−dB Preemphasis 1 to N bit VODB(PP) 80% 20% tPRE Figure 4. t(PRE) Preemphasis Duration Measurement 80% 80% VODB 20% 20% tr tf Figure 5. Driver Output Transition Time 8 Submit Documentation Feedback SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 PARAMETER MEASUREMENT INFORMATION (continued) VID = 0 V IN t PHLD t PLHD VOD = 0 V OUT Figure 6. Propagation Delay Input to Output VA 0V VB Clock Input 0V Ideal Output VY − VZ 1/fo 1/fo Period Jitter Cycle-to-Cycle Jitter Actual Output Actual Output 0V 0V VY − VZ VY − VZ tc(n) tc(n) tc(n +1) tjit(cc) = | tc(n) − tc(n + 1) | tjit(pp) = | tc(n) − 1/fo | Peak-to-Peak Jitter VA PRBS Input VY 0V VB 0V VZ PRBS Output tjit(pp) A. All input pulses are supplied by an Agilent 81250 Stimulus System. B. The measurement is made with the AgilentParBert measurement software. Figure 7. Driver Jitter Measurement Waveforms <3-inch 50 W TL (7,62 cm) 25-inch FR4 (63,5 cm) <3-inch 50 W TL (7,62 cm) Figure 8. AC Test Circuit — Jitter and Output Rise Time Test Circuit The SN65LVCP404 input equalizer provides 5-dB frequency gain to compensate for frequency loss of a shorter backplane transmission line. For characterization purposes, a 25-inch (63,5 cm) FR-4 coupled transmission line is used in place of the backplane trace. The 25-inch trace provides roughly 5 dB of attenuation between 375 MHz and 2.125 GHz, representing closely the characteristics of a short backplane trace. The loss tangent of the FR4 in the test board is 0.018 with an effective ε(r) of 4.1. Submit Documentation Feedback 9 SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 TYPICAL DEVICE BEHAVIOR Eye After 51 inch FR-4 Trace, Input 800 mVPP Eye After 51 inch FR-4 Trace, Input 800 mVPP, Through the 404 With Pre-emphasis at 3 dB 100 ps/div Pre-emphasis Levels 50 ps/div Figure 10. Preemphasis Signal Shape NOTE: 51 Inches (129.54 cm) Input Trace, dR = 4.25 Gbps; 27- 1 PRBS Figure 9. Data Input and Output Pattern 4.25 Gbps Signal Generator 7-1 PRBS 2 800 mVPP Input 35-inches, 88.9 cm FR4 51-inches, 129.54 cm FR4 35-inches, 88.9 cm FR4 Figure 11. Data Output Pattern 10 Submit Documentation Feedback SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 TYPICAL CHARACTERISTICS DETERMINISTIC OUTPUT JITTER vs DIFFERENTIAL INPUT AMPLITUDE 1.4 25 50 4.25 Gbps 27-1 PRBS pattern, The DJ is Measured on the Output of the LVCP404 45 40 20 3.75 Gbps 35 3.125 Gbps 15 30 2.5 Gbps 25 10 20 15 5 10 1.25 Gbps 5 0 0 2 3 4 5 6 7 1.2 1 0.8 0.6 0.4 0.2 0 0 8 500 Figure 12. 1000 1500 0 2000 1 2 3 4 5 6 DR - Data Rate - Gbps Figure 13. SUPPLY NOISE vs DETERMINISTIC JITTER vs DATA RATE 7 8 Figure 14. DETERMINISTIC OUTPUT JITTER vs COMMON-MODE INPUT VOLTAGE 25 35 Noise = 200 mV Noise = 650 mV Noise = 300 mV 30 25 20 Noise = 50 mV 15 Noise = 100 mV Noise = 400 mV 10 5 Deterministic Output Jitter - ps 1 Deterministic Output Jitter - ps 0 DIFFERENTIAL OUTPUT VOLTAGE vs DATA RATE VOD - Differential Output Voltage - VPP DETERMINISTIC OUTPUT JITTER vs DATA RATE 20 4.25 Gbps 15 10 5 0 0 0 4000 3000 1000 2000 DR - Data Rate - Gbps 5000 0 1 2.5 3 0.5 2 1.5 VIC - Common Mode Input Voltage - V Figure 15. Submit Documentation Feedback Figure 16. 11 SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 APPLICATION INFORMATION CONFIGURATION EXAMPLES S10 0 S30 1 S11 0 S31 0 S20 0 S40 1 S21 1 S41 1 S10 0 S30 0 S20 0 S40 0 S21 0 S41 0 1A 1Y 1A 1Y 1B 1Z 1B 1Z 2A 2Y 2Y 2B 2Z 2Z 3A 3Y 3Y 3B 3Z 3Z 4A 4Y 4Y 4B 4Z 4Z S10 0 S30 1 S11 0 S31 0 S20 0 S40 1 S21 0 S41 0 S10 1 S30 0 S11 1 S31 0 S20 1 S40 0 S21 1 S41 0 1A 1Y 1A 1Y 1B 1Z 1B 1Z 2Y 2Y 2Z 2Z 12 S11 0 S31 0 3A 3Y 3Y 3B 3Z 3Z 4Y 4A 4Y 4Z 4B 4Z Submit Documentation Feedback SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 APPLICATION INFORMATION (continued) BANDWIDTH REQUIREMENTS Error free transmission of data over a transmission line has specific bandwidth demands. It is helpful to analyze the frequency spectrum of the transmit data first. For an 8B10B coded data stream at 3.75 Gbps of random data, the highest bit transition density occurs with a 1010 pattern (1.875 GHz). The least transition density in 8B10B allows for five consecutive ones or zeros. Hence, the lowest frequency of interest is 1.875 GHz/5 = 375 MHz. Real data signals consist of higher frequency components than sine waves due to the fast rise time. The faster the rise time, the more bandwidth becomes required. For 80-ps rise time, the highest important frequency component is at least 0.6/(π × 80 ps) = 2.4 GHz. Figure 17shows the Fourier transformation of the 375-MHz and 1.875-GHz trapezoidal signal. Signal Amplitude − dB 0 20 dB/dec 1875 MHz With 80 ps Rise Time −5 20 dB/dec 375 MHz With 80 ps Rise Time −10 40 dB/dec −15 80% 20% tr −20 −25 40 dB/dec tPeriod = 1/f 100 1000 f − Frequency − MHz 1/(pi x 100/60 tr) = 2.4 GHz 10000 Figure 17. Approximate Frequency Spectrum of the Transmit Output Signal With 80 ps Rise Time The spectrum analysis of the data signal suggests building a backplane with little frequency attenuation up to 2 GHz. Practically, this is achievable only with expensive, specialized PCB material. To support material like FR4, a compensation technique is necessary to compensate for backplane imperfections. EXPLANATION OF EQUALIZATION Backplane designs differ widely in size, layer stack-up, and connector placement. In addition, the performance is impacted by trace architecture (trace width, coupling method) and isolation from adjacent signals. Common to most commercial backplanes is the use of FR4 as board material and its related high-frequency signal attenuation. Within a backplane, the shortest to longest trace lengths differ substantially – often ranging from 8 inches up to 40 inches. Increased loss is associated with longer signal traces. In addition, the backplane connector often contributes a good amount of signal attenuation. As a result, the frequency signal attenuation for a 300-MHz signal might range from 1 dB to 4 dB while the corresponding attenuation for a 2-GHz signal might span 6 dB to 24 dB. This frequency dependent loss causes distortion jitter on the transmitted signal. Each LVCP404 receiver input incorporates an equalizer and compensates for such frequency loss. The SN65LVCP404 equalizer provides 5 dB of frequency gain between 375 MHz and 1.875 GHz, compensating roughly for 20 inches of FR4 material with 8-mil trace width. Distortion jitter improvement is substantial, often providing more than 30-ps jitter reduction. The 5-dB compensation is sufficient for most short backplane traces. For longer trace lengths, it is recommended to enable transmit preemphasis in addition. Submit Documentation Feedback 13 SN65LVCP404 www.ti.com SLLS700 – MARCH 2007 APPLICATION INFORMATION (continued) SETTING THE PREEMPHASIS LEVEL The receive equalization compensates for ISI. This reduces jitter and opens the data eye. In order to find the best preemphasis setting for each link, calibration of every link is recommended. Assuming each link consists of a transmitter (with adjustable pre-emphasis such as LVCP404) and the LVCP404 receiver, the following steps are necessary: 1. Set the transmitter and receiver to 0-dB preemphasis; record the data eye on the LVCP404 receiver output. 2. Increase the transmitter preemphasis until the data eye on the LVCP404 receiver output looks the cleanest. 14 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 7-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVCP404RGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN65LVCP404RGZRG4 ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device SN65LVCP404RGZR 17-May-2007 Package Pins RGZ 48 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) MLA 330 16 7.3 7.3 1.5 12 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN65LVCP404RGZR RGZ 48 MLA 346.0 346.0 33.0 Pack Materials-Page 2 W Pin1 (mm) Quadrant 16 PKGORN T2TR-MS P IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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