SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com 1.5/3.0/6.0 Gbps SATA/SAS Redriver Check for Samples: SN75LVCP600S FEATURES • 1 • • • • • Single 3.3 V supply Suitable to receive 6.0 Gbps data over up to >40 inches (1.0 meter) of FR4 PC board Two-level RX and TX Equalization – RX→ 7, 15dB – TX→ 0, –1.3dB Pin-selectable SATA/SAS signaling Programmable squelch threshold for long channels • • Low active power and partial/slumber state support – 106mW TYP (Active Mode @6Gbps) – <11mW (when link in partial/slumber state) Ultra-small package for optimal placement – • 10-pad 2.5mm x 2.5mm QFN High ESD-transient protection – HBM: 9,000V – CDM: 1,500V – MM: 200V APPLICATIONS • Notebook and desktop PCs, docking stations, active cable, servers, workstations (1) DESCRIPTION Vcc[2] GND[6] The SN75LVCP600S is a single channel SATA/SAS signal conditioner supporting data rates up to 6.0Gbps. The device complies with SATA physical spec rev 3.0 and SAS electrical spec 2.0 SN75LVCP600S operates from a single 3.3V supply and has 100Ω line termination with self-biasing feature, making the device suitable for AC coupling. The inputs incorporate an OOB (out-of-band) detector, which automatically squelch the output while maintaining a stable common mode voltage compliant to SATA/SAS link. VBB = 1.7 V TYP LVCP600S RT RX+ [3] TX+ [8] Driver Equalizer RT RX- [4] TX- [7] OOB Detect The SN75LVCP600S handles interconnect losses at its input with selectable equalization settings that can be programmed to match loss in the channel. For data rates of 3Gbps and lower the LVCP600S equalizes signals for a span of up to 50 inches of FR4 board material. For data rates of 6Gbps, the device compensates > 40 inches of FR4 material. Rx/Tx equalization level is controlled by the setting of signal control pins EQ and DE. CTRL MODE DE EQ SQ_TH [1] [9] [5] [10] Figure 1. Data Flow Block Diagram The device is hot-plug capable(1) preventing device damage during device hot-insertion such as async signal plug/removal, unpowered plug/removal, (1) Requires use of AC coupling capacitors at differential inputs powered plug/removal, or surprise plug/removal. and outputs. Table 1. ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE SN75LVCP600SDSKR 600S 10-pin DSK Reel (large) SN75LVCP600SDSKT 600S 10-pin DSK Reel (small) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. EQ SAS Host EQ SATA / SAS Sink ~ 40 " ( 4 mil FR -4 ) EQ = LVCP600S EQ HDD SAS Cable SAS /SATA Host spacing A 0+ B 0- A 0TX + SAS/SATA Host C0 + C 0- HD 3SS 3412 FET MUX RX - HDD B1 + A 1+ LVCP600S RX + LVCP600S B 0+ LVCP600S TX + B 1A 1C 1+ C1 - SEL ~40 " at SAS 6G Figure 2. Typical Application spacing 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com PIN ASSIGNMENTS Top View 10 SQ_TH 9 DE 8 TX+ 4 7 TX- 5 6 GND 1 Vcc 2 RX+ 3 RXEQ LVCP600S DSK 1 MODE Package Thermal Pad It is recomended to solder the package thermal pad to the ground plane for maximum thermal performance. PIN FUNCTIONS PIN NO. NAME I/O TYPE DESCRIPTION HIGH SPEED DIFFERENTIAL I/O 3 RX+ I, CML 4 RX– I, CML 8 TX+ I, CML 7 TX– I, CML Non-inverting and inverting CML differential inputs. These pins are tied to an internal voltage bias by dual termination-resistor circuit. Non-inverting and inverting CML differential outputs. These pins are tied to an internal voltage bias by dual termination-resistor circuit. CONTROL PINS 5 EQ I, LVCMOS Selects equalization settings per Table 2. Internally tied to GND. 9 DE I, LVCMOS Selects de-emphasis settings per Table 2. Internally tied to GND. 1 MODE I, LVCMOS Selects SATA or SAS output levels per Table 2. Internally tied to GND 10 SQ_TH I, LVCMOS Selects squelch threshold settings per Table 2. Internally tied to GND POWER 2 VCC Power Positive supply should be 3.3V ±10% 6 GND Power Supply ground Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S 3 SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com Table 2. EQ and DE Settings CONTROL PINS Level EQ (typ) dB at 6Gbps DE (typ) dB at 6Gbps 0 (default) 7 1 14 SQ_TH (see VOOB spec) MODE 0 Full Level (normal) SATA –1.3 Reduced Level (long channel) SAS SATA/SAS Device Mid Plane/Back Plane SATA/SAS Host < 6" SS Tx Rx LVCP600S S S LVCP600S Rx Tx ~ 40 " ( 1 m ) Trace lengths are suggested values based on TI spice simulations (done over programmable limits of input EQ) to meet SATA/SAS loss and jitter spec. Actual trace length supported by the LVCP600S may be more or less than suggested values and will depend on board layout, trace widths and number of connectors used in the high speed signal path. See eye diagrams at end of datasheet for more placement guidance. Figure 3. Trace Length Example 3.3 V 1 mF 0.1 mF 0.01 mF 1 10 2 9 3 8 10 nF 10 nF 7 1 6 5 4 7 6 LVCP600S 10 nF 10 nF 3 3.3 V 8 9 2 10 nF 0.01 mF 0.1 mF 10 LVCP600S 1 mF 1 10 nF 4 5 SAS Sink SATA/SAS Host 1 10 nF A. Place supply capacitors close to device pin B. EQ selection is set at 7db, device is set in SAS mode, DE and SQ_TH at default settings C. Actual EQ settings depend on device placement relative to host and SATA/SAS device Figure 4. Typical Device Implementation OPERATION DESCRIPTION INPUT EQUALIZATION The SN75LVCP600S supports programmable equalization in its front stage; the equalization settings are shown in Table 2. The input equalizer is designed to recover a signal even when no eye is present at the receiver and will affectively support FR4 trace at the input anywhere from 4" to 40" at SATA 6G speed. In SAS mode, the device meets compliance point IR in a TXRX connection. 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com SAS Drive Plug LVCP600S IR SAS Mode Transmitter Device Compliance Point (IR) signal going to receiver device as measured at this point Main Board/Backplane SAS Receptacle Figure 5. Compliance Point In SAS Mode AUTO LOW POWER (ALP) MODE (see Figure 10) As a redriver, the SN75LVCP600S does not participate in SATA or SAS link power management (PM) states. However, the redriver tracks link-power management mode (Partial and Slumber) by relying on the link differential voltage, VIDp-p. The SATA/SAS link is continuously sending and receiving data even in long periods of disk inactivity by sending SYNC primitives (logical idle), except when the link enters Partial or Slumber mode. In these modes the link is in an electrical-idle state (EID). The device input squelch detector tracks EID status. When the input signal is in the electrical idle state, i.e. VIDp-p <VOOB_SATA/VOOB_SAS and stays in this state for > 10µS, the device automatically enters the low power state. In this state, the output is driven to VCM and the device selectively shuts off internal circuitry to lower power consumption by ~90% of its normal operating power. While in ALP mode, the device continues to actively monitor input signal levels; when the input signal exceeds the SATA/SAS OOB upper threshold level, the device reverts to active state. Exit time from auto low power mode is <50ns (MAX). OUT-OF-BAND (OOB) SUPPORT The squelch detector circuit within the device enables full detection of OOB signaling as specified in the SATA and SAS specifications. Selection of squelch threshold level is made automatically based on the state of MODE pin, SATA or SAS. Squelch circuit ON/OFF time is 8ns max. While in squelch mode, outputs are held to VCM. DEVICE POWER The SN75LVCP600S is designed to operate from a single 3.3V supply. Always practice proper power supply sequencing procedure. Apply VCC first before any input signals are applied to the device. The power down sequence is in reverse order. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT Supply voltage range (2) VCC –0.5 to 4 V Voltage range Differential I/O –0.5 to 4 V –0.5 to VCC + 0.5 V Control I/O Electrostatic discharge (3) ±9000 V Charged-device model (4) ±1500 V Machine model (5) ±200 V Human body model Continuous power dissipation (1) (2) (3) (4) (5) See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B. Tested in accordance with JEDEC Standard 22, Test Method C101-A. Tested in accordance with JEDEC Standard 22, Test Method A115-A. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S 5 SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com THERMAL INFORMATION SN75LVCP600S THERMAL METRIC (1) θJA Junction-to-ambient thermal resistance 55.7 θJCtop Junction-to-case (top) thermal resistance 61.9 θJB Junction-to-board thermal resistance 29.2 ψJT Junction-to-top characterization parameter 1.0 ψJB Junction-to-board characterization parameter 29.3 θJCbot Junction-to-case (bottom) thermal resistance 9.4 (1) UNITS DSK (10) PINS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS typical values for all parameters are at VCC = 3.3 V and TA = 25°C; all temperature limits are specified by design PARAMETER VCC Supply voltage CCOUPLING Coupling capacitor TA Operating free-air temperature TEST CONDITIONS MIN 3 TYP MAX 3.3 3.6 12 UNITS V nF –40 85 °C ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DEVICE PARAMETERS ICCMax Active mode supply current ICCPS Auto power save mode ICC MODE/EQ/DE/SQ_TH = NC, K28.5 pattern at 6Gbps, VID = 700mVpp, (SATA mode) 29 41 MODE/EQ/DE/SQ_TH = VCC, K28.5 pattern at 6Gbps, VID = 700mVpp, (SAS mode) 32 45 When auto low power conditions are met 3.3 5.0 mA 6.0 Gbps 280 330 ps Maximum data rate mA tPDelay Propagation delay Measured using K28.5 pattern, See Figure 8 AutoLPENTRY Auto low power entry time Electrical idle at input, See Figure 10 11 20 μs AutoLPEXIT Auto low power exit time After first signal activity, See Figure 10 30 40 ns 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS OOB VOOB_SAS VOOB_SATA Input OOB threshold (output squelched below this level) Input OOB threshold (output squelched below this level) F = 750MHz; SQ_TH=0, MODE = 1 Measured at receiver pin 88 112 131 F = 750MHz; SQ_TH=1, MODE = 1 Measured at receiver pin 67 85 100 F = 750MHz; SQ_TH=0, MODE = 0 Measured at receiver pin 40 66 86 F = 750MHz; SQ_TH=1, MODE = 0 Measured at receiver pin 35 56 72 mVpp DVdiffOOB OOB differential delta 25 mV DVCMOOB OOB common-mode delta 50 mV tOOB1 OOB mode enter See Figure 9 3 8 ns tOOB2 OOB mode exit See Figure 9 3 8 ns CONTROL LOGIC VIH High-level input voltage VIL Low-level input voltage VINHYS Input hysteresis IIH High-level input current IIL Low-level input current For all control pins 1.4 V 0.5 V 115 MODE, SQ_TH = VCC mV μA 30 EQ, DE = VCC 20 MODE, SQ_TH = GND –30 EQ, DE = GND –10 RECEIVER AC/DC ZDIFFRX Differential input impedance 85 ZSERX Single-ended input impedance 40 VCMRX Common-mode voltage RLDiffRX RXDiffRLSlope RLCMRX VdiffRX IBRX T20-80RX Differential mode return loss (RL) Differential mode RL slope Common-mode return loss Differential input voltage PP Impedance balance Rise/fall time 100 Ω 115 Ω 1.7 f = 150MHz–300MHz 18 26 f = 300MHz–600MHz 14 23 f = 600MHz–1.2GHz 10 17 f = 1.2GHz–2.4GHz 8 14 f = 2.4GHz–3.0GHz 3 V dB 13 –13 f = 300MHz–6.0GHz f = 150MHz–300MHz 5 10 f = 300MHz–600MHz 5 18 f = 600MHz–1.2GHz 2 16 f = 1.2GHz–2.4GHz 1 12 f = 2.4GHz–3.0GHz 1 12 dB/dec dB MODE = 1, f = 1.5GHz and 3.0GHz 275 1600 MODE = 0, f = 1.5GHz and 3.0GHz 225 1600 f = 150MHz–300MHz 30 47 f = 300MHz–600MHz 30 40 f = 600MHz–1.2GHz 20 34 f = 1.2GHz–2.4GHz 10 28 f = 2.4GHz–3.0GHz 10 24 f = 3.0GHz–5.0GHz 4 22 f = 5.0GHz–6.5GHz 4 22 Rise times and fall times measured between 20% and 80% of the signal. SATA/SAS 6 Gbps speed measured 1" from device pin 62 mV/ppd dB 75 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S ps 7 SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TskewRX Differential skew TEST CONDITIONS MIN TYP MAX Difference between the single-ended mid-point of the RX+ signal rising/falling edge, and the single-ended mid-point of the RX– signal falling/rising edge UNITS 30 ps 122 Ω TRANSMITTER AC/DC ZdiffTX Pair differential impedance 85 ZSETX Single-ended input impedance 40 VTXtrans Sequencing transient voltage RLDiffTX Differential mode return loss TXDiffRLSlope RLCMTX Differential mode RL slope Common-mode return loss Transient voltages on the serial data bus during power sequencing (lab load) Impedance balance DiffVppTX Differential output voltage swing DE De-Emphasis Level VCMAC_TX TX AC CM voltage VCMTX 0 f = 150MHz–300MHz 13 22 f = 300MHz–600MHz 8 21 f = 600MHz–1.2GHz 6 20 f = 1.2GHz–2.4GHz 6 17 f = 2.4GHz–3.0GHz 3 f = 300MHz – 3.0GHz 1.2 V dB 17 –13 f = 150MHz–300MHz 5 19 f = 300MHz–600MHz 5 16 f = 600MHz–1.2GHz 2 11 f = 1.2GHz–2.4GHz 1 9 1 10 f = 150MHz–300MHz 30 43 f = 300MHz–600MHz 30 40 f = 600MHz–1.2GHz 20 32 f = 1.2GHz–2.4GHz 10 25 f = 2.4GHz–3.0GHz 10 27 f = 3.0GHz–5.0GHz 4 25 f = 5.0GHz–6.5GHz 4 26 dB/dec dB dB DE = 1, MODE = 1→(SAS), f = 3.0GHz (under no interconnect loss) 385 850 1300 DE = 0, MODE = 0→(SATA), f = 3.0GHz (under no interconnect loss) 400 600 mV/ppd DE = 1 –1.3 DE = 0 0 800 dB At 1.5GHz 20 50 mVppd At 3.0GHz 11 26 At 6.0GHz 13 30 dBmv (rms) Common-mode voltage 1.7 T20-80TX Rise/Fall time Rise times and fall times measured between 20% and 80% of the signal. At 6Gbps SATA or SAS, under no load, measured at the pin TskewTX Differential skew Difference between the single-ended mid-point of the TX+ signal rising/falling edge, and the single-ended mid-point of the TX– signal falling/rising edge, SATA or SAS mode TxR/Flmb TX rise/fall imbalance At 3 Gbps TxAmplmb TX amplitude imbalance 8 Ω –1.2 f = 2.4GHz–3.0GHz IBTX 100 Submit Documentation Feedback 33 V 50 76 ps 4 14 ps 3 18 1.5 10 % Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TRANSMITTER JITTER AT CP TEST CONDITIONS MIN TYP MAX UNITS (1) 3Gbps SATA mode TJTX Total jitter (1) DJTX Deterministic jitter VID = 500 mVpp, UI = 333ps, K28.5 control character, EQ/DE=1 RJTX Residual random jitter VID = 500 mVpp, UI = 333ps, K28.7 control character, EQ/DE=1 0.26 0.38 UIpp 0.13 0.24 UIpp 1.16 1.95 ps-rms 6Gbps SATA mode TJTX Total jitter (1) DJTX Deterministic jitter VID = 500 mVpp, UI = 167ps, K28.5 control character, EQ/DE=1 RJTX Residual random jitter VID = 500 mVpp, UI = 167ps, K28.7 control character, EQ/DE=1 0.37 0.61 UIpp 012 0.32 UIpp 1.15 2.2 ps-rms 3Gbps SAS mode TJTX Total jitter (1) DJTX Deterministic jitter VID = 500 mVpp, UI = 333ps, K28.5 control character, EQ/DE=1 RJTX Residual random jitter VID = 500 mVpp, UI = 333ps, K28.7 control character, EQ/DE=1 0.25 0.37 UIpp 0.12 0.23 UIpp 1.11 2.0 ps-rms 0.35 0.57 UIpp 6Gbps SAS mode TJTX Total jitter (1) DJTX Deterministic jitter VID = 500 mVpp, UI = 167ps, K28.5 control character, EQ/DE=1 0.10 0.29 UIpp RJTX Residual random jitter VID = 500 mVpp, UI = 167ps, K28.7 control character, EQ/DE=1 1.10 2.14 ps-rms (1) TJ = (14.1×RJSD + DJ) where RJSD is one standard deviation value of RJ Gaussian distribution. Jitter measurement is at the CP connector and includes jitter generated at the package connection on the printed circuit board, and at the board interconnect as shown in Figure 6. Jitter Measurement CP 40" 4mil Stripline AWG 4" 4 mil Stripline Figure 6. Jitter Measurement Test Condition Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S 9 SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com -RL dB RX TX 0.30 3 Log Frequency - GHz 6 Figure 7. TX, RX Differential Return Loss Limits IN tPDelay tPDelay OUT Figure 8. Propagation Delay Timing Diagram IN+ Vcm 50mV INtOOB tOOB OUT+ Vcm OUT- Figure 9. OOB Enter and Exit Timing 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com RXP VCMRX RXN tOOB AutoLPEXIT TXP VCMTX TXN AutoLPENTRY Power Saving Mode Figure 10. Auto Low Power Mode Entry and Exit Timing TYPICAL EYE DIAGRAMS AND PERFORMANCE CURVES LVCP600S LVCP600S Output Input (variable ) 4 mil Pattern generator A. Output EQ DE = 2 " ( fixed ) Oscilloscope LVCP600S Input VCC = 3.3V; INPUT = K28.5 pattern at 1.5Gbps; 3.0Gbps and 6.0 Gbps; VID = 1000mVpp; TEMP = 25°C; TRACE WIDTH = 4mil Figure 11. Eye Diagram Measurement Setup for LVCP600S Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S 11 SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com Figure 12. SATA 6.0 Gbps Signal After 16” , Input of LVCP600S (MODE=0) Figure 13. SATA 6.0 Gbps DE= 0, EQ = 1, at Output = 2” after Equalizing (MODE=0) 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com Figure 14. SATA 6.0 Gbps signal after 32” at Input of LVCP600S (MODE=0) Figure 15. SATA 6.0 Gbps DE= 0, EQ = 1, at Output = 2” after Equalizing (MODE=0) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S 13 SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com Figure 16. SATA 6.0 Gbps signal after 40” at Input of LVCP600S (MODE=0) Figure 17. SATA 6.0 Gbps DE= 1, EQ = 1, at Output = 2” after Equalizing (MODE=0) 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com Figure 18. SAS 3.0 Gbps signal after 32” at Input of LVCP600S (MODE=1) Figure 19. SAS 3.0 Gbps DE= 0, EQ = 1, at Output = 2” after Equalizing (MODE=1) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S 15 SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com Figure 20. SAS 6.0 Gbps signal after 32” at Input of LVCP600S (MODE=1) Eye Height = 709.5mV Jitter = 17.888 ps Figure 21. SAS 6.0 Gbps DE= 0, EQ = 1, at Output = 2” after Equalizing (MODE=1) 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com Figure 22. SAS 3.0 Gbps signal after 40” at Input of LVCP600S (MODE=1) Figure 23. SAS 3.0 Gbps DE= 1, EQ = 1, at Output = 2” after Equalizing (MODE=1) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S 17 SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com Figure 24. SAS 6.0 Gbps signal after 40” at Input of LVCP600S (MODE=1) Eye Height = 673 .0 mV Jitter = 20 . 384 ps Figure 25. SAS 6.0 Gbps DE= 1, EQ = 1, at Output = 2” after Equalizing (MODE=1) 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S SN75LVCP600S SLLSE81 – MARCH 2011 www.ti.com SATA MODE DETERMINISTIC JITTER vs DATA RATE SATA MODE DETERMINISTIC JITTER vs LAUNCH AMPLITUDE 50 30 8 in., EQ =1, DE = 0 16 in., EQ =1, DE = 0 24 in., EQ =1, DE = 0 32 in., EQ =1, DE = 1 40 in., EQ =1, DE = 1 45 35 25 Deterministic Jitter (psP−P) Deterministic Jitter (psP−P) 40 As a function of data rate after equalizing for 32 in. of input FR−4 trace EQ = 1, DE = 1 30 25 20 15 20 15 10 10 5 1.5 GbPS 3 GbPS 6 GbPS 5 As a function of input trace length on 4mil FR−4 0 1 1.5 2 2.5 3 3.5 4 4.5 Data Rate (GbPS) 5 5.5 6 0 300 6.5 400 Figure 26. 600 700 800 900 Figure 27. SAS MODE DETERMINISTIC JITTER vs DATA RATE SAS MODE DETERMINISTIC JITTER vs LAUNCH AMPLITUDE 50 40 8 in., EQ =1, DE = 0 16 in., EQ =1, DE = 0 24 in., EQ =1, DE = 0 32 in., EQ =1, DE = 0 40 in., EQ =1, DE = 1 45 40 35 As a function of data rate after equalizing for 32 in. of input FR−4 trace EQ = 1, DE = 0 35 30 Deterministic Jitter (psP−P) Deterministic Jitter (psP−P) 500 Launch Amplitude (mVP−P) 30 25 20 15 25 20 15 10 10 1.5 GbPS 3 GbPS 6 GbPS 5 5 As a function of trace length on FR−4 0 1 1.5 2 2.5 3 3.5 4 4.5 Data Rate (GbPS) 5 5.5 6 6.5 0 300 400 500 600 700 800 900 Launch Amplitude (mVP−P) Figure 28. Figure 29. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): SN75LVCP600S 19 PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) SN75LVCP600SDSKR ACTIVE SON DSK 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN75LVCP600SDSKT ACTIVE SON DSK 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN75LVCP600SDSKR SON DSK 10 3000 180.0 8.4 2.8 2.8 1.0 4.0 8.0 Q2 SN75LVCP600SDSKT SON DSK 10 250 180.0 8.4 2.8 2.8 1.0 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75LVCP600SDSKR SON DSK 10 3000 210.0 185.0 35.0 SN75LVCP600SDSKT SON DSK 10 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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