SN54ABT162501, SN74ABT162501 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS243E – SEPTEMBER 1992 – REVISED FEBRUARY 1999 D D D D D D D D D D SN54ABT162501 . . . WD PACKAGE SN74ABT162501 . . . DGG OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family B-Port Outputs Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA description These 18-bit universal bus transceivers consist of storage elements that can operate either as D-type latches or D-type flip-flops to allow data flow in transparent or clocked modes. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low). The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT162501, SN74ABT162501 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS243E – SEPTEMBER 1992 – REVISED FEBRUARY 1999 description (continued) When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. The SN54ABT162501 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT162501 is characterized for operation from –40°C to 85°C. FUNCTION TABLE† INPUTS OEAB LEAB CLKAB A OUTPUT B L X X X Z H H X L L H H X H H H L ↑ L L H L ↑ H H H L H X B0‡ B0§ H L L X † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. ‡ Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low § Output level before the indicated steady-state input conditions were established 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT162501, SN74ABT162501 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS243E – SEPTEMBER 1992 – REVISED FEBRUARY 1999 logic symbol† OEAB CLKAB LEAB OEBA CLKBA LEBA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 1 55 2 27 30 28 3 EN1 2C3 C3 G2 EN4 5C6 C6 G5 3D 1 1 4 1 6D 54 5 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 41 17 40 19 38 20 37 21 36 23 34 24 33 26 31 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT162501, SN74ABT162501 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS243E – SEPTEMBER 1992 – REVISED FEBRUARY 1999 logic diagram (positive logic) OEAB 1 55 CLKAB LEAB LEBA CLKBA OEBA A1 2 28 30 27 3 1D C1 CLK 54 B1 1D C1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT162501 (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT162501 (A port) . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT162501, SN74ABT162501 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS243E – SEPTEMBER 1992 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 3) SN54ABT162501 VCC VIH Supply voltage VIL VI Low-level input voltage High-level input voltage SN74ABT162501 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 2 2 0.8 Input voltage 0 0.8 V VCC –32 V A port B port –12 –12 A port 48 64 B port 12 12 High level output current High-level IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 Outputs enabled 10 10 –40 mA mA ns/V µs/V 200 125 V V VCC –24 IOH 0 UNIT 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT162501, SN74ABT162501 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS243E – SEPTEMBER 1992 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK A port TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOH B port VCC = 4.5 V, VCC = 5 V, 5V VCC = 4 4.5 VOL A port VCC = 4 4.5 5V B port VCC = 4.5 V, MIN –1.2 SN74ABT162501 MIN –1.2 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOH = –1 mA 2* 2 3.35 3.3 3.35 IOH = –1 mA IOH = –3 mA 3.85 3.8 3.85 3.1 3 3.1 IOH = –12 mA IOL = 48 mA 2.6 A or B ports UNIT V V 2.6 0.55 IOL = 64 mA IOL = 12 mA 0.55 0.55* 0.55 0.8 0.8 0.8 ±1 ±1 ±1 ±20 ±20 ±20 100 Control inputs VCC = 0 to 5.5 V, VI = VCC or GND VCC = 2.1 V to 5.5 V, VI = VCC or GND V mV µA IOZPU VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE or OE = X§ ±50 ±50 ±50 µA IOZPD VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE or OE = X§ ±50 ±50 ±50 µA IOZH‡ VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V or OE ≤ 0.8 V 10 10 10 µA IOZL‡ VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V or OE ≤ 0.8 V –10 –10 –10 µA ±100 µA 50 µA Ioff ICEX IO¶ ICC Outputs high A port B port A or B ports VCC = 0, VCC = 5.5 V, VI or VO ≤ 4.5 V VO = 5.5 V ±100 VCC = 5.5 V, VCC = 5.5 V, VO = 2.5 V VO = 2.5 V VCC = 5.5 V, IO = 0, 0 VI = VCC or GND Outputs high 3 3 3 Outputs low 36 36 36 3 3 3 50 Ci Control inputs Cio A or B ports 50 –50 –110 –180 –50 –180 –50 –180 –25 –55 –90 –25 –90 –25 –90 Outputs disabled VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND ∆ICC# VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 50 50 mA µA pF 9 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 50 mA 3 * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ The parameters IOZH and IOZL include the input leakage current. § For VCC between 2.1 V and 4 V, OE should be less than or equal to 0.5 V to ensure a low state. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 6 MAX –1.2 2.5 Vhys II TA = 25°C SN54ABT162501 TYP† MAX MIN MAX • DALLAS, TEXAS 75265 SN54ABT162501, SN74ABT162501 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS243E – SEPTEMBER 1992 – REVISED FEBRUARY 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ABT162501 MIN fclock tw tsu Clock frequency SN74ABT162501 MIN 150 LEAB or LEBA high Pulse duration Setup time 3 CLKAB or CLKBA high or low 3.3 3.3 A before CLKAB↑ 4.3 4.3 B before CLKBA↑ 4.3 4.3 2.5 2.5 Hold time CLK high CLK low MAX 150 3 A before LEAB↓ or B before LEBA↓ th MAX 1 1 A after CLKAB↑ or B after CLKBA↑ 0 0 A after LEAB↓ or B after LEBA↓ 2 2 UNIT MHz ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) A or B B or A LEAB or LEBA B or A CLKAB or CLKBA B or A OEAB or OEBA B or A OEAB or OEBA B or A VCC = 5 V, TA = 25°C SN54ABT162501 MAX MIN MAX SN74ABT162501 MIN TYP 150 200 1.5 2.6 4 1.5 5.1 1.5 4.8 2 3.4 5.2 2 6.1 2 5.7 2 3.3 4.8 2 6.1 2 5.6 2 3.8 5.2 2 6.4 2 5.9 1.5 3.5 4.7 1.5 6 1.5 5.5 1.5 3.5 4.8 1.5 5.8 1.5 5.3 1.5 3.4 4.6 1.5 5.6 1.5 5.3 2 3.8 4.7 2 5.6 2 5.4 2 4.5 5.7 2 6.9 2 6.5 1.5 3.8 5.3 1.5 6.3 1.5 5.8 150 MIN UNIT MAX 150 MHz ns ns ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ABT162501, SN74ABT162501 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS243E – SEPTEMBER 1992 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V 1.5 V Data Input 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH 1.5 V VOL tPHL tPLZ 3.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 S1 at 7 V (see Note B) tPLH 1.5 V 1.5 V tPZL VOH Output 3V Output Control tPHL 1.5 V Output 1.5 V Output Waveform 2 S1 at Open (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated