× SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 • • • • • Member of the Texas Instruments Widebus Family Independent Asynchronous Inputs and Outputs 1024 Words × 18 Bits Read and Write Operations Can Be Synchronized to Independent System Clocks Programmable Almost-Full/Almost-Empty Flag • • • • • • Input-Ready, Output-Ready, and Half-Full Flags Cascadable in Word Width and/or Word Depth Fast Access Times of 15 ns With a 50-pF Load High-Output Drive for Direct Bus Interface 3-State Outputs Available in 68-Pin PLCC (FN) or Space-Saving 80-Pin Shrink Quad Flat Package (PN) D15 D16 D17 GND RDCLK RDEN1 RDEN2 OE RESET V CC GND OR VCC Q17 Q16 GND Q15 FN PACKAGE (TOP VIEW) 9 10 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VCC Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 VCC Q6 Q5 GND Q4 DAF GND WRTCLK WRTEN1 WRTEN2 VCC AF/AE GND IR HF VCC Q0 Q1 GND Q2 Q3 VCC D14 D13 D12 D11 D10 D9 VCC D8 GND D7 D6 D5 D4 D3 D2 D1 D0 Widebus is a trademark of Texas Instruments Incorporated. Copyright 1991, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 GND GND Q4 Q15 VCC Q14 Q13 GND GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 VCC Q6 Q5 PN PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VCC VCC NC Q3 Q2 GND Q1 Q0 VCC HF IR GND GND AF/AE VCC WRTEN2 WRTEN1 WRTCLK GND NC D8 GND D7 D6 D5 D4 D3 D2 D1 D0 DAF NC 1 NC D14 D13 D12 D11 D10 D9 VCC NC GND GND Q16 Q17 VCC OR GND VCC RESET OE RDEN2 RDEN1 RDCLK GND D17 D16 D15 NC NC NC − No internal connection description A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT7801 is a 1024- × 18-bit FIFO for high speed and fast access times. It processes data at rates up to 40 MHz and access times of 15 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth. The SN74ACT7801 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry adds the ability to synchronize independent read and write (interrupts, requests) to their respective system clock. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 logic symbol† Φ FIFO 1024 × 18 SN74ACT7801 1 RESET WRTCLK WRTEN1 WRTEN2 RDCLK RDEN1 OE RDEN2 DAF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 RESET 29 WRTCLK 30 & 31 IN RDY WRTEN HALF FULL 5 RDCLK 4 ALMOSTFULL/EMPTY & 2 EN1 35 36 33 66 OUT RDY,1 IR HF AF/AE OR RDEN 3 27 26 DEF ALMOST FULL 0 0 38 25 39 24 41 23 42 22 44 21 46 20 47 19 49 17 50 15 Data Data 1 52 14 53 13 55 12 56 11 58 10 59 9 61 8 63 7 64 17 17 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the FN package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 functional block diagram OE D0 − D17 RDCLK RDEN1 RDEN2 Synchronous Read Control Location 1 Location 2 Read Pointer 1024 × 18 RAM WRTCLK WRTEN1 WRTEN2 Synchronous Write Control Write Pointer Location 1023 Location 1024 RESET Reset Logic Register Status Flag Logic DAF Q0 − Q17 OR IR HF AF/AE functional description inputs data in (D0 −D17) Data inputs for 18-bit-wide data to be stored in the memory. Data lines D0 −D8 also carry the almost-full/almost-empty offset value (X) on a high-to-low transition of the define almost-full (DAF) input. reset (RESET) A reset is accomplished by taking reset (RESET) low and generating a minimum of four read-clock (RDCLK) and write-clock (WRTCLK) cycles. This ensures that the internal read and write pointers are reset and that the output-ready flag (OR), the half-full flag (HF), and the input-ready flag (IR) are low; the almost-full/almost-empty flag (AF/AE) is high. The FIFO must be reset upon power up. With the define almost-full (DAF) input at a low level, a low pulse on RESET defines the AF/AE status flag using the almost-full/almost-empty offset value (X), where X is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines the AF/AE flag using the default value of X = 256. write enables (WRTEN1, WRTEN2) The write enables (WRTEN1, WRTEN2) must be high before the rising edge of write clock (WRTCLK) for a word to be written into memory. The write enables do not affect the storage of the almost-full/almost-empty offset value (X). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 functional description (continued) write clock (WRTCLK) Data is written into memory on a low-to-high transition of the write clock (WRTCLK) if the input-ready flag output (IR) and the write-enable control inputs (WRTEN1, WRTEN2) are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all data transfers into the FIFO. The IR flag output is also driven synchronously with respect to the WRTCLK signal. read enables (RDEN1, RDEN2) Both read enables (RDEN1, RDEN2) must be high before the rising edge of read clock (RDCLK) to read a word out of memory. The read enables are not used to read the first word stored in memory. read clock (RDCLK) Data is read out of memory on a low-to-high transition at the read-clock (RDCLK) input if the output-ready flag output (OR) and the output-enable (OE) and read-enable (RDEN1, RDEN2) control inputs are high. RDCLK is a free-running clock and functions as the synchronizing clock for all data transfers out of the FIFO. The OR flag is also driven synchronously with respect to the RDCLK signal. define almost-full (DAF) The high-to-low transition of the define almost-full (DAF) input stores the binary value of data inputs D0−D8 as the almost-full/almost-empty offset value (X). With DAF held low, a low pulse on the reset (RESET) input defines the almost-full/almost-empty flag (AF/AE) using X. output enable (OE) The data-out (Q0−Q17) outputs and the output-ready flag (OR) are in the high-impedance state when the output enable (OE) input is low. OE must be high before the rising edge of read clock (RDCLK) to read a word from memory. outputs data out (Q0 −Q17) The first data word to be loaded into the FIFO is moved to the data out (Q0 − Q17) register on the rising edge of the third read clock (RDCLK) pulse to occur after the first valid write. The read-enable (RDEN1, RDEN2) inputs do not affect this operation. Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2, and the output-ready flag (OR) are high. input-ready flag (IR) The input-ready flag (IR) is high when the FIFO is not full and low when the device is full. During reset, the IR flag is driven low on the rising edge of the second write clock (WRTCLK) pulse. The IR flag is driven high on the rising edge of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low, IR is driven high on the second WRTCLK pulse after the first valid read. output-ready flag (OR) The output-ready flag (OR) is high when the FIFO is not empty and low when it is empty. During reset, the OR flag is set low on the rising edge of the third read clock (RDCLK) pulse. The OR flag is set high on the rising edge of the third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising edge of the first RDCLK pulse after the last word is read. half-full status flag (HF) The half-full flag (HF) is high when the FIFO contains 513 or more words and is low when it contains 512 or less words. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 functional description (continued) almost-full/almost-empty status flag (AF/AE) The almost-full/almost-empty flag (AF/AE) is defined by the almost-full/almost-empty offset value (X). The AF/AE flag is high when the FIFO contains (X + 1) or less words or (1025 − X) or more words. The AF/AE flag is low when the FIFO contains between (X + 2) and (1024 − X) words. programming procedure for AF/AE The almost-full/almost-empty flag (AF/AE) is programmed during each reset cycle. The almost-full/almostempty offset value (X) is either a user-defined value or the default value of X = 256. Below are instructions to program AF/AE using both methods. user-defined X: 1. Take DAF from high to low. 2. If RESET is not already low, take RESET low. 3. With DAF held low, take RESET high. This defines the AF/AE flag using X. 4. To retain the current offset for the next reset, keep DAF low. default X: To redefine the AF/AE flag using the default value of X = 256, hold DAF high during the reset cycle. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 timing diagrams RESET ÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Don’t Care DAF WRTCLK 1 2 WRTEN1 Don’t Care WRTEN2 Don’t Care D0 − D17 3 1 1 2 X† Don’t Care RDCLK 4 2 RDEN1 Don’t Care RDEN2 Don’t Care 3 4 OE ÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌ Q0 − Q17 OR Don’t Care AF/AE Don’t Care HF Don’t Care IR Invalid Don’t Care Store the Value of D0 −D8 as X Define the AF/AE Flag Using the Value of X † X is the binary value of D0 −D8 only. Figure 1. Reset Cycle: Define AF/AE Using the Value of X POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 RESET DAF WRTCLK WRTEN1 WRTEN2 D0 − D17 RDCLK RDEN1 RDEN2 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Don’t Care 1 2 3 4 ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ 1 2 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Don’t Care Don’t Care Don’t Care 1 2 3 4 Don’t Care Don’t Care OE Q0 − Q17 OR AF/AE HF IR ÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ Invalid Don’t Care Don’t Care Don’t Care Don’t Care Define the AF/AE Flag Using the Default Value of X=256 Figure 2. Reset Cycle: Define AF/AE Using the Default Value 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 RESET DAF ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Don’t Care WRTCLK WRTEN1 WRTEN2 D0−D17 RDCLK ÌÌÌÌÌ ÌÌ ÌÌ ÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌ ÌÌ ÌÌ ÌÌÌÌÌÌÌÌÌÌÌ W1 W2 W3 W4 1 2 3 WX+2 W513 W1025−X ÌÌ ÌÌ ÌÌ ÌÌ W1025 RDEN1 RDEN2 OE Q0 − Q17 W1 Invalid OR AF/AE HF IR Figure 3. Write POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 RESET DAF WRTCLK ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Don’t Care 1 2 WRTEN1 WRTEN2 D0 − D17 RDCLK ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ W1025 RDEN1 RDEN2 OE Q0 − Q17 W1 W1 W2 W3 WX+1 WX+2 W513 W514 OR AF/AE HF IR Figure 4. Read 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 W1024−X W1025−X W1024 W1025 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions ′ACT7801-15 ′ACT7801-18 ′ACT7801-20 MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 0.8 V High-level output current −8 −8 −8 mA IOL fclock Low-level output current High-level input voltage 2 16 Clock frequency 40 Data in (D0 −D17) high or low tw tsu th TA Pulse duration Setup time Hold time 2 2 16 28.5 10 12 14 WRTCLK high 7 8.5 10 WRTCLK low 15 15 15 RDCLK high 7 8.5 10 RDCLK low 15 15 15 DAF high 10 10 10 WRTEN1, WRTEN2 high or low 10 10 10 OE, RDEN1, RDEN2 high or low 10 10 10 Data in (D0 −D17) before WRTCLK↑ 5 5 5 WRTEN1, WRTEN2 before WRTCLK↑ 5 5 5 OE, RDEN1, RDEN2 before RDCLK↑ 5 5 5 Reset: RESET low before first WRTCLK and RDCLK↑ 7 7 7 Define AF/AE: D0 −D8 before DAF↓ 5 5 5 Define AF/AE: DAF↓ before RESET↑ 7 7 7 Define AF/AE (default): DAF high before RESET↑ 5 5 5 Data in (D0 −D17) after WRTCLK↑ 1 1 1 WRTEN1, WRTEN2 after WRTCLK↑ 1 1 1 OE, RDEN1, RDEN2 after RDCLK↑ 1 1 1 Reset: RESET low after fourth WRTCLK and RDCLK↑ 0 0 0 Define AF/AE: D0 −D8 after DAF↓ 1 1 1 Define AF/AE: DAF low after RESET↑ 0 0 0 Define AF/AE (default): DAF high after RESET↑ 1 Operating free-air temperature 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 70 0 V 16 35 V mA MHz ns ns ns 1 70 0 70 °C 11 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX VCC = 4.5 V, VCC = 4.5 V, IOH = − 8 mA IOL = 16 mA II IOZ VCC = 5.5 V, VCC = 5.5 V, VI = VCC or 0 VO = VCC or 0 ICC1‡ ICC2‡ Supply current fclock = 25 MHz§ Standby current VI = VIH or VIL ICC3‡ Ci Power-down current VIH = WRTCLK, VI = VCC − 0.2 V or 0 VI = 0, VO = 0, f = 1 MHz 4 pF f = 1 MHz 8 pF Co 2.4 UNIT VOH VOL V 0.5 V ±5 µA ±5 µA 200 230 mA 20 25 mA 400 µA switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (see Figures 9 and 10) PARAMETER fmax tpd tpd¶ tpd tpd FROM (INPUT) TO (OUTPUT) WRTCLK or RDCLK ′ACT7801-15 MIN TYP† MAX 40 5 tPLH tPHL tPLH tPHL ten tdis MAX 35 12 15 5 MIN MAX 28.5 18 5 UNIT MHz 20 Any Q WRTCLK↑ IR 4 10 4 12 4 14 ns RDCLK↑ OR 4 10 4 12 4 14 ns 7 20 7 22 7 24 7 20 7 22 7 24 6 19 6 21 6 23 6 19 6 21 6 23 AF/AE 4 19 4 21 4 23 HF 4 21 4 23 4 25 4 11 4 11 4 11 2 14 2 14 2 14 RDCLK↑ AF/AE WRTCLK↑ RDCLK↑ RESET↓ OE HF Any Q, OR POST OFFICE BOX 655303 ns 10.5 † All typical values are at VCC = 5 V, TA = 25°C. ‡ ICC tested with outputs open. § For frequencies greater than 25 MHz, ICC = 230 mA + (6 mA × [f − 25 MHz]). ¶ This parameter is measured with CL = 30 pF (see Figure 5). 12 MIN ′ACT7801-20 RDCLK↑ WRTCLK↑ tpd ′ACT7801-18 • DALLAS, TEXAS 75265 ns ns ns ns × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs LOAD CAPACITANCE 18 VCC = 5 V TA = 25°C RL = 500 Ω t pd − Propagation Delay Time − ns 17 16 15 14 13 12 11 10 0 30 50 100 150 200 250 300 CL − Load Capacitance − pF Figure 5 POWER DISSIPATION CAPACITANCE vs SUPPLY VOLTAGE Cpd - Power Dissipation Capacitance − pF 68 67 fi = 5 MHz TA = 25°C CL = 50 pF 66 65 64 63 62 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 VCC - Supply Voltage - V Figure 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 calculating power dissipation With ICCF taken from Figure 6, the maximum power dissipation based on all data outputs changing states on each read may be calculated using: Pt = VCC × [ICCF + (N × ∆ICC × dc)] + Σ(CL × VCC2 × fo) A more accurate power calculation based on device use and average number of data outputs switching can be found using: Pt = VCC × [ICC + (N × ∆ICC × dc)] + Σ(Cpd × VCC2 × fi) + Σ(CL × VCC2 × fo) where: = ICC N = ∆ ICC = dc = Cpd = CL = fi = fo = 14 power-down ICC maximum number of inputs driven by a TTL device increase in supply current duty cycle of inputs at a TTL high level of 3.4 V power dissipation capacitance output capacitive load data input frequency data output frequency POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 APPLICATION INFORMATION expanding the SN74ACT7801 The SN74ACT7801 is expandable in width and depth. Expanding in word depth offers special timing considerations: 1. After the first data word is loaded into the FIFO, the word is unloaded, and the output-ready flag output (OR) goes high after (N × 3) read clock (RDCLK) cycles, where N is the number of devices used in depth expansion. 2. After the FIFO is filled, the input-ready flag output (IR) goes low, the first word is unloaded, and the IR flag output is driven high after (N × 2) write clock cycles, where N is the number of devices used in depth expansion. CLOCK ’ACT7801 ’ACT7801 WRTCLK RDCLK RDCLK OR WRTEN1 RDEN1 RDEN1 WRTEN2 RDEN1 WRTEN2 RDEN2 RDEN2 IR RDEN2 IR WRTCLK WRTCLK RDCLK WRTEN1 WRTEN1 WRTEN2 IR OE D0 − D17 D0 − D17 5V Q0−Q17 D0 − D17 OR OR OE OE Q0 − Q17 Q0 − Q17 Figure 7. Word-Depth Expansion: 2048 Words × 18 Bits, N = 2 ’ACT7801 WRTCLK WRTCLK RDCLK RDCLK WRTEN WRTEN1 RDEN1 RDEN WRTEN2 RDEN2 IR OR OE D18 − D35 D0 − D17 Q0 − Q17 IR OE Q18 − Q35 OR ’ACT7801 WRTCLK RDCLK WRTEN1 RDEN1 WRTEN2 RDEN2 IR OR OE D0 − D17 D0 − D17 Q0 − Q17 Q0 − Q17 Figure 8. Word-Width Expansion: 1024 Words × 36 Bits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 × SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991 PARAMETER MEASUREMENT INFORMATION 3V Input From Output Under Test 1.5 V GND RL = 500 Ω tpd CL = 50 pF tpd 3V Output 1.5 V 0V LOAD CIRCUIT TOTEM-POLE OUTPUTS Figure 9. Standard CMOS Outputs (OR, Half Full, AF/AE) 3V 1.5 V Input 1.5 V 0V VCC tPZL ≈ VCC S1 From Output Under Test tPLZ Output RL 0.3 V 1.5 V VOL tPHZ CL tPZH S2 VOH 1.5 V Output 0.3 V ≈0V LOAD CIRCUIT VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES PARAMETER ten tPZH tPZL tdis tPHZ tPLZ RL CL† 500 Ω 50 pF 500 Ω 50 pF S1 S2 Open Closed Closed Open Open Closed Closed Open tpd or tt − 50 pF Open † Includes probe and test-fixture capacitance. Open Figure 10. 3-State Outputs (Any Q, OR) 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74ACT7801-18FN OBSOLETE PLCC FN 68 TBD Call TI Call TI SN74ACT7801-18FNR OBSOLETE PLCC FN 68 TBD Call TI Call TI SN74ACT7801-18FNR OBSOLETE PLCC FN 68 TBD Call TI Call TI SN74ACT7801-20FN OBSOLETE PLCC FN 68 TBD Call TI Call TI SN74ACT7801-20FN OBSOLETE PLCC FN 68 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. 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