SN54ALS190, SN54ALS191, SN74ALS190, SN74ALS191 SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986 • • • • • • Single Down/Up Count Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Dependable Texas Instruments Quality and Reliability SN54ALS190, SN54ALS191 . . . J PACKAGE SN74ALS190, SN74ALS191 . . . D OR N PACKAGE (TOP VIEW) B QB QA CTEN D/U QC QD GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC A CLK RCO MAX/MIN LOAD C D SN54ALS190, SN54ALS191 . . . FK PACKAGE description (TOP VIEW) QD GND NC D C QB B NC VCC A The ’ALS190 and ’ALS191 are synchronous, reversible up/down counters. The ’ALSL90 is a 4-bit decade counter and the ’ALS191 is a 4-bit binary counter. Synchronous counting operation 3 2 1 20 19 QA is provided by having all flip-flops clocked 18 CLK 4 simultaneously so that the outputs change CTEN 17 RCO 5 coincident with each other when so instructed by NC 16 NC 6 the steering logic. This mode of operation D/U 15 MAX/MIN 7 eliminates the output counting spikes normally 14 LOAD QC 8 9 10 11 12 13 associated with asynchronous (ripple clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if NC–No internal connection the enable input CTEN is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up D/U input. When D/U is low, the counter counts up and when D/U is high, it counts down. These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter will be dictated solely by the condition meeting the stable setup and hold times. These counters are fully programmable; that is, the outputs may each be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. The CLK, D/U, and LOAD inputs are buffered to lower the drive requirement, which significantly reduces the loading on, or current required by, clock drivers, etc., for long parallel words. Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (9 or 15) counting up. The ripple clock output produces a low-level output pulse under those same conditions but only while the clock input is low. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation. The SN54ALS190 and SN54ALS191 are characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS190 and SN74ALS191 are characterized for operation from 0°C to 70°C. Copyright 1986, Texas Instruments Incorporated 5BASIC PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS190, SN54ALS190 SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986 ’ALS190 logic symbol† 4 CTEN 5 D/U CLK 14 CTRDIV10 G1 2(CT=0)Z6 M2 (DOWN) 3(CT=9)Z6 M3 (UP) 1,2–/1,3+ 13 G4 LOAD A B C D 11 15 12 6,1,4 MAX/MIN RCO C5 1,5D 1 3 [1] 2 [2] 10 6 [4] 9 7 [8] QA QB QC QD ’ALS190 logic diagram (positive logic) 12 CTEN D/U CLK LOAD A 4 13 5 RCO 14 11 15 3 S C1 1D R B MAX/MIN QA 1 2 S C1 QB 1D R C 10 6 S C1 QC 1D R D 9 7 S C1 1D R † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, J, and N packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QD SN54ALS191, SN54ALS191 SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986 ’ALS191 logic symbol† 4 CTEN 5 D/U CLK LOAD A B C D 14 11 15 CTRDIV10 G1 M2 (DOWN) 2(CT=0)Z6 3(CT=9)Z6 M3 (UP) 12 1,2–/1,3+ G4 13 6,1,4 MAX/MIN RCO C5 5D 1 3 [1] 2 [2] 10 6 [4] 9 7 [8] QA QB QC QD ’ALS191 logic diagram (positive logic) 12 CTEN D/U CLK LOAD 13 5 11 3 S C1 1D R B RCO 14 15 A MAX/MIN 4 QA 1 2 S C1 QB 1D R C 10 6 S C1 QC 1D R D 9 7 S C1 QD 1D R † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, J, and N packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS190, SN54ALS190 SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986 typical load, count, and inhibit sequences ’ALS190 Illustrated below is the following sequence: 1. Load (preset) to BCD seven 2. Count up to eight, nine (maximum), zero, one, and two 3. Inhibit 4. Count down to one, zero (minimum), nine, eight, and seven LOAD A B Data Inputs C D CLOCK D/U CTEN QA QB QC QD MAX/MIN RCO 7 8 9 0 1 2 Count Up 2 Inhibit Load 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 1 0 9 Count Down 8 7 SN54ALS191, SN54ALS191 SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986 typical load, count, and inhibit sequences ’ALS191 Illustrated below is the following sequence: 1. Load (preset) to BCD seven 2. Count up to eight, nine (maximum), zero, one, and two 3. Inhibit 4. Count down to one, zero (minimum), nine, eight, and seven LOAD A B Data Inputs C D CLOCK D/U CTEN QA QB QC QD MAX/MIN RCO 7 8 9 0 1 2 Count Up 2 2 Inhibit 1 0 9 8 7 Count Down Load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALS190, SN54ALS191, SN74ALS190, SN74ALS191 SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range: SN54ALS190, SN54ALS191 . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS190, SN74ALS191 . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C recommended operating conditions SN54ALS190 SN54ALS191 VCC VIH Supply voltage VIL IOH Low-level input voltage IOL Low-level output current NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 tw Pulse duration tsu Hold time TA 0.8 – 0.4 – 0.4 mA 8 mA 4 Setup time tsu V 0.7 ’ALS190 0 20 0 25 ’ALS191 0 20 0 30 ’AS190 25 20 ‘AS191 20 16.5 LOAD low 25 20 Data before LOAD↑ 25 20 CTEN before CLK↑ 45 20 D/U before CLK↑ 45 20 LOAD inactive before CLK↑ 20 20 CLK high or low Data after LOAD↑ 5 5 CTEN after CLK↑ 0 0 D/U after CLK↑ 0 0 Operating free-air temperature V 2 High-level output current Clock frequency UNIT MIN High-level input voltage fclock SN74ALS190 SN74ALS191 – 55 125 V MHz ns ns ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VOL VCC = 4.5 V, VCC = 4.5 V, IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL CTEN OR CLK All others VCC = 5.5 V, SN54ALS190 SN54ALS191 MIN TYP† MAX SN74AAL190 SN74ALS191 MIN TYP† MAX – 1.5 VCC – 2 – 1.5 VCC – 2 0.25 VI = 0.4 V 0.5 UNIT V V 0.25 0.4 0.35 0.5 V 0.1 0.1 mA 20 20 µA – 0.2 – 0.2 – 0.1 – 0.1 mA IO‡ VCC = 5.5 V, VO = 2.25 V – 30 – 112 – 30 – 112 mA ICC VCC = 5.5 V, All inputs at 0 V 12 22 12 22 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS190, SN54ALS191, SN74ALS190, SN74ALS191 SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986 switching characteristics (see Note 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, PARAMETER FROM (INPUT) TO (OUTPUT) RL = 500 Ω, TA = MIN to MAX SN54ALS190 SN74ALS190 SN54ALS191 MIN fmax MAX SN74ALS191 MIN ’ALS190 20 25 ’ALS191 20 30 tPLH tPHL LOAD Any Q tPLH tPHL A, B, C, D Any Q tPLH tPHL CLK RCO tPLH tPHL CLK Any Q tPLH tPHL CLK MAX/MIN tPLH tPHL D/U RCO tPLH tPHL D/U MAX/MIN tPLH tPHL CTEN RCO UNIT MAX MHz 7 37 8 30 8 34 8 30 4 25 4 21 4 25 5 21 5 24 5 20 5 25 5 20 3 26 3 18 3 22 3 18 8 37 8 31 8 34 8 31 12 45 15 37 10 36 10 28 8 35 8 25 8 30 8 25 4 21 4 18 4 23 4 18 ns ns ns ns ns ns ns ns NOTE 1: Load circuit and voltage waveforms are shown in Section 1. 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