TI SN74AS373NSR

SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C – APRIL 1982 – REVISED MARCH 2002
SN54ALS373A, . . . J OR W PACKAGE
SN54AS373 . . . J PACKAGE
SN74ALS373A, SN74AS373 . . . DW, N, OR NS PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
description
These octal transparent D-type latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or a high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
interface or pullup components.
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
1D
1Q
SN54ALS373A, SN54AS373 . . . FK PACKAGE
(TOP VIEW)
2D
2Q
3Q
3D
4D
4
3
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
LE
5Q
5D
While the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
1
8Q
Eight Latches in a Single Package
3-State Bus-Driving True Outputs
Full Parallel Access for Loading
Buffered Control Inputs
pnp Inputs Reduce dc Loading on Data
Lines
OE
VCC
D
D
D
D
D
OE does not affect internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are off.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C – APRIL 1982 – REVISED MARCH 2002
ORDERING INFORMATION
PDIP – N
0°C to 70°C
Tube
SOIC – DW
SOP – NS
–55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SN74ALS373AN
SN74ALS373AN
SN74AS373N
SN74AS373N
Tube
SN74ALS373ADW
Tape and reel
SN74ALS373ADWR
Tube
SN74AS373DW
Tape and reel
SN74AS373DWR
Tape and reel
CDIP – J
Tube
CFP – W
Tube
LCCC – FK
TOP-SIDE
MARKING
Tube
ALS373A
AS373
SN74ALS373ANSR
ALS373A
SN74AS373NSR
74AS373
SNJ54ALS373AJ
SNJ54ALS373AJ
SNJ54AS373J
SNJ54AS373J
SNJ54ALS373AW
SNJ54ALS373AW
SNJ54ALS373AFK
SNJ54ALS373AFK
SNJ54AS373FK
SNJ54AS373FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
LE
1
11
C1
1D
3
1D
To Seven Other Channels
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2
1Q
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C – APRIL 1982 – REVISED MARCH 2002
absolute maximum ratings over operating free-air temperature range (SN54ALS373A,
SN74ALS373A) (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to any output in the high state or power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54ALS373A
SN74ALS373A
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.7
0.8
V
High-level output current
–1
–2.6
mA
IOL
TA
Low-level output current
24
mA
70
°C
High-level input voltage
2
2
V
12
Operating free-air temperature
–55
125
V
0
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ALS373A
MIN
MAX
SN74ALS373A
MIN
MAX
UNIT
fclock
tw
Clock frequency
Pulse duration, LE high
12
10
MHz
ns
tsu
th
Setup time, data before LE↓
10
10
ns
7
7
ns
Hold time, data after LE↓
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C – APRIL 1982 – REVISED MARCH 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = –18 mA
IOH = –0.4 mA
5V
VCC = 4
4.5
IOH = –1 mA
IOH = –2.6 mA
VOL
VCC = 4
4.5
5V
IOL = 12 mA
IOL = 24 mA
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.4 V
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
VOH
ICC
SN54ALS373A
TYP†
MAX
TEST CONDITIONS
VCC = 5.5 V
MIN
SN74ALS373A
TYP†
MAX
MIN
–1.5
VCC–2
2.4
–1.5
UNIT
V
VCC–2
V
3.3
2.4
0.25
–20
0.4
3.2
0.25
0.4
0.35
0.5
V
20
20
µA
–20
–20
µA
0.1
0.1
mA
20
20
µA
–0.1
–0.1
mA
–112
mA
–112
–30
Outputs high
9
16
9
16
Outputs low
16
25
16
25
mA
Outputs disabled
17
27
17
27
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX§
SN54ALS373A
tPLH
tPHL
D
Q
tPLH
tPHL
LE
A Q
Any
tPZH
tPZL
OE
A Q
Any
tPHZ
tPLZ
OE
Any Q
SN74ALS373A
MIN
MAX
MIN
MAX
2
17
2
12
1
19
4
16
6
29
6
22
1
27
7
23
6
22
1
18
5
24
5
20
2
16
1
10
2
24
2
12
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C – APRIL 1982 – REVISED MARCH 2002
absolute maximum ratings over operating free-air temperature range (SN54AS373, SN74AS373)
(unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to any output in the high state or power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 2: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54AS373
SN74AS373
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
0.8
V
High-level output current
–12
–15
mA
IOL
TA
Low-level output current
48
mA
70
°C
High-level input voltage
2
2
V
32
Operating free-air temperature
–55
125
V
0
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54AS373
MIN
fclock
tw
Clock frequency
tsu
th
MAX
SN74AS373
MIN
MAX
UNIT
MHz
Pulse duration, LE high
5.5*
4.5*
ns
Setup time, data before LE↓
2*
2*
ns
Hold time, data after LE↓
3*
3*
ns
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C – APRIL 1982 – REVISED MARCH 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = –18 mA
IOH = –2 mA
5V
VCC = 4
4.5
IOH = –12 mA
IOH = –15 mA
VOL
VCC = 4
4.5
5V
IOL = 32 mA
IOL = 48 mA
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.4 V
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
VOH
ICC
SN54AS373
TYP†
MAX
TEST CONDITIONS
VCC = 5.5 V
MIN
SN74AS373
TYP†
MAX
MIN
–1.2
VCC–2
2.4
–1.2
UNIT
V
VCC–2
V
3.2
2.4
0.27
3.3
0.5
0.32
–0.02
–30
0.5
V
50
50
µA
–50
–50
µA
0.1
0.1
mA
20
20
µA
–0.5
mA
–112
mA
–0.5
–112
–0.02
–30
Outputs high
55
90
55
90
Outputs low
55
85
55
85
mA
Outputs disabled
65
100
65
100
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX§
SN54AS373
tPLH
tPHL
D
Q
tPLH
tPHL
LE
A Q
Any
tPZH
tPZL
OE
A Q
Any
tPHZ
tPLZ
OE
Any Q
SN74AS373
MIN
MAX
MIN
MAX
3
9
3.5
6
3
8
3.5
6
6.5
14.5
6.5
11.5
5
9
5
7.5
2
7.5
2
6.5
4.5
10.5
4.5
9.5
3
10
3
6.5
3
8
3
7
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C – APRIL 1982 – REVISED MARCH 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
tPHZ
1.3 V
1.3 V
0.3 V
tPHL
≈3.5 V
tPLH
VOL
0.3 V
VOH
1.3 V
3.5 V
Input
1.3 V
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
0.3 V
≈0 V
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
83020012A
ACTIVE
LCCC
FK
20
1
TBD
8302001RA
ACTIVE
CDIP
J
20
1
TBD
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
Call TI
N / A for Pkg Type
A42
N / A for Pkg Type
8302001SA
ACTIVE
CFP
W
20
1
TBD
JM38510/37203B2A
ACTIVE
LCCC
FK
20
1
TBD
JM38510/37203BRA
ACTIVE
CDIP
J
20
1
TBD
Call TI
N / A for Pkg Type
SN54ALS373AJ
ACTIVE
CDIP
J
20
1
TBD
Call TI
N / A for Pkg Type
SN54AS373J
ACTIVE
CDIP
J
20
1
TBD
Call TI
N / A for Pkg Type
SN74ALS373ADBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
SN74ALS373ADBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS373ADBRG4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS373ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS373ADWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS373ADWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS373ADWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS373ADWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS373ADWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS373AN
ACTIVE
PDIP
N
20
CU NIPDAU
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
20
Pb-Free
(RoHS)
TBD
Call TI
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS373AN3
OBSOLETE
PDIP
N
20
SN74ALS373ANE4
ACTIVE
PDIP
N
20
SN74ALS373ANSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS373ANSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS373ANSRG4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS373DW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS373DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS373DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS373DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS373DWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS373DWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS373N
ACTIVE
PDIP
N
20
CU NIPDAU
N / A for Pkg Type
20
Addendum-Page 1
Pb-Free
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AS373N3
OBSOLETE
PDIP
N
20
SN74AS373NE4
ACTIVE
PDIP
N
20
SN74AS373NSR
ACTIVE
SO
NS
20
SN74AS373NSRE4
ACTIVE
SO
NS
SN74AS373NSRG4
ACTIVE
SO
SNJ54ALS373AFK
ACTIVE
SNJ54ALS373AJ
ACTIVE
SNJ54ALS373AW
Lead/Ball Finish
MSL Peak Temp (3)
(RoHS)
TBD
Call TI
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LCCC
FK
20
1
TBD
CDIP
J
20
1
TBD
Call TI
N / A for Pkg Type
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
SNJ54AS373FK
ACTIVE
LCCC
FK
20
1
TBD
SNJ54AS373J
ACTIVE
CDIP
J
20
1
TBD
20
Call TI
POST-PLATE N / A for Pkg Type
POST-PLATE N / A for Pkg Type
Call TI
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
16-Jul-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74ALS373ADBR
DB
20
MLA
330
16
8.2
7.5
2.5
12
16
Q1
SN74ALS373ADWR
DW
20
MLA
330
24
10.8
13.0
2.7
12
24
Q1
SN74ALS373ANSR
NS
20
MLA
330
24
8.2
13.0
2.5
12
24
Q1
SN74AS373DWR
DW
20
MLA
330
24
10.8
13.0
2.7
12
24
Q1
SN74AS373NSR
NS
20
MLA
330
24
8.2
13.0
2.5
12
24
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74ALS373ADBR
DB
20
MLA
346.0
346.0
33.0
SN74ALS373ADWR
DW
20
MLA
333.2
333.2
31.75
SN74ALS373ANSR
NS
20
MLA
333.2
333.2
31.75
SN74AS373DWR
DW
20
MLA
333.2
333.2
31.75
SN74AS373NSR
NS
20
MLA
333.2
333.2
31.75
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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