SN74AS8003 DUAL 2-INPUT POSITIVE-NAND GATE SDAS305 – OCTOBER 1999 D PS PACKAGE (TOP VIEW) Packaged in Plastic Small-Outline Package 1A 1B 1Y GND description 1 8 2 7 3 6 4 5 VCC 2B 2A 2Y The SN74AS8003 device contains two independent 2-input positive-NAND gates. It performs the Boolean functions Y = A • B or Y= A + B in positive logic. The SN74AS8003 is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each gate) INPUTS OUTPUT Y A B H H L L X H X L H logic symbol† 1A 1B 2A 2B 1 3 & 2 6 5 7 1Y 2Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1A 1B 2A 2B 1 2 3 1Y 6 7 5 2Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AS8003 DUAL 2-INPUT POSITIVE-NAND GATE SDAS305 – OCTOBER 1999 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability. recommended operating conditions (see Note 1) MIN NOM MAX 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current –2 mA IOL TA Low-level output current 20 mA 70 °C High-level input voltage V 2 Operating free-air temperature V 0 NOTE 1: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = –2 mA VOL II VCC = 4.5 V, VCC = 5.5 V, IOL = 20 mA VI = 7 V IIH IIL IO§ VCC = 5.5 V, VCC = 5.5 V, VI = 2.7 V VI = 0.4 V VCC = 5.5 V, VCC = 5.5 V, VO = 2.25 V VI = 0 V ICCH ICCL MIN TYP‡ MAX UNIT –1.2 V VCC–2 V 0.35 –30 1 0.5 V 0.1 mA 20 µA –0.5 mA –112 mA 1.6 mA VCC = 5.5 V, VI = 4.5 V 3.5 8.7 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics over recommended operating conditions (unless otherwise noted) (see Figure 1) 2 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B Y POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MAX 1 4.5 1 4 UNIT ns SN74AS8003 DUAL 2-INPUT POSITIVE-NAND GATE SDAS305 – OCTOBER 1999 PARAMETER MEASUREMENT INFORMATION 7V RL = R1 = R2 VCC S1 500 Ω From Output Under Test Test Point CL = 50 pF (see Note A) From Output Under Test 500 Ω CL = 50 pF (see Note A) 3.5 V 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V Test Point CL = 50 pF (see Note A) LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS Timing Input 500 Ω From Output Under Test Test Point 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V 1.3 V 1.3 V 3.5 V Input 1.3 V 1.3 V 0.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ 1.3 V tPLH ≈3.5 V 0.3 V tPHL VOH In-Phase Output 1.3 V 1.3 V VOL tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL tPHZ tPHL VOH 1.3 V 0.3 V ≈0 V Out-of-Phase Output (see Note C) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS tPLH VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AS8003PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS8003PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS8003PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74AS8003PSR Package Package Pins Type Drawing SO PS 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.2 6.6 2.5 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AS8003PSR SO PS 8 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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