TI SN74AS821FN

SN54AS821, SN54AS822, SN74AS821, SN74AS822
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 – D2825, DECEMBER 1983 – REVISED JANUARY 1986
•
•
•
•
•
•
•
SN54AS821 . . . JT PACKAGE
SN74AS821 . . . DW OR NT PACKAGE
(TOP VIEW)
Functionally Equivalent to AMD’s AM29821
and AM29822
Provides Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
OC
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
Outputs Have Undershoot Protection
Circuitry
Powerup High-impedance State
Package Options Include Plastic Small
Outline Packages, Both Plastic and
Ceramic Chip Carriers, and Standard
Plastic and Ceramic 300-mil DIPs
Buffered Control Inputs to Reduce DC
Loading Effects
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
VCC
Dependable Texas Instruments Quality and
Reliability
description
These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports,
bidirectional bus drivers with parity, and working registers.
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock the Q outputs on
the ’AS821 will be true, and on the ’AS822 will be complementary to the data input.
A buffered output-control input can be used to place the ten outputs in either a normal logic state (high or low
levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a
bus-organized system without need for interface or pullup components. The output control (OC) does not affect
the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs
are in the high-impedance state.
The SN54AS’ family is characterized for operation over the full military temperature range of – 55°C to 125°C.
The SN74AS’ family is characterized for operation from 0°C to 70°C.
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
3Q
4Q
5Q
NC
6Q
7Q
8Q
1
24
2
23
3
22
4
21
5
20
6
19
7
8
18
17
9
16
10
15
11
14
12
13
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
CLK
3D
4D
5D
NC
6D
7D
8D
4
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
3Q
4Q
5Q
NC
6Q
7Q
8Q
9D
10D
GND
NC
CLK
10Q
9Q
4
5
9D
10D
GND
NC
CLK
10Q
9Q
3D
4D
5D
NC
6D
7D
8D
OC
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
GND
SN54AS822 . . . FK PACKAGE
SN74AS822 . . . FN PACKAGE
(TOP VIEW)
2D
1D
OC
NC
VCC
1Q
2Q
SN54AS822 . . . JT PACKAGE
SN74AS822 . . . DW OR NT PACKAGE
(TOP VIEW)
2D
1D
OC
NC
VCC
1Q
2Q
SN54AS821 . . . FK PACKAGE
SN74AS821 . . . FN PACKAGE
(TOP VIEW)
NC–No internal connection
Copyright  1986, Texas Instruments Incorporated
5BASIC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54AS821, SN74AS821
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 – D2825, DECEMBER 1983 – REVISED JANUARY 1986
’AS821 FUNCTION TABLE
(each flip-flop)
’AS821 logic diagram (positive logic)
OUTPUT
INPUTS
OC
CLK
D
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
H
X
X
Z
OC
CLK
2D
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
2
3
EN
C1
1D
23
22
21
20
19
18
17
16
15
14
3D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
4D
5D
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
6D
7D
8D
9D
10D
Pin numbers shown are for DW, JT, and NT packages.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
5Q
18
6Q
17
7Q
16
8Q
15
9Q
1D
C1
11
4Q
1D
C1
10
20
1D
C1
9
3Q
1D
C1
8
21
1D
C1
7
2Q
1D
C1
6
22
1D
C1
5
1Q
1D
C1
4
23
1D
C1
’AS821 logic symbol†
2
3
4
5
6
7
8
9
10
11
13
C1
1D
1
OC
13
CLK
1
1D
14
10Q
SN54AS822, SN74AS822
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 – D2825, DECEMBER 1983 – REVISED JANUARY 1986
’AS822 FUNCTION TABLE
(each flip-flop)
’AS822 logic diagram positive logic
OUTPUT
INPUTS
OC
CLK
D
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
H
X
X
Z
OC
CLK
1
13
C1
1D
2
’AS822 logic symbol†
1
OC
13
CLK
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
2
3
4
5
6
7
8
9
10
11
C1
2D
3
EN
C1
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
3D
4
4D
5D
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
6D
7D
8D
9D
10D
19
5Q
18
6Q
17
7Q
16
8Q
15
9Q
1D
C1
11
4Q
1D
C1
10
20
1D
C1
9
3Q
1D
C1
8
21
1D
C1
7
2Q
1D
C1
6
22
1D
C1
5
1Q
1D
C1
23
22
21
20
19
18
17
16
15
14
23
1D
14
10Q
1D
Pin numbers shown are for DW, JT, and NT packages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54AS821, SN54AS822, SN74AS821, SN74AS822
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 – D2825, DECEMBER 1983 – REVISED JANUARY 1986
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54AS821, SN54AS822 . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74AS821, SN74AS822 . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
recommended operating conditions
SN54AS821
SN74AS821
SN54AS822
SN74AS822
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
IOL
tw
Low-level output current
Pulse duration, CLK high or low
9
8
ns
tsu
th
Setup time, data before CLK↑
7
6
ns
Hold time, data after CLK↑
0
0
TA
Operating free-air temperature
High-level input voltage
2
2
High-level output current
V
0.8
0.8
V
– 24
– 24
mA
48
mA
32
–55
V
125
ns
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS821
PARAMETER
VIK
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 2 mA
VCC = 4.5 V,
VCC = 4.5 V,
IOH = – 15 mA
IOH = – 24 mA
VOL
VCC = 4.5 V,
VCC = 4.5 V,
IOL = 32 mA
IOL = 48 mA
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2. 7 V
VO = 0.4 V
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0 .4 V
VO= 2.25 V
VOH
’AS821
ICC
VCC = 5
5.5
5V
’AS822
SN74AS821
SN54AS822
MIN
TYP‡ MAX
SN74AS822
TYP‡ MAX
– 1.2
VCC – 2
2.4
– 1.2
VCC – 2
2.4
3.2
2
UNIT
MIN
3.2
V
V
2
0.25
0.5
0.35
– 30
0.5
V
µA
50
50
– 50
– 50
µA
0.1
0.1
mA
20
20
µA
– 0.5
– 0.5
mA
– 112
mA
– 112
– 30
Outputs high
55
88
55
88
Outputs low
68
109
68
109
Outputs disabled
70
113
70
113
Outputs high
55
88
55
88
Outputs low
68
109
68
109
Outputs disabled
70
113
70
mA
113
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54AS821, SN54AS822, SN74AS821, SN74AS822
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 – D2825, DECEMBER 1983 – REVISED JANUARY 1986
switching characteristics (see Note 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
PARAMETER
FROM
TO
(INPUT)
(OUTPUT)
tPLH
tPHL
CLK
Any Q
tPZH
tPZL
OC
Any Q
tPHZ
tPZL
OC
Any Q
R2 = 500 Ω,
TA = MIN to MAX†
SN54AS821
SN74AS821
SN54AS822
SN74AS822
MIN
MAX
MIN
3.5
9
3.5
7.5
3.5
11.5
3.5
10.5
4
12
4
11
4
13
4
12
2
10
2
8
2
10
2
8
UNIT
MAX
ns
ns
ns
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
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Copyright  1998, Texas Instruments Incorporated