SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES264C – APRIL 1999 – REVISED DECEMBER 1999 D D D D DOC (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V VCC Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC D D D D Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup / Pulldown Resistors Package Options Include Plastic Small-Outline (DW), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009. 3.2 TA = 25°C Process = Nominal – Output Voltage – V 2.8 2.4 VCC = 3.3 V 2.0 1.6 VCC = 2.5 V 1.2 0.8 OH VCC = 1.8 V 0.4 TA = 25°C Process = Nominal 2.4 2.0 1.6 1.2 0.8 V V OL – Output Voltage – V 2.8 VCC = 3.3 V 0.4 0 17 34 51 68 85 102 119 IOL – Output Current – mA 136 153 VCC = 2.5 V VCC = 1.8 V –160 –144 –128 –112 –96 170 –80 –64 –48 –32 –16 0 IOH – Output Current – mA Figure 1. Output Voltage vs Output Current This octal bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVCH245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PRODUCT PREVIEW description SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES264C – APRIL 1999 – REVISED DECEMBER 1999 description (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVCH245 is characterized for operation from –40°C to 85°C. terminal assignments DGV, DW, OR PW PACKAGE (TOP VIEW) PRODUCT PREVIEW DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 FUNCTION TABLE (each transceiver) INPUTS 2 OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES264C – APRIL 1999 – REVISED DECEMBER 1999 logic symbol† 19 OE 1 DIR 2 A1 G3 3 EN1 [BA] 3 EN2 [AB] 18 1 B1 2 A2 A3 A4 A5 A6 A7 A8 3 17 4 16 5 15 6 14 7 13 8 12 9 11 B2 B3 B4 B5 B6 B7 B8 PRODUCT PREVIEW † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) DIR 1 19 A1 OE 2 18 B1 To Seven Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES264C – APRIL 1999 – REVISED DECEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† PRODUCT PREVIEW Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Voltage range applied to any input/output when the output is in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any input/output when the output is in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES264C – APRIL 1999 – REVISED DECEMBER 1999 recommended operating conditions (see Note 4) VIH Supply voltage High-level input voltage MAX 1.4 3.6 Data retention only 1.2 VCC = 1.2 V VCC = 1.4 V to 1.6 V VCC 0.65 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0.65 × VCC VI VO IOHS IOLS Low-level input voltage Output voltage Static high-level high level output current† low level output current† Static low-level V 2 GND 0.35 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V Input voltage V 1.7 VCC = 1.2 V VCC = 1.4 V to 1.6 V VIL UNIT V 0.7 0.8 0 3.6 V Active state 0 3-state 0 VCC 3.6 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V –2 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V –8 –4 mA –12 VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V 2 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 8 4 mA 12 ∆t/∆v Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V TA Operating free-air temperature –40 85 °C † Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009. NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PRODUCT PREVIEW VCC MIN Operating SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES264C – APRIL 1999 – REVISED DECEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOHS = –100 µA IOHS = –2 mA, VOH IOHS = –4 mA, IOHS = –8 mA, IOHS = –12 mA, IOLS = 100 µA VOL II Control inputs PRODUCT PREVIEW IBHL‡ IBHH§ VIH = 0.91 V VIH = 1.07 V VIH = 1.7 V VIH = 2 V IOLS = 2 mA, IOLS = 4 mA, VIL = 0.49 V VIL = 0.57 V IOLS = 8 mA, IOLS = 12 mA, VIL = 0.7 V VIL = 0.8 V VI = VCC or GND VI = 0.57 V 1.65 V 1.2 2.3 V 1.75 3V 2.3 1.4 V 0.4 0.45 2.3 V 0.55 3V 0.7 3.6 V ±2.5 2.3 V 45 3V 75 VI = 1.07 V VI = 1.7 V 1.65 V –25 2.3 V –45 3V –75 1.95 V 200 2.7 V 300 3.6 V 500 1.95 V –200 2.7 V –300 3.6 V –500 VI or VO = 3.6 V VO = VCC or GND ICC VI = VCC or GND, Ci Control inputs VI = VCC or GND Cio A or B ports orts VO = VCC or GND IO = 0 UNIT V 1.65 V VI = 0.7 V VI = 0.8 V Ioff IOZ|| MAX 0.2 25 VI = 0 to VCC TYP† VCC–0.2 1.05 1.65 V VI = 0 to VCC IBHHO# 1.4 V MIN 1.4 V to 3.6 V VI = 2 V IBHLO¶ VCC 1.4 V to 3.6 V V µA µA µA µA µA 0 ±10 µA 3.6 V ±12.5 µA 3.6 V 40 µA 2.5 V 3.3 V 2.5 V pF pF F 3.3 V † Typical values are measured at TA = 25°C. ‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. § The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || For I/O ports, the parameter IOZ includes the input leakage current. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES264C – APRIL 1999 – REVISED DECEMBER 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5) VCC = 1.2 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) tpd A or B B or A ns ten OE A or B ns tdis OE A or B ns PARAMETER TYP MIN MAX MIN MAX MIN MAX MIN UNIT MAX operating characteristics, TA = 25°C PARAMETER Power dissipation capacitance Outputs enabled Outputs disabled CL = 0 0, VCC = 1.8 V TYP f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP UNIT pF PRODUCT PREVIEW Cpd d TEST CONDITIONS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES264C – APRIL 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.2 V AND 1.5 V ± 0.1 V 2 × VCC S1 2 kΩ From Output Under Test Open GND CL = 15 pF (see Note A) 2 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 PRODUCT PREVIEW VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.1 V VOL tPHZ VCC/2 VOH VOH – 0.1 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES264C – APRIL 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC VCC/2 0V 0V tsu VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH VCC/2 VCC VCC/2 tPLZ VCC VCC/2 tPZH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VOH Output Output Control (low-level enabling) tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 PRODUCT PREVIEW Timing Input VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES264C – APRIL 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 PRODUCT PREVIEW VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES264C – APRIL 1999 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V S1 500 Ω From Output Under Test 2 × VCC Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw LOAD CIRCUIT VCC VCC Timing Input Input VCC/2 VCC/2 0V VCC/2 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC Output Control (low-level enabling) VCC/2 Input VCC/2 VCC/2 0V tPLH 0V VCC/2 VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 tPLZ tPZL VCC PRODUCT PREVIEW VCC Data Input VCC/2 VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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