ETC SN74CBT162292DGVR

SN74CBT162292
12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS052E – MARCH 1998 – REVISED OCTOBER 2000
D
D
D
D
D
D
D
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of Texas Instruments’ Widebus
Family
TTL-Compatible Control Input Levels
Isolation Under Power-Off Conditions
Make-Before-Break Feature
Internal 500-Ω Pulldown Resistors to
Ground
A-Port Inputs/Outputs Have Equivalent
25-Ω Series Resistors, So No External
Resistors Are Required
Latch-Up Performance Exceeds 250 mA Per
JESD 17
S
1A
NC
2A
NC
3A
NC
GND
4A
NC
5A
NC
6A
NC
7A
NC
VCC
8A
GND
NC
9A
NC
10A
NC
11A
NC
12A
NC
description
The SN74CBT162292 is a 12-bit 1-of-2
high-speed TTL-compatible FET multiplexer/
demultiplexer. The low on-state resistance of the
switch allows connections to be made with
minimal propagation delay.
When the select (S) input is low, port A is
connected to port B1, and RINT is connected to
port B2. When S is high, port A is connected to port
B2, and RINT is connected to port B1.
The A-port inputs/outputs include equivalent 25-Ω
series resistors to reduce overshoot and
undershoot.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
NC
NC
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
NC – No internal connection
ORDERING INFORMATION
Tube
SN74CBT162292DL
Tape and reel
SN74CBT162292DLR
TSSOP – DGG
Tape and reel
SN74CBT162292DGGR
TVSOP – DGV
Tape and reel
SN74CBT162292DGVR
SSOP – DL
–40°C
40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
CBT162292
CBT162292
CY2292
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74CBT162292
12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS052E – MARCH 1998 – REVISED OCTOBER 2000
FUNCTION TABLE
INPUT
S
FUNCTION
L
A port = B1 port
RINT = B2 port
H
A port = B2 port
RINT = B1 port
logic diagram (positive logic)
2
54
1A
1B1
RINT
RINT
53
1B2
30
27
12B1
12A
RINT
RINT
29
12B2
1
S
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74CBT162292
12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS052E – MARCH 1998 – REVISED OCTOBER 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
5.5
VCC
VIH
Supply voltage
4
High-level control input voltage
2
VIL
TA
Low-level control input voltage
Operating free-air temperature
–40
UNIT
V
V
0.8
V
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
II
VCC = 4.5 V,
VCC = 5.5 V,
II = –18 mA
VI = VCC or GND
Ioff
ICC
VCC = 0,
VCC = 5.5 V,
VI or VO = 0 to 7 V
IO = 0,
VCC = 5.5 V,
VI = 3 V or 0
One input at 3.4 V,
VCC = 0,
VCC = 4 V,
TYP at VCC = 4 V
VO = 3 V or 0
∆ICC§
Ci
Cio
Control input
Control input
ron¶
VCC = 4.5 V
MIN
TYP‡
VI = VCC or GND
Other inputs at VCC or GND
MAX
UNIT
–1.2
V
±5
µA
10
µA
3
µA
2.5
mA
3.5
pF
8
pF
VI = 2.4 V,
II = 15 mA
38
55
VI = 0
II = 45 mA
II = 30 mA
39
63
37
55
Ω
VI = 2.4 V,
II = 15 mA
37
55
‡ All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74CBT162292
12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS052E – MARCH 1998 – REVISED OCTOBER 2000
switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
(unless otherwise noted) (see Figure 1)
PARAMETER
tpd†
ten
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
S
A or B
VCC = 4 V
VCC = 5 V
± 0.5 V
MIN
MIN
MAX
1.9
1
10.7
1
UNIT
MAX
1.85
ns
9.5
ns
tdis
S
A or B
1
10.9
1
9.7
ns
† The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
(unless otherwise noted) (see Figure 1)
PARAMETER
DESCRIPTION
VCC = 4 V
VCC = 5 V
± 0.5 V
MIN
MIN
MAX
tmbb‡
Make-before-break time
0
2
0
2
‡ The make-before-break time is the time interval between make and break, during the transition from one selected port to the other.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
ns
SN74CBT162292
12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS052E – MARCH 1998 – REVISED OCTOBER 2000
PARAMETER MEASUREMENT INFORMATION
7V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPZL/tPLZ
tPZH/tPHZ
Open
7V
Open
3V
Output
Control
LOAD CIRCUIT
1.5 V
1.5 V
0V
tPLZ
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
2.3 V
1.2 V
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 7 V
(see Note B)
1.2 V
2.3 V
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when connected to the internal
500-Ω pulldown resistor. Waveform 2 is for an output with internal conditions such that the output is high except when connected
to the internal 500-Ω pulldown resistor.
C. All pulse inputs and DC inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis. Z = RINT = 500 Ω.
F. tPZL and tPZH are the same as ten. Z = RINT = 500 Ω.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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Copyright  2000, Texas Instruments Incorporated