SN74CBTD1G384 SINGLE FET BUS SWITCH WITH LEVEL SHIFTING SCDS066J – JULY 1998 – REVISED JANUARY 2003 D D D DBV OR DCK PACKAGE (TOP VIEW) 5-Ω Switch Connection Between Two Ports TTL-Compatible Control Input Levels Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II A B GND description/ordering information 1 5 VCC 4 OE 2 3 The SN74CBTD1G384 features a single high-speed line switch. The switch is disabled when the output-enable (OE) input is high. A diode to VCC is integrated on the chip to allow for level shifting from 5-V signals at the device inputs to 3.3-V signals at the device outputs. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA 23) – DBV SOT (SOT (SOT-23) –40°C 40°C to 85°C SOT (SC-70) – DCK Reel of 3000 SN74CBTD1G384DBVR Reel of 250 SN74CBTD1G384DBVT Reel of 3000 SN74CBTD1G384DCKR Reel of 250 SN74CBTD1G384DCKT TOP-SIDE MARKING‡ P8D P8D_ P8 P8_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE INPUT OE FUNCTION L A port = B port H Disconnect logic diagram (positive logic) 1 2 A B 4 OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74CBTD1G384 SINGLE FET BUS SWITCH WITH LEVEL SHIFTING SCDS066J – JULY 1998 – REVISED JANUARY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL TA Low-level control input voltage High-level control input voltage MIN MAX 4.5 5.5 2 Operating free-air temperature –40 UNIT V V 0.8 V 85 °C In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no level-shifting effect. NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, See Figure 2 II = –18 mA II ICC VCC = 5.5 V, VCC = 5.5 V, VI = 5.5 V or GND IO = 0, VCC = 5.5 V, VI = 3 V or 0 One input at 3.4 V, Cio(OFF) VO = 3 V or 0, OE = VCC ron¶ VCC = 4.5 V ∆ICC§ Ci Control input Control input MIN TYP‡ VI = VCC or GND Other inputs at VCC or GND MAX UNIT –1.2 V ±1 µA 1.5 mA 2.5 mA 2 pF 3.5 pF VI = 0 II = 64 mA II = 30 mA 5 5 7 7 VI = 2.4 V, II = 15 mA 35 50 Ω ‡ All typical values are at VCC = 5 V, TA = 25°C. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. ¶ Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBTD1G384 SINGLE FET BUS SWITCH WITH LEVEL SHIFTING SCDS066J – JULY 1998 – REVISED JANUARY 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd† A or B B or A ten OE A or B MIN 2 MAX UNIT 0.25 ns 5.9 ns tdis A or B 1 4.7 ns OE † The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). PARAMETER MEASUREMENT INFORMATION 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω S1 tpd tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V Output Control (low-level enabling) LOAD CIRCUIT TEST 1.5 V 0V tPLZ tPZL 3V Input 1.5 V 1.5 V 0V tPLH 1.5 V 3.5 V 1.5 V 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOL tPHZ tPZH VOH Output Output Waveform 1 S1 at 7 V (see Note B) tPHL 1.5 V 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The output is measured with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74CBTD1G384 SINGLE FET BUS SWITCH WITH LEVEL SHIFTING SCDS066J – JULY 1998 – REVISED JANUARY 2003 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4 4 TA = 25°C 3.75 100 µA 3.75 3.5 6 mA 12 mA 3.5 100 µA 3.25 6 mA 12 mA 3 24 mA 3.25 VOH – Output Voltage High – V VOH – Output Voltage High – V TA = 85°C 24 mA 3 2.75 2.5 2.25 2 1.75 1.5 4.5 2.75 2.5 2.25 2 1.75 4.75 5 5.25 5.5 5.75 1.5 4.5 4.75 VCC – Supply Voltage – V 5 VCC – Supply Voltage – V OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4 TA = 0°C VOH – Output Voltage High – V 3.75 3.5 100 µA 3.25 6 mA 12 mA 3 24 mA 2.75 2.5 2.25 2 1.75 1.5 4.5 4.75 5 5.25 5.5 VCC – Supply Voltage – V Figure 2. VOH Values 4 5.25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5.75 5.5 5.75 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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