ETC SN74CBT16233DLR

SN74CBT16233
16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS010K – MAY 1995 – REVISED NOVEMBER 2001
D
D
D
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus  Family
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
1A
2B1
2B2
3A
4B1
4B2
5A
6B1
6B2
7A
8B1
8B2
GND
VCC
9A
10B1
10B2
11A
12B1
12B2
13A
14B1
14B2
15A
16B1
16B2
TEST1
TEST2
description
The SN74CBT16233 is a 16-bit 1-of-2 FET
multiplexer/demultiplexer used in applications in
which two separate data paths must be
multiplexed onto, or demultiplexed from, a single
path. This device can be used for memory
interleaving, where two different banks of memory
need to be addressed simultaneously. The device
can be used as two 8-bit to 16-bit multiplexers or
as one 16-bit to 32-bit multiplexer.
Two select (SEL1 and SEL2) inputs control the
data flow. When the TEST inputs are asserted, the
A port is connected to both the B1 and the B2
ports. SEL1, SEL2, and the TEST inputs can be
driven with a 5-V CMOS, a 5-V TTL, or a
low-voltage TTL driver.
This device is designed so it does not have
through current when switching directions.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1B1
1B2
2A
3B1
3B2
4A
5B1
5B2
6A
7B1
7B2
8A
GND
VCC
9B1
9B2
10A
11B1
11B2
12A
13B1
13B2
14A
15B1
15B2
16A
SEL1
SEL2
ORDERING INFORMATION
Tube
SN74CBT16233DL
Tape and reel
SN74CBT16233DLR
TSSOP – DGG
Tape and reel
SN74CBT16233DGGR
TVSOP – DGV
Tape and reel
SN74CBT16233DGVR
SSOP – DL
–40°C
40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
CBT16233
CBT16233
CY233
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74CBT16233
16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS010K – MAY 1995 – REVISED NOVEMBER 2001
FUNCTION TABLE
(each multiplexer/demultiplexer)
INPUTS
SEL
TEST
FUNCTION
L
L
A = B1
H
L
A = B2
X
H
A = B1 and A = B2
logic diagram (positive logic)
1A
1
56
1B1
9A
15
42
9B1
55
41
1B2
8A
45
11
8B1
9B2
16A
31
12
TEST1
16B1
26
8B2
SEL1
25
30
16B2
SEL2
27
TEST2
29
28
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
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SN74CBT16233
16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS010K – MAY 1995 – REVISED NOVEMBER 2001
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VIL
TA
Low-level control input voltage
High-level control input voltage
MIN
MAX
UNIT
4.75
5.25
V
2
Operating free-air temperature
–40
V
0.8
V
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
II
ICC
∆ICC‡
Control inputs
Ci
Control inputs
TEST CONDITIONS
VCC = 4.75 V,
VCC = 0,
II = –18 mA
VI = 5.25 V
VCC = 5.25 V,
VCC = 5.25 V,
VI = 5.25 V or GND
IO = 0,
VCC = 5.25 V,
VI = 3 V or 0
One input at 3.4 V,
Cio(OFF)
VO = 3 V or 0
ron§
VCC = 4.75 V
MIN
TYP†
VI = VCC or GND
Other inputs at VCC or GND
MAX
UNIT
–1.2
V
10
µA
±1
µA
3
µA
2.5
mA
4.5
pF
4
pF
VI = 0
II = 64 mA
II = 30 mA
5
5
7
7
VI = 2.4 V,
II = 15 mA
7
12
Ω
† All typical values are at VCC = 5 V, TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
§ Measured by the voltage drop between A and B terminals at the indicated current through the switch. On-state resistance is determined by the
lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd¶
A or B
B or A
tpd
SEL
A
ten
tdis
TEST or SEL
TEST or SEL
MIN
MAX
UNIT
0.25
ns
1.6
5.3
ns
B
1.3
5.2
ns
B
1
5.3
ns
¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
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3
SN74CBT16233
16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS010K – MAY 1995 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
3V
Output
Control
LOAD CIRCUIT
1.5 V
1.5 V
0V
tPLZ
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
3.5 V
1.5 V
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 7 V
(see Note B)
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
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Copyright  2001, Texas Instruments Incorporated