SN74LVC1G06 www.ti.com SCES295V – JUNE 2000 – REVISED NOVEMBER 2012 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT Check for Samples: SN74LVC1G06 FEATURES 1 • 2 • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Input and Open-Drain Output Accept Voltages up to 5.5 V Max tpd of 4 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V • • DBV PACKAGE (TOP VIEW) N.C. 1 5 2 GND 3 VCC N.C. Y 2 3 YZP PACKAGE (TOP VIEW) DNU A1 A2 A B1 B2 GND C1 C2 Y YZV PACKAGE (TOP VIEW) GND A1 B1 A2 B2 6 VCC A 2 5 N.C. GND 3 4 Y A 2 GND 3 5 VCC 4 Y DSF PACKAGE (TOP VIEW) N.C. A GND 1 6 2 5 3 4 VCC N.C. Y 1 2 A DNU VCC B A No ball C GND Y Table 2. YZV PACKAGE TERMINAL ASSIGNMENTS 1 2 A A VCC B GND Y VCC Y 1 Table 1. YZP PACKAGE TERMINAL ASSIGNMENTS VCC DNU – Do not use A 1 N.C. Y 4 DRY PACKAGE (TOP VIEW) N.C. N.C. – No internal connection See mechanical drawings for dimensions. VCC 5 1 GND 4 DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) A A Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2012, Texas Instruments Incorporated SN74LVC1G06 SCES295V – JUNE 2000 – REVISED NOVEMBER 2012 www.ti.com DESCRIPTION/ORDERING INFORMATION This single inverter buffer/driver is designed for 1.65-V to 5.5-V VCC operation. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. The output of the SN74LVC1G06 device is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA. This device is fully specified for partial-power-down applications using Ioff.The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (3) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) Reel of 3000 SN74LVC1G06YZPR _ _ _CT_ NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZV (Pb-free) Reel of 3000 SN74LVC1G06YZVR ____ CT Reel of 3000 SN74LVC1G06DBVR Reel of 250 SN74LVC1G06DBVT Reel of 3000 SN74LVC1G06DCKR Reel of 250 SN74LVC1G06DCKT SOT (SOT-23) – DBV –40°C to 85°C SOT (SC-70) – DCK C06_ CT_ Jumbo Tube of SN74LVC1G06DCKJ 10000 (1) (2) (3) SOT (SOT-553) – DRL Reel of 4000 SN74LVC1G06DRLR CT_ µQFN – DSF Reel of 5000 SN74LVC1G06DSFR CT QFN – DRY Reel of 5000 SN74LVC1G06DRYR CT Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). YZV: The actual top-side marking is on two lines. Line 1 has four characters to denote year, month, day, and assembly/test site. Line 2 has two characters which show the family and function code. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Table 3. FUNCTION TABLE INPUT A OUTPUT Y H L L Z LOGIC DIAGRAM (POSITIVE LOGIC) DBV, DCK, DSF, DRY, DRL, and YZP PACKAGE A 2 4 Y YZV PACKAGE A 2 2 4 Y Submit Documentation Feedback Copyright © 2000–2012, Texas Instruments Incorporated Product Folder Links: SN74LVC1G06 SN74LVC1G06 www.ti.com SCES295V – JUNE 2000 – REVISED NOVEMBER 2012 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) –0.5 6.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA (3) Continuous current through VCC or GND Package thermal impedance (4) θJA DBV package 206 DCK package 252 DRL package 142 YZP package 132 YZV package 123 DSF package 300 DRY package Tstg (1) (2) (3) (4) °C/W 234 Storage temperature range –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 1.65 5.5 1.5 VCC = 1.65 V to 1.95 V VIH MIN VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V V 2 0.7 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage V 0.65 × VCC VCC = 4.5 V to 5.5 V VIL UNIT 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V V 0.3 × VCC VI Input voltage 0 5.5 V VO Output voltage 0 5.5 V VCC = 1.65 V 4 VCC = 2.3 V IOL Low-level output current Δt/Δv Input transition rise or fall rate 8 16 VCC = 3 V VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V TA (1) Operating free-air temperature mA 24 ns/V 5 –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2000–2012, Texas Instruments Incorporated Product Folder Links: SN74LVC1G06 3 SN74LVC1G06 SCES295V – JUNE 2000 – REVISED NOVEMBER 2012 www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOL = 100 μA VOL 1.65 V to 5.5 V 0.1 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 32 mA V 0.55 4.5 V VI = 5.5 V or GND UNIT 0.4 3V IOL = 24 mA A input MAX IOL = 4 mA IOL = 16 mA II MIN TYP (1) VCC 0.55 0 to 5.5 V ±1 μA 0 ±10 μA 1.65 V to 5.5 V 10 μA 3 V to 5.5 V 500 μA Ioff VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND 3.3 V 4 pF Co VO = VCC or GND 3.3 V 5 pF (1) All typical values are at VCC = 3.3 V, TA = 25°C. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) A Y tpd VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2.2 6.5 1.1 4 1.2 4 1 3 ns Operating Characteristics TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 3 3 4 6 Submit Documentation Feedback UNIT pF Copyright © 2000–2012, Texas Instruments Incorporated Product Folder Links: SN74LVC1G06 SN74LVC1G06 www.ti.com SCES295V – JUNE 2000 – REVISED NOVEMBER 2012 PARAMETER MEASUREMENT INFORMATION (OPEN DRAIN) VLOAD S1 RL From Output Under Test Open TEST GND RL CL (see Note A) S1 tPZL (see Notes E and F) VLOAD tPLZ (see Notes E and G) VLOAD tPHZ/tPZH VLOAD LOAD CIRCUIT INPUT VCC VI 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VM tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns VCC VCC 3V VCC VLOAD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC CL RL V∆ 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu th VI VM Input VM VM VM Data Input 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VM VOL tPHL tPLZ VLOAD/2 VM tPZH VOH Output VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM tPZL VOH VM VI Output Control tPHL tPLH Output VI VM VOL VOL tPHZ Output Waveform 2 S1 at VLOAD (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VM VLOAD/2 − V∆ VLOAD/2 ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VM. G. tPLZ is measured at VOL + V∆. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2000–2012, Texas Instruments Incorporated Product Folder Links: SN74LVC1G06 5 SN74LVC1G06 SCES295V – JUNE 2000 – REVISED NOVEMBER 2012 www.ti.com REVISION HISTORY Changes from Revision U (June 2011) to Revision V • 6 Page Added Jumbo Reel to ORDERING INFORMATION TABLE. ............................................................................................... 2 Submit Documentation Feedback Copyright © 2000–2012, Texas Instruments Incorporated Product Folder Links: SN74LVC1G06 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) SN74LVC1G06DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C065 ~ C06F ~ C06R ~ C06T) SN74LVC1G06DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C065 ~ C06F ~ C06R ~ C06T) SN74LVC1G06DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C065 ~ C06F ~ C06R ~ C06T) SN74LVC1G06DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C065 ~ C06F ~ C06R) SN74LVC1G06DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C065 ~ C06F ~ C06R) SN74LVC1G06DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C065 ~ C06F ~ C06R) SN74LVC1G06DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CT5 ~ CTF ~ CTK ~ CTR ~ CTT) SN74LVC1G06DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CT5 ~ CTF ~ CTK ~ CTR ~ CTT) SN74LVC1G06DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CT5 ~ CTF ~ CTK ~ CTR ~ CTT) SN74LVC1G06DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CT5 ~ CTF ~ CTK ~ CTR) SN74LVC1G06DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CT5 ~ CTF ~ CTK ~ CTR) SN74LVC1G06DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CT5 ~ CTF ~ CTK ~ CTR) SN74LVC1G06DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CT7 ~ CTR) SN74LVC1G06DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CT7 ~ CTR) SN74LVC1G06DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CT SN74LVC1G06DSFR ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CT SN74LVC1G06YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 (CT7 ~ CTN) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Orderable Device Status (1) SN74LVC1G06YZVR ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YZV 4 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) SNAGCU Level-1-260C-UNLIM (4) -40 to 85 CT (7 ~ N) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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OTHER QUALIFIED VERSIONS OF SN74LVC1G06 : • Enhanced Product: SN74LVC1G06-EP NOTE: Qualified Version Definitions: Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G06DBVR SOT-23 DBV 5 3000 178.0 9.0 3.17 1.37 4.0 8.0 Q3 SN74LVC1G06DBVR SOT-23 DBV 5 3000 178.0 9.2 SN74LVC1G06DBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.55 4.0 8.0 Q3 3.23 3.17 1.37 4.0 8.0 SN74LVC1G06DBVT SOT-23 DBV 5 250 178.0 9.2 Q3 3.3 3.2 1.55 4.0 8.0 SN74LVC1G06DCKR SC70 DCK 5 3000 178.0 Q3 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SN74LVC1G06DCKR SC70 DCK 5 3000 SN74LVC1G06DCKR SC70 DCK 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 178.0 9.0 2.4 2.5 1.2 4.0 8.0 SN74LVC1G06DCKT SC70 DCK 5 Q3 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 SN74LVC1G06DCKT SC70 DCK SN74LVC1G06DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 SN74LVC1G06DRLR SOT Q3 DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3 3.23 W Pin1 (mm) Quadrant SN74LVC1G06DRLR SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SN74LVC1G06DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 SN74LVC1G06DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 SN74LVC1G06YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 SN74LVC1G06YZVR DSBGA YZV 4 3000 178.0 9.2 1.0 1.0 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G06DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G06DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G06DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G06DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G06DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G06DCKR SC70 DCK 5 3000 205.0 200.0 33.0 SN74LVC1G06DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G06DCKT SC70 DCK 5 250 205.0 200.0 33.0 SN74LVC1G06DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G06DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G06DRLR SOT DRL 5 4000 180.0 180.0 30.0 SN74LVC1G06DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74LVC1G06DRYR SON DRY 6 5000 180.0 180.0 30.0 SN74LVC1G06DSFR SON DSF 6 5000 180.0 180.0 30.0 SN74LVC1G06YZPR DSBGA YZP 5 3000 220.0 220.0 35.0 SN74LVC1G06YZVR DSBGA YZV 4 3000 220.0 220.0 35.0 Pack Materials-Page 2 D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.858 mm D: Max = 0.918 mm, Min =0.858 mm E: Max = 0.918 mm, Min =0.858 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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