TI SN74LVC1G3157DRYR

SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F – JANUARY 2003 – REVISED FEBRUARY 2007
FEATURES
•
•
•
•
•
•
•
•
1.65-V to 5.5-V VCC Operation
Useful for Both Analog and Digital
Applications
Specified Break-Before-Make Switching
Rail-to-Rail Signal Handling
High Degree of Linearity
High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
•
DBV PACKAGE
(TOP VIEW)
B2
DCK PACKAGE
(TOP VIEW)
GND
2
5
VCC
B1
3
4
A
1
6
S
GND
2
5
VCC
B1
3
4
A
DRY PACKAGE
(TOP VIEW)
B2
1
DRL PACKAGE
(TOP VIEW)
B2
S
6
1
Low On-State Resistance, Typically ≈6 Ω
(VCC = 4.5 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
6
S
GND
2
5
VCC
B1
3
4
A
B2
1
6
S
GND
2
5
VCC
B1
3
4
A
YZP PACKAGE
(BOTTOM VIEW)
B1
3 4
GND
2 5
B2
1 6
A
VCC
S
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single-pole, double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes of
up to VCC (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING (2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74LVC1G3157YZPR
_ _ _ C5_
SON – DRY
Reel of 5000
SN74LVC1G3157DRYR
C5_
SOT (SOT-23) – DBV
Reel of 3000
SN74LVC1G3157DBVR
CC5_
SOT (SC-70) – DCK
Reel of 3000
SN74LVC1G3157DCKR
C5_
SOT (SOT-553) – DRL
Reel of 4000
SN74LVC1G3157DRLR
C5_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F – JANUARY 2003 – REVISED FEBRUARY 2007
FUNCTION TABLE
CONTROL
INPUT
S
ON
CHANNEL
L
B1
H
B2
LOGIC DIAGRAM (POSITIVE LOGIC)
1
B2
4
6
S
B1
A
3
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range (2)
–0.5
6.5
V
VIN
Control input voltage range (2) (3)
–0.5
6.5
V
VI/O
Switch I/O voltage range (2) (3) (4) (5)
–0.5
VCC + 0.5
V
IIK
Control input clamp current
VIN < 0
–50
mA
IIOK
I/O port diode current
VI/O < 0 or VI/O > VCC
±50
mA
II/O
On-state switch current (6)
VI/O = 0 to VCC
±128
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal
impedance (7)
DBV package
165
DCK package
259
DRL package
142
DRY package
234
YZP package
Tstg
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2
Storage temperature range
UNIT
°C/W
123
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground unless otherwise specified.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 5.5 V maximum.
VI, VO, VA, and VBn are used to denote specific conditions for VI/O.
II, IO, IA, and IBn are used to denote specific conditions for II/O.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F – JANUARY 2003 – REVISED FEBRUARY 2007
Recommended Operating Conditions
(1)
MIN
MAX
UNIT
VCC
1.65
5.5
V
VI/O
0
VCC
V
VIN
0
5.5
V
VIH
High-level input voltage, control input
VIL
Low-level input voltage, control input
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
VCC × 0.75
VCC = 1.65 V to 1.95 V
V
VCC × 0.7
VCC = 2.3 V to 5.5 V
VCC × 0.25
VCC = 1.65 V to 1.95 V
VCC = 1.65 V to 1.95 V
20
VCC = 2.3 V to 2.7 V
20
VCC = 3 V to 3.6 V
10
VCC = 4.5 V to 5.5 V
(1)
V
VCC × 0.3
VCC = 2.3 V to 5.5 V
ns/V
10
–40
°C
85
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
On-state switch resistance (2)
ron
rrange
Difference of on-state
resistance between
switches (2) (4) (5)
∆ron
ron(flat)
(1)
(2)
(3)
(4)
(5)
(6)
On-state switch resistance
over signal range (2) (3)
ON resistance flatness (2) (4) (6)
TEST CONDITIONS
See Figure 1 and
Figure 2
VI = 0 V
IO = 4 mA
VI = 1.65 V
IO = –4 mA
VI = 0 V
IO = 8 mA
VI = 2.3 V
IO = –8 mA
VI = 0 V
IO = 24 mA
VI = 3 V
IO = –24 mA
VI = 0 V
IO = 30 mA
VI = 2.4 V
IO = –30 mA
VI = 4.5 V
IO = –30 mA
0 ≤ VBn ≤ VCC
1.65 V
2.3 V
3V
4.5 V
MIN
TYP (1)
MAX
11
20
15
50
8
12
11
30
7
9
9
20
6
7
7
12
7
UNIT
Ω
15
IA = –4 mA
1.65 V
140
IA = –8 mA
2.3 V
45
IA = –24 mA
3V
18
IA = –30 mA
4.5 V
10
VBn = 1.15
V
IA = –4 mA
1.65 V
0.5
VBn = 1.6 V
IA = –8 mA
2.3 V
0.1
VBn = 2.1 V
IA = –24 mA
3V
0.1
VBn = 3.15
V
IA = –30 mA
4.5 V
0.1
IA = –4 mA
1.65 V
110
IA = –8 mA
2.3 V
26
IA = –24 mA
3V
9
IA = –30 mA
4.5 V
4
0 ≤ VBn ≤ VCC
(see Figure 1 and Figure 2)
See Figure 1
VCC
Ω
Ω
Ω
TA = 25°C
Measured by the voltage drop between I/O pins at the indicated current through the switch. ON resistance is determined by the lower of
the voltages on the two (A or B) ports.
Specified by design
∆ron = ron(max) – ron(min) measured at identical VCC, temperature, and voltage levels
This parameter is characterized, but not tested in production.
Flatness is defined as the difference between the maximum and minimum values of ON resistance over the specified range of
conditions.
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3
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F – JANUARY 2003 – REVISED FEBRUARY 2007
Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
MIN
TYP (1)
MAX
±0.05
±1 (1)
±1
UNIT
Ioff (7)
Off-state switch leakage
current
0 ≤ VI, VO ≤ VCC
(see Figure 3 )
IS(on)
On-state switch leakage
current
VI = VCC or GND, VO = Open
(see Figure 4)
5.5 V
IIN
Control input current
0 ≤ VIN≤ VCC
0 V to
5.5 V
±0.05
ICC
Supply current
VIN = VCC or GND
5.5 V
1
∆ICC
Supply-current change
VIN = VCC – 0.6 V
5.5 V
Cin
Control input
capacitance
S
5V
2.7
pF
Cio(off)
Switch input/ouput
capacitance
Bn
5V
5.2
pF
Cio(on)
Switch input/ouput
capacitance
(7)
4
TEST CONDITIONS
Bn
1.65 V to
5.5 V
5V
A
Ioff is the same as IS(off) (off-state switch leakage current).
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±1
±0.1 (1)
±1
17.3
17.3
±1 (1)
µA
µA
µA
10
µA
500
µA
pF
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F – JANUARY 2003 – REVISED FEBRUARY 2007
Analog Switch Characteristics
TA = 25°C
PARAMETER
Frequency
response (1)
(switch on)
Crosstalk (2)
(between
switches)
Feed-through
attenuation (2)
(switch off)
Charge injection (3)
Total harmonic
distortion
(1)
(2)
(3)
FROM
(INPUT)
A or Bn
B1 or B2
A or Bn
S
A or Bn
TO
(OUTPUT)
Bn or A
B2 or B1
TEST CONDITIONS
RL = 50 Ω,
fin = sine wave
(see Figure 6 )
RL = 50 Ω,
fin = 10 MHz (sine wave)
(see Figure 7 )
Bn or A
CL = 5 pF, RL = 50 Ω,
fin = 10 MHz (sine wave)
(see Figure 8 )
A
CL = 0.1 nF, RL = 1 MΩ
(see Figure 9 )
Bn or A
VI = 0.5 Vp-p, RL = 600 Ω,
fin = 600 Hz to 20 kHz (sine wave)
(see Figure 10 )
VCC
TYP
1.65 V
300
2.3 V
300
3V
300
4.5 V
300
1.65 V
–54
2.3 V
–54
3V
–54
4.5 V
–54
1.65 V
–57
2.3 V
–57
3V
–57
4.5 V
–57
3.3 V
3
5V
7
1.65 V
0.1
2.3 V
0.025
3V
0.015
4.5 V
0.01
UNIT
MHz
dB
dB
pC
%
Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
Adjust fin voltage to obtain 0 dBm at input.
Specified by design
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5 and Figure 11)
PARAMETER
tpd (1)
ten
tB-M (4)
(2)
(3)
(4)
TO
(OUTPUT)
A or Bn
Bn or A
S
Bn
(2)
tdis (3)
(1)
FROM
(INPUT)
VCC = 1.8 V
± 0.15 V
MIN
VCC = 2.5 V
± 0.2 V
MAX
MIN
2
MAX
VCC = 3.3 V
± 0.3 V
MIN
1.2
MAX
VCC = 5 V
± 0.5 V
MIN
0.8
0.3
7
24
3.5
14
2.5
7.6
1.7
5.7
3
13
2
7.5
1.5
5.3
0.8
3.8
0.5
0.5
0.5
0.5
UNIT
MAX
ns
ns
ns
tpd is the slower of tPLH or tPHL. The propagation delay is calculated RC time constant of the typical on-state resistance of the switch and
the specified load capacitance when driven by an ideal voltage source (zero output impedance).
ten is the slower of tPZL or tPZH.
tdis is the slower of tPLZ or tPHZ.
Specified by design
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F – JANUARY 2003 – REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION
ron =
VI – VO
Figure 1. On-State Resistance Test Circuit
120
VCC = 1.65 V
100
ron
80
60
40
VCC = 2.3 V
20
VCC = 3 V
VCC = 4.5 V
0
0
1
2
3
4
5
VI - V
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
6
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IO
Ω
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F – JANUARY 2003 – REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Off-State Switch Leakage-Current Test Circuit
VCC
S
VIL or VIH
SW
VCC
B1
VI
1
VIL
2
VIH
1
SW
B2
S
2
VO
VO = Open
A
A
GND
VI = VCC or GND
Figure 4. On-State Switch Leakage-Current Test Circuit
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F – JANUARY 2003 – REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
VCC
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
50 pF
50 pF
50 pF
50 pF
500 W
500 W
500 W
500 W
0.3 V
0.3 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
8
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F – JANUARY 2003 – REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
50 Ω
RL = 50 Ω
Figure 6. Frequency Response (Switch On)
S
VCC
VIL or VIH
TEST CONDITION
VIL
20log10(VO2/VI)
VIH
20log10(VO1/VI)
VCC
S
B1
VB1
fin
VB2
A
Analyzer
B2
GND
50 Ω
RL
RL = 50 Ω
Figure 7. Crosstalk (Between Switches)
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F – JANUARY 2003 – REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
50 Ω
RL = 50 Ω
Figure 8. Feedthrough
VCC
VCC
S
B1
LOGIC
INPUT
1
SW
B2
VOUT
2
RGEN
VGE
A
GND
RL
CL
RL/CL = 1 MΩ/100 pF
LOGIC
INPUT
OFF
VOUT
ON
OFF
∆VOUT
Q = (∆VOUT) (CL)
Figure 9. Charge-Injection Test
10
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F – JANUARY 2003 – REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
10 kΩ
600 Ω
Figure 10. Total Harmonic Distortion
VCC
VCC
S
B1
VI = VCC/2
B2
VO
A
GND
VS
RL
CL
RL/CL = 50 Ω/35 pF
VO
0.9 x VO
tD
Figure 11. Break-Before-Make Internal Timing
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11
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74LVC1G3157DBVRE4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74LVC1G3157DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74LVC1G3157DCKRE4
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74LVC1G3157DCKRG4
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74LVC1G3157DRLRG4
ACTIVE
SOT
DRL
6
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74LVC1G3157DRYRG4
ACTIVE
SON
DRY
6
5000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G3157DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G3157DCKR
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G3157DGVR
PREVIEW
SOT-23
DBV
6
SN74LVC1G3157DRLR
ACTIVE
SOT
DRL
6
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G3157DRYR
ACTIVE
SON
DRY
6
5000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G3157YZPR
ACTIVE
DSBGA
YZP
6
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2009
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G3157 :
• Automotive: SN74LVC1G3157-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SN74LVC1G3157DBVR
SOT-23
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DBV
6
3000
180.0
9.2
3.23
3.17
1.37
4.0
8.0
Q3
SN74LVC1G3157DBVR
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
SN74LVC1G3157DCKR
SC70
DCK
6
3000
180.0
8.4
2.24
2.34
1.22
4.0
8.0
Q3
SN74LVC1G3157DCKR
SC70
DCK
6
3000
180.0
9.2
2.24
2.34
1.22
4.0
8.0
Q3
SN74LVC1G3157DRLR
SOT
DRL
6
4000
180.0
9.2
1.78
1.78
0.69
4.0
8.0
Q3
SN74LVC1G3157DRYR
SON
DRY
6
5000
179.0
8.4
1.2
1.65
0.7
4.0
8.0
Q1
SN74LVC1G3157YZPR
DSBGA
YZP
6
3000
180.0
8.4
1.02
1.52
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC1G3157DBVR
SOT-23
DBV
6
3000
205.0
200.0
33.0
SN74LVC1G3157DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
SN74LVC1G3157DCKR
SC70
DCK
6
3000
202.0
201.0
28.0
SN74LVC1G3157DCKR
SC70
DCK
6
3000
205.0
200.0
33.0
SN74LVC1G3157DRLR
SOT
DRL
6
4000
202.0
201.0
28.0
SN74LVC1G3157DRYR
SON
DRY
6
5000
203.0
203.0
35.0
SN74LVC1G3157YZPR
DSBGA
YZP
6
3000
220.0
220.0
34.0
Pack Materials-Page 2
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