SN74LVC2GU04 DUAL INVERTER GATE SCES197J – APRIL 1999 – REVISED FEBRUARY 2003 D D D D D D D D D D D Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.7 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Unbuffered Outputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DBV OR DCK PACKAGE (TOP VIEW) 1A GND 2A 1 6 2 5 3 4 1Y VCC 2Y YEA, YEP, YZA, OR YZP PACKAGE (BOTTOM VIEW) 2A GND 1A 3 4 2 5 1 6 2Y VCC 1Y description/ordering information This dual inverter is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2GU04 contains two inverters with unbuffered outputs and performs the Boolean function Y = A. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA NanoStar – WCSP (DSBGA) 0.17-mm Small Bump – YEA NanoFree – WCSP (DSBGA) 0.17-mm Small Bump – YZA (Pb-free) NanoStar – WCSP (DSBGA) 0.23-mm Large Bump – YEP –40°C to 85°C SN74LVC2GU04YEAR SN74LVC2GU04YZAR Reel of 3000 _ _ _CD_ CD SN74LVC2GU04YEPR NanoFree – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) 23) – DBV SOT (SOT (SOT-23) TOP-SIDE MARKING‡ SN74LVC2GU04YZPR Reel of 3000 SN74LVC2GU04DBVR Reel of 250 SN74LVC2GU04DBVT CU4 CU4_ SN74LVC2GU04DCKR SOT (SC-70) (SC 70) – DCK Reel of 3000 SN74LVC2GU04DCKT CD CD_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVC2GU04 DUAL INVERTER GATE SCES197J – APRIL 1999 – REVISED FEBRUARY 2003 FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H logic diagram (positive logic) 1A 2A 1 6 3 4 1Y 2Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVC2GU04 DUAL INVERTER GATE SCES197J – APRIL 1999 – REVISED FEBRUARY 2003 recommended operating conditions (see Note 4) MIN MAX 1.65 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 5.5 V VO Output voltage 0 VCC –4 V IO = –100 mA IO = 100 mA High-level input voltage 0.75 × VCC V 0.25 × VCC VCC = 1.65 V VCC = 2.3 V IOH High-level output current VCC = 3 V mA –24 –32 4 VCC = 2.3 V Low-level output current V –8 –16 VCC = 4.5 V VCC = 1.65 V IOL V 8 mA 16 VCC = 3 V 24 VCC = 4.5 V 32 TA Operating free-air temperature –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 5.5 V IOH = –100 mA IOH = –4 mA VOH 1.65 V VCC–0.1 1.2 2.3 V 1.9 IOH = –8 mA IOH = –16 mA VIL = 0 V VIH= VCC A inputs VI = 5.5 V or GND VI = 5.5 V or GND, MAX V 3.8 IOL = 100 mA IOL = 4 mA 1.65 V to 5.5 V 0.1 1.65 V 0.45 IOL = 8 mA IOL = 16 mA 2.3 V 0.3 0.4 3V V 0.55 4.5 V IO = 0 UNIT 2.3 4.5 V IOL = 24 mA IOL = 32 mA II ICC TYP† 2.4 3V IOH = –24 mA IOH = –32 mA VOL MIN 0.55 0 to 5.5 V ±5 mA 1.65 V to 5.5 V 10 mA Ci VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. 3.3 V 7 pF switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 1.2 5.5 1 4 1.1 3.7 1 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 3 SN74LVC2GU04 DUAL INVERTER GATE SCES197J – APRIL 1999 – REVISED FEBRUARY 2003 operating characteristics, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V TYP VCC = 2.5 V TYP f = 10 MHz 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 VCC = 3.3 V TYP 8 VCC = 5 V TYP 23 UNIT pF SN74LVC2GU04 DUAL INVERTER GATE SCES197J – APRIL 1999 – REVISED FEBRUARY 2003 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH – V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MECHANICAL DATA MPDS026D – FEBRUARY 1997 – REVISED FEBRUARY 2002 DBV (R-PDSO-G6) PLASTIC SMALL-OUTLINE 0,95 6X 6 0,50 0,25 0,20 M 4 1,70 1,50 1 0,15 NOM 3,00 2,60 3 Gage Plane 3,00 2,80 0,25 0°–8° 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-5/G 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MPDS114 – FEBRUARY 2002 DCK (R-PDSO-G6) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 6 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0°–8° 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-3/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-203 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MXBG003A NOVEMBER 2001 – REVISED MAY 2002 YEA (R–XBGA–N6) DIE–SIZE BALL GRID ARRAY 0,50 A 0,95 0,85 B 0,25 C 1,45 1,35 1,00 B ÉÉ ÉÉ 0,50 A 1 2 PIN A1 INDEX AREA 6X 0,19 0,15 0,05 M C A B 0,05 M C 0,35 MAX 0,05 C 0,50 MAX SEATING PLANE 0,15 0,10 C 4203167–3/C 04/2002 NOTES: A. B. C. D. E. All linear dimensions are in millimeters. This drawing is subject to change without notice. NanoStar package configuration. Package complies to JEDEC MO–211 variation EA. This package is tin–lead (SnPb). Refer to the 6 YZA package (drawing 4204151) for lead–free. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MXBG005A – JANUARY 2002 – REVISED APRIL 2002 YZA (R-XBGA-N6) DIE-SIZE BALL GRID ARRAY 0,50 A 0,95 0,85 B 0,25 C 1,00 1,45 1,35 B 0,50 A 1 2 Pin A1 Index Area 6X 0,19 0,15 0,05 M C A B 0,05 M C 0,35 MAX 0,05 C 0,50 MAX Seating Plane 0,15 0,10 C 4204151-3/B 03/2002 NOTES: A. B. C. D. E. All linear dimensions are in millimeters. This drawing is subject to change without notice. NanoFree package configuration. Package complies to JEDEC MO-211 variation EA. This package is lead-free. Refer to the 6 YEA package (drawing 4203167) for tin-lead (SnPb). NanoFree is a trademark of Texas Instruments. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MXBG019 – OCTOBER 2002 YZP (R-XBGA-N6) DIE-SIZE BALL GRID ARRAY 0,50 A 0,95 0,85 B 0,25 C 1,00 1,45 1,35 B 0,50 A 1 2 Pin A1 Index Area 6X 0,25 0,20 0,05 M C A B 0,05 M C 0,05 C 0,50 Max Seating Plane 0,20 0,15 C 4204741-3/A 10/2002 NOTES: A. B. C. NOTES: D. All linear dimensions are in millimeters. This drawing is subject to change without notice. NanoFree package configuration. This package is lead-free. Refer to the 6 YEP package (drawing 4204725) for tin-lead (SnPb). NanoFree is a trademark of Texas Instruments. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MXBG022 – OCTOBER 2002 YEP (R-XBGA-N6) DIE-SIZE BALL GRID ARRAY 0,50 A 0,95 0,85 B 0,25 C 1,00 1,45 1,35 B 0,50 A 1 2 Pin A1 Index Area 6X 0,25 0,20 0,05 M C A B 0,05 M C 0,05 C 0,50 Max Seating Plane 0,20 0,15 C 4204725-3/A 10/2002 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. NanoFree package configuration. This package is tin-lead (SnPb). Refer to the 6 YZP package (drawing 420741) for lead-free. NanoFree is a trademark of Texas Instruments. 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