TI SN74LVCH16646A

SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318H – NOVEMBER 1993 – REVISED JUNE 1998
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Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
Power Off Disables Outputs, Permitting
Live Insertion
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit bus transceiver and register is
designed for 1.65-V to 3.6-V VCC operation.
DGG OR DL PACKAGE
(TOP VIEW)
1DIR
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OE
The SN74LVCH16646A can be used as two 8-bit
transceivers or one 16-bit transceiver. The device
consists of bus transceiver circuits, D-type
flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers.
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with the SN74LVCH16646A.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port can be stored in either register or in both. The select-control
(SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select
control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored
and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high),
A data can be stored in one register and/or B data can be stored in the other register.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318H – NOVEMBER 1993 – REVISED JUNE 1998
description (continued)
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The SN74LVCH16646A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
DATA I/O†
INPUTS
OPERATION OR FUNCTION
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
X
X
↑
X
X
X
Input
Unspecified
Store A, B unspecified{
X
X
X
↑
X
X
Unspecified
Input
Store B, A unspecified{
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input
Input
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B Bus
L
H
H or L
X
H
X
Input
Output
Stored A data to bus
† The data-output functions may be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
2
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SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
OE
L
DIR
L
CLKAB CLKBA
X
X
SAB
X
BUS B
BUS A
BUS A
BUS B
SCAS318H – NOVEMBER 1993 – REVISED JUNE 1998
SBA
L
OE
L
DIR
H
DIR
X
X
H
X
X
X
CLKAB CLKBA
↑
X
↑
X
↑
↑
SAB
L
SBA
X
BUS B
BUS A
BUS A
OE
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
CLKAB
X
SAB
SBA
X
X
X
X
X
X
STORAGE FROM
A, B, OR A AND B
OE
L
L
DIR
L
H
CLKAB
X
H or L
CLKBA
H or L
X
SAB
X
H
SBA
H
X
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
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3
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318H – NOVEMBER 1993 – REVISED JUNE 1998
logic symbol†
1OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
1A1
56
1
55
54
2
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
3
G7
29
28
30
31
27
26
G10
10 EN8 [BA]
10 EN9 [AB]
C11
G12
C13
G14
≥1
5
1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
7
1
2A3
2A4
2A5
2A6
2A7
2A8
≥1
7
51
49
9
48
10
47
12
45
13
44
14
43
15
16
≥1
8
1 14
12 11D
42
≥1
1B3
1B4
1B5
1B6
1B7
1B8
2B1
9
41
17
40
19
38
20
37
21
36
23
34
24
33
POST OFFICE BOX 655303
1B2
12 1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
1B1
2
8
13D 14
2A2
52
5 1
6D
6
4D
5
• DALLAS, TEXAS 75265
2B2
2B3
2B4
2B5
2B6
2B7
2B8
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318H – NOVEMBER 1993 – REVISED JUNE 1998
logic diagram (positive logic)
1OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
56
1
55
54
2
3
One of Eight Channels
1D
C1
1A1
5
52
1B1
1D
C1
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
To Seven Other Channels
29
28
30
31
27
26
One of Eight Channels
1D
C1
2A1
15
42
2B1
1D
C1
To Seven Other Channels
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5
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318H – NOVEMBER 1993 – REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input voltage range, VI: (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
VCC
Supply voltage
VIH
High-level input voltage
VIL
VI
VO
IOH
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
Input voltage
Output voltage
High level output current
High-level
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
MAX
3.6
1.5
UNIT
V
0.65 × VCC
V
1.7
2
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
Low-level input voltage
IOL
MIN
1.65
0.7
V
0.8
0
5.5
V
High or low state
0
3 state
0
VCC
5.5
V
VCC = 1.65 V
VCC = 2.3 V
–4
VCC = 2.7 V
VCC = 3 V
–12
–8
mA
–24
VCC = 1.65 V
VCC = 2.3 V
4
VCC = 2.7 V
VCC = 3 V
12
8
mA
24
0
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318H – NOVEMBER 1993 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –4 mA
1.65 V
VCC–0.2
1.2
2.3 V
1.7
2.7 V
2.2
3V
2.4
3V
2.2
IOH = –8 mA
VOH
12 mA
IOH = –12
IOH = –24 mA
IOL = 100 µA
VOL
II
Control inputs
A or B ports
0.2
0.45
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
3V
0.55
VI = 0 to 5.5 V
VI = 0.58 V
3.6 V
±5
Ioff
IOZ¶
VO = 0 to 5.5 V
ICC
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V#
Control inputs
Cio
A or B ports
µA
‡
45
23V
2.3
µA
–45
75
3V
–75
3..6 V
±500
0
±10
µA
3.6 V
±10
µA
IO = 0
20
36V
3.6
One input at VCC – 0.6 V,
Other inputs at
VCC or GND
VI = VCC or GND
V
‡
1 65 V
1.65
VI = 1.7 V
VI = 0.8 V
UNIT
V
1.65 V
VI or VO = 5.5 V
Ci
MAX
1.65 V to 3.6 V
VI = 2 V
VI = 0 to 3.6 V§
∆ICC
TYP†
IOL = 4 mA
IOL = 8 mA
VI = 1.07 V
VI = 0.7 V
II(hold)
(
)
MIN
VCC
1.65 V to 3.6 V
20
2.7 V to 3.6 V
500
3.3 V
VO = VCC or GND
3.3 V
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This information was not available at the time of publication.
§ This is the bus-hold maximum dynamic current required to switch the input from one state to another.
¶ For I/O ports, the parameter IOZ includes the input leakage current, but not II(hold).
# This applies in the disabled state only.
µA
µA
5
pF
8.5
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 2 through 4)
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
‡
VCC = 2.7 V
MIN
‡
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
UNIT
MAX
fclock
tw
Clock frequency
150
MHz
Pulse duration, CLK high or low
‡
‡
3.3
3.3
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
‡
‡
3.2
2.9
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
‡
‡
0
0.3
ns
‡ This information was not available at the time of publication.
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7
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318H – NOVEMBER 1993 – REVISED JUNE 1998
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
VCC = 1.8 V
± 0.15 V
MIN
fmax
tpd
VCC = 2.5 V
± 0.2 V
MAX
†
CLKAB or CLKBA
SAB or SBA
A or B
ten
tdis
OE
A or B
ten
tdis
DIR
A or B
MIN
MAX
†
VCC = 2.7 V
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
†
†
†
†
6.8
1.3
5.7
†
†
†
†
7.9
1.8
6.7
†
†
†
†
9.2
1.7
7.7
†
†
†
†
8.5
1.3
6.9
†
†
†
†
7.7
2.1
6.9
†
†
†
†
8.5
1.4
7.2
†
†
†
†
7.8
2
7
ns
ns
ns
† This information was not available at the time of publication.
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
per transceiver
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
TYP
†
†
60
†
†
12
Outputs enabled
Outputs disabled
f = 10 MHz
† This information was not available at the time of publication.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
pF
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318H – NOVEMBER 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1k Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1k Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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9
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318H – NOVEMBER 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS318H – NOVEMBER 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
Output
Control
(low-level
enabling)
2.7 V
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
0V
tPZL
2.7 V
Output
1.5 V
1.5 V
tsu
Input
1.5 V
Input
tPLZ
3V
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
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