SPT7820 10-BIT, 20 MSPS, TTL OUTPUT, A/D CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • • • Monolithic 20 MSPS Converter On-Chip Track/Hold Bipolar ±2.0 V Analog Input 60 dB SNR @ 1 MHz Input Low Power (1.0 W Typical) 5 pF Input Capacitance TTL Outputs Medical Imaging Professional Video Radar Receivers Instrumentation Electronic Warfare Digital Communications GENERAL DESCRIPTION The SPT7820 A/D converter is a 10-bit monolithic converter capable of word rates of a minimum of 20 MSPS. On board track/hold function assures excellent dynamic performance without the need for external components. Drive requirement problems are minimized with an input capacitance of only 5 pF. Inputs and outputs are TTL compatible to interface with TTL logic systems. An overrange output signal is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is very low at only 1.0 watt with power supply voltages of +5.0 and -5.2 volts. The SPT7820 also provides a wide input voltage swing of ±2.0 volts. The SPT7820 is available in 28-lead ceramic sidebrazed DIP, PDIP and SOIC packages over the commercial, industrial and military temperature ranges. Contact the factory for availability of die and /883 versions. BLOCK DIAGRAM Coarse A/D 4 Analog Prescaler AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA T/H Amplifier Bank Successive Interpolation Stage i Successive Interpolation Stage i+1 Successive Interpolation Stage N Decoding Network Analog Input Digital Output 10 ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages VCC ........................................................................... +6 V VEE ........................................................................... -6 V Output Digital Outputs ......................................... +30 to -30 mA Temperature Operating Temperature ............................ -55 to +125 °C Junction Temperature1 .............................................. +175 °C Lead Temperature, (soldering 10 seconds) ........ +300 °C Storage Temperature ................................ -65 to +150 °C Input Voltages Analog Input ............................................... VFB≤VIN≤VFT VFT, VFB .............................................................. +3.0 V, -3.0 V Reference Ladder Current ..................................... 12 mA CLK Input .................................................................. VCC Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=Tmin - Tmax, VCC=+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=20 MHz, 50% clock duty cycle, unless otherwise specified. PARAMETERS TEST CONDITIONS TEST LEVEL Resolution DC Accuracy (+25 °C) Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Bias Current Input Resistance Input Resistance Input Capacitance Input Bandwidth +FS Error -FS Error Reference Input Reference Ladder Resistance Reference Ladder Tempco Timing Characteristics Maximum Conversion Rate Overvoltage Recovery Time Pipeline Delay (Latency) Output Delay Aperture Delay Time Aperture Jitter Time Acquisition Time MIN SPT7820A TYP MAX 10 ±Full Scale 100 kHz Sample Rate VIN=0 V TA=-55 to +125 °C TA=-55 to +125 °C 3 dB Small Signal SPT7820B TYP MAX UNITS 10 V V VI ±1.0 ±0.5 Guaranteed V VI IV VI IV V V V V ±2.0 30 fCLK=1 MHz MIN Bits ±1.5 ±0.75 Guaranteed ±2.0 30 100 75 300 300 5 120 ±2.0 ±2.0 100 75 300 300 5 120 ±2.0 ±2.0 V 60 µA 75 µA kΩ kΩ pF MHz LSB LSB VI V 500 800 0.8 500 800 0.8 Ω Ω/°C VI V IV V V V V 20 20 MHz ns 14 1 5 20 1 Clock Cycle 18 ns ns ps-RMS ns 8.7 8.3 7.0 Bits Bits Bits 60 75 fCLK=1 MHz TA=+25 °C TA=+25 °C TA=+25 °C TA=+25 °C LSB LSB Dynamic Performance Effective Number of Bits fIN=1 MHz fIN=3.58 MHz fIN=10.0 MHz 20 20 14 1 5 20 9.2 8.8 7.5 1 18 Typical thermal impedances (unsoldered, in free air): 28L sidebrazed DIP: θja = 50 °C/W, 28L plastic DIP: θja = 50 °C/W, 28L SOIC: θja = 100 °C/W. SPT7820 2 3/11/97 ELECTRICAL SPECIFICATIONS TA=Tmin - Tmax, VCC=+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=20 MHz, 50% clock duty cycle, unless otherwise specified. PARAMETERS Dynamic Performance Signal-To-Noise Ratio (Without Harmonics) fIN=1 MHz fIN=3.58 MHz fIN=10.0 MHz Harmonic Distortion fIN=1 MHz fIN=3.58 MHz fIN=10.0 MHz TEST CONDITIONS Power Supply Requirements Voltages VCC DVCC -VEE Currents ICC DICC -IEE Power Dissipation Power Supply Rejection SPT7820A TYP MAX MIN SPT7820B TYP MAX UNITS I IV IV I IV IV I IV IV 57 55 52 56 54 52 50 47 43 60 58 55 58 56 54 53 50 46 54 52 49 53 51 49 47 44 40 57 55 52 55 53 51 49 46 42 dB dB dB dB dB dB dB dB dB TA=+25 °C TA=0-70, -25 to +85 °C TA=-55 to +125 °C* TA=+25 °C TA=0-70, -25 to +85 °C TA=-55 to +125 °C* TA=+25 °C TA=0-70, -25 to +85 °) TA=-55 to +125 °C* I IV IV I IV IV I IV IV 57 54 50 56 53 50 46 45 45 60 57 53 58 55 52 48 47 47 54 51 47 53 50 47 43 42 42 57 54 50 55 52 49 45 44 44 dB dB dB dB dB dB dB dB dB I IV IV I IV IV I IV IV V V V 55 52 48 54 51 48 44 43 41 57 52 49 45 51 48 45 41 40 38 54 dB dB dB dB dB dB dB dB dB dB VI VI I I IV IV 2.4 VI VI 2.4 IV IV IV I I I I V 4.75 4.75 -4.95 TA=+25 °C TA=0-70, -25 to +85 °C TA=-55 to +125 °C* fIN=3.58 MHz TA=+25 °C TA=0-70, -25 to +85 °C TA=-55 to +125 °C* fIN=10.0 MHz TA=+25 °C TA=0-70, -25 to +85 °C TA=-55 to +125 °C* Spurious Free Dynamic Range TA=+25 °C, fIN=1 MHz Differential Phase TA=+25 °C, fIN=3.58 & 4.35 MHz Differential Gain TA=+25 °C, fIN=3.58 & 4.35 MHz Digital Outputs Logic 1 Voltage Logic 0 Voltage MIN TA=+25 °C TA=0-70, -25 to +85 °C TA=-55 to +125 °C* TA=+25 °C TA=0-70, -25 to +85 °C TA=-55 to +125 °C* TA=+25 °C TA=0-70, -25 to +85 °C TA=-55 to +125 °C* Signal-to-Noise and Distortion fIN=1 MHz Digital Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Pulse Width Low (CLK) Pulse Width High (CLK) TEST LEVEL 55 47 67 0.2 0.5 52 44 67 0.2 0.7 Degree % fCLK=1 MHz TA=+25 °C TA=+25 °C 0 0 20 20 +5 +5 4.5 0.8 +20 +20 300 2.4 0 0 20 20 +5 +5 4.5 0.8 +20 +20 V V µA µA ns 300 ns fCLK=1 MHz TA=+25 °C TA=+25 °C TA=+25 °C TA=+25 °C (5 V ±0.25 V, -5.2 ±0.25 V) 2.4 V 0.6 V 0.6 5.0 -5.2 118 40 40 1.0 1.0 5.25 5.25 -5.45 145 55 57 1.3 4.75 4.75 -4.95 5.0 -5.2 118 40 40 1.0 1.0 5.25 5.25 -5.45 145 55 57 1.3 V V V mA mA mA W LSB *Temperature tested /883 only. SPT7820 3 3/11/97 TEST LEVEL TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characterization data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. Figure 1A: Timing Diagram A A A A A A A CLK Output Data AA A AA AA AA A N+1 N tpwH A A N-2 A AA N+2 tpwL td N-1 Data Valid N Data Valid N+1 Figure 1B: Single Event Clock CLK AA AA A AAAAAAAAAAAA AA A AAAAAAAAAAAA A AAAAAAAAAAAA td Output Data Data Valid Table I - Timing Parameters PARAMETERS DESCRIPTION MIN td CLK to Data Valid Prop Delay tpwH tpwL TYP MAX UNITS - 14 18 ns CLK High Pulse Width 20 - 300 ns CLK Low Pulse Width 20 - - ns SPT7820 4 3/11/97 TYPICAL PERFORMANCE CHARACTERISTICS THD vs Input Frequency SNR vs Input Frequency 80 70 70 Total Harmonic Distortion (dB) 80 Signal-to-Noise Ratio (dB) fs = 20 MSPS 60 50 40 30 20 fs = 20 MSPS 60 50 40 30 20 100 100 102 101 101 Input Frequency (MHz) Signal-to-Noise and Distortion (dB) SINAD vs Input Frequency 80 80 70 70 SNR, THD, SINAD (dB) fs =20 MSPS 60 50 40 30 60 50 20 40 20 102 101 A A A A A A A A SNR, THD, SINAD vs Sample Rate SNR, THD SINAD fIN = 1 MHz 30 100 102 Input Frequency (MHz) 100 Input Frequency (MHz) 101 102 Sample Rate (MSPS) SNR, THD, SINAD vs Temperature Spectral Response 65 0 fS = 20 MSPS fIN = 1 MHz SNR SNR SNR, THD, SINAD (dB) 60 Amplitude (dB) -30 -60 -90 THD THD 55 SINAD 50 fS = 20 MSPS fIN = 1 MHz 45 -120 40 0 1 2 3 4 5 6 7 8 9 10 Input Frequency (MHz) -25 0 +25 +50 +75 Temperature (°C) SPT7820 5 3/11/97 TYPICAL INTERFACE CIRCUIT device. The use of ground planes is recommended to achieve optimum device performance. DGND is needed for the DVCC return path (40 mA typical) and for the return path for all digital output logic interfaces. AGND and DGND should be separated from each other and connected together only at the device through a ferrite bead. The SPT7820 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7820 in normal circuit operation. The following section provides a description of the pin functions and outlines critical performance criteria to consider for achieving the optimal device performance. A Schottky or hot carrier diode connected between AGND and VEE is required. The use of separate power supplies between VCC and DVCC is not recommended due to potential power supply sequencing latch-up conditions. Using the recommended interface circuit shown in figure 2 will provide optimum device performance for the SPT7820. POWER SUPPLIES AND GROUNDING The SPT7820 requires -5.2 V and +5 V analog supply voltages. The +5 V supply is common to analog VCC and digital DVCC. A ferrite bead in series with each supply line is intended to reduce the transient noise injected into the analog VCC. These beads should be connected as closely as possible to the device. The connection between the beads and the SPT7820 should not be shared with any other device. Each power supply pin should be bypassed as closely as possible to the device. Use 0.1 µF for VEE and VCC, and 0.01 µF for DVCC (chip caps are preferred). VOLTAGE REFERENCE The SPT7820 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the voltage reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800 Ω. The +2.5 V voltage source for reference VFT must be current limited to 20 mA maximum if a different driving circuit is used in place of the recommended reference circuit shown in figures 2 and 3. In addition, there are three reference AGND and DGND are the two grounds available on the SPT7820. These two internal grounds are isolated on the Figure 2 - Typical Interface Circuit R1 CLK CLK 100 Ω ± 2.5 V Max VIN 6 5 + 10 kΩ Trim 1 µF C2 .01 µF 30 kΩ 2R C3 .01 µF + IC2 OP-07 8 +5 V - 5.2 V 2R D7 D6 D5 D4 D3 D2 4 D1 .01 µF 30 kΩ C4 .01 µF 2R D0 (LSB) VSB SUCCESSIVE INTERPOLATION STAGE # N 7 R 6 -2.5 V 1 µF + C5 .01 µF VFB VEE .01 µF D8 C6 .1 µF C8 C7 .1 µF C9 DGND 1 10 kΩ 2 SUCCESSIVE INTERPOLATION STAGE # 1 2R VRM DGND 3 ANALOG PRESCALER R VST DVCC GND VFT C1 .01 µF DVCC 4 +2.5 V VOUT (REF-03) D9 (MSB) VCC IC1 VIN AGND + AGND C19 1 µF VEE +5V D10 (Overrange) D I G IT A L O U 2 4 COARSE A/D VCC VIN (±2 V) DECODING NETWORK (TTL) C10 .01 µF C11 .01 µF Notes to prevent latch-up due to power sequencing: FB FB FB 1) D1 = Schottky or hot carrier diode, P/N IN5817. D1 2) FB = Ferrite bead, Fair Rite P/N 2743001111 10 µF to be mounted as close to the device as possible. The ferrite bead to the ADC connection should not be shared with any other device. 3) C1-C11 = Chip cap (recommended) mounted as close to the device's pin as possible. 4) Use of a separate supply for VCC and DVCC is not recommended. -5.2 V (Analog) 5) R1 provides current limiting to 45 mA. 6) C6, C7, C8 and C9 should be ten times larger than C10 and C11. 7) C8 = C9 = a 0.1 µF cap in parallel with a 4.7 µF cap. 10 µF + AGND + +5 V (Analog) DGND SPT7820 6 3/11/97 ladder taps (VST, VRM and VSB). VST is the sense for the top of the reference ladder (+2.0 V), VRM is the midpoint of the ladder (0.0 V typ) and VSB is the sense for the bottom of the reference ladder (-2.0 V). The voltages seen at VST and VSB are the true full scale input voltages of the device when VFT and VFB are driven to the recommended voltages (+2.5 V and -2.5 V typical respectively). These points should be used to monitor the actual full scale input voltage of the device and should not be driven to the expected ideal values as is commonly done with standard flash converters. When not being used, a decoupling capacitor of .01 µF (chip cap preferred) connected to AGND from each tap is recommended to minimize high frequency noise injection. ANALOG INPUT VIN is the analog input. The full scale input range will be 80% of the reference voltage or ±2 volts with VFB=-2.5 V and VFT=+2.5 V. The drive requirements for the analog inputs are minimal when compared to conventional Flash converters due to the SPT7820’s extremely low input capacitance of only 5 pF and very high input resistance of 300 kΩ. For example, for an input signal of ±2 V p-p with an input frequency of 10 MHz, the peak output current required for the driving circuit is only 628 µA. Figure 3 - Analog Equivalent Input Circuit CLOCK INPUT VCC Analog Prescaler VIN A A A A A The SPT7820 is driven from a single-ended TTL input (CLK). The CLK pulse width (tpwH) must be kept between 20 ns and 300 ns to ensure proper operation of the internal track-andhold amplifier. (See timing diagram.) When operating the SPT7820 at sampling rates above 3 MSPS, it is recommended that the clock input duty cycle be kept at 50% but performance will not be degraded if kept within the range of 40-60%. The analog input signal is latched on the rising edge of the CLK. VFT A A The clock input must be driven from fast TTL logic (VIH ≤4.5 V, TRISE <6 ns). In the event the clock is driven from a high current source, use a 100 Ω resistor in series to current limit to approximately 45 mA. VEE An example of a reference driver circuit recommended is shown in figure 2. IC1 is REF-03, the +2.5 V reference with a tolerance of 0.6% or +/- 0.015 V. The potentiometer R1 is 10 kΩ and supports a minimum adjustable range of up to 150 mV. IC2 is recommended to be an OP-07 or equivalent device. R2 and R3 must be matched to within 0.1% with good TC tracking to maintain a 0.3 LSB matching between VFT and VFB. If 0.1% matching is not met, then potentiometer R4 can be used to adjust the VFB voltage to the desired level. VFT and VFB should be adjusted such that VST and VSB are exactly +2.0 V and -2.0 V respectively. DIGITAL OUTPUTS The format of the output data (D0-D9) is straight binary. (See table II.) The outputs are latched on the rising edge of CLK with a propagation delay of 14 ns (typ). There is a one clock cycle latency between CLK and the valid output data. (See the timing diagram.) Table II - Output Data Information The analog input range will scale proportionally with respect to the reference voltage if a different input range is required. The maximum scaling factor for device operation is ± 20% of the recommended reference voltages of VFT and VFB. However, because the device is laser trimmed to optimize performance with ± 2.5 V references, the accuracy of the device will degrade if operated beyond a ± 2% range. ANALOG INPUT OVERRANGE D1O OUTPUT CODE D9-DO >+2.0 V + 1/2 LSB +2.0 V -1 LSB 1 O 11 1111 11 1111 0.0 V -2.0 V +1 LSB O O ØØ ØØØØ ØØØØ OO OOOO OOOØ <-2.0 V O OO OOOO OOOO 1111 111Ø (Ø indicates the flickering bit between logic 0 and 1). The following errors are defined: +FS error = top of ladder offset voltage = ∆(+FS -VST+1 LSB) -FS error = bottom of ladder offset voltage = ∆(-FS -VSB -1 LSB) where the +FS (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -FS input voltage is defined as the output transition between 0-00 and 0-01. The rise times and fall times of the digital outputs are not symmetrical. The propagation delay of the rise time is typically 14 ns and the fall time is typically 6 ns. (See figure 4.) The nonsymmetrical rise and fall times create approximately 8 ns of invalid data. SPT7820 7 3/11/97 Figure 4 - Digital Output Characteristics N CLK In N+1 2.4 V Rise Time 6 nsec 6 ns typ. 3.5 V Data Out (Actual) 2.4 V AAA AAA AAA AAA AAA (N-2) 0.8 V 0.5 V Data Out (Equivalent) Invalid Data (N-1) tpd1 (14 ns typ.) (N-2) Invalid Data (N-1) AA AA AA AA AA Invalid Data Invalid Data (N) (N-1) OVERRANGE OUTPUT EVALUATION BOARD The OVERRANGE OUTPUT (D10) is an indication that the analog input signal has exceeded the positive full scale input voltage by 1 LSB. When this condition occurs, D10 will switch to logic 1. All other data outputs (D0 to D9) will remain at logic 1 as long as D10 remains at logic 1. This feature makes it possible to include the SPT7820 into higher resolution systems. The EB7820 evaluation board is available to aid designers in demonstrating the full performance of the SPT7820. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note describing the operation of this board as well as information on the testing of the SPT7820 is also available. Contact the factory for price and availability. SPT7820 8 3/11/97 PACKAGE OUTLINES 28-Lead Sidebrazed 28 MILLIMETERS MIN MAX SYMBOL A 0.077 0.093 1.96 2.36 0.016 0.095 J B C D E F G H I J 0.020 0.105 .050 typ 0.060 0.235 1.412 0.605 0.012 0.620 0.41 2.41 0.00 1.02 5.46 35.26 14.86 0.23 15.24 0.51 2.67 1.27 1.52 5.97 35.86 15.37 0.30 15.75 I 1 INCHES MIN MAX H G A 0.040 0.215 1.388 0.585 0.009 0.600 E F C B D 28-Lead Plastic DIP K 28 SYMBOL A I 1 J H G A B F C D INCHES MIN MAX B C D E F G H I J K MILLIMETERS MIN MAX 0.200 0.120 0.170 0.135 0.020 0.100 0.067 0.013 0.180 0.622 0.555 1.460 0.085 5.08 3.05 4.32 3.43 0.51 2.54 1.70 0.33 4.57 15.80 14.10 37.08 2.16 E SPT7820 9 3/11/97 PACKAGE OUTLINES 28-Lead SOIC SYMBOL 28 I H INCHES MIN MAX MILLIMETERS MIN MAX A B C 0.696 0.004 0.712 0.012 .050 typ 17.68 0.10 0.00 18.08 0.30 1.27 D E F 0.014 0.009 0.080 0.019 0.012 0.100 0.36 0.23 2.03 0.48 0.30 2.54 G H I 0.016 0.394 0.291 0.050 0.419 0.299 0.41 10.01 7.39 1.27 10.64 7.59 1 A F B C D G E SPT7820 10 3/11/97 PIN ASSIGNMENTS PIN FUNCTIONS DGND 1 28 D0 2 27 V D1 3 26 AGND D2 4 25 V D3 5 24 V D4 6 23 V SB D5 7 22 V DVCC DIP/PDIP/SOIC FB RM 21 V D7 9 20 V ST D8 10 19 V D10 18 V DGND Digital Ground D0-D9 TTL Outputs (D0=LSB) D10 TTL Output Overrange CLK Clock VEE -5.2 V Supply (Analog) AGND Analog Ground VCC +5.0 V supply (Analog) VIN Analog Input DVCC Digital +5.0 V Supply VRM Middle of Voltage Reference Ladder VFT Force for Top of Reference Ladder VST Sense for Top of Reference Ladder VFB Force for Bottom of Reference Ladder VSB Sense for Bottom of Reference Ladder CC 8 11 Function EE D6 D9 Name IN FT CC 12 17 DGND 13 16 V DV CC 14 15 CLK AGND EE ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE TYPE SPT7820AIJ -25 to +85 °C 28L Sidebrazed DIP SPT7820BIJ SPT7820ACN SPT7820BCN -25 to +85 °C 0 to +70 °C 0 to +70 °C 28L Sidebrazed DIP 28L Plastic DIP 28L Plastic DIP SPT7820ACS 0 to +70 °C 28L SOIC SPT7820BCS SPT7820AMJ SPT7820BMJ 0 to +70 °C -55 to +125 °C -55 to +125 °C 28L SOIC 28L Sidebrazed DIP 28L Sidebrazed DIP SPT7820 11 3/11/97