SST25WF020A 2 Mbit 1.8V SPI Serial Flash Features • Single Voltage Read and Write Operations - 1.65-1.95V • Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 • High Speed Clock Frequency - 40MHz • Superior Reliability - Endurance: 100,000 Cycles - Greater than 20 years Data Retention • Ultra-Low Power Consumption: - Active Read Current: 4 mA (typical) - Standby Current: 10 µA (typical) - Power-down Mode Standby Current: 4 µA (typical) • Flexible Erase Capability - Uniform 4 KByte sectors - Uniform 64 KByte overlay blocks • Page Program Mode - 256 Bytes/Page • Fast Erase and Page-Program: - Chip-Erase Time: 300 ms (typical) - Sector-Erase Time: 40 ms (typical) - Block-Erase Time: 80 ms (typical) - Page-Program Time: 3 ms/ 256 bytes (typical) • End-of-Write Detection - Software polling the BUSY bit in Status Register • Hold Pin (HOLD#) - Suspend a serial sequence without deselecting the device • Write Protection (WP#) - Enables/Disables the Lock-Down function of the status register • Software Write Protection - Write protection through Block-Protection bits in status register • Temperature Range - Industrial: -40°C to +85°C 2013 Microchip Technology Inc. • Packages Available - 8-lead SOIC (150 mils) - 8-contact USON (2mm x 3mm) • All devices are RoHS compliant Product Description SST25WF020A is a member of the Serial Flash 25 Series family and feature a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. SPI serial flash memory is manufactured with proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. This Serial Flash significantly improve performance and reliability, while lowering power consumption. The device writes (Program or Erase) with a single power supply of 1.65-1.95V. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. SST25WF020A is offered in 8-lead SOIC and 8-contact USON packages. See Figure 2-1 for the pin assignments. Preliminary DS21392A-page 1 SST25WF020A 1.0 FUNCTIONAL BLOCK DIAGRAM SuperFlash Memory X - Decoder Address Buffers and Latches Y - Decoder I/O Buffers and Data Latches Control Logic Serial Interface CE# SCK SI SO WP# HOLD# 25139 F01.0 FIGURE 1-1: DS21392A-page 2 FUNCTIONAL BLOCK DIAGRAM Preliminary 2013 Microchip Technology Inc. SST25WF020A 2.0 PIN DESCRIPTION CE# 1 8 VDD SO 2 7 HOLD# WP# 3 6 SCK VSS 4 5 SI CE# 1 SO 2 Top View 7 HOLD# 3 6 SCK VSS 4 5 SI 25139 08-uson Q3A P1.0 8-Lead SOIC TABLE 2-1: VDD WP# 25139 08-soic-P0.0 FIGURE 2-1: 8 8-Contact USON PIN ASSIGNMENTS PIN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the input/output timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. The device is deselected and placed in Standby mode when CE# is high. WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI Flash memory while device is selected. VDD Power Supply To provide power supply voltage: 1.65-1.95V for SST25WF020A VSS Ground 2013 Microchip Technology Inc. Preliminary DS21392A-page 3 SST25WF020A 3.0 MEMORY ORGANIZATION The SST25WF020A SuperFlash memory arrays are organized in 64 uniform 4 KByte sectors, with four 64 KByte overlay erasable blocks. Top of Memory Block 63 03FFFFH 03F000H ... Number of Sectors ... Number of 64 KByte Blocks 3 030FFFH 030000H ... 01FFFFH 01F000H ... ... 31 ... ... 48 1 01FFFFH 010000H 00FFFFH 00F000H 16 ... ... 15 0 001FFFH 001000H 000FFFH 000000H 1 0 Bottom of Memory Block 25139 F51.0 FIGURE 3-1: 4.0 MEMORY MAP DEVICE OPERATION The SST25WF020A supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 4-1, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal. SST25WF020A is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). CE# SCK MODE 3 MODE 3 MODE 0 MODE 0 SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB SO HIGH IMPEDANCE DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB FIGURE 4-1: DS21392A-page 4 25139 F03.0 SPI PROTOCOL Preliminary 2013 Microchip Technology Inc. SST25WF020A 4.0.1 HOLD In the hold mode, serial sequences underway with the SPI Flash memory are paused without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The Hold mode ends when the rising edge of the HOLD# signal coincides with the SCK active low state. HOLD# must not rise or fall when SCK logic level is high. See Figure 4-2 for Hold Condition waveform. Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH. If CE# is driven active high during a Hold condition, the device returns to standby mode. The device can then be re-initiated with the command sequences listed in Table 5-1. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 4-2 for Hold timing. SCK HOLD# Active Hold Active 25139 F05.1 FIGURE 4-2: 4.1 HOLD CONDITION WAVEFORM Write Protection SST25WF020A provides software Write protection. The Write Protect pin (WP#) enables or disables the lockdown function of the status register. The Block-Protection bits (BP0, BP1, TB, and BPL) in the status register 4.1.1 provide Write protection to the memory array and the status register. See Table 4-3 for the Block-Protection description. WRITE PROTECT PIN (WP#) The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write- TABLE 4-1: Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 4-1). When WP# is high, the lock-down function of the BPL bit is disabled. CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION WP# BPL Execute WRSR Instruction L 1 Not Allowed L 0 Allowed H X Allowed 2013 Microchip Technology Inc. Preliminary DS21392A-page 5 SST25WF020A 4.2 Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the Memory Write protection. TABLE 4-2: During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4-2 describes the function of each bit in the software status register. SOFTWARE STATUS REGISTER Default at Power-up Read/Write 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 0 R WEL 1 = Device is memory Write enabled 0 = Device is not memory Write enabled 0 R 2 BP01 Indicate current level of block write protection (See Table 4-3) 0 or 1 R/W 3 BP11 Indicate current level of block write protection (See Table 4-3) 0 or 1 R/W 4 RES Reserved for future use 0 N/A 5 TB1 1 = 1/4 or 1/2 Bottom Memory Blocks are protected (See Table 4-3) 0 = 1/2 or 1/4 Top Memory Blocks are protected 0 or 1 R/W 6 RES Reserved for future use 0 N/A 7 BPL1 1 = BP0, BP1, TB, and BPL are read-only bits 0 = BP0, BP1, TB, and BPL are read/writable 0 or 1 R/W Bit Name Function 0 BUSY 1 1. BP0, BP1, TB, and BPL bits are non-volatile memory bits. 4.2.1 BUSY (BIT 0) The Busy bit determines whether there is an internal Erase or Program operation in progress. A ‘1’ for the Busy bit indicates the device is busy with an operation in progress. A ‘0’ indicates the device is ready for the next valid operation. 4.2.2 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is ‘0’. Chip-Erase can only be executed if Block-Protection bits are all ‘0’. BP0 and BP1 select the protected area and TB allocates the protected area to the higher-order address area (Top Blocks) or lowerorder address area (Bottom Blocks). WRITE ENABLE LATCH (WEL–BIT 1) The Write-Enable-Latch bit indicates the status of the internal Write-Enable-Latch memory. If the WEL bit is set to ‘1’, it indicates the device is Write enabled. If the bit is set to ‘0’ (reset), it indicates the device is not Write enabled and does not accept any Write (Program/ Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: • • • • • • • Power-up Write-Disable (WRDI) instruction completion Page-Program instruction completion Sector-Erase instruction completion 64 KByte Block-Erase instruction completion Chip-Erase instruction completion Write-Status-Register instruction completion 4.2.3 BLOCK-PROTECTION (BP0, BP1, AND TB–BITS 2, 3, AND 5) The Block-Protection (BP0, BP1, and TB) bits define the size of the memory area to be software protected against any memory Write (Program or Erase) operation, see Table 4-3. The Write-Status-Register (WRSR) instruction is used to program the BP0, BP1, and TB DS21392A-page 6 Preliminary 2013 Microchip Technology Inc. SST25WF020A 4.2.4 BLOCK PROTECTION LOCK-DOWN (BPL–BIT 7) BP1, TB, and BPL bits. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is ‘Don’t Care’. When the WP# pin is driven low (VIL), it enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to ‘1’, it prevents any further alteration of the BP0, TABLE 4-3: SOFTWARE STATUS REGISTER BLOCK PROTECTION Status Register Bit Protection Level TB BP1 BP0 0 (Full Memory Array unprotected) X 0 0 None T1 (1/4 Top Memory Block protected) 0 0 1 030000H-03FFFFH T2 (1/2 Top Memory Block protected) 0 1 0 020000H-03FFFFH B1 (1/4 Bottom Memory Block protected) 1 0 1 000000H-00FFFFH B2 (1/2 Bottom Memory Block protected) 1 1 0 000000H-01FFFFH 3 (Full Memory Array protected) X 1 1 000000H-03FFFFH 2013 Microchip Technology Inc. Preliminary Protected Memory Address DS21392A-page 7 SST25WF020A 5.0 INSTRUCTIONS Instructions are used to read, write (Erase and Program), and configure the SST25WF020A devices. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-Enable (WREN) instruction must be executed prior to SectorErase, Block-Erase, Page-Program, Write-Status-Register, or Chip-Erase instructions. The complete instructions are provided in Table 5-1. All instructions are synchronized off a high-to-low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with TABLE 5-1: the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. DEVICE OPERATION INSTRUCTIONS Address Dummy Data Maximum Cycle(s)2 Cycle(s) Cycle(s) Frequency Instruction Description Op Code Cycle1 Read Read Memory 0000 0011b (03H) 3 0 1 to ∞ 25 MHz High-Speed Read Read Memory at Higher Speed 0000 1011b (0BH) 3 1 1 to ∞ 40 MHz 4 KByte SectorErase3 Erase 4 KByte of memory array 0010 0000b (20H) 1101 0111b (D7H) 3 0 0 64 KByte BlockErase4 Erase 64 KByte block of memory array 1101 1000b (D8H) 3 0 0 Chip-Erase Erase Full Memory Array 0110 0000b (60H) or 1100 0111b (C7H) 0 0 0 Page-Program To program up to 256 Bytes 0000 0010b (02H) 3 0 1 to 256 RDSR5 Read-Status-Register 0000 0101b (05H) 0 0 1 to ∞ WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 WREN Write-Enable 0000 0110b (06H) 0 0 0 0 0 0 WRDI Write-Disable 0000 0100b (04H) RDID6, 7 Read-ID 1010 1011b (ABH) 3 0 1 to ∞ JEDEC-ID JEDEC ID Read 1001 1111b (9FH) 0 0 4 to ∞ DPD Deep Power-Down Mode 1011 1001b (B9H) 0 0 0 RDPD7 Release from Deep PowerDown or Read ID 1010 1011b (ABH) 0 0 0 1. 2. 3. 4. 5. 6. One bus cycle is eight clock periods. Address bits above the most significant bit of each density can be VIL or VIH. 4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH. 64 KByte Block-Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. Device ID is read after three dummy address bytes. The Device ID output stream is continuous until terminated by a low-tohigh transition on CE#. 7. The instructions Release from Deep Power down and Read-ID are similar instructions (ABH). Executing Read-ID requires the ABH instruction, followed by 24 dummy address bits to retrieve the Device ID. Release from Deep Power-Down only requires the instruction ABH. DS21392A-page 8 Preliminary 2013 Microchip Technology Inc. SST25WF020A 5.1 Read (25 MHz) The Read instruction, 03H, supports up to 25 MHz Read. The device outputs a data stream starting from the specified address location. The data stream is continuous through all addresses until terminated by a lowto-high transition on CE#. The internal address pointer automatically increments until the highest memory address is reached. Once the highest memory address is reached, the address pointer automatically incre- ments to the beginning (wrap-around) of the address space. For example, for 2 Mbit density, once the data from the address location 3FFFFH is read, the next output is from address location 000000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits A23-A0. CE# must remain active low for the duration of the Read cycle. See Figure 5-1 for the Read sequence. CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 23 24 15 16 31 32 39 40 47 48 55 56 63 64 70 MODE 0 ADD. 03 SI ADD. ADD. MSB MSB N DOUT HIGH IMPEDANCE SO N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT MSB 25139 F06.0 FIGURE 5-1: 5.2 READ SEQUENCE High-Speed-Read (40 MHz) The High-Speed-Read instruction supporting up to 40 MHz Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-Speed-Read cycle. See Figure 5-2 for the HighSpeed-Read sequence. through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space. For example, for 2 Mbit density, once the data from address location 3FFFFH is read, the next output will be from address location 000000H. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80 MODE 0 0B SI ADD. ADD. ADD. X MSB N DOUT HIGH IMPEDANCE SO N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT MSB 25139 F07.0 FIGURE 5-2: HIGH-SPEED-READ SEQUENCE 2013 Microchip Technology Inc. Preliminary DS21392A-page 9 SST25WF020A 5.3 Page-Program The Page-Program instruction programs up to 256 Bytes of data in the memory. The data for the selected page address must be in the erased state (FFH) before initiating the Page-Program operation. A Page-Program applied to a protected memory area will be ignored. Prior to the program operation, execute the WREN instruction. the internal, self-timed, Page-Program operation. See Figure 5-3 for the Page-Program sequence and Figure 6-8 for the Page-Program flow chart. When executing Page-Program, the memory range for the SST25WF020A is divided into 256-Byte page boundaries. The device handles the shifting of more than 256 Bytes of data by maintaining the last 256 Bytes as the correct data to be programmed. If the target address for the Page-Program instruction is not the beginning of the page boundary (A[7:0] are not all zero), and the number of bytes of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be programmed at the start of that target page. To execute a Page-Program operation, the host drives CE# low, then sends the Page-Program command cycle (02H), three address cycles, followed by the data to be programmed, and then drives CE# high. The programmed data must be between 1 to 256 Bytes and in whole byte increments; sending less than a full byte will cause the partial byte to be ignored. Poll the BUSY bit in the Status register, or wait TPP, for the completion of CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 23 24 15 16 31 32 39 MODE 0 SI ADD. 02 MSB SO ADD. ADD. Data Byte 0 LSB MSB LSB MSB LSB HIGH IMPEDANCE 2079 2078 2077 2076 2075 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 CE#(cont’) SCK(cont’) SI(cont’) Data Byte 1 MSB SO(cont’) Data Byte 255 Data Byte 2 LSB MSB LSB MSB LSB HIGH IMPEDANCE 25139 F60.1 FIGURE 5-3: DS21392A-page 10 PAGE-PROGRAM SEQUENCE Preliminary 2013 Microchip Technology Inc. SST25WF020A 5.4 Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H or D7H, followed by address bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE# must be driven high before the instruction is executed. Poll the BUSY bit in the Software Status register, or wait TSE, for the completion of the internal self-timed Sector-Erase cycle. See Figure 5-4 for the Sector-Erase sequence and Figure 6-9 for the flow chart. CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 23 24 15 16 31 MODE 0 MSB ADD. ADD. 20 or D7 SI ADD. MSB SO HIGH IMPEDANCE 2539 F13.0 FIGURE 5-4: 5.5 SECTOR-ERASE SEQUENCE 64-KByte Block-Erase The 64-KByte Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. Applying this instruction to a protected memory area results in the instruction being ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. Initiate the 64-Byte Block-Erase instruction by executing an 8-bit command, D8H, followed by address bits [A23-A0]. Address bits [AMS-A16] (AMS = Most Significant Address) determine the block address (BAX), remaining address bits can be VIL or VIH. CE# must be driven high before executing the instruction. Poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase cycle. See Figure 5-5 for the 64-KByte Block-Erase sequences and Figure 6-9 for the flow chart. CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 D8 SI MSB SO 15 16 23 24 31 MODE 0 ADDR ADDR ADDR MSB HIGH IMPEDANCE 25139 F15.0 FIGURE 5-5: 64-KBYTE BLOCK-ERASE SEQUENCE 2013 Microchip Technology Inc. Preliminary DS21392A-page 11 SST25WF020A 5.6 Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction is ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. Initiate the Chip- Erase instruction by executing an 8-bit command, 60H or C7H. CE# must be driven high before the instruction is executed. Poll the BUSY bit in the Software Status register, or wait TCE, for the completion of the internal selftimed Chip-Erase cycle. See Figure 5-6 for the ChipErase sequence and Figure 6-10 for the flow chart. CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 60 or C7 SI MSB SO HIGH IMPEDANCE 25139 F16.0 FIGURE 5-6: 5.7 CHIP-ERASE SEQUENCE Read-Status-Register (RDSR) The Read-Status-Register (RDSR) instruction, 05H, allows reading of the status register. The status register may be read at any time even during a Write (Program/ Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 5-7 for the RDSR instruction sequence. CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MODE 0 05 SI MSB SO HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out 25139 F17.0 FIGURE 5-7: DS21392A-page 12 READ-STATUS-REGISTER (RDSR) SEQUENCE Preliminary 2013 Microchip Technology Inc. SST25WF020A 5.8 Write-Enable (WREN) The Write-Enable (WREN) instruction, 06H, sets the Write-Enable-Latch bit in the Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow execution of the Write-Status-Register (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared upon the rising edge CE# of the WRSR instruction. CE# must be driven low before entering the WREN instruction, and CE# must be driven high before executing the WREN instruction. See Figure 5-8 for the WREN instruction sequence. CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 06 SI MSB SO HIGH IMPEDANCE 25139 F18.0 FIGURE 5-8: 5.9 WRITE ENABLE (WREN) SEQUENCE Write-Disable (WRDI) The Write-Disable (WRDI) instruction, 04H, resets the Write-Enable-Latch bit to ‘0’, thus preventing any new Write operations. CE# must be driven low before enter- ing the WRDI instruction, and CE# must be driven high before executing the WRDI instruction. See Figure 5-11 for the WRDI instruction sequence. CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 04 SI MSB SO HIGH IMPEDANCE 25139 F19.0 FIGURE 5-9: WRITE DISABLE (WRDI) SEQUENCE 2013 Microchip Technology Inc. Preliminary DS21392A-page 13 SST25WF020A 5.10 Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to the BP0, BP1, TB, and BPL bits of the status register. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. Poll the BUSY bit in the Software Status register, or wait TWRSR, for the completion of the internal self-timed Write-Status-Register cycle. See Figure 5-10 for WREN and WRSR instruction sequences and Figure 611 for the WRSR flow chart. ‘1’ to lock-down the status register, but cannot be reset from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1, and TB bits in the status register can all be changed. As long as BPL bit is set to ‘0’ or WP# pin is driven high (VIH) prior to the low-to-high transition of the CE# pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to ‘1’ to lock down the status register as well as altering the BP0, BP1, and TB bits at the same time. See Table 4-1 for a summary description of WP# and BPL functions. Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to ‘1’. When the WP# is low, the BPL bit can only be set from ‘0’ to CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MODE 0 01 06 SI MSB SO MODE 3 MSB STATUS REGISTER IN 7 6 5 4 3 2 1 0 MSB HIGH IMPEDANCE 25139 F20.0 FIGURE 5-10: DS21392A-page 14 WRITE-ENABLE (WREN) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE Preliminary 2013 Microchip Technology Inc. SST25WF020A 5.11 Power-Down The Deep Power-Down (DPD) instruction puts the device in the lowest power consumption mode – the Deep Power-Down mode. This instruction is ignored if the device is busy with an internal write operation. While the device is in DPD mode, all instructions are ignored except for the Release Deep Power-Down instruction or Read ID. before the standby current ISB is reduced to the deep power-down current IDPD. See Figure 5-11 for the DPD instruction sequence. Exit the power-down state using the Release from Deep Power-Down or Read ID instruction. CE# must be driven low before sending the Release from Deep Power-Down command cycle (ABH), and then driving CE# high. The device will return to Standby mode and be ready for the next instruction after TSBR. See Figure 5-12. for the Release from Deep Power-Down sequence. To initiate deep power-down, input the Deep PowerDown instruction (B9H) while driving CE# low. CE# must be driven high before executing the DPD instruction. After driving CE# high, it requires a delay of TDPD CE# TDPD MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 B9 SI MSB SO HIGH IMPEDANCE 25139 F46.1 FIGURE 5-11: DEEP POWER-DOWN SEQUENCE CE# TSBR MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 AB SI MSB SO HIGH IMPEDANCE 25139 F47.1 FIGURE 5-12: RELEASE FROM DEEP POWER-DOWN SEQUENCE 2013 Microchip Technology Inc. Preliminary DS21392A-page 15 SST25WF020A 5.12 Read-ID The Read-ID instruction identifies the device as SST25WF020A. Use the Read-ID instruction to identify SST25WF020A when using multiple manufacturers in the same socket. See Table 5-2. command, ABH, followed by 24 dummy address bits. Following the Read-ID instruction, and 24 address dummy bits, the device ID continues to output with continuous clock input until terminated by a low-to-high transition on CE#. The device ID information is read by executing an 8-bit TABLE 5-2: PRODUCT IDENTIFICATION SST25WF020A ID Address Data XXXXXXH 34H CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 23 24 15 16 31 32 39 40 47 48 55 56 63 MODE 0 XX AB SI XX MSB XX MSB HIGH IMPEDANCE SO Device ID Device ID Device ID Device ID HIGH IMPEDANCE MSB 25139 F22.1 Note: The Device ID output stream is continuous until terminated by a low-to-high transition on CE#. FIGURE 5-13: 5.13 READ-ID SEQUENCE JEDEC Read-ID The JEDEC Read-ID instruction identifies the device ID information of SST25WF020A. The device information can be read by executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, a 32bit device ID information is output from the device. The Device ID information is assigned by the manufacturer and contains the Device ID 1 in the first byte, the type of mem- ory in the second byte, the memory capacity of the device in the third byte, and a reserved code in the fourth byte. The 4-Byte code outputs repeatedly with continuous clock input until a low-to-high transition on CE#. See Figure 5-14 for the instruction sequence. The JEDEC Read ID instruction is terminated by a low to high transition on CE# at any time during data output. CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 MODE 0 SI SO 9F HIGH IMPEDANCE 16 62 MSB 12 00 MSB 25139 F23.1 FIGURE 5-14: TABLE 5-3: JEDEC READ-ID SEQUENCE JEDEC READ-ID DATA-OUT Device ID Product SST25WF020A DS21392A-page 16 Device ID 1 (Byte 1) 62H Memory Type (Byte 2) 16H Memory Capacity (Byte 3) 12H Preliminary Reserved Code (Byte 4) 00H 2013 Microchip Technology Inc. SST25WF020A 6.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Output shorted for no more than one second. No more than one output shorted at a time. TABLE 6-1: OPERATING RANGE TABLE 6-2: AC CONDITIONS OF TEST Range Ambient Temp VDD Input Rise/Fall Time Output Load Industrial -40°C to +85°C 1.65-1.95V 5ns CL = 30 pF 2013 Microchip Technology Inc. Preliminary DS21392A-page 17 SST25WF020A 6.1 Power-Up Specifications All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 1.8V in less than 180 ms). See Table 6-3 and Figure 6-2 for more information. TABLE 6-3: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 VDD Min to Read Operation 100 µs TPU-WRITE1 VDD Min to Write Operation 100 µs 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. VDD VDD Max Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. VDD Min TPU-READ TPU-WRITE Device fully accessible Time 25139 F27.0 FIGURE 6-1: DS21392A-page 18 POWER-UP TIMING DIAGRAM Preliminary 2013 Microchip Technology Inc. SST25WF020A 6.2 Hardware Data Protection SST25WF020A provides a power-up reset function. To ensure that the power reset circuit will operate correctly, the device must meet the conditions shown in Figure 6-2 and Table 6-4. Microchip does not guarantee the data in the event of an instantaneous power failure that occurs during a Write operation. VDD VDD Max VDD Min VBOT TPD 0V 25139 F48.0 FIGURE 6-2: TABLE 6-4: POWER-DOWN TIMING DIAGRAM RECOMMENDED SYSTEM POWER-DOWN TIMINGS Symbol Parameter TPD Power-down time VBOT Power-down voltage 6.3 Min Max 10 Units ms 0.2 V Software Data Protection SST25WF020A prevents unintentional operations by not recognizing commands under the following conditions: • After inputting a Write command, if the rising CE# edge timing is not in a bus cycle (8 CLK units of SCK) • When the Page-Program data is not in 1-byte increments • If the Write Status Register instruction is input for two bus cycles or more. 6.4 Decoupling Capacitor A 0.1µF ceramic capacitor must be provided to each device and connected between VDD and VSS to ensure that the device will operate correctly. 2013 Microchip Technology Inc. Preliminary DS21392A-page 19 SST25WF020A 6.5 DC Characteristics TABLE 6-5: DC OPERATING CHARACTERISTICS Limits Symbol Parameter IDDR Typ1 Min Max Units Test Conditions Read Current 6 mA CE#=0.1 VDD/0.9 VDD@25 MHz, SO=open IDDR2 Read Current 8 mA CE#=0.1 VDD/0.9VDD@40 MHz, SO=open IDDW Program and Erase Current 15 mA CE#=VDD ISB Standby Current 50 µA CE#=VDD, VIN=VDD or VSS IDPD Deep Power-Down 10 µA CE#=VDD, VIN=VDD or VSS ILI Input Leakage Current 2 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 2 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage -0.3 0.3 V VDD=VDD Min VIH Input High Voltage 0.7 VDD VDD+0.3 V VDD=VDD Max VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min VOH Output High Voltage V IOH=-100 µA, VDD=VDD Min VDD-0.2 1. Value characterized, not fully tested in production. TABLE 6-6: CAPACITANCE (TA = 25°C, F=1 MHZ, OTHER PINS OPEN) Parameter Description COUT1 Output Pin Capacitance CIN 1 Input Capacitance Test Condition Maximum VOUT = 0V 12 pF VIN = 0V 6 pF 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 6-7: Symbol NEND1 RELIABILITY CHARACTERISTICS Parameter Minimum Specification Units Test Method Endurance 100,000 Cycles JEDEC Standard A117 Status Register Write Cycle 100,000 Cycles JEDEC Standard A117 20 Years JEDEC Standard A103 100 + IDD mA TDR1 Data Retention ILTH1 Latch Up JEDEC Standard 78 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. DS21392A-page 20 Preliminary 2013 Microchip Technology Inc. SST25WF020A 6.6 AC Characteristics TABLE 6-8: Symbol AC OPERATING CHARACTERISTICS Parameter Limits - 25 MHz Min Typ Limits - 40 MHz Max Min Typ Max Units FCLK1 Serial Clock Frequency TSCKH Serial Clock High Time 14 11.5 ns 14 11.5 ns 25 40 MHz TSCKL Serial Clock Low Time TSCKR Serial Clock Rise Time 5 5 ns TSCKF Serial Clock Fall Time 5 5 ns TCES2 TCEH2 TCHS2 TCHH2 CE# Active Setup Time 10 10 ns CE# Active Hold Time 10 10 ns CE# Not Active Setup Time 10 10 ns CE# Not Active Hold Time 10 10 ns TCPH CE# High Time 25 TCHZ CE# High to High-Z Output TCLZ SCK Low to Low-Z Output 0 0 ns TDS Data In Setup Time 5 5 ns TDH Data In Hold Time 5 5 ns 5 5 ns 25 ns 15 15 ns THLS HOLD# Low Setup Time THHS HOLD# High Setup Time 5 5 ns THLH HOLD# Low Hold Time 5 5 ns THHH HOLD# High Hold Time 5 THZ HOLD# Low to High-Z Output 9 9 ns TLZ HOLD# High to Low-Z Output 12 12 ns TOH Output Hold from SCK Change TV Output Valid from SCK TWPS WP# Setup Time 20 20 5 1 ns 1 8 11 ns 8 11 20 ns ns TWPH WP# Hold Time TWRSR Status Register Write Time 10 10 ms TDPD CE# High to Deep Power-Down 5 5 µs TSBR Deep Power-Down (CE# High) to Standby Mode 5 5 µs TSE Sector-Erase 40 150 ms TBE TCE ns 40 150 Block-Erase 80 250 80 250 ms Chip-Erase 0.3 3 0.3 3 s 3.0 3.5 3.0 3.5 ms 0.20 + n*3.30/ 256 n byte 0.15 + n*2.85/ 256 0.20 + n*3.30/ 256 ms Page-Program (256 Byte) TPP 20 n Byte n byte 0.15 + n*2.85/ 256 1. Maximum clock frequency for Read instruction, 03H, is 25 MHz 2. Relative to SCK 2013 Microchip Technology Inc. Preliminary DS21392A-page 21 SST25WF020A TCPH CE# TCES TCHH TCHS TCEH SCK TDS TDH TSCKF TSCKR MSB SI LSB HIGH-Z HIGH-Z SO 25139 F24.0 FIGURE 6-3: SERIAL INPUT TIMING DIAGRAM CE# TSCKL TSCKH SCK TOH TCLZ SO TCHZ MSB LSB TV SI 25139 F25.0 FIGURE 6-4: SERIAL OUTPUT TIMING DIAGRAM CE# THHH THLS THLH THHS SCK THLH THZ TLZ SO SI HOLD# 25139 F26.1 FIGURE 6-5: DS21392A-page 22 HOLD TIMING DIAGRAM Preliminary 2013 Microchip Technology Inc. SST25WF020A CE# TWPH TWPS WP# 25139 F49.0 FIGURE 6-6: STATUS REGISTER WRITE TIMING VIHT VHT INPUT VHT REFERENCE POINTS OUTPUT VLT VLT VILT 25139 F28.0 AC test inputs are driven at VIHT (0.8VDD) for a logic ‘1’ and VILT (0.2VDD) for a logic ‘0’. Measurement reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 6-7: AC INPUT/OUTPUT REFERENCE WAVEFORMS 2013 Microchip Technology Inc. Preliminary DS21392A-page 23 SST25WF020A Start 06H Write Enable 02H Address 1 Address 2 Address 3 Page Program sequence Data 0 • • • Data 255 Start program on rising edge of CE# No 05H Status Register Read command Busy (Bit 0) = ‘0’? Check Program Completion Yes End of programming 25139 F41.1 FIGURE 6-8: DS21392A-page 24 PAGE-PROGRAM FLOW CHART Preliminary 2013 Microchip Technology Inc. SST25WF020A Start 06H Write Enable 20H/D7 or D8H Address 1 Sector-Erase (20H/D7H) or 64-KByte Block-Erase (D8H) sequence Address 2 Address 3 Start Erase on rising edge of CE# 05H No Busy (Bit 0) = ‘0’? Status Register Read command Check Erase Completion Yes End of Erase 25139 F42.1 FIGURE 6-9: SECTOR-ERASE OR 64-KBYTE BLOCK-ERASE FLOW CHART 2013 Microchip Technology Inc. Preliminary DS21392A-page 25 SST25WF020A Start 06H 60H/C7H Write Enable Chip-Erase Start Erase on rising edge of CE# 05H No Busy (Bit 0) = ‘0’? Status Register Read command Check Erase Completion Yes End of Erase 25139 F44.1 FIGURE 6-10: DS21392A-page 26 CHIP-ERASE FLOW CHART Preliminary 2013 Microchip Technology Inc. SST25WF020A Start 06H 01H Write Enable Write-StatusRegister Sequence Data Start Write on rising edge of CE# 05H No Busy (Bit 0) = ‘0’? Status Register Read command Check Write Completion Yes End WriteStatus-Register 25139 F45.1 FIGURE 6-11: WRITE-STATUS-REGISTER (WRSR) FLOW CHART 2013 Microchip Technology Inc. Preliminary DS21392A-page 27 SST25WF020A 7.0 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X XXX Device Tape/Reel Indicator Operating Frequency XX XX Endurance/ Temperature Package Valid Combinations: SST25WF020AT-40-5I-NP SST25WF020A-40-5I-SN SST25WF020AT-40-5I-SN Device: SST25WF020A = 2 Mbit,1.65-1.95V, Serial Flash Memory Tape and Reel Flag: T = Tape and Reel Operating Frequency: 40 = 40 MHz Endurance: 5 = 100,000 cycles Temperature: I = -40°C to +85°C Package: NP SN = USON (2mm x 3mm Body), 8-contact = SOIC (150 mil Body), 8-lead DS21392A-page 28 Preliminary 2013 Microchip Technology Inc. SST25WF020A 8.0 Note: PACKAGING DIAGRAMS For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013 Microchip Technology Inc. Preliminary DS21392A-page 29 SST25WF020A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21392A-page 30 Preliminary 2013 Microchip Technology Inc. SST25WF020A 2013 Microchip Technology Inc. Preliminary DS21392A-page 31 SST25WF020A DS21392A-page 32 Preliminary 2013 Microchip Technology Inc. SST25WF020A TABLE 8-1: Revision • A • REVISION HISTORY Description Date Initial release of data sheet 2013 Microchip Technology Inc. Feb 2013 Preliminary DS21392A-page 33 SST25WF020A THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. DS21392A-page 34 Preliminary 2013 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62077-026-9 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2013 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary DS21392A-page 35 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-66-152-7160 Fax: 81-66-152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 2013 Microchip Technology Inc. Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 Preliminary DS21392A-page 36