8 Mbit / 16 Mbit (x8) Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet FEATURES: • Organized as 1M x8 / 2M x8 • Single Voltage Read and Write Operations - 3.0-3.6V for SST39LF080/016 - 2.7-3.6V for SST39VF080/016 • Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention • Low Power Consumption: - Active Current: 15 mA (typical) - Standby Current: 4 µA (typical) - Auto Low Power Mode: 4 µA (typical) • Sector-Erase Capability - Uniform 4 KByte sectors • Block-Erase Capability - Uniform 64 KByte blocks • Fast Read Access Time: - 55 ns for SST39LF080/016 - 70 and 90 ns for SST39VF080/016 • Latched Address and Data PRODUCT DESCRIPTION The SST39LF/VF080 and SST39LF/VF016 devices are 1M x8 / 2M x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF080/016 write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF080/016 write (Program or Erase) with a 2.73.6V power supply. They conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39LF/VF080 and SST39LF/VF016 devices provide a typical Byte-Program time of 14 µsec. The devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39LF/VF080 and SST39LF/VF016 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during • Fast Erase and Byte-Program: - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Byte-Program Time: 14 µs (typical) - Chip Rewrite Time: 15 seconds (typical) for SST39LF/VF080 30 seconds (typical) for SST39LF/VF016 • Automatic Write Timing - Internal VPP Generation • End-of-Write Detection - Toggle Bit - Data# Polling • CMOS I/O Compatibility • JEDEC Standard - Flash EEPROM Pinouts and command sets • Packages Available - 40-Pin TSOP (10mm x 20mm) - 48-Ball TFBGA (6mm x 8mm) Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. They also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39LF/VF080 and SST39LF/VF016 are offered in 40-pin TSOP and 48-ball TFBGA packaging. See Figures 1 and 2 for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. © 2000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. 396-2 11/00 S71146 These specifications are subject to change without notice. 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet block size of 64 KByte. The Sector-Erase operation is initiated by executing a six-byte-command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte-command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. The SST39LF/VF080 and SST39LF/VF016 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 15 mA to typically 4 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 1 mA/MHz of read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto Low Power mode after power-up with CE# held steadily low until the first address transition or CE# is driven high. Read The Read operation of the SST39LF/VF080 and SST39LF/VF016 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Chip-Erase Operation The SST39LF/VF080 and SST39LF/VF016 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 8 for timing diagram, and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Byte-Program Operation The SST39LF/VF080 and SST39LF/VF016 are programmed on a byte-by-byte basis. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the ByteProgram operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Write Operation Status Detection The SST39LF/VF080 and SST39LF/VF016 provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The Endof-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or blockby-block) basis. The SST39LF/VF080 and SST39LF/ VF016 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform © 2000 Silicon Storage Technology, Inc. 2 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within TRC. Data# Polling (DQ7) When the SST39LF/VF080 and SST39LF/VF016 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 17 for a flowchart. Common Flash Memory Interface (CFI) The SST39LF/VF080 and SST39LF/VF016 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1’s and 0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 17 for a flowchart. Product Identification The Product Identification mode identifies the device as the SST39LF080, SST39VF080, SST39LF016 and SST39VF016 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SST39LF/VF080 and SST39LF/ VF016. Users may wish to use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram and Figure 18 for the Software ID Entry command sequence flowchart. Data Protection The SST39LF/VF080 and SST39LF/VF016 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Manufacturer’s ID Device ID SST39LF/VF080 SST39LF/VF016 VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. 3 4 5 6 7 8 9 Address Data 0000H BFH 11 0001H 0001H D8H D9H 12 396 PGM T1.2 Product Identification Mode Exit/CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform and Figure 18 for a flowchart. Software Data Protection (SDP) The SST39LF/VF080 and SST39LF/VF016 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST39LF/VF080 and SST39LF/VF016 devices are shipped with the Software Data Protection permanently © 2000 Silicon Storage Technology, Inc. 2 10 TABLE 1: PRODUCT IDENTIFICATION Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. 1 3 S71146 396-2 11/00 13 14 15 16 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet FUNCTIONAL BLOCK DIAGRAM SuperFlash Memory X-Decoder Memory Address Address Buffer & Latches Y-Decoder CE# I/O Buffers and Data Latches Control Logic OE# WE# DQ7 - DQ0 396 ILL B1.2 SST39LF/VF160 SST39LF/VF080 A16 A15 A14 A13 A12 A11 A9 A8 WE# NC NC NC A18 A7 A6 A5 A4 A3 A2 A1 SST39LF/VF080 SST39LF/VF016 A16 A15 A14 A13 A12 A11 A9 A8 WE# NC NC NC A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A17 VSS NC A19 A10 DQ7 DQ6 DQ5 DQ4 VDD VDD NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Standard Pinout Top View Die Up A17 VSS A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VDD VDD NC DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 396 ILL F01.2 FIGURE 1: PIN ASSIGNMENTS FOR 40-PIN TSOP TOP VIEW (balls facing down) TOP VIEW (balls facing down) SST39LF/VF080 4 3 2 1 A9 A8 WE# NC NC A7 NC A18 A11 NC NC A6 A16 A17 NC 6 A20 VSS 5 A12 A19 A10 DQ6 DQ7 NC DQ5 NC 4 VDD DQ4 3 NC DQ2 DQ3 VDD NC A5 DQ0 NC NC DQ1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F G 2 1 H A14 A13 A15 A16 A17 NC A9 A20 VSS A8 A11 A12 A19 A10 DQ6 DQ7 WE# NC NC NC DQ5 NC VDD DQ4 NC NC NC NC DQ2 DQ3 VDD A21 A7 A18 A6 A5 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E DQ0 NC F NC DQ1 G 396 ILL F21.0 5 A14 A13 A15 396 ILL F20.0 6 SST39LF/VF016 H FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA © 2000 Silicon Storage Technology, Inc. 4 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 2: PIN DESCRIPTION Symbol Pin Name Address Inputs AMS-A0 DQ7-DQ0 Data Input/output CE# OE# WE# VDD Chip Enable Output Enable Write Enable Power Supply Vss NC Ground No Connection Note: Functions To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 3.0-3.6V for SST39LF080/016 2.7-3.6V for SST39VF080/016 AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. Standby Write Inhibit Product Identification Hardware Mode Software Mode Notes: 2 3 4 5 Unconnected pins. TABLE 3: OPERATION MODES SELECTION Mode CE# OE# Read VIL VIL Program VIL VIH Erase VIL VIH 1 396 PGM T2.2 6 7 WE# VIH VIL VIL A9 AIN AIN X DQ DOUT DIN X VIH X X X VIL X X X VIH X X X High Z High Z/ DOUT High Z/ DOUT VIL VIL VIH VH Manufacturer's ID (BFH) Device ID (1) VIL VIL VIH AIN Address AIN AIN Sector or block address, XXH for Chip-Erase X X X AMS(2) - A1 = VIL, A0 = VIL A20(2) - A1 = VIL, A0 = VIH See Table 4 (1) Device ID D8H for SST39LF/VF080 and D9H for SST39LF/VF016 (2) AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. 396 PGM T3.2 8 9 10 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. 5 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle Addr(1) Data 2nd Bus Write Cycle Addr(1) Data 3rd Bus Write Cycle Addr(1) Data 4th Bus Write Cycle Addr(1) Data 5th Bus Write Cycle Addr(1) Data 6th Bus Write Cycle Addr(1) Data Byte-Program Sector-Erase Block-Erase Chip-Erase Software ID Entry CFI Query Entry Software ID Exit/ CFI Exit Software ID Exit/ CFI Exit 5555H 5555H 5555H 5555H 5555H 5555H XXH AAH AAH AAH AAH AAH AAH F0H 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 55H 55H 55H 55H 55H 55H 5555H 5555H 5555H 5555H 5555H 5555H A0H 80H 80H 80H 90H 98H WA(3) 5555H 5555H 5555H 2AAAH 2AAAH 2AAAH SAx(2) BAx(2) 5555H 5555H AAH 2AAAH 55H 5555H F0H Data AAH AAH AAH 55H 55H 55H 30H 50H 10H 396 PGM T4.1 Notes: (1) (2) (3) (4) Address format A14-A0 (Hex), Addresses A15, A16, A17, A18 and A19 are “Don’t Care” for Command sequence for SST39LF/VF080. Addresses A15, A16, A17, A18, A19 and A20 are “Don’t Care” for Command sequence for SST39LF/VF016. SAx for Sector-Erase; uses AMS-A12 address lines BAx, for Block-Erase; uses AMS-A16 address lines AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. WA = Program byte address Both Software ID Exit operations are equivalent Notes for Software ID Entry Command Sequence 1. With AMS -A1 = 0; SST Manufacturer's ID = BFH, is read with A0 = 0, SST39LF/VF080 Device ID = D8H, is read with A0 = 1. SST39LF/VF016 Device ID = D9H, is read with A0 = 1. AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. 2. The device does not remain in Software Product ID Mode if powered down. TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF/VF080 AND SST39LF/VF016 Address Data Data 10H 51H 11H 52H Query Unique ASCII string “QRY” 12H 59H 13H 01H Primary OEM command set 14H 07H 15H 00H Address for Primary Extended Table 16H 00H 17H 00H Alternate OEM command set (00H = none exists) 18H 00H 19H 00H Address for Alternate OEM extended Table (00H = none exits) 1AH 00H Note 1: Refer to CFI publication 100 for more details. © 2000 Silicon Storage Technology, Inc. 396 PGM T5.3 6 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39LF/VF080 AND SST39LF/VF016 Address Data Data VDD Min. (Program/Erase) 1BH 27H1) 30H(1) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1CH 36H VDD Max. (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 00H VPP min. (00H = no VPP pin) 1EH 00H VPP max. (00H = no VPP pin) 1FH 04H Typical time out for Byte-Program 2N µs (24 = 16 µs) 20H 00H Typical time out for min. size buffer program 2N µs (00H = not supported) 21H 04H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) 22H 06H Typical time out for Chip-Erase 2N ms (26 = 64 ms) 23H 01H Maximum time out for Byte-Program 2N times typical (21 x 24 = 32 µs) 24H 00H Maximum time out for buffer program 2N times typical 25H 01H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) 26H 01H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms) 1 2 3 4 5 6 396 PGM T6.1 Note (1) 30H for SST39LF080/016 and 27H for SST39VF080/016 TABLE 7A: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF080 Address Data Data 27H 14H Device size = 2N Bytes (14H = 20; 220 = 1M Bytes) 28H 00H Flash Device Interface description; 0000H = x8-only asynchronous interface 29H 00H 2AH 00H Maximum number of byte in multi-byte write = 2N (00H = not supported) 2BH 00H 2CH 02H Number of Erase Sector/Block sizes supported by device 2DH FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size) 2EH 00H y = 255 + 1 = 256 sectors (00FFH = 255) 2FH 10H 30H 00H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) 31H 0FH Block Information (y + 1 = Number of blocks; z x 256B = block size) 32H 00H y = 15 + 1 = 16 blocks (000FH = 15) 33H 00H 34H 01H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) 396 PGM T7a.0 TABLE 7B: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF016 Address Data Data 27H 15H Device size = 2N Byte (15H = 21; 221 = 2M Bytes) 28H 00H Flash Device Interface description; 0000H = x8-only asynchronous interface 29H 00H 2AH 00H Maximum number of byte in multi-byte write = 2N (00H = not supported) 2BH 00H 2CH 02H Number of Erase Sector/Block sizes supported by device 2DH FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size) 2EH 01H y = 511 + 1 = 512 sectors (01FFH = 511) 2FH 10H 30H 00H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) 31H 1FH Block Information (y + 1 = Number of blocks; z x 256B = block size) 32H 00H y = 31 + 1 = 32 blocks (001FH = 31) 33H 00H 34H 01H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) 396 PGM T7b.1 © 2000 Silicon Storage Technology, Inc. 7 S71146 396-2 11/00 7 8 9 10 11 12 13 14 15 16 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55°C to +125°C Storage Temperature ...................................................................................................................... -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential ............................................................................ -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ........................................................ -1.0V to VDD + 1.0V Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C Output Short Circuit Current(1) ................................................................................................................................................................. 50 mA Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE FOR SST39LF080/016 Range Ambient Temp VDD Commercial 0°C to +70 °C 3.0 - 3.6V OPERATING RANGE FOR SST39VF080/016 Range Ambient Temp VDD Commercial 0°C to +70°C 2.7 - 3.6V Industrial -40°C to +85°C 2.7 - 3.6V AC CONDITIONS OF TEST Input Rise/Fall Time ......... 5 ns Output Load ..................... CL = 30 pF for SST39LF080/016 ........................................ CL = 100 pF for SST39VF080/016 See Figures 14 and 15 © 2000 Silicon Storage Technology, Inc. 8 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TABLE 8: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST39LF080/016 AND 2.7-3.6V FOR SST39VF080/016 Limits Symbol Parameter Min Max Units Test Conditions IDD Power Supply Current ISB IALP Read Program and Erase Standby VDD Current Auto Low Power Current 20 25 20 20 mA mA µA µA Input Leakage Current Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage 0.7 VDD Input High Voltage (CMOS) VDD-0.3 Output Low Voltage Output High Voltage VDD-0.2 Supervoltage for A9 pin 11.4 Supervoltage Current for A9 pin 1 1 0.8 0.3 µA µA V V V V V V V µA ILI ILO VIL VILC VIH VIHC VOL VOH VH IH 0.2 12.6 200 396 PGM T9.1 TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter (1) TPU-READ TPU-WRITE(1) Address input = VIL/VIH, at f=1/TRC Min., VDD=VDD Max. CE#=OE#=VIL,WE#=VIH , all I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD = VDD Max. CE#=VILC, VDD = VDD Max. All inputs = VIHC or VILC WE# = VIHC VIN =GND to VDD, VDD = VDD Max. VOUT =GND to VDD, VDD = VDD Max. VDD = VDD Min. VDD = VDD Max. VDD = VDD Max. VDD = VDD Max. IOL = 100 µA, VDD = VDD Min. IOH = -100 µA, VDD = VDD Min. CE# = OE# =VIL, WE# = VIH CE# = OE# = VIL, WE# = VIH, A9 = VH Max. Power-up to Read Operation Power-up to Program/Erase Operation Minimum Units 100 100 µs µs 396 PGM T10.1 CIN(1) Input Capacitance 3 4 5 6 7 8 10 11 Maximum 12 pF VIN = 0V 2 9 Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: CAPACITANCE (Ta = 25 °C, f=1 Mhz, other pins open) Parameter Description Test Condition CI/O(1) I/O Pin Capacitance VI/O = 0V 1 12 6 pF Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 396 PGM T11.0 TABLE 11: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification (1) NEND TDR(1) VZAP_HBM(1) VZAP_MM(1) ILTH(1) Endurance Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up 13 Units Test Method 10,000 100 2000 Cycles Years Volts JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 200 Volts JEDEC Standard A115 100 + IDD mA 14 15 16 JEDEC Standard 78 396 PGM T12.0 Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. © 2000 Silicon Storage Technology, Inc. 9 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet AC CHARACTERISTICS TABLE 12: READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF080/016 AND 2.7-3.6V FOR SST39VF080/016 SST39LF080/016-55 SST39VF080/016-70 Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change Min 55 Max Min 70 Max 55 55 30 SST39VF080/016-90 Min 90 70 70 35 0 0 0 0 90 90 45 0 0 15 15 20 20 0 Max 0 30 30 0 Units ns ns ns ns ns ns ns ns ns 396 PGM T13.2 TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TBP Byte-Program Time TAS Address Setup Time TAH Address Hold Time TCS WE# and CE# Setup Time TCH WE# and CE# Hold Time TOES OE# High Setup Time TOEH OE# High Hold Time TCP CE# Pulse Width TWP WE# Pulse Width TWPH (1) WE# Pulse Width High TCPH (1) CE# Pulse Width High TDS Data Setup Time TDH (1) Data Hold Time TIDA (1) Software ID Access and Exit Time TSE Sector-Erase TBE Block-Erase TSCE Chip-Erase Min Max 20 0 30 0 0 0 10 40 40 30 30 30 0 150 25 25 100 Units µs ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms 396 PGM T14.0 Note: (1) This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. © 2000 Silicon Storage Technology, Inc. 10 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TAA TRC 1 ADDRESS AMS-0 2 TCE CE# 3 TOE OE# 4 TOHZ TOLZ VIH WE# HIGH-Z DQ7-0 TCHZ TOH TCLZ HIGH-Z DATA VALID 5 DATA VALID Note: AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. 396 ILL F02.1 6 7 FIGURE 3: READ CYCLE TIMING DIAGRAM 8 9 INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 10 ADDR TDH TWP 11 WE# TAS TDS TWPH 12 OE# TCH 13 CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 14 DATA BYTE (ADDR/DATA) 396 ILL F03.1 Note: AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. 16 FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. 11 15 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ7-0 AA 55 A0 DATA SW0 SW1 SW2 BYTE (ADDR/DATA) 396 ILL F04.1 Note: AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS AMS-0 TCE CE# TOES TOEH OE# TOE WE# DQ7 DATA DATA# DATA# DATA 396 ILL F05.1 Note: AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. FIGURE 6: DATA# POLLING TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. 12 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet 1 ADDRESS AMS-0 TCE 2 CE# TOES TOE TOEH OE# 3 4 WE# 5 DQ6 TWO READ CYCLES WITH SAME OUTPUTS 6 396 ILL F06.1 Note: AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. 7 FIGURE 7: TOGGLE BIT TIMING DIAGRAM 8 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA 9 TSCE SIX-BYTE CODE FOR CHIP-ERASE 5555 10 CE# 11 OE# 12 TWP WE# 13 DQ7-0 AA 55 80 AA 55 10 SW0 SW1 SW2 SW3 SW4 SW5 14 396 ILL F08.1 15 Note: The device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 13) AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. 16 FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. 13 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TBE SIX-BYTE CODE FOR BLOCK-ERASE 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA BAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 50 SW0 SW1 SW2 SW3 SW4 SW5 396 ILL F09.1 Note: The device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 13) AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM TSE SIX-BYTE CODE FOR SECTOR-ERASE 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA SAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 30 SW0 SW1 SW2 SW3 SW4 SW5 396 ILL F10.1 Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 13) AMS = Most significant address AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016. FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. 14 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 5555 2AAA 1 5555 0000 0001 2 CE# 3 OE# 4 TIDA TWP WE# TWPH DQ7-0 AA 55 SW0 SW1 5 TAA BF 90 Device ID 6 SW2 Note: Device ID = D9H for SST39LF/VF016 D8H for SST39LF/VF080 396 ILL F11.3 FIGURE 11: SOFTWARE ID ENTRY AND READ 7 8 9 THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS A14-0 5555 2AAA 10 5555 11 CE# 12 OE# 13 TIDA TWP WE# TWPH DQ7-0 AA 55 SW0 SW1 14 TAA 98 15 SW2 396 ILL F12.0 FIGURE 12: CFI QUERY ENTRY AND READ © 2000 Silicon Storage Technology, Inc. 15 S71146 396-2 11/00 16 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 DQ7-0 5555 2AAA AA 5555 55 F0 TIDA CE# OE# TWP WE# T WHP SW0 SW1 SW2 396 ILL F13.0 FIGURE 13: SOFTWARE ID EXIT/CFI EXIT © 2000 Silicon Storage Technology, Inc. 16 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet VIHT 1 VIT INPUT REFERENCE POINTS VOT OUTPUT 2 VILT 396 ILL F14.1 3 « AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Inputs rise and fall times (10% 90%) are <5 ns. Note: VIT–VINPUT Test VOT–VOUTPUT Test VIHT–VINPUT HIGH Test VILT–VINPUT LOW Test 4 5 FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS 6 7 TO TESTER 8 TO DUT 9 CL 396 ILL F15.1 10 FIGURE 15: A TEST LOAD EXAMPLE 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. 17 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 396 ILL F16.1 FIGURE 16: BYTE-PROGRAM ALGORITHM © 2000 Silicon Storage Technology, Inc. 18 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet 1 Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated 2 3 4 Read DQ7 Read byte Wait TBP, TSCE, TSE or TBE 5 Read same byte Program/Erase Completed No Is DQ7 = true data? 6 Yes No Does DQ6 match? 7 Program/Erase Completed 8 Yes 9 Program/Erase Completed 10 396 ILL F17.0 11 12 13 FIGURE 17: WAIT OPTIONS 14 15 16 © 2000 Silicon Storage Technology, Inc. 19 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet CFI Query Entry Command Sequence Software Product ID Entry Command Sequence Software ID Exit/CFI Exit Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: F0H Address: XXH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Wait TIDA Load data: 98H Address: 5555H Load data: 90H Address: 5555H Load data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Software ID Return to normal operation 396 ILL F18.1 FIGURE 18: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS © 2000 Silicon Storage Technology, Inc. 20 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence 1 Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H 2 3 Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 80H Address: 5555H Load data: 80H Address: 5555H 4 5 6 Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH 7 8 9 Load data: 10H Address: 5555H Load data: 30H Address: SAX Load data: 50H Address: BAX 10 11 Wait TSCE Wait TSE Wait TBE Chip erased to FFH Sector erased to FFH Block erased to FFH 12 13 14 396 ILL F19.1 15 FIGURE 19: ERASE COMMAND SEQUENCE 16 © 2000 Silicon Storage Technology, Inc. 21 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet Device SST39xFxxx - Speed Suffix1 Suffix2 XXX XX XX Package Modifier I = 40 pins K = 48 pins Numeric = Die modifier Package Type E = TSOP (10mm x 20mm) B2 = TFBGA (6mm x 8mm) Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 55 = 55 ns 70 = 70 ns 90 = 90 ns Device Density 080 = 8 Megabit 016 = 16 Megabit Voltage L = 3.0-3.6V V = 2.7-3.6V SST39LF080 Valid combinations SST39LF080-55-4C-EI SST39LF080-55-4C-B2K SST39VF080 Valid combinations SST39VF080-70-4C-EI SST39VF080-70-4C-B2K SST39VF080-90-4C-EI SST39VF080-90-4C-B2K SST39VF080-90-4I-EI SST39VF080-90-4I-B2K SST39LF016 Valid combinations SST39VF016-55-4C-EI SST39VF016-55-4C-B2K SST39VF016 Valid combinations SST39VF016-70-4C-EI SST39VF016-70-4C-B2K SST39VF016-90-4C-EI SST39VF016-90-4C-B2K SST39VF016-90-4I-EI SST39VF016-90-4I-B2K Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. © 2000 Silicon Storage Technology, Inc. 22 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet PACKAGING DIAGRAMS 1 1.05 0.95 PIN # 1 IDENTIFIER .50 BSC 2 .270 .170 3 10.10 9.90 4 5 0.15 0.05 18.50 18.30 0.70 0.50 Note: 6 7 20.20 19.80 8 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 40.TSOP-EI-ILL.3 3. Coplanarity: 0.1 (±.05) mm. 9 40-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 20MM SST PACKAGE CODE: EI 10 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. 23 S71146 396-2 11/00 8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016 Data Sheet TOP VIEW BOTTOM VIEW 8.00 ± 0.20 5.60 0.80 6 6 5 5 4.00 4 6.00 ± 0.20 3 4 0.80 3 2 2 1 1 A B C D E F G H H G F E D C B A A1 CORNER 0.335 ± 0.035 (48X) A1 CORNER 1.10 ± 0.10 SIDE VIEW 0.15 SEATING PLANE 48ba TFBGA.B2K.6x8-ILL.1 0.23 ± 0.04 Note: 1. Complies with the general requirements of JEDEC publication 95 MO-210, although some dimensions may be more stringent. (This specific outline variant has not yet been registered) 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 48-BALL THIN PROFILE FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM SST PACKAGE CODE: B2K Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873 © 2000 Silicon Storage Technology, Inc. 24 S71146 396-2 11/00