ST24E64 ST25E64 SERIAL EXTENDED ADDRESSING COMPATIBLE WITH I2C BUS 64K (8K x 8) EEPROM PRELIMINARY DATA COMPATIBLE with I2C EXTENDED ADDRESSING TWO WIRE SERIAL INTERFACE, SUPPORTS 400kHz PROTOCOL 1 MILLION ERASE/WRITE CYCLES, OVER the FULL SUPPLY VOLTAGE RANGE 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE – 4.5V to 5.5V for ST24E64 version – 2.5V to 5.5V for ST25E64 version WRITE CONTROL FEATURE BYTE and PAGE WRITE (up to 32 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCES 8 8 1 1 PSDIP8 (B) 0.25mm Frame SO8 (M) 200mil Width Figure 1. Logic Diagram VCC DESCRIPTION The ST24/25E64 are 64K bit electrically erasable programmable memories (EEPROM), organized as 8 blocks of 1024 x 8 bits. The ST25E64 operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. 3 E0-E2 SCL SDA ST24E64 ST25E64 WC Table 1. Signal Names E0 - E2 Chip Enable Inputs SDA Serial Data Address Input/Output SCL Serial Clock WC Write Control VCC Supply Voltage VSS Ground VSS November 1996 This is preliminary information on a new product now in development or undergoing evaluatio n.Details are subject to change without notice. AI01204B 1/16 ST24E64, ST25E64 Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections ST24E64 ST25E64 ST24E64 ST25E64 E0 E1 E2 VSS 1 2 3 4 8 7 6 5 E0 E1 E2 VCC WC SCL SDA VSS AI01205B 1 2 3 4 8 7 6 5 VCC WC SCL SDA AI01206C Table 2. Absolute Maximum Ratings (1) Symbol Value Unit Ambient Operating Temperature –40 to 125 °C TSTG Storage Temperature –65 to 150 °C TLEAD Lead Temperature, Soldering 215 260 °C TA Parameter VIO Input or Output Voltages VCC Supply Voltage VESD (SO8) (PSDIP8) 40 sec 10 sec Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model) (3) (2) –0.6 to 6.5 V –0.3 to 6.5 V 4000 V 500 V Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. 100pF through 1500Ω; MIL-STD-883C, 3015.7 3. 200pF through 0Ω; EIAJ IC-121 (condition C) DESCRIPTION (cont’d) Each memory is compatible with the I2C extended addressing standard, two wire serial interface which uses a bi-directional data bus and serial clock. The ST24/25E64carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. The ST24/25E64 behave as 2/16 slave devices in the I 2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START conditiongenerated by the bus master. The START condition is followed by a stream of 4 bits (identification code 1010), 3 bit Chip Enable input to form a 7 bit Device Select, plus one read/write bit and terminated by an acknowledge bit. ST24E64, ST25E64 Table 3. Device Select Code Device Code Chip Enable RW Bit b7 b6 b5 b4 b3 b2 b1 b0 Device Select 1 0 1 0 E2 E1 E0 RW Note: The MSB b7 is sent first. Table 4. Operating Modes Mode Current Address Read Random Address Read RW bit Bytes ’1’ 1 ’0’ 1 ’1’ Initial Sequence START, Device Select, RW = ’1’ START, Device Select, RW = ’0’, Address, reSTART, Device Select, RW = ’1’ Sequential Read ’1’ 1 to 8192 Byte Write ’0’ 1 START, Device Select, RW = ’0’ Page Write ’0’ 32 START, Device Select, RW = ’0’ When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. In this way, up to 8 ST24/25E64 may be connected to the same I2C bus and selected individually, allowing a total addressing field of 512 Kbit. Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Untill the VCC voltage has reached the POR threshold value, the internal reset is active: all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. SIGNALS DESCRIPTION Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A As CURRENT or RANDOM Mode resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3) Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. Aresistor must be connectedfrom the SDA bus line to VCC to act as pull up (see Figure 3). Chip Enable (E0 - E2). These chip enable inputs are used to set the 3 least significant bits of the 7 bit device select code. They may be driven dynamically or tied to VCC or VSS to establish the device select code. Note that the VIL and VIH levels for the inputs are CMOS, not TTL compatible. Write Control (WC). The Write Control feature WC is useful to protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC at VIH) or disable (WC at VIL) the internal write protection. When pin WC is unconnected, the WC input is internally read as VIL (see Table 5). When WC = ’1’, Device Select and Address bytes are acknowledged; Data bytes are not acknowledged. Refer to the AN404 Application Note for more detailed information about Write Control feature. 3/16 ST24E64, ST25E64 Figure 3. Maximum RL Value versus Bus Capacitance (C BUS) for an I2C Bus, fC = 400kHz 20 VCC 16 RL max (kΩ) RL 12 RL SDA MASTER CBUS SCL 8 CBUS 4 VCC = 5V 0 25 50 75 CBUS (pF) DEVICE OPERATION 2 I C Bus Background The ST24/25E64support the extended addressing I2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The ST24/25E64 are always slave devices in all communications. Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the ST24/25E64 continuously monitor the SDA and SCL signals for a START condition and will not respond unless one is given. Stop Condition. STOPis identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the ST24/25E64 and the bus master. A STOP condition at the end of a Read command forces the standby state. A 4/16 100 AI01115 STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. Data Input. During data input the ST24/25E64 sample the SDA bus signal on the rising edge of the clock SCL. For correct device operation the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. Device Selection. To start communication between the bus master and the slave ST24/25E64, the master must initiate a START condition. The 8 bits sent after a START condition are made up of a device select of 4 bits that identifies the device type, 3 Chip Enable bits and one bit for a READ (RW = 1) or WRITE (RW = 0) operation. There are two modes both for read and write. These are summarised in Table 4 and described hereafter. A communication between the master and the slave is ended with a STOP condition. ST24E64, ST25E64 Table 5. Input Parameters (1) (TA = 25 °C, f = 400 kHz ) Symbol Parameter Test Condition Min Max Unit CIN Input Capacitance (SDA) 8 pF CIN Input Capacitance (other pins) 6 pF 20 kΩ ZWCL WC Input Impedance VIN ≤ 0.3 VCC 5 ZWCH WC Input Impedance VIN ≥ 0.7 VCC 500 tLP Low-pass filter input time constant (SDA and SCL) kΩ 100 ns Max Unit Note: 1. Sampled only, not 100% tested. Table 6. DC Characteristics (TA = –40 to 85 °C or 0 to 70 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V) Symbol Parameter Test Condition ILI Input Leakage Current (SCL, SDA, E0-E2) 0V ≤ VIN ≤ VCC ±2 µA ILO Output Leakage Current 0V ≤ VOUT ≤ VCC SDA in Hi-Z ±2 µA 2 mA 1 mA VIN = VSS or VCC, VCC = 5V 100 µA VIN = VSS or VCC, VCC = 5V, fC = 400kHz 300 µA VIN = VSS or VCC, VCC = 2.5V 5 µA VIN = VSS or VCC, VCC = 2.5V, fC = 400kHz 50 µA ICC Supply Current (ST24 series) Supply Current (ST25 series) ICC1 ICC2 Supply Current (Standby) (ST24 series) Supply Current (Standby) (ST25 series) Min fC = 400kHz (Rise/Fall time < 30ns) VIL Input Low Voltage (SCL, SDA) –0.3 0.3 VCC V VIH Input High Voltage (SCL, SDA) 0.7 VCC VCC + 1 V VIL Input Low Voltage (E0-E2, WC) –0.3 0.5 V VIH Input High Voltage (E0-E2, WC) VCC – 0.5 VCC + 1 V IOL = 3mA, VCC = 5V 0.4 V IOL = 2.1mA, VCC = 2.5V 0.4 V VOL Output Low Voltage Output Low Voltage (ST25 series) 5/16 ST24E64, ST25E64 Table 7. AC Characteristics (TA = –40 to 85 °C or 0 to 70 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V) Symbol Alt tCH1CH2 tR tCL1CL2 Max Unit Clock Rise Time 300 ns tF Clock Fall Time 300 ns tDH1DH2 (1) tR SDA Rise Time 20 300 ns (1) tF SDA Fall Time 20 300 ns Clock High to Input Transition 600 ns Clock Pulse Width High 600 ns 600 ns 0 µs Clock Pulse Width Low 1.3 µs tDL1DL1 tCHDX (2) tSU:STA Parameter Min tCHCL tHIGH tDLCL tHD:STA Input Low to Clock Low (START) tCLDX tHD:DAT Clock Low to Input Transition tCLCH tLOW tDXCX tSU:DAT Input Transition to Clock Transition 100 ns tCHDH tSU:STO Clock High to Input High (STOP) 600 ns tDHDL tBUF Input High to Input Low (Bus Free) 1.3 µs tAA Clock Low to Next Data Out Valid 200 tCLQX tDH Data Out Hold Time 200 fC fSCL Clock Frequency 400 kHz tW tWR Write Time 10 ms tCLQV (3) 1000 ns ns Notes: 1. Sampled only, not 100% tested. 2. For a reSTART condition, or following a write cycle. 3. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP conditions. AC MEASUREMENT CONDITIONS DEVICE OPERATION (cont’d) Input Rise and Fall Times ≤ 50ns Input Pulse Voltages 0.2VCC to 0.8VCC Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC Memory Addressing. A data byte in the memory is addressed through 2 bytes of address information. The Most Significant Byte is sent first and the Least significant Byte is sent after. The Least Significant Byte addresses a block of 256 bytes, bits b12,b11,b10,b9,b8 of the Most Significant Byte select one block among 32 blocks (one block is 256 bytes). Figure 4. AC Testing Input Output Waveforms Most Significant Byte 0.8VCC 0.7VCC X X X b12 b11 b10 b9 b8 b3 b2 b1 b0 X = Don’t Care. 0.2VCC 0.3VCC AI00825 Least Significant Byte b7 6/16 b6 b5 b4 ST24E64, ST25E64 Figure 5. AC Waveforms tCLCH tCHCL SCL tDLCL tDXCX tCHDH SDA IN tCHDX START CONDITION tCLDX tDHDL SDA INPUT SDA CHANGE STOP & BUS FREE SCL tCLQV tCLQX DATA VALID SDA OUT DATA OUTPUT tDHDL SCL tW SDA IN tCHDH STOP CONDITION tCHDX WRITE CYCLE START CONDITION AI00795 7/16 ST24E64, ST25E64 Figure 6. I2C Bus Protocol SCL SDA START CONDITION SCL 1 SDA MSB SDA INPUT 2 STOP CONDITION SDA CHANGE 3 7 8 9 ACK START CONDITION SCL 1 SDA MSB 2 3 7 8 9 ACK STOP CONDITION AI00792 Write Operations Following a START condition the master sends a device select code with the RW bit reset to ’0’. The ST24/25E64 acknowledge this and waits for 2 bytes of address. These 2 address bytes (8 bits each) provide access to any of the 32 blocks of 256 bytes each. Writing in the ST24/25E64 may be inhibited if input pin WC is taken high. For the ST24/25E64 versions, any write command with WC = ’1’ (during a period of time from the START condition untill the end of the 2 Bytes Address) will not modify data and will NOT be acknowledged on data bytes, as in Figure 9. Byte Write. In the Byte Write mode the master sends one data byte, which is acknowledgedby the 8/16 ST24/25E64. The master then terminates the transfer by generating a STOP condition. Page Write. The Page Write mode allows up to 32 bytes to be written in a single write cycle, provided that they are all located in the same row of 32 bytes in the memory, that is the same Address bits (b12 to b5). The master sends one up to 32 bytes of data, which are each acknowledged by the ST24/25E64. After each byte is transfered, the internal byte address counter (5 Least Significant Bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter ’roll-over’ which could result in data being overwritten. Note that for any write mode, the generation by the master of the STOP condition starts the internal memory pro- ST24E64, ST25E64 gram cycle. This STOP condition will trigger an internal memory program cycle only if the STOP condition is internally decoded right after the ACK bit; any STOP condition decoded out of this ”10th bit” time slot will not trigger the internal programming cycle. All inputs are disabled until the completion of this cycle and the ST24/25E64 will not respond to any request. Minimizing System Delay by Polling On ACK. During the internal Write cycle, the ST24/25E64 disable itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the Write time (tW) is given in the AC Characteristics table, this timing value may be reduced by an ACK polling sequence issued by the master. The sequence is: – Initial condition: a Write is in progress (see Figure 7). – Step 1: the Master issues a START condition followed by a Device Select byte. (1st byte of the new instruction) – Step 2: if the ST24/25E64 are internally writing, no ACK will be returned. The Master goes back to Step1. If the ST24/25E64have terminated the internal writing, it will issue an ACK. The ST24/25E64are ready to receive the second part of the instruction (the first byte of this instruction was already sent during Step1). Figure 7. Write Cycle Polling using ACK WRITE Cycle in Progress START Condition DEVICE SELECT with RW = 0 NO First byte of instruction with RW = 0 already decoded by ST24xxx ACK Returned YES NO Next Operation is Addressing the Memory YES Send Byte Address ReSTART STOP Proceed WRITE Operation Proceed Random Address READ Operation AI01099B 9/16 ST24E64, ST25E64 Figure 8. Write Modes Sequence with Write Control = 0 WC ACK BYTE ADDR ACK BYTE ADDR ACK DATA IN STOP DEV SEL START BYTE WRITE ACK R/W WC ACK DEV SEL START PAGE WRITE ACK BYTE ADDR ACK BYTE ADDR ACK DATA IN 1 DATA IN 2 R/W WC (cont’d) ACK DATA IN N STOP PAGE WRITE (cont’d) ACK AI01106 Read Operations On delivery, the memory content is set at all ”1’s” (or FFh). Current Address Read. The ST24/25E64 have an internal 13 bits address counter. Each time a byte is read, this counter is incremented. For the Current Address Read mode, following a START condition, the master sends a Device Select with the RW bit set to ’1’. The ST24/25E64acknowledge this and outputs the byte addressed by the internal address counter. This counter is then incremented. The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition. 10/16 Random Address Read. A dummy write is performed to load the address into the address counter, see Figure 10. This is followed by another START condition from the master and the byte address repeated with the RW bit set to ’1’. The ST24/25E64 acknowledge this and outputs the byte addressed. The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition. Sequential Read. This mode can be initiated with either a Current Address Read or a Random Address Read. However, in this case the master DOES acknowledge the data byte output and the ST24/25E64 continue to output the next byte in ST24E64, ST25E64 Figure 9. Write Modes Sequence with Write Control = 1 WC ACK BYTE ADDR ACK BYTE ADDR NO ACK DATA IN STOP DEV SEL START BYTE WRITE ACK R/W WC ACK DEV SEL START PAGE WRITE ACK BYTE ADDR ACK BYTE ADDR NO ACK DATA IN 1 DATA IN 2 R/W WC (cont’d) NO ACK DATA IN N STOP PAGE WRITE (cont’d) NO ACK AI01120 sequence. To terminate the stream of bytes, the master must NOT acknowledge the last byte output, but MUST generate a STOP condition. The output data is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. After a count of the last memory address, the address counter will ’roll-over’ and the memory will continue to output data. Acknowledge in Read Mode. In all read modes the ST24/25E64 wait for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the ST24/25E64terminate the data transfer and switch to a standby state. 11/16 ST24E64, ST25E64 Figure 10. Read Modes Sequence ACK DATA OUT STOP START DEV SEL NO ACK R/W ACK RANDOM ADDRESS READ BYTE ADDR ACK DEV SEL * ACK ACK DATA OUT 1 ACK NO ACK DATA OUT N BYTE ADDR ACK BYTE ADDR ACK DEV SEL * START START ACK R/W ACK DATA OUT R/W R/W DEV SEL * NO ACK STOP START DEV SEL SEQUENTIAL RANDOM READ BYTE ADDR R/W ACK SEQUENTIAL CURRENT READ ACK START START DEV SEL * ACK STOP CURRENT ADDRESS READ ACK DATA OUT 1 R/W NO ACK STOP DATA OUT N AI01105B Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 4th byte) must be identical. 12/16 ST24E64, ST25E64 ORDERING INFORMATION SCHEME Example: Range Operating Voltage 24 4.5V to 5.5V 25 2.5V to 5.5V ST24E64 E Extended Addressing M 1 TR Package B PSDIP8 0.25mm Frame M SO8 200mil Width Temperature Range 1 0 to 70 °C 6 –40 to 85 °C Option TR Tape & Reel Packing 3 * –40 to 125 °C Note: 3 * Temperature Range on special request only. Parts are shipped with the memory content set at all ”1’s” (FFh). For a list of available options (Operating Voltage, Range, Package, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. 13/16 ST24E64, ST25E64 PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame mm Symb Typ inches Min Max A 3.90 A1 Min Max 5.90 0.154 0.232 0.49 – 0.019 – A2 3.30 5.30 0.130 0.209 B 0.36 0.56 0.014 0.022 B1 1.15 1.65 0.045 0.065 C 0.20 0.36 0.008 0.014 D 9.20 9.90 0.362 0.390 – – – – 6.00 6.70 0.236 0.264 – – – – 7.80 – 0.307 – E 7.62 E1 e1 2.54 eA eB Typ 0.300 0.100 10.00 L 3.00 N 8 0.394 3.80 0.118 8 PSDIP8 A2 A1 B A L e1 eA eB B1 D C N E1 E 1 PSDIP-a Drawing is not o scale 14/16 0.150 ST24E64, ST25E64 SO8 - 8 lead Plastic Small Outline, 200 mils body width mm Symb Typ Min A inches Max Typ Min 2.03 A1 0.10 A2 0.080 0.25 0.004 1.78 B 0.35 0.45 – – D 5.15 E Max 0.010 0.070 0.014 0.018 – – 5.35 0.203 0.211 5.20 5.40 0.205 0.213 – – – – H 7.70 8.10 0.303 0.319 L 0.50 0.80 0.020 0.031 α 0° 10° 0° 10° N 8 C 0.20 e 1.27 CP 0.008 0.050 8 0.10 0.004 SO8b A2 A C B CP e D N E H 1 A1 α L SO-b Drawing is not to scale 15/16 ST24E64, ST25E64 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil -Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 16/16