ST92195B
32-64K ROM HCMOS MCU WITH
ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
DATA BRIEFING
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Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
0°C to +70°C operating temperature range
Up to 24 MHz. operation @ 5V±10%
Min. instruction cycle time: 165ns at 24 MHz.
32, 48, 56 or 64 Kbytes ROM
256 bytes RAM of Register file (accumulators or
index registers)
256 bytes of on-chip static RAM
2, 6 or 8 Kbytes of TDSRAM (Teletext and
Display Storage RAM)
28 fully programmable I/O pins
Serial Peripheral Interface
Flexible Clock controller for OSD, Data Slicer
and Core clocks running from a single low
frequency external crystal.
Enhanced display controller with 26 rows of
40/80 characters
– Serial and Parallel attributes
– 10x10 dot matrix, 512 ROM characters, definable by user
– 4/3 and 16/9 supported in 50/60Hz and 100/
120 Hz mode
– Rounding, fringe, double width, double height,
scrolling, cursor, full background color, halfintensity color, translucency and half-tone
modes
Teletext unit, including Data Slicer, Acquisition
Unit and up to 8 Kbytes RAM for data storage
VPS and Wide Screen Signalling slicer (on
some devices)
Integrated Sync Extractor and Sync Controller
14-bit Voltage Synthesis for tuning reference
voltage
Up to 6 external interrupts plus one NonMaskable Interrupt
8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability
16-bit watchdog timer with 8-bit prescaler
One 16-bit standard timer with 8-bit prescaler
4-channel A/D converter; 5-bit guaranteed
PSDIP56
TQFP64
See end of document for ordering information
Rich instruction set and 14 addressing modes
Versatile
development
tools,
including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and hardware
emulators with Real-Time Operating System
available from third parties
■ Pin-compatible EPROM and OTP devices
available
Device Summary
■
■
Device
Program
Memory
TDS VPS/
RAM WSS
Package
ST92195B1
32K ROM
2K
Yes
ST92195B2
32K ROM
6K
No
ST92195B3
32K ROM
6K
Yes
ST92195B4
48K ROM
6K
Yes
PSDIP56/
ST92195B5
48K ROM
8K
Yes
TQFP64
ST92195B6
56K ROM
8K
Yes
ST92195B7
64K ROM
8K
Yes
ST92T195B7
64K OTP
8K
Yes
ST92E195B7
64K EPROM
8K
Yes
CSDIP56
/CQFP64
Rev. 2.5
January 2000
1/22
1
ST92195B - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92195B microcontroller is developed and
manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register programming model for ultra-fast context switching
and real-time event response. The intelligent onchip peripherals offload the ST9 core from I/O and
data management processing tasks allowing critical application tasks to get the maximum use of
core resources. The ST92195B MCU supports low
power consumption and low voltage operation for
power-efficient and low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.
The general-purpose registers can be used as accumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges.
Two basic addressable spaces are available: the
Memory space and the Register File, which includes the control and status registers of the onchip peripherals.
1.1.2 Power Saving Modes
To optimize performance versus power consumption, a range of operating modes can be dynamically selected.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution until an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
and interrupt controller keep running at a frequen-
2/22
cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (Low power WFI).
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
1.1.3 I/O Ports
Up to 28 I/O lines are dedicated to digital Input/
Output. These lines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
timer and output, analog inputs, external interrupts
and serial or parallel I/O.
1.1.4 TV Peripherals
A set of on-chip peripherals form a complete system for TV set and VCR applications:
– Voltage Synthesis
– VPS/WSS Slicer
– Teletext Slicer
– Teletext Display RAM
– OSD
1.1.5 On Screen Display
The human interface is provided by the On Screen
Display module, this can produce up to 26 lines of
up to 80 characters from a ROM defined 512 character set. The character resolution is 10x10 dot.
Four character sizes are supported. Serial attributes allow the user to select foreground and
background colors, character size and fringe background. Parallel attributes can be used to select
additional foreground and background colors and
underline on a character by character basis.
1.1.6 Teletext and Display Storage RAM
The internal Teletext and Display storage RAM
can be used to store Teletext pages as well as Display parameters.
ST92195B - GENERAL DESCRIPTION
INTRODUCTION (Cont’d)
1.1.7 Teletext, VPS and WSS Data Slicers
The three on-board data slicers using a single external crystal are used to extract the Teletext, VPS
and WSS information from the video signal. Hardware Hamming decoding is provided.
1.1.8 Voltage Synthesis Tuning Control
14-bit Voltage Synthesis using the PWM (Pulse
Width Modulation)/BRM (Bit Rate Modulation)
technique can be used to generate tuning voltages
for TV set applications. The tuning voltage is output on one of two separate output pins.
1.1.9 PWM Output
Control of TV settings can be made with up to
eight 8-bit PWM outputs, with a maximum frequency of 23,437Hz at 8-bit resolution (INTCLK = 12
MHz). Low resolutions with higher frequency operation can be programmed.
1.1.10 Serial Peripheral Interface (SPI)
The SPI bus is used to communicate with external
devices via the SPI, or I C bus communication
standards. The SPI uses a single data line for data
input and output. A second line is used for a synchronous clock signal.
1.1.11 Standard Timer (STIM)
The ST92195B has one Standard Timer (STIM0)
that includes a programmable 16-bit down counter
and an associated 8-bit prescaler with Single and
Continuous counting modes.
1.1.12 Analog/Digital Converter (ADC)
In addition there is a 4-channel Analog to Digital
Converter with integral sample and hold, fast
5.75µs conversion time and 6-bit guaranteed resolution.
3/22
ST92195B - GENERAL DESCRIPTION
INTRODUCTION (Cont’d)
Figure 1. ST92195B Block Diagram
Up to 64
Kbytes ROM
256 bytes
RAM
256 bytes
Register File
8/16-bit
CPU
NMI
INT[7:4]
INT2
INT0
MEMORY BUS
Up to 8
Kbytes TRI
TDSRAM
P0[7:0]
I/O
PORT 2
6
P2[5:0]
I/O
PORT 3
4
P3[7:4]
I/O
PORT 4
8
P4[7:0]
I/O
PORT 5
2
P5[1:0]
DATA
SLICER
& ACQUISITIO N
UNIT
Interrupt
Management
RCCU
SYNC.
EXTRACTION
16-BIT
TIMER/
WATCHDOG
VPS/WSS
DATA
SLICER
SPI
REGISTER BUS
SDO/SDI
SCK
8
MMU
ST9+ CORE
OSCIN
OSCOUT
RESET
RESETO
I/O
PORT 0
TXCF
CVBS1
WSCR
WSCF
CVBS2
AIN[4:1]
EXTRG
ADC
MCFM
TIMING AND
CLOCK CTRL
SYNC
CONTROL
STOUT
STANDARD
TIMER
ON
SCREEN
DISPLAY
VSO[2:1]
VOLTAGE
SYNTHESIS
PWM
D/A CONVERTER
VSYNC
HSYNC/CSYNC
CSO
FREQ.
PXFM
MULTIP.
R/G/B/FB
TSLU
HT
All alternate functions (Italic characters) are mapped on Ports 0, 2, 3, 4 and 5
4/22
PWM[7:0]
ST92195B - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION
VDD
P0.3
P0.4
P0.5
P0.6
P0.7
RESET
P2.0/INT7
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
VDD
Figure 2. 64-Pin Package Pin-Out
1
64
16
48
32
VSS
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRST0
GND
N.C.
N.C.
N.C.
WSCF
VPP/WSCR
AVDD3
TEST0
MCFM
JTCK
TXCF
CVBSO
AVDD2
JTMS
CVBS2
CVBS1
AGND
N.C.
GND
AIN4/P0.2
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
B
G
R
FB
SDO/SDI/P5.1
INT2/SCK/P5.0
VDD
JTDO
N.C. = Not connected
5/22
ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
RESET Reset (input, active low). The ST9+ is initialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
R/G/B Red/Green/Blue. Video color analog DAC
outputs.
FB Fast Blanking. Video analog DAC output.
VDD Main power supply voltage (5V±10%, digital)
WSCF, WSCR Analog pins for the VPS/WSS slicer . These pins must be tied to ground or not connected.
VPP: On EPROM/OTP devices, the WSCR pin is
replaced by VPP which is the programming voltage
pin. VPP should be tied to GND in user mode.
MCFM Analog pin for the display pixel frequency
multiplier.
OSCIN, OSCOUT Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.
VSYNC Vertical Sync. Vertical video synchronisation input to OSD. Positive or negative polarity.
HSYNC/CSYNC Horizontal/Composite sync. Horizontal or composite video synchronisation input to
OSD. Positive or negative polarity.
PXFM Analog pin for the Display Pixel Frequency
Multiplier
AVDD3 Analog V DD of PLL. This pin must be tied
to VDD externally.
GND Digital circuit ground.
AGND Analog circuit ground (must be tied externally to digital GND).
CVBS1 Composite video input signal for the Teletext slicer and sync extraction.
CVBS2 Composite video input signal for the VPS/
WSS slicer. Pin AC coupled.
AVDD1, AVDD2 Analog power supplies (must be
tied externally to AVDD3).
TXCF Analog pin for the Teletext slicer line PLL.
CVBSO, JTDO, JTCK Test pins: leave floating.
TEST0 Test pins: must be tied to AVDD2.
JTRST0 Test pin: must be tied to GND.
Figure 3. 56-Pin Package Pin-Out
INT7/P2.0
RESET
P0.7
P0.6
P0.5
P0.4
P0.3
AIN4/P0.2
P0.1
P0.0
CSO/RE SET0/P3.7
P3.6
P3.5
P3.4
B
G
R
FB
SDI/SDO/ P5.1
SCK/INT2/P5. 0
VDD
JTDO
WSCF
VPP/WSCR
AVDD3
TEST 0
MCFM
JTCK
6/22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
P4.7/PWM7/EX TRG/ST OUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRSTO
GND
AGND
CVBS1
CVBS2
JTMS
AVDD2
CVBSO
TXCF
ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
Figure 4. ST92195B Required External components (56-pin package)
+5V
U1
P20
1µF
C2
S1
P07
P06
P05
P04
P03
P02
P01
P00
P37
P36
P35
P34
10k
R1
D1
1N4148
RST
L2
10uH
C4
C6
B
G
R
FB
10µF
100nF
C9
C11
22pF
4.7nF
R3
100 nF
P51
P50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P2.0/INT7
RESETN
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2/AIN4
P0.1
P0.0
P3.7/RESET0/CSO
P3.6
P3.5
P3.4
B
G
R
FB
P5.1/SDI/SDO
P5.0/SCK/INT2
VDD
JTDO
WSCF
WSCR
AVDD3
TEST0
MCFM
JTCK
SDIP56
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6 /VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3 /TSLU/HT
P4.2/PWM2
ST92195B
P4.1/PWM1
P4.0/PWM0
VSYNC
HSY NC/CSYNC
AVDD1
PXFM
JTRST0
GND
AGND
CVBS1
CVBS2
JTMS
AVDD2
CVBSO
TXCF
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
C1
P21
P22
P23
P24
P25
82pF
Y1
4Mhz
C3
+5V
82pF
P47
P46
P45
P44
P43
P42
P41
P40
L1
10uH
VSYNC
H SYNC
C5
100nF
C7
R2
C8
22pF
5.6k
C10
C12
470nF
C14
82pF
C15
100nF
10µF
4.7nF
CVBS
C13
5.6k
R4
15k
C16
2.2nF
7/22
ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
Figure 5. ST92195B Required External Components (64-pin package)
C1
1µF
10k
R1
S1
+5V
D1
1N4148
RST
C2
82pF
C4
82pF
C3
100nF
Y1
L1
P03
P04
P05
P06
P07
C5
P20
P21
P22
P23
P24
P25
4Mhz
10uH
P02
P01
P00
P37
P36
P35
P34
B
G
R
FB
C7
VSS
P0.2/AIN4
P0.1
P0.0
P3.7/RESET0/CSO
P3.6
P3.5
P3.4
B
G
R
FB
P5.1/SDI/SDO
P5.0/SCK/INT2
VDD
JTDO
ST92195B
100nF
QFP64
C12
C11
100nF
C14
C15
4.7nF
22pF
R3
5.6k
8/22
GND
EXTRG/SLOUT/P4.7/PWM7
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
HT/TSLU/P4.3/PWM3
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
CSYNC/HSYNC
AVDD1
PXFM
JTRST0
GND
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P47
P46
P45
P44
P43
P42
P41
P40
C8
C9
5.6k
C13
L2
100nF
VSYNC
HSYNC
100nF
R2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
NC
WSCF
WSCR
AVDD3
TEST0
MCFM
JTCK
TXCF
CVBSO
AVDD2
JTMS
CVBS2
CVBS1
AGND
NC
P5.0
1
2
3
4
5
6
7
8
9
10
11
12
P5.1 13
14
15
16
VDD
P0.3
P0.4
P0.5
P0.6
P0.7
RESETN
INT7/P2.0
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
VDD
10uF
100nF
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
C6
U1
10uF
+5V
10uH
22pF
C10
4.7nF
ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
P0[7:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0]
I/O Port Lines (Input/Output, TTL or CMOS compatible).
28 lines grouped into I/O ports, bit programmable
as general purpose I/O or as Alternate functions
(see I/O section).
Important: Note that open-drain outputs are for
logic levels only and are not true open drain.
1.2.1 I/O Port Alternate Functions.
Each pin of the I/O ports of the ST92195B may assume software programmable Alternate Functions
(see Table 1).
Table 1. ST92195B I/O Port Alternate Function Summary
Port
Name
General
Purpose I/O
Pin No.
Alternate Functions
TQFP64 SDIP56
P0.0
4
10
P0.1
3
9
P0.2
2
8
P0.3
63
7
I/O
P0.4
62
6
I/O
P0.5
61
5
I/O
P0.6
60
4
I/O
P0.7
59
3
I/O
P2.0
57
1
P2.1
56
56
P2.2
P2.3
P2.4
All ports useable
for general purpose I/O (input,
output or bidirectional)
55
55
54
54
53
53
I/O
I/O
AIN4
I
INT7
I
External Interrupt 7
AIN1
I
A/D Analog Data Input 1
INT5
I
External Interrupt 5
INT0
I
External Interrupt 0
AIN2
I
A/D Analog Data Input 2
INT6
I
External Interrupt 6
VSO1
O
Voltage Synthesis Output 1
NMI
I
Non Maskable Interrupt Input
AIN3
I
A/D Analog Data Input 3
INT4
I
External Interrupt 4
O
Voltage Synthesis Output 2
P2.5
52
52
P3.4
8
14
I/O
P3.5
7
13
I/O
P3.6
6
12
I/O
P3.7
5
11
P4.0
40
P4.1
P4.2
VSO2
P4.3
P4.4
A/D Analog Data Input 4
RESET0
O
Internal Reset Output
CSO
O
Composite Sync output
42
PWM0
O
PWM Output 0
41
43
PWM1
O
PWM Output 1
42
44
PWM2
O
PWM Output 2
PWM3
O
PWM Output 3
TSLU
O
Translucency Digital Output
HT
O
Half-tone Output
PWM4
O
PWM Output 4
43
44
45
46
9/22
ST92195B - GENERAL DESCRIPTION
Port
Name
General
Purpose I/O
Pin No.
Alternate Functions
TQFP64 SDIP56
P4.5
45
47
PWM5
O
PWM Output 5
P4.6
46
48
PWM6
O
PWM Output 6
EXTRG
I
A/D Converter External Trigger Input
47
49
PWM7
O
PWM Output 7
STOUT
O
Standard Timer Output
INT2
I
External Interrupt 2
SCK
O
SPI Serial Clock
SDO
O
SPI Serial Data Out
SDI
I
SPI Serial Data In
P4.7
P5.0
All ports useable
for general purpose I/O (input,
output or bidirectional)
P5.1
14
13
20
19
1.2.2 I/O Port Styles
Pins
P0[7:0]
P2[5,4,3,2]
P2[1,0]
P3.7
P3[6,5,4]
P4[7:0]
P5[1:0]
Weak Pull-Up
no
no
no
yes
no
no
no
Port Style
Standard I/O
Standard I/O
Schmitt trigger
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Reset Values
BID / OD / TTL
BID / OD / TTL
BID / OD / TTL
AF / PP / TTL
BID / OD / TTL
BID / OD / TTL
BID / OD / TTL
Legend:
AF= Alternate Function, BID = Bidirectional, OD = Open Drain
PP = Push-Pull, TTL = TTL Standard Input Levels
How to Read this Table
To configure the I/O ports, use the information in
this table and the Port Bit Configuration Table in
the I/O Ports Chapter of the datasheet.
– If WPU = yes, then the WPU can be enabled/disable by software
– If WPU = no, then enabling the WPU by software
has no effect
Port Style= the hardware characteristics fixed for
each port line.
Inputs:
– If port style = Standard I/O, either TTL or CMOS
input level can be selected by software.
– If port style = Schmitt trigger, selecting CMOS or
TTL input by software has no effect, the input will
always be Schmitt Trigger.
Weak Pull-Up = This column indicates if a weak
pull-up is present or not.
Alternate Functions (AF) = More than one AF
cannot be assigned to an external pin at the same
time:
An alternate function can be selected as follows.
AF Inputs:
– AF is selected implicitly by enabling the corresponding peripheral. Exception to this are ADC
analog inputs which must be explicitly selected
as AF by software.
10/22
ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
AF Outputs or Bidirectional Lines:
– In the case of Outputs or I/Os, AF is selected
explicitly by software.
Example 1: ADC trigger digital input
AF: EXTRG, Port: P4.7, Port Style: Standard I/O.
Write the port configuration bits (for TTL level):
P4C2.7=1
P4C1.7=0
P4C0.7=1
Enable the ADC trigger by software as described
in the ADC chapter.
Example 2: PWM 0 output
AF: PWM0, Port: P4.0
Write the port configuration bits (for output pushpull):
P4C2.0=0
P4C1.0=1
P4C0.0=1
Example 3: ADC analog input
AF: AIN1, Port : P2.1, Port style: does not apply to
analog inputs
Write the port configuration bits:
P2C2.1=1
P2C1.1=1
P2C0.1=1
11/22
ST92195B - GENERAL DESCRIPTION
1.3 MEMORY MAP
Internal ROM
The ROM memory is mapped in a single continuous area starting at address 0000h in MMU segment 00h.
Device
Size
Start
Address
End
Address
ST92195B1/B2/B3
32K
0000h
7FFFh
ST92195B4/B5
48K
0000h
BFFFh
ST92195B6
56K
0000h
DFFFh
ST92195B7
64K
0000h
FFFFh
Internal RAM, 256 bytes
The internal RAM is mapped in MMU segment
20h; from address FF00h to FFFFh.
Internal TDSRAM
The Internal TDSRAM is mapped starting at address 8000h in MMU segment 22h. It is a fully static memory.
Size
Start
Address
End
Address
ST92195B1
2K
8000h
87FFh
ST92195B2/B3/B4
6K
8000h
97FFh
ST92195B5/B6/B7
8K
8000h
9FFFh
Device
Figure 6. ST92195B Memory Map
229FFFh
Reserved
max. 8 Kbytes
TDSRAM
228000h
SEGMENT 22h
64 Kbytes
Internal
RAM
256 bytes
22C000h
22BFFFh
228000h
227FFFh
Reserved
224000h
223FFFh
Reserved
SEGMENT 21h
64 Kbytes
22FFFFh
220000h
21FFFFh
PAGE 91 - 16 Kbytes
PAGE 90 - 16 Kbytes
PAGE 89 - 16 Kbytes
PAGE 88 - 16 Kbytes
Reserved
210000h
20FFFFh
20FFFFh
PAGE 83 - 16 Kbytes
20C000h
20BFFFh
20FF 00h
SEGMENT 20h
64 Kbytes
Reserved
PAGE 82 - 16 Kbytes
208000h
207FFFh
Reserved
PAGE 81 - 16 Kbytes
204000h
203FFFh
Reserved
PAGE 80 - 16 Kbytes
200000h
00FFFFh
PAGE 3 - 16 Kbytes
00C000h
00BFFFh
SEGMENT 0
64 Kbytes
Internal ROM
max. 64 Kbytes
PAGE 2 - 16 Kbytes
008000h
007FFFh
PAGE 1 - 16 Kbytes
004000h
003FFFh
PAGE 0 - 16 Kbytes
000000h
12/22
ST92195B - ELECTRICAL CHARACTERISTICS
2 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V DD
Supply Voltage
VSS - 0.3 to V SS + 7.0
V
V SSA
Analog Ground
VSS - 0.3 to V SS + 0.3
V
V DDA
Analog Supply Voltage
V
VI
Input Voltage
VDD -0.3 to VDD +0.3
VSS - 0.3 to V DD +0.3
V
VSS - 0.3 to V DD +0.3
V AI
Analog Input Voltage (A/D Converter)
VO
Output Voltage
VSS - 0.3 to V DD + 0.3
V
TSTG
Storage Temperature
- 55 to + 150
°C
Pin Injected Current
- 5 to + 5
mA
- 50 to +5 0
mA
IINJ
V
VSSA - 0.3 to VDDA +0.3
Maximum Accumulated Pin
Injected Current In Device
Note: Stress above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
Min.
Max.
0
70
°C
TA
Operating Temperature
VDD
Supply Voltage
4.5
5.5
V
VDDA
Analog Supply Voltage (PLL)
4.5
5.5
V
fOSCE
External Oscillator Frequency
3.3
8.7
MHz
fOSCI
Internal Clock Frequency (INTCLK)
24
MHz
13/22
ST92195B - ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified)
Symbol
Parameter
Test Conditions
VIHCK
Clock In high level
External clock
VILCK
Clock in low level
External clock
VIH
Input high level
TTL
VIL
Input low level
TTL
VIH
Input high level
CMOS
VIL
Input low level
CMOS
VIHRS
Reset in high level
VILRS
Reset in low level
VHYRS
Reset in hysteresis
VIHY
P2.(1:0) input hysteresis
VIHVH
HSYNC/VSYNC input high level
VILVH
HSYNC/VSYNC input low level
VHYHV
HSYNC/VSYNC input hysteresis
VOH
Output high level
Push-pull Ild=-0.8mA
VOL
Output low level
Push-pull ld=+1.6mA
Value
Min.
Max.
0.7 V DD
Unit
V
0.3 VDD
2.0
V
V
0.8
0.8 V DD
V
V
0.2 VDD
0.7 V DD
V
V
0.3 VDD
0.3
V
V
0.9
V
0.7 V DD
V
0.3 VDD
0.5
V
V
V DD-0.8
V
0.4
V
bidir. state
IWPU
Weak pull-up current
VOL= 3V
µA
50
VOL= 7V
350
ILKIO
I/O pin input leakage current
0<VIN<VDD
-10
+10
µA
ILKRS
Reset pin input
0<VIN<VDD
-10
+10
µA
ILKAD
A/D pin input leakage current
alternate funct. op. drain
-10
+10
µA
ILKOS
OSCIN pin input leakage current
0<VIN<VDD
-10
+10
µA
14/22
ST92195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
PIN CAPACITANCE
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified))
Symbol
C IO
Parameter
Value
Conditions
min
Pin Capacitance Digital Input/Output
max
10
Unit
pF
CURRENT CONSUMPTION
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified)
Symbol
Parameter
Value
Condition s
min
typ.
max
Unit
IDD1
Run Mode Current
notes 1,2; all On
70
100
mA
IDDA1
Run Mode Analog Current
(pin VDDA )
Timing Controller On
35
50
mA
IDD2
HALT Mode Current
notes 1,4
10
100
µA
IDDA2
HALT Mode Analog Current
(pin VDDA )
notes 1,4
40
100
µA
Notes:
1. Port 0 is configured in push-pull output mode (output is high). Ports 2, 3, 4 and 5 are configured in bi-directional weak pull-up mode resistor.
The external CLOCK pin (OSCIN) is driven by a square wave external clock at 8 MHz. The internal clock prescaler is in divide-by-1 mode.
2. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock.
All peripherals working including Display.
3. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock.
The TDSRAM interface and the Slicers are working; the Display controller is not working.
4. VSYNC and HSYNC tied to VSS. External CLOCK pin (OSCIN) is hold low. All peripherals are disabled.
EXTERNAL INTERRUPT TIMING TABLE (rising or falling edge mode)
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified))
Symbol
Parameter
Conditions
INTCLK=24 MHz.
Value
min
Unit
max
TwLR
low level pulse width
TpC+12
95
ns
TwHR
high level pulse width
TpC+12
95
ns
TpC is the INTCLK clock period.
15/22
ST92195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
SPI TIMING TABLE
(VDD= 5V +/-10%; TA = 0 to 70°C; Cload= 50pF)
Symbol
Parameter
Conditi on
Value
min
max
tbd
Unit
TsDI
Input Data Set-up Time
ThDI
Input Data Hold Time
TdOV
SCK to Output Data Valid
ThDO
Output Data Hold Time
tbd
ns
TwSKL
SCK Low Pulse Width
tbd
ns
TwSKH
SCK High Pulse Width
tbd
ns
(1)
OSCIN/2 as internal Clock
1INTCLK
ns
+100ns
ns
tbd
ns
(1) TpC is the OSCIN clock period; TpMC is the “Main Clock Frequency” period.
SKEW CORRECTOR TIMING TABLE
(VDD= 5V +/-10%, TA = 0 to 70°C, unless otherwise specified)
Symbol
Tjskw
Parameter
Jitter on RGB output
Conditions
36 MHz Skew corrector clock frequency
max
Value
Unit
5*
ns
(*) The OSD jitter is measured from leading edge to leading edge of a single character row on consecutive TV lines. The value is an envelope
of 100 fields
16/22
ST92195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
OSD DAC CHARACTERISTICS (ROM DEVICES ONLY)
(VDD= 5V +/-10%, TA = 0 to 70°C, unless otherwise specified).
Symbol
Parameter
Conditio ns
Value
Unit
min
typical
max
300
500
700
Ohm
code= 111
1.000
1.250
V
code= 011
0.450
0.500
V
code= 000
0.025
0.080
V
V
Output impedance: FB,R,G,B
Output voltage: FB,R,G,B
Cload= 20pF
RL = 100K
FB= 1
2.4
2.7
3.4
FB= 0
0
0.025
0.080
V
+/-5
%
Global voltage accuracy
OSD DAC CHARACTERISTICS (EPROM AND OTP DEVICES ONLY)
(VDD= 5V +/-10%, TA = 0 to 70°C, unless otherwise specified).
Symbol
Parameter
Conditions
Value
Unit
min
typical
max
300
500
700
Ohm
code= 111
1.100
1.400
V
code= 011
0.600
0.800
V
code= 000
0.200
0.350
V
Output impedance: FB,R,G,B
Output voltage: FB,R,G,B
FB= 1
FB= 0
Global voltage accuracy
Cload= 20pF
RL = 100K
VDD-0.8
V
0.400
V
+/-5
%
17/22
ST92195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
A/D CONVERTER, EXTERNAL TRIGGER TIMING TABLE
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified
Symbol
Parameter
Tlow
Pulse Width
Thigh
Pulse Distance
Text
Period/fast Mode
Tstr
Start Conversion Delay
OSCIN divide by
2;min/max
Value
OSCIN divide
by 1; min/max
min
max
1.5
INTCLK
Unit
ns
ns
78+1
INTCLK
µs
0.5
1.5
INTCLK
Core Clock issued by Timing Controller
Tlow
Pulse Width
ns
Thigh
Pulse Distance
ns
Text
Period/fast Mode
µs
Tstr
Start Conversion Delay
ns
A/D CONVERTER. ANALOG PARAMETERS TABLE
(VDD= 5V +/-10%; TA = 0 to 70°C; unless otherwise specified))
Parameter
Value
typ (*)
Analog Input Range
Conversion Time Fast/Slow
Sample Time Fast/Slow
Power-up Time
Resolution
Differential Non Linearity
Unit
min
max
(**)
VSS
V DD
V
Note
78/138
INTCLK
(1,2)
51.5/87.5
INTCLK
(1)
µs
60
8
bits
1.5
2.5
LSBs
(4)
Integral Non Linearity
2
3
LSBs
(4)
Absolute Accuracy
2
3
LSBs
(4)
Input Resistance
1.5
Kohm
(3)
Hold Capacitance
1.92
pF
Notes: (*)
(**)
(1)
(2)
(3)
(4)
18/22
The values are expected at 25 Celsius degrees with VDD= 5V
’LSBs’ , as used here, as a value of VDD/256
@ 24 MHz external clock
including Sample time
it must be considered as the on-chip series resistance before the sampling capacitor
DNL ERROR= max {[V(i) -V(i-1)] / LSB-1}
INL ERROR= max {[V(i) -V(0)] / LSB-i}
ABSOLUTE ACCURACY= overall max conversion error
ST92195B - GENERAL INFORMATION
3 GENERAL INFORMATION
3.1 PACKAGE MECHANICAL DATA
Figure 7. 56-Pin Shrink Plastic Dual In Line Package, 600-mil Width
Dim.
mm
Min
Typ
A
inches
Max
Min
Typ
6.35
A1
0.38
0.015
A2
3.18
4.95 0.125
0.195
b
0.41
0.016
b2
0.89
0.035
C
0.20
0.38 0.008
D
50.29
53.21 1.980
E
E1
15.01
12.32
1.78
eA
15.24
eB
L
2.92
PDIP56S
0.015
2.095
0.591
14.73 0.485
e
Max
0.250
0.580
0.070
0.600
17.78
0.700
5.08 0.115
0.200
Number of Pins
N
56
Figure 8. 64-Pin Thin Quad Flat Package
Dim
mm
Min
Typ
A
Min
Typ
Max
1.60
0.063
0.15 0.002
0.006
A1
0.05
A2
1.35 1.40 1.45 0.053 0.055 0.057
B
0.30 0.37 0.45 0.012 0.015 0.018
C
0.09
0.20 0.004
0.008
D
16.00
0.630
D1
14.00
0.551
D3
12.00
0.472
E
16.00
0.630
E1
14.00
0.551
E3
12.00
0.472
e
0.80
K
L
L1
inches
Max
0°
3.5°
0.031
7°
0.45 0.60 0.75 0.018 0.024 0.030
L1
1.00
L
0.039
Number of Pins
N
64
ND
16
NE
16
K
19/22
ST92195B - GENERAL INFORMATION
PACKAGE MECHANICAL DATA (Cont’d)
Figure 9. 56-Pin Shrink Ceramic Dual In Line Package, 600-mil Width
Dim.
mm
Min
Typ
A
Min
Typ
4.17
Max
0.164
A1
0.76
B
0.38
0.46
0.56 0.015 0.018 0.022
B1
0.76
0.89
1.02 0.030 0.035 0.040
C
0.23
0.25
0.38 0.009 0.010 0.015
D
50.04 50.80 51.56 1.970 2.000 2.030
D1
E1
0.030
48.01
1.890
14.48 14.99 15.49 0.570 0.590 0.610
e
1.78
0.070
G
14.12 14.38 14.63 0.556 0.566 0.576
G1
18.69 18.95 19.20 0.736 0.746 0.756
G2
CDIP56SW
inches
Max
1.14
0.045
G3
11.05 11.30 11.56 0.435 0.445 0.455
G4
15.11 15.37 15.62 0.595 0.605 0.615
L
2.92
S
5.08 0.115
1.40
0.200
0.055
Number of Pins
N
56
Figure 10. 64-Pin Ceramic Quad Flat Package
Dim
mm
Min
Typ
A
A1
B
inches
Max
Min
Typ
3.27
0.50
0.020
0.30 0.35 0.45 0.012 0.014 0.018
C
0.13 0.15 0.23 0.005 0.006 0.009
D
16.65 17.20 17.75 0.656 0.677 0.699
D1
13.57 13.97 14.37 0.534 0.550 0.566
D3
12.00
0.472
e
0.80
0.031
G
12.70
0.500
G2
0.96
0.038
L
0.35 0.80
0.014 0.031
0
8.31
0.327
Number of Pins
CQFP064W
20/22
Max
0.129
N
64
ST92195B - GENERAL INFORMATION
3.2 ORDERING INFORMATION
Each device is available for production in a user
programmable version (OTP) as well as in factory
coded version (ROM). OTP devices are shipped to
customer with a default blank content FFh, while
ROM factory coded parts contain the code sent by
customer. The common EPROM versions for debugging and prototyping features the maximum
memory size and peripherals of the family. Care
must be taken to only use resources available on
the target device.
3.2.1 Transfer Of Customer Code
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file generated by the development tool. All unused bytes
must be set to FFh.
Figure 11. ROM Factory Coded Device Types
TEMP.
DEVICE PACKAGE RANGE / XXX
Code name (defined by STMicroelectronics)
1= standard 0 to +70 °C
B= Plastic DIP56
T= Plastic TQFP64
ST92195B1
ST92195B2
ST92195B3
ST92195B4
ST92195B5
ST92195B6
ST92195B7
Figure 12. OTP User Programmable Device Types
DEVICE PACKAGE
TEMP.
RANGE / XXX
Code name (defined by STMicroelectronics)
1= 0 to +70 °C
B= Plastic DIP56
T= Plastic TQFP64
ST92T195B7
Figure 13. EPROM User Programmable Device Types
DEVICE PACKAGE
TEMP.
RANGE
0= 25 °C
B= Ceramic DIP 56 pin
T= Ceramic QFP 64 pin
ST92E195B7
21/22
ST92195B - GENERAL INFORMATION
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved.
Purchase of I2 C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
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22/22