STLC3055N
WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT
1
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
FEATURES
Figure 1. Package
MONOCHIP SLIC OPTIMISED FOR WLL &
VoIP APPLICATIONS
IMPLEMENT ALL KEY FEATURES OF THE
BORSHT FUNCTION
SINGLE SUPPLY (5.5 TO 12V)
BUILT IN DC/DC CONVERTER CONTROLLER
SOFT BATTERY REVERSAL WITH
PROGRAMMABLE TRANSITION TIME.
ON-HOOK TRANSMISSION.
PROGRAMMABLE OFF-HOOK DETECTOR
THRESHOLD
METERING PULSE GENERATION AND
FILTER
INTEGRATED RINGING
INTEGRATED RING TRIP
PARALLEL CONTROL INTERFACE (3.3V
LOGIC LEVEL)
PROGRAMMABLE CONSTANT CURRENT FEED
SURFACE MOUNT PACKAGE
INTEGRATED THERMAL PROTECTION
DUAL GAIN VALUE OPTION
BCD III S, 90V TECHNOLOGY
-40 TO +85°C OPERATING RANGE
TQFP44
Table 1. Order Codes
Part Number
Package
STLC3055N
E-STLC3055N
TQFP44
TQFP44
(*)
(*) ECOPACK® (see Section 9)
2
DESCRIPTION
The STLC3055N is a SLIC device specifically designed for WLL (Wireless Local Loop) and ISDNTerminal Adaptors and VoIP applications. One of
the distinctive characteristic of this device is the
ability to operate with a single supply voltage (from
+5.5V to +12V) and self generate the negative battery by means of an on chip DC/DC converter controller that drives an external MOS switch.
Figure 2. Block Diagram
PD
GAIN
SETTING
D0
D1
D2
DET
INPUT LOGIC AND DECODER
OUTPUT LOGIC
BGND
Status and functions
TIP
TX
RX
SUPERVISION
LINE
OUTPUT
DRIVER
STAGE
ZAC1
ZAC
RING
AC PROC
RS
CREV
ZB
DC PROC
CLK
RSENSE
GATE
VF
DC/DC
CKTTX
CSVR
CONV.
CTTX1
CTTX2
TTX PROC
REFERENCE
FTTX
Vcc
Vss
Agnd
CVCC
VPOS
VBAT
VOLT.
REG.
Vbat
RTTX
February 2006
CAC
ILTF RD IREF RLIM RTH
AGND
Rev. 10
1/25
STLC3055N
2 DESCRIPTION (continued)
The battery level is properly adjusted depending on the operating mode. A useful characteristic for these
applications is the integrated ringing generator.
The control interface is a parallel type with open drain output and 3.3V logic levels.
The metering pulses are generated on chip starting from two logic signals (0, 3.3V) one define the metering pulse frequency and the other the metering pulse duration. An on chip circuit then provides the proper
shaping and filtering. Metering pulse amplitude and shaping (rising and decay time) can be programmed
by external components. A dedicated cancellation circuit avoid possible CODEC input saturation due to
Metering pulse echo.
Constant current feed can be set from 20mA to 40mA. Off-hook detection threshold is programmable from
5mA to 9mA.
The device, developed in BCDIIIS technology (90V process), operates in the extended temperature range
and integrates a thermal protection that sets the device in power down when Tj exceeds 140°C.
N.C.
VBAT
BGND
41
RING
TIP
42
N.C.
N.C.
43
N.C.
CREV
44
N.C.
VBAT1
Figure 3. Pin Connection
40
39
38
37
36
35
34
RTH
29
IREF
N.C.
6
28
RLIM
N.C.
7
27
AGND
DET
8
26
CVCC
CKTTX
9
25
VPOS
CTTX1
10
24
RSENSE
CTTX2
11
23
GATE
12
13
14
15
16
17
18
19
20
21
22
CLK
30
5
VF
PD
GAIN SET
TX
RD
ZB
31
4
CAC
3
RS
D2
ZAC
ILTF
RX
CSVR
32
ZAC1
33
2
FTTX
1
D1
RTTX
D0
D00TL488-MOD
Table 2. Absolute Maximum Ratings
Symbol
Vpos
A/BGND
Parameter
Positive Supply Voltage
AGND to BGND
Unit
-0.4 to +13
V
-1 to +1
V
-0.4 to 5.5
V
Max. junction Temperature
150
°C
Vbtot (1)
Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device supply
pins).
90
V
ESD
RATING
Human Body Model
±1750
V
Charged Device Model
±500
V
Vdig
Tj
Pin D0, D1, D2, DET, CKTTX
Value
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.
RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)
2/25
STLC3055N
Table 3. Operating Range
Symbol
Parameter
Value
5.5 to +12
V
AGND to BGND
-100 to +100
mV
Vdig
Pin D0, D1, D2, DET, CKTTX, PD
-0.25 to 5.25
V
Top
Ambient Operating Temperature Range
-40 to +85
°C
-74 max.
V
Vpos
A/BGND
Vbat (1)
Positive Supply Voltage
Unit
Self Generated Battery Voltage
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.
RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 11)
Table 4. Thermal Data
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction to Ambient
Typ.
Value
Unit
60
°C/W
Table 5. Pin Description
N°
Pin
1
D0
Control Interface: input bit 0.
Function
2
D1
Control Interface: input bit 1.
3
D2
Control interface: input bit 2.
4
PD
Power Down input. Normally connected to CVCC (or to logic level high).
5
Gain
SET
6,7,36,
38,39,40,42
NC
Not connected.
8
DET
Logic interface output of the supervision detector (active low).
9
CKTTX
Metering pulse clock input (12 KHz or 16KHz square wave).
10
CTTX1
Metering burst shaping external capacitor.
11
CTTX2
Metering burst shaping external capacitor.
12
RTTX
Metering pulse cancellation buffer output. TTX filter network should be connected to this
point. If not used should be left open.
13
FTTX
Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering.
14
RX
15
ZAC1
RX buffer output, (the AC impedance is connected from this node to ZAC).
16
ZAC
AC impedance synthesis.
17
RS
Protection resistors image (the image resistor is connected from this node to ZAC).
18
ZB
Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from
this node to AGND. ZA impedance is connected from this node to ZAC1).
19
CAC
20
TX
4 wire output port (TX output). The signal is referred to AGND. If connected to single supply
CODEC input it must be DC decoupled with proper capacitor.
21
VF
Feedback input for DC/DC converter controller.
Control gain interface: 0 Level Rxgain = 0dB Txgain = -6dB
1 Level Rxgain = +6dB Txgain = -12dB
4 wire input port (RX input). A 100kΩ external resistor must be connected to AGND to bias
the input stage. This signal is referred to AGND. If connected to single supply CODEC
output it must be DC decoupled with proper capacitor.
AC feedback input, AC/DC split capacitor (CAC).
3/25
STLC3055N
Table 5. (continued)
N°
Pin
Function
22
CLK
Power Switch Controller Clock (typ. 125KHz). This pin can also be connected to CVCC or
AGND. When the CLK pin is connected to CVCC an auto-oscillation is internally generated
and it is used instead of the external clock. When the CLK pin is connected to AGND, the
GATE output is disabled.
23
24
GATE
25
3
Driver for external Power MOS transistor (P-channel).
RSENSE Voltage input for current sensing. RSENSE should be connected close to this pin and
VPOS pin. The PCB layout should minimize the extra resistance introduced by the copper
tracks.
VPOS
Positive supply
26
CVCC
Internal positive voltage supply filter.
27
AGND
Analog Ground, must be shorted with BGND.
28
RLIM
Constant current feed programming pin (via RLIM). RLIM should be connected close to this
pin and AGND pin to avoid noise injection.
29
IREF
Internal bias current setting pin. RREF should be connected close to this pin and AGND pin
to avoid noise injection.
30
RTH
Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin
and AGND pin to avoid noise injection.
31
RD
DC feedback and ring trip input. RD should be connected close to this pin and AGND pin to
avoid noise injection.
32
ILTF
Transversal line current image output.
33
CSVR
Battery supply filter capacitor.
34
BGND
Battery Ground, must be shorted with AGND.
35
VBAT
Regulated battery voltage self generated by the device via DC/DC converter. Must be
shorted to VBAT1.
37
RING
2 wire port; RING wire (Ib is the current sunk into this pin).
41
TIP
43
CREV
2 wire port; TIP wire (Ia is the current sourced from this pin).
Reverse polarity transition time control. One proper capacitor connected between this pin
and AGND is setting the reverse polarity transition time. This is the same transition time
used to shape the "trapezoidal ringing" during ringing injection.
44
VBAT1
Frame connection. Must be shorted to VBAT.
FUNCTIONAL DESCRIPTION
The STLC3055N is a device specifically developed for WLL VoIP and ISDN-TA applications.
It is based on a SLIC core, on purpose optimised for these applications, with the addition of a DC/DC converter controller to fulfil the WLL and ISDN-TA design requirements.
The SLIC performs the standard feeding, signalling and transmission functions.
It can be set in four different operating modes via the D0, D1, D2 pins of the control logic interface (0 to
3.3V logic levels). The loop status is carried out on the DET pin (active low).
The DET pin is an open drain output to allow easy interfacing with both 3.3V and 5V logic levels.
The four possible SLIC’s operating modes are:
■
Power Down
■
High Impedance Feeding (HI-Z)
■
Active
■
Ringing
4/25
STLC3055N
Table 6 shows how to set the different SLIC operating modes.
Table 6. SLIC Operating Modes.
PD
D0
D1
D2
Operating Mode
0
0
0
X
Power Down
1
0
0
X
H.I. Feeding (HI-Z)
1
0
1
0
Active Normal Polarity
1
0
1
1
Active Reverse Polarity
1
1
1
0
Active TTX injection (N.P.)
1
1
1
1
Active TTX injection (R.P.)
1
1
0
0/1
Ring (D2 bit toggles @ fring)
3.1 DC/DC Converter
The DC/DC converter controller is driving an external power MOS transistor (P-Channel) in order to generate the negative battery voltage needed for device operation.
The DC/DC converter controller is synchronised with an external CLK (125KHz typ.)or with an internal
clock generated when the pin CLK is connected to CVCC. One sensing resistor in series to Vpos supply
allows to fix the maximum allowed input peak current. This feature is implemented in order to avoid overload on Vpos supply in case of line transient (ex. ring trip detection).
The typical value is obtained for a sensing resistor equal to 110mΩ that will guarantee an average current
consumption from Vpos < 700mA. When in on-hook the self generated battery voltage is set to a predefined value.
This value can be adjusted via one external resistor (RF1) and it is typical -50V. When RING mode is selected this value is increased to -70V typ.
Once the line goes in off-hook condition, the DC/DC converter automatically adjust the generated battery
voltage in order to feed the line with a fixed DC current (programmable via RLIM) optimising in this way
the power dissipation.
3.2 OPERATING MODES
3.2.1 Power Down
When this mode is selected the SLIC is switched off and the TIP and RING pins are in high impedance.
Also the line detectors are disabled therefore the off-hook condition cannot be detected.
This mode can be selected in emergency condition when it is necessary to cut any current delivered to the
line.
This mode is also forced by STLC3055N in case of thermal overload (Tj > 140°C).
In this case the device goes back to the previous status as soon as the junction temperature decrease
under the hysteresis threshold.
No AC transmission is possible in this mode.
3.2.2 High Impedance Feeding (HI-Z)
This operating mode is normally selected when the telephone is in on-hook in order to monitor the line
status keeping the power consumption at the minimum.
The output voltage in on-hook condition is equal to the self generated battery voltage (-50V typ).
When off-hook occurs the DET becomes active (low logic level).
5/25
STLC3055N
The off-hook threshold in HI-Z mode is the same value as programmed in ACTIVE mode.
The DC characteristic in HI-Z mode is just equal to the self generated battery with 2x(1600Ω+Rp) in series
(see fig. 4), where Rp is the external protection resistance.
No AC transmission is possible in this mode.
Figure 4. DC Characteristic in HI-Z Mode.
IL
Vbat
2x(R1+Rp)
Slope: 2x(R1+Rp)
(R1=1600ohm)
VL
Vbat (-50V)
3.2.3 Active
3.2.3.1 DC Characteristics & Supervision
When this mode is selected the STLC3055N provides both DC feeding and AC transmission.
The STLC3055N feeds the line with a constant current fixed by RLIM (20mA to 40mA range). The on-hook
voltage is typically 40V allowing on-hook transmission; the self generated Vbat is -50V typ.
If the loop resistance is very high and the line current cannot reach the programmed constant current feed
value, the STLC3055N behaves like a 40V voltage source with a series impedance equal to the protection
resistors 2xRp (typ. 2x50Ω). Fig. 5 shows the typical DC characteristic in ACTIVE mode.
Figure 5. DC Characteristic in ACTIVE Mode
IL
Ilim
(20 to
40mA)
2Rp
10V
VL
Vbat (-50V)
The line status (on/off hook) is monitored by the SLIC’S supervision circuit. The off-hook threshold can
be programmed via the external resistor RTH in the range from 5mA to 9mA.
Independently on the programmed constant current value, the TIP and RING buffers have a current
source capability limited to 80mA typ. Moreover the power available at Vbat is controlled by the DC/DC
converter that limits the peak current drawn from the Vpos supply. The maximum allowed current peak is
set by RSENSE resistor.
3.2.3.2 AC Characteristics
The SLIC provides the standard SLIC transmission functions:
Once in active mode the SLIC can operate with two different Tx, Rx Gain. Setting properly by the Gain set
6/25
STLC3055N
control bit (see table 7).
Table 7. Gain Set in Active Mode
Gain set
4 to 2 wire Gain
2 to 4 wire Gain
Impedance Synthesis Scale Factor
0
0dB
-6dB
x 50
1
+6dB
-12dB
x 25
■
Input impedance synthesis: can be real or complex and is set by a scaled (x50 or x25) external ZAC
impedance.
■
Transmit and receive: The AC signal present on the 2W port (TIP/RING) is transferred to the TX output
with a -6dB or -12dB gain and from the RX input to the 2W port with a 0dB or +6dB gain.
2 to 4 wire conversion: The balance impedance can be real or complex, the proper cancellation is
obtained by means of two external impedance ZA and ZB
Once in Active mode (D1=1) the SLIC can operate in different states setting properly D0 and D2 control
bits (see also Table 8).
■
Table 8. SLIC states in ACTIVE mode
D0
D1
D2
0
1
0
Active Normal Polarity
Operating Mode
0
1
1
Active Reverse Polarity
1
1
0
Active TTX injection (N.P.)
1
1
1
Active TTX injection (R.P.)
3.2.3.3 Polarity Reversal
The D2 bit controls the line polarity, the transition between the two polarities is performed in a "soft" way.
This means that the TIP and RING wire exchange their polarities following a ramp transition (see fig.6).
The transition time is controlled by an external capacitor CREV. This capacitor is also setting the shape
of the ringing trapezoidal waveform. When the control pins set battery reversal the line polarity is reversed
with a proper transition time set via an external capacitor (CREV).
Figure 6. TIP/RING Typical Transition from Direct to Reverse Polarity
GND
TIP
4V typ.
40V typ
ON-HOOK
dV/dT set
by CREV
RING
3.2.3.4 Metering Pulse Injection (Ttx)
The metering pulses circuit consists of a burst shaping generator that gives a square wave shaped and a
low pass filter to reduce the harmonic distortion of the output signal.
The metering pulse is obtained starting from two logic signals:
■
CKTTX: is a square wave at the TTX frequency (12 or 16KHz) and should be permanently applied to
7/25
STLC3055N
the CKTTX pin or at least for all the duration of the TTX pulse (including rising and decay phases).
D0: enable the TTX generation circuit and define the TTX pulse duration.
These two signals are processed by a dedicated circuitry integrated on chip that generate the metering
pulse as an amplitude modulated shaped squarewave (SQTTX) (see fig.7).
■
Both the amplitude and the envelope of the squarewave (SQTTX) can be programmed by means of external components. In particular the amplitude is set by the two resistors RLV and the shaping by the capacitor CS.
Figure 7. Metering Pulse Generation Circuit.
Low Pass Filter
C1
CTTX1
RLV
BURST
SHAPING
SQTTX
CS
RTTX
R2 FTTX OP1
R1
+
GENERATOR
CFL
C2
Sinusoidal wave
pulse metering
RLV
CTTX2
D0
CKTTX
Required external components vs. filter order.
Order
CFL
1
X
2
3
X
R1
C1
R2
C2
THD
X
X
X
X
6%
X
X
X
X
3%
13%
Square wave pulse metering
The waveform so generated is then filtered and injected on the line.
The low pass filter can be obtained using the integrated buffer OP1 connected between pin FTTX (OP1
non inverting input) and RTTX (OP1 output) (see fig.7) and implementing a "Sallen and Key" configuration.
Depending on the external components count it is possible to build an optimised application depending
on the distortion level required. In particular harmonic distortion levels equal to 13%, 6% and 3% can be
obtained respectively with first, second and third order filters (see fig.7).
The circuit showed in the "Application diagram" is related to the simple first order filter.
Once the shaped and filtered signal is obtained at RTTX buffer output it is injected on the TIP/RING pins
with a +6dB gain or +12dB gain.
It should be noted that this is the nominal condition obtained in presence of ideal TTX echo cancellation
(obtained via proper setting of RTTX and CTTX).
In addition the effective level obtained on the line will depend on the line impedance and the protection resistors value. In the typical application (TTX line impedance =200Ω, RP = 50Ω, and ideal TTX echo cancellation) the metering pulse level on the line will be 1.33 or 2.66 times the level applied to the RTTX pin.
As already mentioned the metering pulse echo cancellation is obtained by means of two external components (RTTX and CTTX) that should match the line impedance at the TTX frequency. This simple network
has a double effect:
■
Synthesize a low output impedance at the TIP/RING pins at the TTX frequency.
■
Cut the eventual TTX echo that will be transferred from the line to the TX output.
8/25
STLC3055N
3.2.4 Ringing
When this mode is selected STLC3055N self generate an higher negative battery (-70V typ.) in order to
allow a balanced ringing signal of typically 65Vpeak.
In this condition both the DC and AC feedback are disabled and the SLIC line drivers operate as voltage
buffers. The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in
fact controls the line polarity (0=direct; 1=reverse). As in the ACTIVE mode the line voltage transition is
performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see fig.8).
The shaping is defined by the CREV external capacitor.
Selecting the proper capacitor value it is possible to get different crest factor values.
The following table shows the crest factor values obtained with a 20Hz and 25Hz ring frequency and with
1REN. These value are valid either with European or USA specification
Figure 8. TIP/RING Typical Ringing Waveform
GND
TIP
2.5V typ.
65V
typ.
dV/dT set
by CREV
RING
VBAT
2.5V typ.
Table 9. :
CREV
CREST FACTOR @20Hz
CREST FACTOR @25Hz
22nF
1.2
1.26
27nF
1.25
1.32
33nF
1.33
Not significant (*)
(*) Distorsion already less than 10%.
The ring trip detection is performed sensing the variation of the AC line impedance from on hook (relatively
high) to off-hook (low). This particular ring trip method allows to operate without DC offset superimposed
on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given
negative battery. It should be noted that such a method is optimised for operation on short loop applications and may not operate properly in presence of long loop applications (> 500Ω ). Once ring trip is detected, the DET output is activated (logic level low), at this point the card controller or a simple logic circuit
should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3055N
in the proper operating mode (normally ACTIVE).
3.2.4.1 Ring Level in Presence of More Telephone in Parallel
As already mentioned above the maximum current that can be drawn from the Vpos supply is controlled
and limited via the external RSENSE. This will limit also the power available at the self generated negative
battery.
If for any reason the ringer load will be too low the self generated battery will drop in order to keep the
power consumption to the fixed limit and therefore also the ring voltage level will be reduced.
In the typical application with RSENSE = 110mΩ the peak current from Vpos is limited to about 900mA,
which correspond to an average current of 700mA max. In this condition the STLC3055N can drive up to
9/25
STLC3055N
3REN with a ring frequency fr=25Hz (1REN = 1800Ω + 1.0µF, European standard).
In order to drive up to 5REN (1REN= 6930Ω + 8µF, US standard) it is necessary to modify the external
components as follows:
CREV = 15nF
RD = 2.2KΩ
Rsense = 100mΩ
3.3 Layout Recommendation
A properly designed PCB layout is a basic issue to guarantee a correct behaviour and good noise performances. Noise sources can be identified in not enough good grounds, not enough low impedance supplies and parasitic coupling between PCB tracks and high impedance pins of the device.
Particular care must be taken on the ground connection and in this case the star configuration allows surely to avoid possible problems (see Application Diagram Figg. 9 and 10).
The ground of the power supply (VPOS) has to be connected to the center of the star, let’s call this point
Supply GND. This point should show a resistance as low as possible, that means it should be a ground
plane.
In particular to avoid noise problems the layout should prevent any coupling between the DC/DC converter components that are referred to PGND (CVPOS, CD, L) and analog pins that are referred to AGND (ex:
RD, IREF, RTH, RLIM, VF). AGND and BGND must be shorter together. The GND connection of protection components have to be connected to the Supply GDND.
As a first reccomendation the components CV, L, D1, CVPOS, RSENSE should be kept as close as possible to each other and isolated from the other components.
Additional improvements can be obtained:
■ decoupling the center of the star from the analog ground of STLC3055N using small chokes.
■ adding a capacitor in the range of 100nF between VPOS and AGND in order to filter the switch
frequency on VPOS.
3.4 External Components List
In order to properly define the external components value the following system parameters have to be defined:
■
The AC input impedance shown by the SLIC at the line terminals "Zs" to which the return loss
measurement is referred. It can be real (typ. 600Ω) or complex.
■
The AC balance impedance, it is the equivalent impedance of the line "Zl" used for evaluation of the
trans-hybrid loss performances (2/4 wire conversion). It is usually a complex impedance.
■
The value of the two protection resistors Rp in series with the line termination. The line impedance at
the TTX frequency "Zlttx".
■
The metering pulse level amplitude measured at line termination "VLOTTX". In case of low order
filtering, VLOTTX represents the amplitude (Vrms) of the fundamental frequency component. (typ 12 or
16KHz).
■
Pulse metering envelope rise and decay time constant "τ".
■
The slope of the ringing waveform "∆VTR/∆T ".
■
The value of the constant current limit current "Ilim".
■
The value of the off-hook current threshold "ITH".
■
The value of the ring trip rectified average threshold current "IRTH".
■
The value of the required self generated negative battery "VBATR" in ring mode (max value is 70V).
This value can be obtained from the desired ring peak level + 5V.
■
The value of the maximum current peak sunk from Vpos "IPK".
10/25
STLC3055N
Table 10. External Components
Name
Function
Formula
100kΩ 5%
RRX
Rx input bias resistor
RREF
Bias setting current
RREF = 1.3/Ibias
Ibias = 50µA
CSVR
Negative Battery Filter
CSVR = 1/(2π ⋅ fp ⋅ 1.8MΩ)
fp = 50Hz
Ring Trip threshold setting
resistor
RD = 100/IRTH
2KΩ < RD < 5KΩ
RD
CAC
Rp > 30Ω
RLIM
Current limiting programming
RLIM = 1300/Ilim
32.5kΩ < RLIM < 65kΩ
RTH
Off-hook threshold programming
(ACTIVE mode)
RTH = 290/ITH
27kΩ < RTH < 52kΩ
Reverse polarity transition time
programming
CREV = ((1/3750) · ∆T/∆VTR)
CREV
RDD
26kΩ 1%
1.5nF 10%
100V
4.12kΩ 1%
@ IRTH = 24mA
22µF 20% 15V
@ RD = 4.12kΩ
AC/DC split capacitance
Line protection resistor
RP
Typ. Value
50Ω 1%
52.3kΩ 1%
@ Ilim = 25mA
32.4kΩ 1%
@ITH = 9mA
22nF 10% 10V
@ 12V/ms
100kΩ
Pull up resistors
CVCC
Internally supply filter capacitor
100nF 20% 10V
CVpos
Positive supply filter capacitor
with low impedance for switch
mode power supply
100µF(4)
CV
CVB
CRD (6)
100µF 20% 100V (5)
Battery supply filter capacitor with
low impedance for switch mode
power supply
High frequency noise filter
470nF 20% 100V
High frequency noise filter
100nF 10% 15V
Q1
DC/DC converter switch P ch.
MOS transistor
RDS(ON)≤1.2Ω,VDS = -100V
Total gate charge=20nC max.
with VGS=4.5V and VDS=1V
ID>500mA
D1
DC/DC converter series diode
Vr > 100V, tRR ≤ 50ns
SMBYW01-200
or equivalent
RSENSE = 100mV/IPK
110mΩ
@IPK = 900mA
RSENSE DC/DC converter peak current
limiting
RF1
Negative battery programming
level
RF2
Negative battery programming level
L
DC/DC converter inductor
250KΩ<RF1<300KΩ (7)
Possible choiches:
IRF9510 or IRF9520 or
IRF9120 or equivalent
300kΩ 1%
@ VBATR = -70V
9.1kΩ 1%
DC resistance ≤ 0.1Ω (8)
L=100µH
SUMIDA CDRH125 or equivalent
Table 11. External Components @Gain Set = 0
Name
Function
Formula
Typ. Value
RS
Protection resistance image
RS = 50 ⋅ (2Rp)
5kΩ @ Rp = 50Ω
ZAC
Two wire AC impedance
ZAC = 50 ⋅ (Zs - 2Rp)
25kΩ 1% @ Zs = 600Ω
ZA (1)
SLIC impedance balancing
network
ZA = 50 ⋅ Zs
30kΩ 1% @ Zs = 600Ω
ZB (1)
Line impedance balancing
network
ZB = 50 ⋅ Zl
30kΩ 1% @ Zl = 600Ω
11/25
STLC3055N
Table 11. External Components @Gain Set = 0 (continued)
Name
Function
CCOMP
AC feedback loop compensation
CH
Formula
Trans-Hybrid Loss frequency
compensation
fo = 250kHz
CCOMP = 1/(2π⋅fo⋅100⋅(RP))
Typ. Value
120pF 10% 10V @ Rp = 50Ω
CH = CCOMP
120pF 10% 10V
RTTX (3) Pulse metering cancellation resistor
RTTX = 50Re (Zlttx+2Rp)
CTTX (3) Pulse metering cancellation
capacitor
CTTX = 1/{50⋅2π⋅fttx[-lm(Zlttx)]}
RLV
Pulse metering level resistor
CS
Pulse metering shaping capacitor CS = τ/(2⋅RLV)
CFL
Pulse metering filter capacitor
RLV = 63.3·103··α·VLOTTX
α = (|Zlttx + 2Rp|/|Zlttx|)
15kΩ @Zlttx = 200Ω real
100nF 10% 10V (2)
@ Zlttx = 200Ω real
16.2kΩ @ VLOTTX = 170mVrms
100nF 10% 10V
@ τ = 3.2ms, RLV = 16.2kΩ
CFL = 2/(2π⋅fttx⋅RLV)
1.5nF 10% 10V
@fttx = 12kHz RLV = 16.2kΩ
Table 12. External Components @Gain Set = 1
Name
Function
Formula
Typ. Value
RS
Protection resistance image
RS = 25 ⋅ (2Rp)
ZAC
Two wire AC impedance
ZAC = 25 ⋅ (Zs - 2Rp)
ZA (1)
SLIC impedance balancing
network
ZA = 25 ⋅ Zs
15kΩ 1% @ Zs = 600Ω
ZB (1)
Line impedance balancing
network
ZB = 25 ⋅ Zl
15kΩ 1% @ ZI = 600Ω
AC feedback loop compensation
fo = 250kHz
CCOMP = 2/(2π⋅fo⋅100⋅(RP))
Trans-Hybrid Loss frequency
compensation
CH = CCOMP
CCOMP
CH
2.55kΩ @ Rp = 50Ω
RTTX = 25Re (Zlttx+2Rp)
CTTX (3) Pulse metering cancellation
capacitor
CTTX = 1/25⋅2π⋅fttx⋅[-lm(Zlttx)]
Pulse metering level resistor
CS
Pulse metering shaping capacitor CS = τ/(2⋅RLV)
CFL
Pulse metering filter capacitor
220pF 10% 10VL @ Rp = 50Ω
220pF 10% 10V
RTTX (3) Pulse metering cancellation
resistor
RLV
12.5kΩ 1% @ Zs = 600Ω
RLV = 31.7·103··α·VLOTTX
α = (|Zlttx + 2Rp|/|Zlttx|)
7.5kΩ @Zlttx = 200Ω real
100nF 10% 10V (2)
@ Zlttx = 200Ω real
16.2kΩ @ VLOTTX = 340mVrms
100nF 10% 10V
@ τ = 3.2ms, RLV = 16.2kΩ
CFL = 2/(2π⋅fttx⋅RLV)
1.5nF 10% 10V
@fttx = 12kHz RLV = 16.2kΩ
(1) In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|.
(2) In this case CTTX is just operating as a DC decoupling capacitor (fp=100Hz).
(3) Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following formula:
ZTTX=50*(Zlttx+2Rp).
(4) CVpos should be defined depending on the power supply current capability and maximum allowable ripple.
(5) For low ripple application use 2x47µ F in parallel.
(6) Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input).
(7) RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as follows:
267kΩ
280kΩ
294kΩ
300kΩ
VBAT(ACTIVE)
-46V
-48V
-49V
-50V
VBATR(RING)
-62V
-65V
-68V
-70V
VBATR should be defined considering the ring peak level required (Vringpeak=VBATR-6V typ.).
The above relation is valid provided that the Vpos power supply current capability and the RSENSE programming allow to source all the
current requested by the particular ringer load configuration.
(8) For high efficiency in HI-Z mode coil resistance @125kHz must be < 3Ω
12/25
STLC3055N
Figure 9. Application Diagram.
VPOS
CVPOS
CVCC
RX
TX
RX
TX
RSENSE
RRX
RS
AGND BGND
CVCC
VPOS
RS
RSENSE
ZAC
CCOMP
Q1
P-ch
GATE
D1
ZAC1
VBAT
ZAC
ZB
CH
RF1
CVB
ZA
CV
VF
ZB
L
RF2
VDD
CLK
CLK
GAIN SET
RDD
RP
TIP
TIP
STLC3055N
CONTROL
INTERFACE
RP
RING
DET
DET
D0
D0
D1
D1
D2
D2
PD
PD
TTX CLOCK
RING
CSVR
CREV
CSVR
CREV
CKTTX
RTH
CTTX1
RLIM
RLV
RLV
CS
IREF
CTTX2
RREF
FTTX
RTTX
ILTF
CAC
RLIM
RTH
RD
CFL
RTTX
RD
CRD
D00TL489A
AGND
CAC
CTTX
BGND
SYSTEM GND
SUGGESTED GROUND LAY-OUT
PGND
Figure 10. Application Diagram without Metering Pulse Generation.
VPOS
CVPOS
CVCC
RX
TX
RX
TX
RSENSE
RRX
RS
AGND BGND
CVCC
VPOS
RS
ZAC
CCOMP
P-ch
GATE
D1
ZAC1
VBAT
ZAC
RF1
CVB
ZA
ZB
CH
Q1
RSENSE
CV
VF
ZB
L
RF2
VDD
CLK
GAIN SET
RDD
RP
STLC3055N
CONTROL
INTERFACE
CLK
RP
D0
D0
D1
D1
D2
D2
PD
PD
CSVR
CREV
CSVR
CREV
CKTTX
RTH
CTTX1
RLIM
CTTX2
IREF
FTTX
RING
RING
DET
DET
TIP
TIP
RREF
RTTX
CAC
ILTF
RLIM
RTH
RD
RD
CRD
D00TL490/B
AGND
BGND
CAC
SYSTEM GND
SUGGESTED GROUND LAY-OUT
PGND
13/25
STLC3055N
4
ELECTRICAL CHARACTERISTICS
Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25°C.
External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table.
Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow
correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85°C.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS
Vlohi
Line voltage
Il = 0, HI-Z
(High impedance feeding)
Tamb = 0 to 85°C
44
50
V
Vlohi
Line voltage
Il = 0, HI-Z
(High impedance feeding)
Tamb = -40 to 85°C
42
48
V
Vloa
Line voltage
Il = 0, ACTIVE
Tamb = 0 to 85°C
33
40
V
Vloa
Line voltage
Il = 0, ACTIVE
Tamb = -40 to 85°C
31
37
V
Ilim
Lim. current programming
range
ACTIVE mode
20
40
mA
Ilima
Lim. current accuracy
ACTIVE mode.
Rel. to programmed value
20mA to 40mA
-10
10
%
Feeding resistance
HI-Z (High Impedance feeding)
2.4
3.6
kΩ
Rfeed HI
AC CHARACTERISTICS
L/T
Long. to transv.
(see Appendix for test circuit)
Rp = 50Ω, 1% tol.,
ACTIVE N. P., RL = 600Ω (*)
f = 300 to 3400Hz
50
58
dB
T/L
Transv. to long.
(see Appendix for test circuit)
Rp = 50Ω, 1% tol.,
ACTIVE N. P., RL = 600Ω (*)
f = 300 to 3400Hz
40
45
dB
T/L
Transv. to long.
(see Appendix for test circuit)
Rp = 50Ω, 1% tol.,
ACTIVE N. P., RL = 600Ω (*)
f = 1kHz
48
53
dB
2W return loss
300 to 3400Hz,
ACTIVE N. P., RL = 600Ω (*)
22
26
dB
THL
Trans-hybrid loss
300 to 3400Hz,
20Log|VRX/VTX|,
ACTIVE N. P., RL = 600Ω (*)
30
dB
Ovl
2W overload level
at line terminals on ref. imped.
ACTIVE N. P., RL = 600Ω (*)
3.2
dBm
TXoff
TX output offset
ACTIVE N. P., RL = 600Ω (*)
-250
250
mV
G24
Transmit gain abs.
0dBm @ 1020Hz,
ACTIVE N. P., RL = 600Ω (*)
-6.4
-5.6
dB
G42
Receive gain abs.
0dBm @ 1020Hz,
ACTIVE N. P., RL = 600Ω (*)
-0.4
0.4
dB
2WRL
14/25
STLC3055N
4
ELECTRICAL CHARACTERISTICS
Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25°C.
External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table.
Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow
correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85°C.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
G24f
TX gain variation vs. freq.
rel. 1020Hz; 0dBm,
300 to 3400Hz,
ACTIVE N. P., RL = 600Ω (*)
-0.12
0.12
dB
G24f
RX gain variation vs. freq.
rel. 1020Hz; 0dBm,
300 to 3400Hz,
ACTIVE N. P., RL = 600Ω (*)
-0.12
0.12
dB
V2Wp
Idle channel noise at line 0dB
gainset
psophometric filtered
ACTIVE N. P., RL = 600Ω (*)
Tamb = 0 to +85°C
-73
-68
dBmp
V2Wp
Idle channel noise at line 0dB
gainset
psophometric filtered
ACTIVE N. P., RL = 600Ω (*)
Tamb = -40 to +85°C
-68
V4Wp
Idle channel noise at line 0dB
gainset
psophometric filtered
ACTIVE N. P., RL = 600Ω (*)
Tamb = 0 to +85°C
-75
V4Wp
Idle channel noise at line 0dB
gainset
psophometric filtered
ACTIVE N. P., RL = 600Ω (*)
Tamb = -40 to +85°C
-75
Total Harmonic Distortion
ACTIVE N. P., RL = 600Ω (*)
Metering pulse level on line
ACTIVE - TTX; Gain Set = 1
Zl = 200Ω fttx = 12kHz;
Thd
VTTX
CLKfreq
CLK operating range
dBmp
-70
dBmp
-44
260
340
-10%
125
dBmp
dB
mVrms
10%
kHz
(*) RL: Line Resistance
RING
Vring
Line voltage
RING D2 toggling @ fr = 25Hz
Load = 3REN;
Crest Factor = 1.25
1REN = 1800Ω + 1.0µF
Tamb = 0 to +85°C
45
49
Vrms
Vring
Line voltage
RING D2 toggling @ fr = 25Hz
Load = 3REN;
Crest Factor = 1.25
1REN = 1800Ω + 1.0µF
Tamb = -40 to +85°C
44
48
Vrms
10.5
DETECTORS
IOFFTHA
Off/hook current threshold
ACT. mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
ROFTHA
Off/hook loop resistance
threshold
ACT. mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
3.4
kΩ
IONTHA
On/hook current threshold
ACT. mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
6
mA
mA
15/25
STLC3055N
4
ELECTRICAL CHARACTERISTICS
Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25°C.
External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table.
Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow
correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85°C.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
RONTHA
On/hook loop resistance
threshold
ACT. mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
8
kΩ
IOFFTHI
Off/hook current threshold
Hi Z mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
10.5
mA
ROFFTHI
Off/hook loop resistance
threshold
Hi Z mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
800
Ω
IONTHI
On/hook current threshold
Hi Z mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
6
mA
RONTHI
On/hook loop resistance
threshold
Hi Z mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
8
Irt
Ring Trip detector threshold
range
RING
20
50
mA
Irta
Ring Trip detector threshold
accuracy
RING
-15
15
%
Trtd
Ring trip detection time
RING
Td
Dialling distortion
ACTIVE
Rlrt
(1)
ThAl
kΩ
TBD
-1
Loop resistance
Tj for th. alarm activation
ms
1
ms
500
Ω
160
°C
(1) Rlrt = Maximum loop resistance (incl. telephone) for correct ring trip detection.
DIGITAL INTERFACE
INPUTS: D0, D1, D2, PD, CLK
OUTPUTS: DET
Vih
In put high voltage
Vil
Input low voltage
Iih
Input high current
Iil
Input low current
Vol
Output low voltage
2
V
0.8
V
-10
10
µA
-10
10
µA
0.45
V
Iol = 1mA
PSRR AND POWER CONSUMPTION
PSERRC
Ivpos
Ipk
16/25
Power supply rejection Vpos to
2W port
Vripple = 100mVrms
50 to 4000Hz
Vpos supply current @ ii = 0
HI-Z On-Hook
ACTIVE On-Hook,
RING (line open)
Peak current limiting accuracy
RING Off-Hook
RSENSE = 110mΩ
26
-20%
36
dB
13
50
55
25
80
90
mA
mA
mA
950
+20%
mApk
STLC3055N
5
APPENDIX A
5.1 STLC3055N Test Circuits
Referring to the application diagram shown in fig. 9 of the STLC3055N datasheet and using as external
components the Typ. Values specified in the "External Components" Tables 10 and 11 (pages 11, 12) find
below the proper configuration for each measurement.
All measurements requiring DC current termination should be performed using "Wandel & Goltermann
DC Loop Holding Circuit GH-1" or equivalent.
Figure 11. 2W Return Loss
2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs)
W&G GH1
Zref
TX
TIP
600ohm
100µF
Vs
STLC3055N
application
circuit
100mA
DC max
1Kohm
E
Zin = 100K
200 to 6kHz
100µF
1Kohm
RX
RING
Figure 12. THL Trans Hybrid Loss
THL = 20Log|Vrx/Vtx|
W&G GH1
TIP
TX
100µF
600ohm
Vtx
STLC3055N
application
circuit
100mA
DC max
Zin = 100K
200 to 6kHz
100µF
RING
RX
Vrx
17/25
STLC3055N
Figure 13. G24 Transmit Gain
G24 = 20Log|2Vtx/E|
W&G GH1
TIP
TX
100µF
600ohm
Vtx
100mA
DC max
Zin = 100K
200 to 6kHz
STLC3055N
application
circuit
E
100µF
RX
RING
Figure 14. G42 Receive Gain
G42 = 20Log|VI/Vrx|
W&G GH1
TIP
TX
100µF
Vl
600ohm
100mA
DC max
Zin = 100K
200 to 6kHz
STLC3055N
application
circuit
100µF
RX
RING
Vrx
Figure 15. PSRRC Power supply rejection Vpos to 2W port
PSSRC = 20Log|Vn/Vl|
W&G GH1
TIP
TX
100µF
Vl
600ohm
100mA
DC max
Zin = 100K
200 to 6kHz
STLC3055N
application
circuit
100µF
RING
~
18/25
RX
VPOS
Vn
STLC3055N
Figure 16. L/T Longitudinal to Transversal Conversion
L/T = 20Log|Vcm/Vl|
300ohm
W&G GH1
100µF
TIP
TX
100µF
Impedance matching
better than 0.1%
Vcm
100mA
DC max
STLC3055N
application
circuit
Vl
Zin = 100K
200 to 6kHz
100µF
RX
RING
300ohm
100µF
Figure 17. T/L Transversal to Longitudinal Conversion
T/L = 20Log|Vrx/Vcm|
300ohm
100µF
W&G GH1
TIP
TX
100µF
STLC3055N
application
circuit
100mA
DC max
Impedance matching
better than 0.1%
600ohm
Vcm
Zin = 100K
200 to 6kHz
100µF
RING
300ohm
RX
Vrx
100µF
Figure 18. VTTX Metering Pulse Level on Line
TIP
Vlttx
200ohm
TX
STLC3055N
application
circuit
RING
RX
CKTTX
fttx (12 or 16kHz)
19/25
STLC3055N
Figure 19. V2Wp and W4Wp: Idle Channel Psophometric Noise at Line and TX.
V2Wp = 20Log|Vl/0.774l|; V4Wp = 20Log|Vtx/0.774l|
W&G GH1
TIP
TX
100µF
600ohm
100mA
DC max
Zin = 100K
200 to 6kHz
Vl
psophometric
filtered
100µF
RX
RING
6
Vtx
psophometric
filtered
STLC3055N
application
circuit
APPENDIX B
6.1 STLC3055N Overvoltage Protection
Figure 20. Simplified Configuration for Indoor Overvoltage Protection
STPR120A
BGND
STLC3055N
2x
SM6T39A
TIP
RING
RP1
RP2
TIP
RP1
RP2
RING
VBAT
STPR120A
RP1 = 30ohm:
RP2 =Fuse or PTC > 18ohm
Figure 21. Standard Overvoltage Protection Configuration for K20 Compliance
BGND
STLC3055N
RP1
2x
SM6T39A
TIP
RP2
TIP
RP2
RING
LCP1521
RING
RP1
VBAT
RP1 = 30ohm:
RP2 =Fuse or PTC > 18ohm
20/25
STLC3055N
7
APPENDIX C
7.1 TYPICAL STATE DIAGRAM FOR STLC3055N OPERATION
Figure 22.
Normally used for
On Hook Transmission
Tj>Tth
PD=0, D0=D1=0
Active
On Hook
Power
Down
Ring Pause
D0=0, D1=1,
D2=0
Ring Burst
Ring Burst
D0=1, D1=0,
D2=0/1
PD=1,
D0=D1=0
Ringing
On Hook Detection for T>Tref
HI-Z
Feeding
Ring Trip
Detection
Active
Off Hook
On Hook Condition
Off Hook Detection
D0=0, D1=1,
D2=0
Off Hook Detection
Note: all state transitions are under the microprocessor control.
21/25
STLC3055N
8
APPENDIX D
8.1 STLC3055Q STLC3055N compatibility.
STLC3055N is pin to pin compatible with the old STLC3055Q but offer a better performance in term of
Power consumption and can be set in a new gain configuration in order to be compatible with the 3.3V
codec.
8.1.1 Typical power consumption comparison
Table 13.
Operative mode
STLC3055Q
STLC3055N
HI-Z
52 - 60mA
13 - 25mA
Active on hook
93 - 115mA
50 - 80mA
Ring (no REN)
120 - 140mA
55 - 90mA
To meet this result some differences, with a minimum impact on the application, has been introduced in
STLC3055N.
8.1.2 Hardware difference:
■
RX input. In STLC3055N it is necessary a 100kΩ external resistor between RX input and
AGND to bias the input stage.
■
Rp. The STLC3055N required a Rp value of 50Ω instead of 41Ω.
■
TTX filter. To optimize the ttx signal dynamic we have change the values of RLV and CFL;
Table 14.
Component
STLC3055Q
STLC3055N
100kΩ
RRX
Rp
41Ω
50Ω
RLV
27kΩ
16.2kΩ
CFL
1nF
1.5nF
STLC3055Q
STLC3055N
8.1.3 Parameter differences:
Table 15.
Parameter
Absolute Max. Rating
Operating Range
17V
13V
15.8V
12V
Typ Metering pulse level (Gs 1)
Typ Metering pulse level (Gs 0)
22/25
340mVrms
200mVrms
170mVrms
STLC3055N
9
PACKAGE INFORMATION
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect. The category of second Level Interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 23. TQFP44 (10 x 10) Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.60
A1
0.05
A2
1.35
B
0.30
0.063
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.37
0.45
0.012
0.015
0.018
C
0.09
0.20
0.004
D
11.80
12.00
12.20
0.464
0.472
0.480
D1
9.80
10.00
10.20
0.386
0.394
0.401
D3
8.00
0.008
0.315
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
E3
8.00
0.315
e
0.80
0.031
L
0.45
0.60
L1
0.75
0.018
1.00
k
OUTLINE AND
MECHANICAL DATA
MAX.
0.024
0.030
TQFP44 (10 x 10 x 1.4mm)
0.039
0˚(min.), 3.5˚(typ.), 7˚(max.)
D
D1
A
A2
A1
23
33
34
22
0.10mm
.004
B
E
B
E1
Seating Plane
12
44
11
1
C
L
e
K
TQFP4410
0076922 D
23/25
STLC3055N
Table 16. Revision History
Date
Revision
September 2003
4
First Issue
October 2004
5
Update Functional Description and Electrical Characteristics. Aligned
the graphic style to be compliant with the new “Corporate Technical
Pubblications Design Guide”
October 2004
6
Modified the application diagrams and some typo errors.
November 2004
7
Removed all max. values of the ‘Line Voltage’ parameter on the page
14/24.
Changed the unit from mA to % of the ‘Ilima’ parameter on the page 14/
24.
January 2005
8
Add pin 4 PD in Applications and Block Diagram
Add in Table 2 ‘ESD Rating’
July 2005
9
Changed VTTX value
February 2006
10
Added part number “E-STLC3055N” (ECOPACK).
Added RRX resistance in the figures 9 and 10.
Added Appendix D.
24/25
Description of Changes
STLC3055N
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
25/25