STMICROELECTRONICS TDA7468D

TDA7468D
TWO BANDS DIGITALLY CONTROLLED
AUDIO PROCESSOR WITH BASS ALC SURROUND
1
■
■
■
■
■
■
■
■
■
■
2
FEATURES
Figure 1. Package
INPUT MULTIPLEXER
– 4 STEREO INPUTS
– SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
ONE STEREO OUTPUT
BASS ALC
TREBLE AND BASS CONTROL IN 2.0dB
STEPS
VOLUME CONTROL IN 1.0dB STEPS
TWO SPEAKER ATTENUATORS:
– TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
– INDEPENDENT MUTE FUNCTION
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
EXTERNALLY ADJUSTABLE SURROUND
DESCRIPTION
The TDA7468D is a volume tone (bass and treble)
balance (Left/Right) processor for quality audio
SO28
Table 1. Order Codes
Part Number
Package
TDA7468D
SO28
TDA7468D13TR
Tape & Reel
applications in Hi-Fi systems.
Selectable input gain is provided. Control of all the
functions is accomplished by serial bus.
The AC signal setting is obtained by resistor networks and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained
Figure 2. PIN CONNECTION (Top view)
VS
1
28
GND
MIC
2
27
CREF
IN1_L
3
26
IN1_R
IN2_L
4
25
IN2_R
IN3_R
IN3_L
5
24
IN4_L
6
23
IN4_R
MUX_L
7
22
MUX_R
IS_L
8
21
IS_R
TREBLE_L
9
20
TREBLE_R
BASSI_L
10
19
BASSI_R
BASSO_L
11
18
BASSO_R
OUT_L
12
17
OUT_R
DGND
13
16
ALC
SCL
14
15
SDA
D99AU1057
June 2004
REV. 1
1/22
2/22
IN-L4
IN-L3
IN-L2
IN-L1
ALC
MIC-MIX
IN-R1
IN-R2
IN-R3
IN-R4
50K
50K
50K
50K
50K
50K
50K
50K
D99AU1058A
6
5
4
3
16
50K
2
26
25
24
23
INPUT
SELECT
0dB, 6dB
10dB, 14dB
INPUT
SELECT
+
+
MUX-L
7
buffer gain:
0 to 14dB gain
/ 2dB step
buffer gain:
0 to 14dB gain
/ 2dB step
22
MUX-R
IS-L
8
50K
50K
0dB
6dB
9dB
12dB
VARIABLE
MIX
non-inverting
inverting
HALF_WAVE
RECTIFIER
BASS_ALC
CONTROL
0dB VARIABLE
MIX
6dB
9dB
12dB
non-inverting
inverting
21
IS-R
+
+
+
63dB att.
/1dB step
+ 6dB gain
63dB att.
/1dB step
+ 6dB gain
TREBLE
gm
TREBLE-L
9
-14 to +14dB
/2dB step
gm
19
BASS
-14 to +14dB
/2dB step
18
BASSI-L
10
BASSO-L
11
-14 to +14dB
/2dB step
BASS
CREF
27
SUPPLY
GND
28
VREF
-24 att.
/8dB step
-24 att.
/8dB step
BASSO-R
I2C BUS DECODER + LATCHES
TREBLE
-14 to +14dB
/2dB step
20
TREBLE-R BASSI-R
1
12
13
15
14
17
VS
OUT-L
DGND
SDA
SCL
OUT-R
TDA7468D
Figure 3. BLOCK DIAGRAM
TDA7468D
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
VS
Parameter
Value
Unit
10.5
V
0 to 70
°C
-55 to 150
°C
Value
Unit
85
°C/W
Operating Supply Voltage
Tamb
Operating Ambient Temperature
Tstg
Storage Temperature Range
Table 3. THERMAL DATA
Symbol
Rth j-pin
Parameter
Thermal Resistance Junction-pins
Table 4. QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
9
10
V
VS
Supply Voltage
5
VCL
Max. input signal handling
2
THD
Total Harmonic Distortion VI = 1Vrms; f = 1KHz
Vrms
0.01
Total Harmonic Distortion VI = 0.1Vrms; f = 1KHz
%
%
0.1
%
S/N
Signal to Noise Ratio Vout = 1Vrms (0dB)
100
dB
SC
Channel Separation f = 1KHz
90
dB
Input Gain (2dB step)
0
14
dB
Volume Control (1dB step)
-87
0
dB
Treble Control (2dB step)
-14
+14
dB
Bass Control (2dB step)
-14
+14
dB
Mute Attenuation
86
dB
3/22
TDA7468D
ELECTRICAL CHARACTERISTICS
(refer to the test circuit Tamb = 25°C, VS = 9V, f = 1KHz all controls flat (G = 0dB), unless otherwise
specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
5
9
10
V
9
mA
60
90
dB
35
50
2
2.5
Vrms
dB
SUPPLY
VS
Supply Voltage
IS
Supply Current
SVR
Ripple Rejection
INPUT STAGE
RIN
Input Resistance
VCL
Clipping Level
SIN
Input Separation
80
100
Ginmin
Minimum Input Gain
-1
0
Ginmax
Maximum Input Gain
14
dB
Step Resolution
2
dB
Gstep
THD = 0.3%
65
1
KΩ
dB
MIC
RIN
Input Resistance
Gmic1
Mic Input Gain 1
14
dB
Gmic2
Mic Input Gain 2
10
dB
35
50
65
KΩ
Gmic3
Mic Input Gain 3
6
dB
Gmin4
Mic Input Gain 4
0
dB
MIXmic
Mixing Rate
50
%
SURROUND
Rin
Input Resistance
35
50
65
KΩ
Ginmin
Minimum Input Gain
-1
0
1
dB
Ginmax
Maximum Input Gain
12
Inverting Gain
-1
Mixmin
Minimum Mixing Rate
0
%
Mixmax
Maximum Mixing Rate
100
%
GinV
Crosstal
k
Gbuffer
Crosstalk of Mux Output to 100%
IS
dB
40
Buffer Gain
dB
6
dB
63
dB
VOLUME CONTROL
CRANGE1 Vol 1 Control Range
AVMAX1
Vol 1 Max. Attenuation
61
63
65
dB
ASTEP1
Vol 1 Step Resolution
0.5
1
1.5
dB
Match1
Matching
TBD
CRANGE2 Vol 2 Control Range
dB
24
dB
AVMAX2
Vol 2 Max. Attenuation
22
24
26
dB
ASTEP2
Vol 2 Step Resolution
7
8
9
dB
Match2
Matching
AVMAX1+ Vol 1 + Vol 2 Max Attenuation
AVMAX2
4/22
TBD
dB
84
dB
TDA7468D
ELECTRICAL CHARACTERISTICS (continua)
(refer to the test circuit Tamb = 25°C, VS = 9V, f = 1KHz all controls flat (G = 0dB), unless otherwise
specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
BASS CONTROL
Gb
Control Range
±12.0
±14.0
±16.0
dB
BSTEP
Step Resolution
1
2
3
dB
Internal Feedback Resistance
33
44
55
KΩ
RB
Max. Boost/cut
BASS ALC CONTROL
Rattack1
Attack Time Resistor 1
12.5
KΩ
Rattack2
Attack Time Resistor 2
25
KΩ
Rattack3
Attack Time Resistor 3
50
KΩ
Rattack4
Attack Time Resistor 4
100
KΩ
Thresh1
Threshold 1
700
mVrms
Thresh2
Threshold 2
485
mVrms
Thresh3
Threshold 3
320
mVrms
Thresh4
Threshold 4
170
mVrms
TREBLE CONTROL
Gt
Control Range
TSTEP
Step Resolution
Rt
Max. Boost/cut
+13.0
+14.0
+15.0
dB
1
2
3
dB
Internal Resistance
25
KΩ
2.5
Vrms
AUDIO OUTPUTS
VOCL
RL
VOUT
Clipping Level
THD = 0.3%
Output Load Resistance
2
2
DC Voltage Level
KΩ
4.5
V
5
µV
GENERAL
ENO
Output Noise
BW = 20Hz to 20KHz;
All gains 0dB;
output muted
S/N
Signal to Noise Ratio
SC
Channel Separation Left/Right
d
Distortion
10
100
dB
90
dB
AV = 0; VI = 0.1Vrms ;
0.1
AV = 0; VI = 1Vrms ;
SC
15
µV
flat
All gains 0dB; VO = 1Vrms ;
%
0.01
%
Channel Separation left/right
90
dB
Total Tracking Error
0
1
dB
1
V
BUS INPUT
VIL
Input Low Voltage
VIH
Input High Voltage
IIN
Input Current
VIN = 0.4V
VO
Output Voltage (ACK)
IO = 1.6mA
2.5
V
-5
0.4
5
µA
0.8
V
5/22
6/22
IN-R1
IN-R2
IN-R3
IN-R4
0.47µF
0.47µF
0.47µF
0.47µF
1M
0.47µF
IN-L4
IN-L3
IN-L2
IN-L1
ALC
0.47µF
MIC-MIX
0.47µF
0.47µF
0.47µF
0.47µF
50K
50K
50K
50K
50K
50K
50K
50K
D99AU1059A
6
5
4
3
16
50K
2
26
25
24
23
INPUT
SELECT
0dB, 6dB
10dB, 14dB
INPUT
SELECT
+
+
MUX-L
7
buffer gain:
0 to 14dB gain
/ 2dB step
buffer gain:
0 to 14dB gain
/ 2dB step
22
MUX-R
IS-L
8
50K
50K
0dB
6dB
9dB
12dB
VARIABLE
MIX
non-inverting
inverting
+
VARIABLE
MIX
HALF_WAVE
RECTIFIER
BASS_ALC
CONTROL
0dB
6dB
9dB
12dB
non-inverting
inverting
21
IS-R
+
+
63dB att.
/1dB step
+ 6dB gain
63dB att.
/1dB step
+ 6dB gain
TREBLE
BASS
-14 to +14dB
/2dB step
BASSI-R
100nF
5.6K
11
BASSO-L
10
BASSI-L
9
gm
-14 to +14dB
/2dB step
BASS
TREBLE-L
-14 to +14dB
/2dB step
gm
19
100nF
GND
28
VREF
27
SUPPLY
-24 att.
/8dB step
-24 att.
/8dB step
BASSO-R
18
I2C BUS DECODER + LATCHES
TREBLE
-14 to +14dB
/2dB step
20
TREBLE-R
3.3nF
10µF
CREF
1
12
13
15
14
17
VS
OUT-L
DGND
SDA
SCL
OUT-R
TDA7468D
Figure 4. TEST CIRCUIT
TDA7468D
3
APPLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -63dB (mute) with 1dB
step resolution for this first one, 0 to 24dB (mute) with 8dB step resolution for the last one.
The very high resolution allows the implementation of systems free from any noisy acoustical effect.
The TDA7468D audioprocessor provides 2 bands tones control.
3.1 Bass, Stages
The Bass cell has an internal resistor Ri = 44KΩ typical.
Several filter types can be implemented, connecting external components to the Bass IN and OUT pins.
The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and
R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed
as follows:
1
F C = ----------------------------------------------------------------2 ⋅ π ⋅ R1 ⋅ R2 ⋅ C 1 ⋅ C2
R2 C2 + R2 C1 + R i C1
A V = ---------------------------------------------------------------R 2 C1 + R2 C2
R 1 ⋅ R2 ⋅ C1 ⋅ C 2
Q = -------------------------------------------------R2 C1 + R2 C2
Viceversa, once FC, AV, and Ri internal value are fixed, the external components values will be:
2
AV – 1
C1 = -----------------------------------------2 ⋅ π ⋅ FC ⋅ Ri ⋅ Q
Q ⋅ C1
C2 = -----------------------------2
AV – 1 – Q
2
AV – 1 – Q
R2 = ----------------------------------------------------------------------2 ⋅ π ⋅ C1 ⋅ FC ⋅ ( A V – 1 ) ⋅ Q
3.2 Treble Stage
The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and
an external capacitor connected between treble pins and ground.
3.3 CREF
The suggested 10µF reference capacitor (CREF) value can be reduced to 4.7µF if the application requires
faster power ON.
Figure 5.
Ri internal
IN
OUT
C1
C2
R2
D95AU313
7/22
TDA7468D
4
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7468D and vice versa takes place through the 2 wires
I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
4.1 Data Validity
As shown in fig. 6, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in fig.7 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
4.4 Acknowledge
The master (µP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
4). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse. The audio processor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time.
In this case the master transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data. This approach of
course is less protected from misworking.
Figure 6. Data Validity on the I2CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 7. Timing Diagram of I2CBUS
SCL
I2CBUS
SDA
D99AU1032
START
STOP
Figure 8. Acknowledge on the I2CBUS
SCL
1
2
3
7
8
9
SDA
MSB
START
8/22
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
TDA7468D
5
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
■
■
■
■
■
A start condition (S)
A chip address byte, containing the TDA7468D address
A subaddress bytes
A sequence of data (N byte + acknowledge)
A stop condition (P)
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
DATA 1 to DATA n
MSB
ACK
X
LSB
X
X
B
DATA
MSB
ACK
LSB
DATA
ACK
P
D96AU420
ACK = Acknowledge
S = Start; P = Stop
A = Address
B = Auto Increment
6
EXAMPLES
6.1 No Incremental Bus
The TDA7468D receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition.
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA
LSB
MSB
0 D3 D2 D1 D0 ACK
X
X
LSB
DATA
ACK
P
D96AU421
6.2 Incremental Bus
The TDA7468D receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS
from "XXX1000" to "XXX1111" of DATA are ignored.
The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the
loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA 1 to DATA n
LSB
X
MSB
1 D3 D2 D1 D0 ACK
X
LSB
DATA
ACK
P
D96AU422
Table 5. POWER ON RESET CONDITION
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
0
9/22
TDA7468D
7
DATA BYTES
Address = (HEX) 10001000.
Table 6. FUNCTION SELECTION: First byte (subaddress)
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
B
0
0
0
0
INPUT SELECT & MIC
X
X
X
B
0
0
0
1
INPUT GAIN
X
X
X
B
0
0
1
0
SURROUND
X
X
X
B
0
0
1
1
VOLUME LEFT
X
X
X
B
0
1
0
0
VOLUME RIGHT
X
X
X
B
0
1
0
1
TREBLE & BASS
X
X
X
B
0
1
1
0
OUTPUT
X
X
X
B
0
1
1
1
BASS ALC
B = 1: INCREMENTAL BUS; ACTIVE
B = 0: NO INCREMENTAL BUS
X = INDIFFERENT 0/1
Table 7. INPUT SELECTION & MIC
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
INPUT SELECT
0
0
0
IN1
0
0
1
IN2
0
1
0
IN3
0
1
1
IN4
MUTE (IN5)
1
ON (IN5)
0
OFF
MIC
10/22
0
0
Gain: 14dB
0
1
Gain: 10dB
1
0
Gain: 6dB
1
1
Gain: 0dB
1
OFF
0
ON
TDA7468D
Table 8. INPUT GAIN SELECTION
MSB
D7
D6
D5
D4
D3
LSB
INPUT GAIN
D2
D1
D0
2dB STEPS
0
0
0
0dB
0
0
1
2dB
0
1
0
4dB
0
1
1
6dB
1
0
0
8dB
1
0
1
10dB
1
1
0
12dB
1
1
1
14dB
GAIN = 0 to 30dB
Table 9. SURROUND
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
SURROUND
D0
SURROUND MODE
1
ON
0
OFF
GAIN
0
0
0dB
0
1
6dB
1
0
9dB
1
1
12dB
MIXING
0
0
0
inverting : 100%
0
0
1
inverting :50%
0
1
0
inverting : 25%
0
1
1
0%
1
0
0
non-inverting : 100%
1
0
1
non-inverting : 75%
1
1
0
non-inverting : 50%
1
1
1
mute
BUFFER GAIN
1
0
0
6dB
11/22
TDA7468D
Table 10. VOLUME
MSB
D7
D6
D5
D4
D3
LSB
VOLUME
D2
D1
D0
1dB STEPS
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
8dB STEPS
0
0
0
0dB
0
0
1
-8dB
0
1
0
-16dB
0
1
1
-24dB
1
0
0
-32dB
1
0
1
-40dB
1
1
0
-48dB
1
1
1
-56dB
VOLUME 2
0
0
0dB
0
1
-8dB
1
0
-16dB
1
1
-24dB
VOLUME = 0 to-87dB
Table 11. VOLUME setting 1
Target Volume (dB)
12/22
Volume1 1dB step (dB)
Volume1 8dB step (dB)
Volume2 8dB step (dB)
0
0
-8
0
0
0
-1
-1
-2
-2
-3
-3
-4
-4
-5
-5
-6
-6
-7
-7
-8
0
-9
-1
-10
-2
-11
-3
-12
-4
-13
-5
-14
-6
-15
-7
TDA7468D
Table 11. VOLUME setting 1 (continua)
Target Volume (dB)
Volume1 1dB step (dB)
Volume1 8dB step (dB)
Volume2 8dB step (dB)
-16
0
-16
0
-17
-1
-18
-2
-19
-3
-20
-4
-21
-5
-22
-6
-23
-7
-24
0
-32
0
-40
0
-48
0
-24
0
-25
-1
-26
-2
-27
-3
-28
-4
-29
-5
-30
-6
-31
-7
-32
0
-33
-1
-34
-2
-35
-3
-36
-4
-37
-5
-38
-6
-39
-7
-40
0
-41
-1
-42
-2
-43
-3
-44
-4
-45
-5
-46
-6
-47
-7
-48
0
-49
-1
-50
-2
-51
-3
-52
-4
-53
-5
-54
-6
-55
-7
Target Volume (dB)
Volume1 1dB step (dB)
Volume1 8dB step (dB)
Volume2 8dB step (dB)
-56
0
-56
0
-57
-1
13/22
TDA7468D
Table 11. VOLUME setting 1 (continua)
-58
-2
-59
-3
-60
-4
-61
-5
-62
-6
-63
-7
-64
0
-65
-1
-66
-2
-67
-3
-68
-4
-69
-5
-70
-6
-71
-7
-72
0
-73
-1
-74
-2
-75
-3
-76
-4
-77
-5
-78
-6
-79
-7
-80
0
-81
-1
-82
-2
-83
-3
-84
-4
-85
-5
-86
-6
-87
-7
-56
8
-56
-16
-56
-24
Table 12. VOLUME setting 2
Target Volume (dB)
Volume1 1dB step (dB)
Volume1 8dB step (dB)
Volume2 8dB step (dB)
0
0
0
0
-1
-1
-2
-2
-3
-3
-4
-4
-5
-5
-6
-6
-7
-7
14/22
TDA7468D
Table 12. VOLUME setting 2 (continua)
Target Volume (dB)
Volume1 1dB step (dB)
Volume1 8dB step (dB)
Volume2 8dB step (dB)
-8
0
-8
0
-9
-1
-10
-2
-11
-3
-12
-4
-13
-5
-14
-6
-15
-7
-16
0
-16
0
-17
-1
-18
-2
-19
-3
-20
-4
-21
-5
-22
-6
-23
-7
-24
0
-16
-8
-25
-1
-26
-2
-27
-3
-28
-4
-29
-5
-30
-6
-31
-7
-32
0
-16
-16
-33
-1
-34
-2
-35
-3
-36
-4
-37
-5
-38
-6
-39
-7
-40
0
-16
-24
-41
-1
-42
-2
-43
-3
-44
-4
-45
-5
-46
-6
-47
-7
15/22
TDA7468D
Table 12. VOLUME setting 2 (continua)
Target Volume (dB)
Volume1 1dB step (dB)
Volume1 8dB step (dB)
Volume2 8dB step (dB)
-48
0
-24
-24
-49
-1
-50
-2
-51
-3
-52
-4
-53
-5
-54
-6
-55
-7
-56
0
-32
-24
-57
-1
-58
-2
-59
-3
-60
-4
-61
-5
-62
-6
-63
-7
-64
0
-40
-24
-65
-1
-66
-2
-67
-3
-68
-4
-69
-5
-70
-6
-71
-7
-72
0
-48
-24
-73
-1
-74
-2
-75
-3
-76
-4
-77
-5
-78
-6
-79
-7
-80
0
-56
-24
-81
-1
-82
-2
-83
-3
-84
-4
-85
-5
-86
-6
-87
-7
16/22
TDA7468D
Table 13. TREBLE & BASS SELECTION
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
TREBLE
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
0
0
0
14dB
1
0
0
1
12dB
1
0
1
0
10dB
1
0
1
1
8dB
1
1
0
0
6dB
1
1
0
1
4dB
1
1
1
0
2dB
1
1
1
1
0dB
BASS (*)
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
0
0
0
14dB
1
0
0
1
12dB
1
0
1
0
10dB
1
0
1
1
8dB
1
1
0
0
6dB
1
1
0
1
4dB
1
1
1
0
2dB
1
1
1
1
0dB
(*) When BASS is programmed in the range -14dB/0dB, ALC is automatically switched to "OFF".
Table 14. OUTPUT
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
MUTE
0
ON
1
OFF
17/22
TDA7468D
Table 15. BASS ALC
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
BASS ALC
D0
ALC Mode
1
ON
0
OFF
Detector
1
ON
0
OFF
Release Current Circuit
1
ON
0
OFF
Attack Time Resistor
0
0
12.5KΩ
0
1
25KΩ
1
0
50KΩ
1
1
100KΩ
Threshold
0
0
700mVrms
0
1
485mVrms
1
0
320mVrms
1
1
170mVrms
Attack Mode
0
MODE 1: Fixed Resistor
1
MODE 2: Adaptive
Figure 9. BASS ALC : Threshold curve
VO
(VRMS)
1
Figure 10. BASS ALC : THD
D00AU1100
Supply Voltage : 9.0V
Frequency : 60Hz
Bassfilter : 60Hz/28dB boost
Internal release circuit : ON
Attack mode : 12.5kohm, mode2(adaptive)
D99AU1101A
THD
[%]
10
Supply Voltage : 9.0V
Frequency : 60Hz
Bassfilter : 60Hz/28dB boost
Internal release circuit : ON
Attack mode : 12.5kohm, mode2(adaptive)
1
Threshold1
Threshold2
old1
Threshold
Thresh
0.01
Thresh
old2
4
Threshold
Threshold4
0.1
3
0.1
Threshold3
0.001
0.01
18/22
0.1
1
VIN(VRMS)
0.01
0.1
1
VIN(VRMS)
TDA7468D
8
IC1
Figure 11. PINS: IN1_L, IN1_R, IN2_L, IN2_R,
IN3_L, IN3_R, IN4_L, IN4 _R, IS_L,
IS_R, MIC
Figure 15. PINS: BASSI_L, BASSI_R
VS
20µA
VS
20µA
45K
GND
50K
GND
Vref
BASSO-L,BASSO-R
D99AU1096
D99AU1092
Figure 16. PINS: BASSO_L, BASSO_R
Figure 12. PINS: OUT_L, OUT_R, IMUX_L,
MUX_R
VS
20µA
VS
20µA
45K
10Ω
GND
BASSI-L,BASSI-R
D99AU1097
GND
D99AU1093
Figure 17. PIN: ALC
Figure 13. PINS: TREBLE_L, TREBLE_R
VS
20µA
VS
20µA
100K
GND
25K
D99AU1098
GND
D99AU1094
Figure 18. PIN: CREF
VS
Figure 14. PINS: SCL, SDA
20µA
VS
25K
20µA
25K
GND
GND
D99AU1099
D99AU1095
19/22
TDA7468D
Figure 19. SO20 Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
B
0.33
0.51
0.013
0.200
C
0.23
0.32
0.009
0.013
D (1)
12.60
13.00
0.496
0.512
E
7.40
7.60
0.291
0.299
e
1.27
0.050
H
10.0
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.40
1.27
0.016
0.050
k
ddd
OUTLINE AND
MECHANICAL DATA
0˚ (min.), 8˚ (max.)
0.10
0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO20
0016022 D
20/22
TDA7468D
Table 16. Revision History
Date
Revision
Description of Changes
January 2004
2
First Issue in EDOCS DMS
June 2004
3
Changed the Style-sheet in compliance to the new “Corporate Technical
Pubblications Design Guide”
21/22
TDA7468D
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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22/22