STMICROELECTRONICS STM8AF6176

STM8AF5xxx STM8AF6x69/7x/8x/9x/Ax
Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROM,
10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 to 5.5 V
Datasheet − production data
Features
■
Core
– Max fCPU: 24 MHz
– Advanced STM8A core with Harvard
architecture and 3-stage pipeline
– Average 1.6 cycles/instruction resulting in
10 MIPS at 16 MHz fCPU for industry
standard benchmark
■
Memories
– Program memory: 32 to 128 Kbytes Flash
program; data retention 20 years at 55 °C
– Data memory: up to 2 Kbytes true data
EEPROM; endurance 300 kcycles
– RAM: 2 Kbytes to 6 Kbytes
■
Clock management
– Low-power crystal resonator oscillator with
external clock input
– Internal, user-trimmable 16 MHz RC and
low-power 128 kHz RC oscillators
– Clock security system with clock monitor
■
■
■
■
Reset and supply management
– Wait/auto-wakeup/Halt low-power modes
with user definable clock gating
– Low consumption power-on and powerdown reset
Interrupt management
– Nested interrupt controller with 32 vectors
– Up to 37 external interrupts on 5 vectors
Timers
– 2 general purpose 16-bit timers with up to 3
CAPCOM channels each (IC, OC, PWM)
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, deadtime insertion and flexible synchronization
– 8-bit AR basic timer with 8-bit prescaler
– Auto-wakeup timer
– Window and independent watchdog timers
I/Os
– Up to 68 user pins (11 high sink I/Os)
– Highly robust I/O design, immune against
current injection
July 2012
This is information on a product in full production.
LQFP80 14x14
LQFP64 10x10
LQFP32 7x7
LQFP48 7x7
VFQFPN32 5x5
■
Communication interfaces
– High speed 1 Mbit/s CAN 2.0B interface
– USART with clock output for synchronous
operation - LIN master mode
– LINUART LIN 2.1 compliant, master/slave
modes with automatic resynchronization
– SPI interface up to 10 Mbit/s or fMASTER/2
– I2C interface up to 400 Kbit/s
■
Analog to digital converter (ADC)
– 10-bit resolution, 2 LSB TUE, 1 LSB
linearity and up to 16 multiplexed channels
■
Operating temperature up to 150 °C
■
Qualification conforms to AEC-Q100 rev G
Table 1.
Device summary(1)
Part numbers: STM8AF52xx (with CAN)
STM8AF52AA, STM8AF52A9, STM8AF52A8, STM8AF528A,
STM8AF5289, STM8AF5288, STM8AF5269, STM8AF5268
Part numbers: STM8AF6269/8x/Ax
STM8AF62AA, STM8AF62A9, STM8AF62A8, STM8AF628A,
STM8AF6289, STM8AF6288, STM8AF6286, STM8AF6269,
STM8AF62A6,
Part numbers: STM8AF51xx (with CAN)(2)
STM8AF51AA, STM8AF51A9, STM8AF51A8, STM8AF519A,
STM8AF5199, STM8AF5198, STM8AF518A, STM8AF5189,
STM8AF5188, STM8AF5179, STM8AF5178, STM8AF5169,
STM8AF5168
Part numbers: STM8AF6169/7x/8x/9x/Ax(2)
STM8AF61AA, STM8AF61A9, STM8AF61A8, STM8AF619A,
STM8AF6199, STM8AF6198, STM8AF618A, STM8AF6189,
STM8AF6188, STM8AF6186, STM8AF6179, STM8AF6178,
STM8AF6176, STM8AF6169
1. In the order code, ‘F’ applies to devices with Flash program
memory and data EEPROM while ‘H’ refers to devices with
Flash program memory only. ‘F’ is replaced by ‘P’ for devices
with FASTROM (see Tables 2, 3, 4, and 5, and Figure 52).
2. Not recommended for new design.
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1
Contents
STM8AF52/62xx, STM8AF51/61xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
5.2
5.1.1
Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.3
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 16
5.2.1
SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.2
Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
Flash program and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5
2/110
STM8A central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4.1
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4.2
Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4.3
Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4.4
Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5.2
16 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . 18
5.5.3
128 kHz low-speed internal RC oscillator (LSI) . . . . . . . . . . . . . . . . . . . 19
5.5.4
24 MHz high-speed external crystal oscillator (HSE) . . . . . . . . . . . . . . 19
5.5.5
External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.5.6
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6
Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.7
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7.1
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7.2
Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7.3
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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5.7.4
Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . 21
5.7.5
Basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.8
Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.9
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.10
6
Contents
5.9.1
Universal synchronous/asynchronous receiver transmitter (USART) . . 23
5.9.2
Universal asynchronous receiver/transmitter with LIN support
(LINUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.9.3
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.9.4
Inter integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.9.5
Controller area network interface (beCAN) . . . . . . . . . . . . . . . . . . . . . . 27
Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8
Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3.1
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.3.2
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.3.3
External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 65
10.3.4
Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67
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10.3.5
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.6
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.3.7
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.3.8
TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 77
10.3.9
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.3.10 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.4
11
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.4.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.4.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 88
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
13
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
13.1
Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 99
13.1.1
13.2
13.3
14
4/110
STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13.2.1
STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13.2.2
C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM8AF52xx product line-up with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM8AF62xx product line-up without CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM8AF/H/P51xx product line-up with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STM8AF/H/P61xx product line-up without CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Peripheral clock gating bits (CLK_PCKENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Peripheral clock gating bits (CLK_PCKENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ADC naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Legend/abbreviation for the pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM8A microcontroller family pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory model 128K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Temporary memory unprotection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM8A interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Operating lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Total current consumption in Run, Wait and Slow mode. General conditions
for VDD apply, TA = -40 °C to 150 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Total current consumption in Halt and Active-halt modes. General conditions for VDD
applied. TA = -40 °C to 55 °C unless otherwise stated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Typical peripheral current consumption VDD = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC accuracy for VDDA = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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List of tables
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
6/110
STM8AF52/62xx, STM8AF51/61xx
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LQFP 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 90
LQFP 64-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 91
LQFP 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 93
LQFP 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 95
VFQFPN 32-lead very thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
STM8A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash memory organization of STM8A products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LQFP/VFQFPN 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typ. IDD(RUN)HSE vs. VDD @fCPU = 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 64
Typ. IDD(RUN)HSE vs. fCPU @ VDD = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . 64
Typ. IDD(RUN)HSI vs. VDD @ fCPU = 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 64
Typ. IDD(WFI)HSE vs. VDD @ fCPU = 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 64
Typ. IDD(WFI)HSE vs. fCPU @ VDD = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . . 64
Typ. IDD(WFI)HSI vs. VDD @ fCPU = 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 64
HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical HSI frequency vs VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typical LSI frequency vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Typical VIL and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Typical pull-up resistance RPU vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 72
Typical pull-up current Ipu vs VDD @ four temperatures(1) . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typ. VOL @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typ. VOL @ VDD = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VOL @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VDD - VOH @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typ. VDD - VOH @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typical NRST VIL and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Typical NRST pull-up resistance RPU vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Typical NRST pull-up current Ipu vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI timing diagram in slave mode and with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI timing diagram in slave mode and with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
LQFP 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
LQFP 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LQFP 64-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
LQFP 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LQFP 48-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
8/110
STM8AF52/62xx, STM8AF51/61xx
LQFP 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP 32-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5). . . . . . . . . . . . . . . 97
Ordering information scheme(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
1
Introduction
Introduction
This datasheet refers to the STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx
products with 32 to 128 Kbytes of program memory.
In the order code, the letter ‘F’ refers to product versions with Flash and data EEPROM, ‘H’
to product versions with Flash only, and ‘P’ to product versions with FASTROM. The
identifiers ‘F’, ‘H’, and ‘P’ do not coexist in a given order code.
The datasheet contains the description of family features, pinout, electrical characteristics,
mechanical data and ordering information.
●
For complete information on the STM8A microcontroller memory, registers and
peripherals, please refer to STM8S and STM8A microcontroller families reference
manual (RM0016).
●
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S and STM8A Flash programming manual (PM0051).
●
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
●
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
Doc ID 14395 Rev 9
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Description
2
STM8AF52/62xx, STM8AF51/61xx
Description
The STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx automotive 8-bit
microcontrollers described in this datasheet offer from 32 Kbytes to 128 Kbytes of non
volatile memory and integrated true data EEPROM. They are referred to as high density
STM8A devices in the STM8S and STM8A microcontroller families reference manual
(RM0016).
The STM8AF51xx and STM8AF52xx series feature a CAN interface.
All devices of the STM8A product line provide the following benefits: reduced system cost,
performance and robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k
write/erase cycles and a high system integration level with internal clock oscillators,
watchdog, and brown-out reset.
Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to application scalability across a common
family product architecture with compatible pinout, memory map and and modular
peripherals. Full documentation is offered with a wide choice of development tools.
Product longevity is ensured in the STM8A family thanks to their advanced core which is
made in a state-of-the art technology for automotive applications with 3.3 V to 5.5 V
operating supply.
All STM8A and ST7 microcontrollers are supported by the same tools including
STVD/STVP development environment, the STice emulator and a low-cost, third party incircuit debugging tool.
10/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Product line-up
3
Product line-up
Table 2.
STM8AF52xx product line-up with CAN
..
Order code
Package
STM8AF/P52AA
LQFP80
(14x14)
STM8AF/P528A
High
density
Flash
program
memory
(bytes)
Data
RAM
EEPROM
(bytes)
(bytes)
10-bit
A/D
chan.
Timers
(IC/OC/PWM)
Serial
interfaces
I/0
wakeup
pins
128 K
68/37
64 K
2K
STM8AF/P52A9
STM8AF/P5289
LQFP64
(10x10)
STM8AF/P5269
6K
1K
128 K
LQFP48
(7x7)
STM8AF/P5268
Table 3.
64 K
32 K
STM8AF/P52A8
STM8AF/P5288
16
128 K
CAN,
1x8-bit: TIM4
LIN(UART)
3x16-bit: TIM1,
, SPI,
TIM2, TIM3
USART,
(9/9/9)
I²C
52/36
2K
64 K
10
32 K
38/35
1K
STM8AF62xx product line-up without CAN
Order code
Package
STM8AF/P62AA
LQFP80
(14x14)
STM8AF/P628A
STM8AF/P62A9
STM8AF/P6289
STM8AF/P6288
STM8AF/P6286
Data
RAM
EEPROM
(bytes)
(bytes)
10-bit
A/D
chan.
Serial
interfaces
I/0
wakeup
pins
68/37
2K
64 K
16
64 K
2K
32 K
LQFP48
(7x7)
128 K
LQFP32
(7x7)
64 K
1K
1x8-bit: TIM4
LIN(UART),
3x16-bit: TIM1,
SPI,
TIM2, TIM3
USART, I²C
(9/9/9)
52/36
6K
10
2K
7
VFQFPN32
STM8AF/P62A6
(5x5)
Timers
(IC/OC/PWM)
128 K
128 K
LQFP64
(10x10)
STM8AF/P6269
STM8AF/P62A8
High
density
Flash
program
memory
(bytes)
128 K
Doc ID 14395 Rev 9
38/35
1x8-bit: TIM4
3x16-bit: TIM1, LIN(UART),
TIM2, TIM3
SPI, I²C
(8/8/8)
25/23
11/110
Product line-up
.
Table 4.
STM8AF52/62xx, STM8AF51/61xx
STM8AF/H/P51xx product line-up with CAN
Order code
Package
STM8AF/H/P51AA
STM8AF/H/P519A
High
density
Flash
program
memory
(bytes)
Data
RAM
EEPROM
(bytes)
(bytes)
10-bit
A/D
chan.
Timers
(IC/OC/PWM)
Serial
interfaces
I/0
wakeup
pins
128 K
LQFP80
(14x14)
96 K
STM8AF/H/P518A
64 K
STM8AF/H/P51A9
128 K
STM8AF/H/P5199
96 K
68/37
6K
2K
16
STM8AF/H/P5189
LQFP64
(10x10)
64 K
1.5 K
STM8AF/H/P5179
48 K
3K
STM8AF/H/P5169
32 K
2K
1K
STM8AF/H/P51A8
128 K
6K
2K
STM8AF/H/P5198
96 K
STM8AF/H/P5188
LQFP48
(7x7)
64 K
4K
10
1.5 K
STM8AF/H/P5178
48 K
3K
STM8AF/H/P5168
32 K
2K
12/110
CAN,
1x8-bit: TIM4
LIN(UART)
3x16-bit: TIM1,
, SPI,
TIM2, TIM3
USART,
(9/9/9)
I²C
4K
1K
Doc ID 14395 Rev 9
52/36
38/35
STM8AF52/62xx, STM8AF51/61xx
²
Table 5.
Product line-up
STM8AF/H/P61xx product line-up without CAN
Order code
Package
STM8AF/H/P61AA
STM8AF/H/P619A
High
density
Data
Flash
RAM
EEPROM
program (bytes)
(bytes)
memory
(bytes)
10-bit
A/D
chan.
Timers
(IC/OC/PWM)
I/0
Serial
wakeup
interfaces
pins
128 K
LQFP80
(14x14)
96 K
STM8AF/H/P618A
64 K
STM8AF/H/P61A9
128 K
STM8AF/H/P6199
96 K
68/37
6K
2K
16
STM8AF/H/P6189
LQFP64
(10x10)
64 K
4K
1.5 K
STM8AF/H/P6179
48 K
3K
STM8AF/H/P6169
32 K
2K
1K
STM8AF/H/P61A8
128 K
6K
2K
STM8AF/H/P6198
STM8AF/H/P6188
LQFP48
(7x7)
STM8AF/H/P6178
STM8AF/H/P6186
STM8AF/H/P6176
LQFP32
(7x7)/
1x8-bit: TIM4
3x16-bit:
TIM1, TIM2,
TIM3
(9/9/9)
LIN(UART),
SPI,
USART, I²C
52/36
96 K
10
64 K
4K
48 K
3K
64 K
4K
1.5 K
7
48 K
3K
Doc ID 14395 Rev 9
38/35
1x8-bit: TIM4
3x16-bit:
TIM1, TIM2,
TIM3 (8/8/8)
LIN(UART),
SPI, I²C
25/23
13/110
Block diagram
4
STM8AF52/62xx, STM8AF51/61xx
Block diagram
Figure 1.
STM8A block diagram
Reset block
XTAL 1-24 MHz
Clock controller
Reset
Reset
RC int. 16 MHz
Detector
POR
RC int. 128 kHz
BOR
Clock to peripherals and core
Window WDG
STM8A CORE
IWDG
Master/slave
automatic
resynchronization
400 Kbit/s
10 Mbit/s
Up to 128 Kbyte
high density program
Flash
Debug/SWIM
LINUART
I2C
SPI
Address and data bus
Single wire
debug interf.
Up to 2 Kbytes
data EEPROM
Up to 6 Kbytes
RAM
Boot ROM
LIN master
SPI emul.
USART
16-bit advanced control
timer (TIM1)
1 Mbit/s
beCAN
16-bit general purpose
(TIM2, TIM3)
Up to
16 channels
8-bit AR timer
(TIM4)
10-bit ADC
AWU timer
1. Legend:
ADC: Analog-to-digital converter
beCAN: Controller area network
BOR: Brownout reset
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent window watchdog
LINUART: Local interconnect network universal asynchronous receiver transmitter
POR: Power on reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
Window WDG: Window watchdog
14/110
Doc ID 14395 Rev 9
Up to
9 CAPCOM
channels
STM8AF52/62xx, STM8AF51/61xx
5
Product overview
Product overview
This section is intended to describe the family features that are actually implemented in the
products covered by this datasheet.
For more detailed information on each feature please refer to the STM8S and STM8A
microcontroller families reference manual (RM0016).
5.1
STM8A central processing unit (CPU)
The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency
and performance. It contains 21 internal registers (six directly addressable in each execution
context), 20 addressing modes including indexed indirect and relative addressing and 80
instructions.
5.1.1
5.1.2
5.1.3
Architecture and registers
●
Harvard architecture
●
3-stage pipeline
●
32-bit wide program memory bus with single cycle fetching for most instructions
●
X and Y 16-bit index registers, enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
●
8-bit accumulator
●
24-bit program counter with 16-Mbyte linear memory space
●
16-bit stack pointer with access to a 64 Kbyte stack
●
8-bit condition code register with seven condition flags for the result of the last
instruction.
Addressing
●
20 addressing modes
●
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
●
Stack pointer relative addressing mode for efficient implementation of local variables
and parameter passing
Instruction set
●
80 instructions with 2-byte average instruction size
●
Standard data movement and logic/arithmetic functions
●
8-bit by 8-bit multiplication
●
16-bit by 8-bit and 16-bit by 16-bit division
●
Bit manipulation
●
Data transfer between stack and accumulator (push/pop) with direct stack access
●
Data transfer using the X and Y registers or direct memory-to-memory transfers
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Product overview
STM8AF52/62xx, STM8AF51/61xx
5.2
Single wire interface module (SWIM) and debug module (DM)
5.2.1
SWIM
The single wire interface module, SWIM, together with an integrated debug module, permits
non-intrusive, real-time in-circuit debugging and fast memory programming. The interface
can be activated in all device operation modes and can be connected to a running device
(hot plugging).The maximum data transmission speed is 145 bytes/ms.
5.2.2
Debug module
The non-intrusive debugging module features a performance close to a full-flavored
emulator. Besides memory and peripheral operation, CPU operation can also be monitored
in real-time by means of shadow registers.
5.3
5.4
●
R/W of RAM and peripheral registers in real-time
●
R/W for all resources when the application is stopped
●
Breakpoints on all program-memory instructions (software breakpoints), except the
interrupt vector table
●
Two advanced breakpoints and 23 predefined breakpoint configurations
Interrupt controller
●
Nested interrupts with three software priority levels
●
24 interrupt vectors with hardware priority
●
Five vectors for external interrupts (up to 37 depending on the package)
●
Trap and reset interrupts
Flash program and data EEPROM
●
32 Kbytes to 128 Kbytes of high density single voltage Flash program memory
●
Up to 2 Kbytes true (not emulated) data EEPROM
●
Read while write: writing in the data memory is possible while executing code in the
Flash program memory.
The whole Flash program memory and data EEPROM are factory programmed with 0x00.
5.4.1
16/110
Architecture
●
The memory is organized in blocks of 128 bytes each
●
Read granularity: 1 word = 4 bytes
●
Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel
●
Writing, erasing, word and block management is handled automatically by the memory
interface.
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
5.4.2
Product overview
Write protection (WP)
Write protection in application mode is intended to avoid unintentional overwriting of the
memory. The write protection can be removed temporarily by executing a specific sequence
in the user software.
5.4.3
Protection of user boot code (UBC)
If the user chooses to update the Flash program memory using a specific boot code to
perform in application programming (IAP), this boot code needs to be protected against
unwanted modification.
In the STM8A a memory area of up to 128 Kbytes can be protected from overwriting at user
option level. Other than the standard write protection, the UBC protection can exclusively be
modified via the debug interface, the user software cannot modify the UBC protection status.
The UBC memory area contains the reset and interrupt vectors and its size can be adjusted
in increments of 512 bytes by programming the UBC and NUBC option bytes
(see Section 9: Option bytes on page 51).
Figure 2.
Data
EEPROM
memory
Flash memory organization of STM8A products
Data memory area
Option bytes
UBC area
Remains write protected during IAP
Programmable area from 1 Kbyte
(first two pages) up to program memory
end - maximum 128 Kbytes
Flash
program
memory
Program memory area
Write access possible for IAP
5.4.4
Read-out protection (ROP)
The STM8A provides a read-out protection of the code and data memory which can be
activated by an option byte setting (see the ROP option byte in section 10).
The read-out protection prevents reading and writing Flash program memory, data memory
and option bytes via the debug module and SWIM interface. This protection is active in all
device operation modes. Any attempt to remove the protection by overwriting the ROP
option byte triggers a global erase of the program and data memory.
The ROP circuit may provide a temporary access for debugging or failure analysis. The
temporary read access is protected by a user defined, 8-byte keyword stored in the option
byte area. This keyword must be entered via the SWIM interface to temporarily unlock the
device.
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Product overview
STM8AF52/62xx, STM8AF51/61xx
If desired, the temporary unlock mechanism can be permanently disabled by the user
through OPT6/NOPT6 option bytes.
5.5
Clock controller
The clock controller distributes the system clock coming from different oscillators to the core
and the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness.
5.5.1
Features
●
5.5.2
Clock sources
–
16 MHz high-speed internal RC oscillator (HSI)
–
128 kHz low-speed internal RC (LSI)
–
1-24 MHz high-speed external crystal (HSE)
–
Up to 24 MHz high-speed user-external clock (HSE user-ext)
●
Reset: After reset the microcontroller restarts by default with an internal 2-MHz clock
(16 MHz/8). The clock source and speed can be changed by the application program
as soon as the code execution starts.
●
Safe clock switching: Clock sources can be changed safely on the fly in Run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
●
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
●
Wakeup: In case the device wakes up from low-power modes, the internal RC
oscillator (16 MHz/8) is used for quick startup. After a stabilization time, the device
switches to the clock source that was selected before Halt mode was entered.
●
Clock security system (CSS): The CSS permits monitoring of external clock sources
and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.
●
Configurable main clock output (CCO): This feature permits to outputs a clock signal
for use by the application.
16 MHz high-speed internal RC oscillator (HSI)
●
Default clock after reset 2 MHz (16 MHz/8)
●
Fast wakeup time
User trimming
The register CLK_HSITRIMR with two trimming bits plus one additional bit for the sign
permits frequency tuning by the application program. The adjustment range covers all
possible frequency variations versus supply voltage and temperature. This trimming does
not change the initial production setting.
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STM8AF52/62xx, STM8AF51/61xx
5.5.3
Product overview
128 kHz low-speed internal RC oscillator (LSI)
The frequency of this clock is 128 kHz and it is independent from the main clock. It drives
the independent watchdog or the AWU wakeup timer.
In systems which do not need independent clock sources for the watchdog counters, the
128 kHz signal can be used as the system clock. This configuration has to be enabled by
setting an option byte (OPT3/OPT3N, bit LSI_EN).
5.5.4
24 MHz high-speed external crystal oscillator (HSE)
The external high-speed crystal oscillator can be selected to deliver the main clock in
normal Run mode. It operates with quartz crystals and ceramic resonators.
5.5.5
●
Frequency range: 1 MHz to 24 MHz
●
Crystal oscillation mode: preferred fundamental
●
I/Os: standard I/O pins multiplexed with OSCIN, OSCOUT
External clock input
An external clock signal can be applied to the OSCIN input pin of the crystal oscillator. The
frequency range is 0 to 24 MHz.
5.5.6
Clock security system (CSS)
The clock security system protects against a system stall in case of an external crystal clock
failure.
In case of a clock failure an interrupt is generated and the high-speed internal clock (HSI) is
automatically selected with a frequency of 2 MHz (16 MHz/8).
Table 6.
Peripheral clock gating bits (CLK_PCKENR1)
Control bit
Peripheral
PCKEN17
TIM1
PCKEN16
TIM3
PCKEN15
TIM2
PCKEN14
TIM4
PCKEN13
LINUART
PCKEN12
USART
PCKEN11
SPI
PCKEN10
I2C
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Product overview
Table 7.
5.6
STM8AF52/62xx, STM8AF51/61xx
Peripheral clock gating bits (CLK_PCKENR2)
Control bit
Peripheral
PCKEN27
CAN
PCKEN26
Reserved
PCKEN25
Reserved
PCKEN24
Reserved
PCKEN23
ADC
PCKEN22
AWU
PCKEN21
Reserved
PCKEN20
Reserved
Low-power operating modes
For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between lowest
power consumption, fastest start-up time and available wakeup sources.
●
Wait mode
In this mode, the CPU is stopped but peripherals are kept running. The wakeup is
performed by an internal or external interrupt or reset.
●
Active-halt mode with regulator on
In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is
generated at programmable intervals by the auto wake up unit (AWU). The main
voltage regulator is kept powered on, so current consumption is higher than in Activehalt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the
internal AWU interrupt, external interrupt or reset.
●
Active-halt mode with regulator off
This mode is the same as Active-halt with regulator on, except that the main voltage
regulator is powered off, so the wake up time is slower.
●
Halt mode
CPU and peripheral clocks are stopped, the main voltage regulator is powered off.
Wakeup is triggered by external event or reset.
In all modes the CPU and peripherals remain permanently powered on, the system clock is
applied only to selected modules. The RAM content is preserved and the brown-out reset
circuit remains activated.
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STM8AF52/62xx, STM8AF51/61xx
5.7
Timers
5.7.1
Watchdog timers
Product overview
The watchdog system is based on two independent timers providing maximum security to
the applications. The watchdog timer activity is controlled by the application program or
option bytes. Once the watchdog is activated, it cannot be disabled by the user program
without going through reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
timing perfectly. The application software must refresh the counter before time-out and
during a limited time window. If the counter is refreshed outside this time window, a reset is
issued.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve malfunctions due to hardware
or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure. If the hardware watchdog feature is enabled through the device
option bits, the watchdog is automatically enabled at power-on, and generates a reset
unless the key register is written by software before the counter reaches the end of count.
5.7.2
Auto-wakeup counter
This counter is used to cyclically wakeup the device in Active-halt mode. It can be clocked by
the internal 128 kHz internal low-frequency RC oscillator or external clock.
LSI clock can be internally connected to TIM3 input capture channel 1 for calibration.
5.7.3
Beeper
This function generates a rectangular signal in the range of 1, 2 or 4 kHz which can be
output on a pin. This is useful when audible sounds without interference need to be
generated for use in the application.
5.7.4
Advanced control and general purpose timers
STM8A devices described in this datasheet, contain up to three 16-bit advanced control and
general purpose timers providing nine CAPCOM channels in total. A CAPCOM channel can
be used either as input compare, output compare or PWM channel. These timers are
named TIM1, TIM2 and TIM3.
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Product overview
Table 8.
STM8AF52/62xx, STM8AF51/61xx
Advanced control and general purpose timers
Timer
Counter
width
TIM1
16-bit
Counter
type
Prescaler
Channels
factor
Up/down 1 to 65536
TIM2
16-bit
Up
TIM3
16-bit
Up
2n
n = 0 to 15
2n
n = 0 to 15
Inverted Repetition
outputs
counter
trigger
unit
External
trigger
Break
input
4
3
Yes
Yes
Yes
Yes
3
None
No
No
No
No
2
None
No
No
No
No
TIM1 - advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and bridge driver.
●
16-bit up, down and up/down AR (auto-reload) counter with 16-bit fractional prescaler.
●
Four independent CAPCOM channels configurable as input capture, output compare,
PWM generation (edge and center aligned mode) and single pulse mode output
●
Trigger module which allows the interaction of TIM1 with other on-chip peripherals. In
the present implementation it is possible to trigger the ADC upon a timer event.
●
External trigger to change the timer behavior depending on external signals
●
Break input to force the timer outputs into a defined state
●
Three complementary outputs with adjustable dead time
●
Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break
TIM2, TIM3 - 16-bit general purpose timers
5.7.5
●
16-bit auto-reload up-counter
●
15-bit prescaler adjustable to fixed power of two ratios 1…32768
●
Timers with three or two individually configurable CAPCOM channels
●
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
Basic timer
The typical usage of this timer (TIM4) is the generation of a clock tick.
Table 9.
TIM4
Timer
Counter
width
Counter
type
TIM4
8-bit
Up
22/110
Prescaler
Channels
factor
2n
n = 0 to 7
Inverted Repetition
outputs
counter
0
None
No
trigger
unit
External
trigger
Break
input
No
No
No
●
8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128
●
Clock source: master clock
●
Interrupt source: 1 x overflow/update
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
5.8
Product overview
Analog to digital converter (ADC)
The STM8A products described in this datasheet contain a 10-bit successive approximation
ADC with up to 16 multiplexed input channels, depending on the package.
The ADC name differs between the datasheet and the STM8A/S reference manual (see
Table 10).
Table 10.
ADC naming
Peripheral name in datasheet
Peripheral name in reference manual
(RM0016)
ADC
ADC2
ADC features
5.9
●
10-bit resolution
●
Single and continuous conversion modes
●
Programmable prescaler: fMASTER divided by 2 to 18
●
Conversion trigger on timer events, and external events
●
Interrupt generation at end of conversion
●
Selectable alignment of 10-bit data in 2 x 8 bit result registers
●
Shadow registers for data consistency
●
ADC input range: VSSA ≤VIN ≤VDDA
●
Schmitt-trigger on analog inputs can be disabled to reduce power consumption
Communication interfaces
The following sections give a brief overview of the communication peripheral. Some
peripheral names differ between the datasheet and the STM8A/S reference manual (see
Table 11).
Table 11.
5.9.1
Communication peripheral naming correspondence
Peripheral name in datasheet
Peripheral name in reference manual
(RM0016)
USART
UART1
LINUART
UART3
Universal synchronous/asynchronous receiver transmitter (USART)
The devices covered by this datasheet contain one USART interface. The USART can
operate in standard SCI mode (serial communication interface, asynchronous) or in SPI
emulation mode. It is equipped with a 16 bit fractional prescaler. It features LIN master
support.
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Product overview
STM8AF52/62xx, STM8AF51/61xx
Detailed feature list:
●
Full duplex, asynchronous communications
●
NRZ standard format (mark/space)
●
High-precision baud rate generator system
–
●
Programmable data word length (8 or 9 bits)
●
Configurable stop bits: Support for 1 or 2 stop bits
●
LIN master mode:
–
LIN break and delimiter generation
–
LIN break and delimiter detection with separate flag and interrupt source for
readback checking.
●
Transmitter clock output for synchronous communication
●
Separate enable bits for transmitter and receiver
●
Transfer detection flags:
●
●
●
●
24/110
Common programmable transmit and receive baud rates up to fMASTER/16
–
Receive buffer full
–
Transmit buffer empty
–
End of transmission flags
Parity control:
–
Transmits parity bit
–
Checks parity of received data byte
Four error detection flags:
–
Overrun error
–
Noise error
–
Frame error
–
Parity error
Six interrupt sources with flags:
–
Transmit data register empty
–
Transmission complete
–
Receive data register full
–
Idle line received
–
Parity error
–
LIN break and delimiter detection
Two interrupt vectors:
–
Transmitter interrupt
–
Receiver interrupt
●
Reduced power consumption mode
●
Wakeup from mute mode (by idle line detection or address mark detection)
●
Two receiver wakeup modes:
–
Address bit (MSB)
–
Idle line
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
5.9.2
Product overview
Universal asynchronous receiver/transmitter with LIN support
(LINUART)
The devices covered by this datasheet contain one LINUART interface. The interface is
available on all the supported packages. The LINUART is an asynchronous serial
communication interface which supports extensive LIN functions tailored for LIN slave
applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.1.
Detailed feature list:
LIN mode
Master mode
●
LIN break and delimiter generation
●
LIN break and delimiter detection with separate flag and interrupt source for read back
checking.
Slave mode
●
Autonomous header handling – one single interrupt per valid header
●
Mute mode to filter responses
●
Identifier parity error checking
●
LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI)
clock source
●
Break detection at any time, even during a byte reception
●
Header errors detection:
–
Delimiter too short
–
Synch field error
–
Deviation error (if automatic resynchronization is enabled)
–
Framing error in synch field or identifier field
–
Header time-out
UART mode
●
Full duplex, asynchronous communications - NRZ standard format (mark/space)
●
High-precision baud rate generator
–
A common programmable transmit and receive baud rates up to fMASTER/16
●
Programmable data word length (8 or 9 bits) – 1 or 2 stop bits – parity control
●
Separate enable bits for transmitter and receiver
●
Error detection flags
●
Reduced power consumption mode
●
Multi-processor communication - enter mute mode if address match does not occur
●
Wakeup from mute mode (by idle line detection or address mark detection)
●
Two receiver wakeup modes:
–
Address bit (MSB)
–
Idle line
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Product overview
5.9.3
STM8AF52/62xx, STM8AF51/61xx
Serial peripheral interface (SPI)
The devices covered by this datasheet contain one SPI. The SPI is available on all the
supported packages.
5.9.4
●
Maximum speed: 8 Mbit/s or fMASTER/2 both for master and slave
●
Full duplex synchronous transfers
●
Simplex synchronous transfers on two lines with a possible bidirectional data line
●
Master or slave operation - selectable by hardware or software
●
CRC calculation
●
1 byte Tx and Rx buffer
●
Slave mode/master mode management by hardware or software for both master and
slave
●
Programmable clock polarity and phase
●
Programmable data order with MSB-first or LSB-first shifting
●
Dedicated transmission and reception flags with interrupt capability
●
SPI bus busy status flag
●
Hardware CRC feature for reliable communication:
–
CRC value can be transmitted as last byte in Tx mode
–
CRC error checking for last received byte
Inter integrated circuit (I2C) interface
The devices covered by this datasheet contain one I2C interface. The interface is available
on all the supported packages.
●
●
–
Clock generation
–
Start and stop generation
2
I C slave features:
–
Programmable I2C address detection
–
Stop bit detection
●
Generation and detection of 7-bit/10-bit addressing and general call
●
Supports different communication speeds:
●
●
26/110
I2C master features:
–
Standard speed (up to 100 kHz),
–
Fast speed (up to 400 kHz)
Status flags:
–
Transmitter/receiver mode flag
–
End-of-byte transmission flag
–
I2C busy flag
Error flags:
–
Arbitration lost condition for master mode
–
Acknowledgement failure after address/data transmission
–
Detection of misplaced start or stop condition
–
Overrun/underrun if clock stretching is disabled
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
●
●
5.9.5
Product overview
Interrupt:
–
Successful address/data communication
–
Error condition
–
Wakeup from Halt
Wakeup from Halt on address detection in slave mode
Controller area network interface (beCAN)
The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the
CAN protocol version 2.0A and B. It is equipped with a receive FIFO and a very versatile
filter bank. Together with a filter match index, this allows a very efficient message handling in
today’s car network architectures. The CPU is significantly unloaded. The maximum
transmission speed is 1 Mbit/s.
Transmission
●
Three transmit mailboxes
●
Configurable transmit priority by identifier or order request
Reception
●
11- and 29-bit ID
●
1 receive FIFO (3 messages deep)
●
Software-efficient mailbox mapping at a unique address space
●
FMI (filter match index) stored with message for quick message association
●
Configurable FIFO overrun
●
Time stamp on SOF reception
●
6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking
configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID.
●
Filtering modes (mixable):
–
Mask mode permitting ID range filtering
–
ID list mode
Interrupt management
●
Maskable interrupt
●
Software-efficient mailbox mapping at a unique address space
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Product overview
5.10
STM8AF52/62xx, STM8AF51/61xx
Input/output specifications
The product features four I/O types:
●
Standard I/O 2 MHz
●
Fast I/O up to 10 MHz
●
High sink 8 mA, 2 MHz
●
True open drain (I2C interface)
To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum
slew rate. The rise and fall times are similar to those of standard I/Os.
The analog inputs are equipped with a low leakage analog switch. Additionally, the schmitttrigger input stage on the analog I/Os can be disabled in order to reduce the device standby
consumption.
STM8A I/Os are designed to withstand current injection. For a negative injection current of
4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. Thanks to
this feature, external protection diodes against current injection are no longer required.
28/110
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STM8AF52/62xx, STM8AF51/61xx
Pinouts and pin description
6
Pinouts and pin description
6.1
Package pinouts
LQFP 80-pin pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PD7/TLI
PD6/LINUART_RX
PD5/LINUART_TX
PD4 (HS)/TIM2_CH1/BEEP
PD3 (HS)/TIM2_CH2
PD2 (HS)/TIM3_CH1
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2
PI7
PI6
PE0/CLK_CCO
PE1/I2C_SCL
PE2/I 2C_SDA
PE3/TIM1_BKIN
PE4
PG7
PG6
PG5
PI5
PI4
Figure 3.
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PI3
PI2
PI1
PI0
PG4
PG3
PG2
PG1/CAN_RX(1)
PG0/CAN_TX(1)
PC7/SPI_MISO
PC6/SPI_MOSI
VDDIO_2
VSSIO_2
PC5/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PC0/ADC_ETR
PE5/SPI_NSS
AIN11/PF3
VREF+
VDDA
VSSA
VREFAIN10/PF0
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4
AIN3/PB3
AIN2/PB2
AIN1/PB1
AIN0/PB0
TIM1_ETR/PH4
TIM1_CH3N/PH5
TIM1_CH2N/PH6
TIM1_CH1N/PH7
AIN8/PE7
AIN9/PE6
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
TIM2_CH3/PA3
USART_RX/PA4
USART_TX/PA5
USART_CK/PA6
(HS) PH0
(HS) PH1
PH2
PH3
AIN15/PF7
AIN14/PF6
AIN13/PF5
AIN12/PF4
1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines.
2. (HS) stands for high sink capability.
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Pinouts and pin description
LQFP 64-pin pinout
PD7/TLI
PD6/LINUART_RX
PD5/LINUART_TX
PD4 (HS)/TIM2_CH1/ BEEP
PD3 (HS)/TIM2_CH2/ADC_ETR
PD2 (HS)/TIM3_CH1
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2
PE0/CLK_CCO
PE1/I2C_SCL
PE2/I2C_SDA
PE3/TIM1_BKIN
PE4
PG7
PG6
PG5
Figure 4.
STM8AF52/62xx, STM8AF51/61xx
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PI0
PG4
PG3
PG2
PG1/CAN_RX(1)
PG0/CAN_TX(1)
PC7/SPI_MISO
PC6/SPI_MOSI
VDDIO_2
VSSIO_2
PC5/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
AIN11/PF3
VREF+
VDDA
VSSA
VREFAIN10/PF0
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4
TIM1_ETR/AIN3/PB3
TIM1_CH3N/AIN2/PB2
TIM1_CH2N/AIN1/PB1
TIM1_CH1N/AIN0/PB0
AIN8/PE7
AIN9/PE6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
TIM2_CH3/PA3
USART_RX/PA4
USART_TX/PA5
USART_CK/PA6
AIN15/PF7
AIN14/PF6
AIN13/PF5
AIN12/PF4
1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines.
2.
30/110
HS stands for high sink capability.
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
LQFP 48-pin pinout
PD7/TLI
PD6/LINUART_RX
PD5/LINUART_TX
PD4 (HS)/TIM2_CH1/BEEP
PD3 (HS)/TIM2_CH2/ADC_ETR
PD2 (HS)/TIM3_CH1
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2
PE0/CLK_CCO
PE1/I2C_SCL
PE2/I2C_SDA
PE3/TIM1_BKIN
Figure 5.
Pinouts and pin description
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
3
34
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 2223 24
PG1/CAN_Rx
PG0/CAN_Tx
PC7/SPI_MISO
PC6/SPI_MOSI
VDDIO_2
VSSIO_2
PC5/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
VDDA
VSSA
AIN7/PB7
AIN6/PB6
AIN5/PB5
AIN4/PB4
TIM1_ETR/AIN3/PB3
TIM1_CH3N/AIN2/PB2
TIM1_CH2N/AIN1/PB1
TIM1_CH1N/AIN0/PB0
AIN8/PE7
AIN9/PE6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
TIM2_CH3/PA3
USART_RX/PA4
USART_TX/PA5
USART_CK/PA6
1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines.
2.
HS stands for high sink capability.
Doc ID 14395 Rev 9
31/110
Pinouts and pin description
LQFP/VFQFPN 32-pin pinout
PD7/TLI
PD6/LINUART_RX
PD5/LINUART_TX
PD4 (HS)/TIM2_CH1/BEEP
PD3 (HS)/TIM2_CH2/ADC_ETR
PD2 (HS)/TIM3_CH1/TIM2_CH3
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2/CLK_CCO/TIM1_BRK
Figure 6.
STM8AF52/62xx, STM8AF51/61xx
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 1516
PC7/SPI_MISO
PC6/SPI_MOSI
PC5/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
VDDA
VSSA
I2C_SDA/AIN5/PB5
I2C_SCL/AIN4/PB4
TIM1_ETR/AIN3/PB3
TIM1_CH3N/AIN2/PB2
TIM1_CH2N/AIN1/PB1
TIM1_CH1N/AIN0/PB0
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
VDDIO
AIN12/PF4
1.
HS stands for high sink capability.
Table 12.
Legend/abbreviation for the pin description table
Type
I= input, O = output, S = power supply
Input
CM = CMOS (standard for all I/Os)
Output
HS = high sink (8 mA)
Level
Output speed
Port and control
configuration
Reset state
32/110
O1 = Standard (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Input
float = floating, wpu = weak pull-up
Output
T = true open drain, OD = open drain, PP = push pull
Bold X (pin state after reset release).
Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 13.
Pinouts and pin description
STM8A microcontroller family pin description
LQFP48
LQFP32/VFQFPN32
Type
floating
wpu
Ext. interrupt
High sink
Speed
OD
PP
Output
LQFP64
Input
LQFP80
Pin number
1
1
1
1
NRST
I/O
-
X
—
—
—
—
—
2
2
2
2
PA1/OSCIN(1)
I/O
X
X
—
— O1
X
X
Port A1
Resonator/
crystal in
—
3
3
3
3
PA2/OSCOUT
I/O
X
X
X
— O1
X
X
Port A2
Resonator/
crystal out
—
4
4
4
-
VSSIO_1
S
—
—
—
—
—
—
—
I/O ground
—
5
5
5
4
VSS
S
—
—
—
—
—
—
—
Digital ground
—
6
6
6
5
VCAP
S
—
—
—
—
—
—
— 1.8 V regulator capacitor
—
7
7
7
6
VDD
S
—
—
—
—
—
—
—
Digital power supply
—
8
8
8
7
VDDIO_1
S
—
—
—
—
—
—
—
I/O power supply
—
9
9
9
-
PA3/TIM2_CH3
I/O
X
X
X
— O1
X
X
Port A3
Timer 2 channel 3
TIM3_CH1
[AFR1]
10 10 10
-
PA4/USART_RX I/O
X
X
X
— O3
X
X
Port A4
USART
receive
—
11 11 11
-
PA5/USART_TX I/O
X
X
X
— O3
X
X
Port A5
USART
transmit
—
12 12 12
-
PA6/USART_CK I/O
X
X
X
— O3
X
X
Port A6
USART
synchronous
clock
—
13
-
-
-
PH0
I/O
X
X
—
HS O3
X
X
Port H0
—
—
14
-
-
-
PH1
I/O
X
X
—
HS O3
X
X
Port H1
—
—
15
-
-
-
PH2
I/O
X
X
—
— O1
X
X
Port H2
—
—
16
-
-
-
PH3
I/O
X
X
—
— O1
X
X
Port H3
—
—
17 13
-
-
PF7/AIN15
I/O
X
X
—
— O1
X
X
Port F7
Analog
input 15
—
18 14
-
-
PF6/AIN14
I/O
X
X
—
— O1
X
X
Port F6
Analog
input 14
—
19 15
-
-
PF5/AIN13
I/O
X
X
—
— O1
X
X
Port F5
Analog
input 13
—
20 16
-
8
PF4/AIN12
I/O
X
X
—
— O1
X
X
Port F4
Analog
input 12
—
21 17
-
-
PF3/AIN11
I/O
X
X
—
— O1
X
X
Port F3
Analog
input 11
—
Pin name
Doc ID 14395 Rev 9
Main
function
(after
reset)
Default
alternate
function
Reset
Alternate
function
after remap
[option bit]
—
33/110
Pinouts and pin description
Table 13.
STM8AF52/62xx, STM8AF51/61xx
STM8A microcontroller family pin description (continued)
floating
wpu
Ext. interrupt
High sink
Speed
OD
PP
-
VREF+
S
—
—
—
—
—
—
—
ADC positive reference
voltage
—
9
VDDA
S
—
—
—
—
—
—
—
Analog power supply
—
24 20 14 10
VSSA
S
—
—
—
—
—
—
—
Analog ground
—
25 21
-
-
VREF-
S
—
—
—
—
—
—
—
ADC negative reference
voltage
—
26 22
-
-
PF0/AIN10
I/O
X
X
—
— O1
X
X
Port F0
Analog
input 10
—
27 23 15
-
PB7/AIN7
I/O
X
X
X
— O1
X
X
Port B7
Analog input
7
—
28 24 16
-
PB6/AIN6
I/O
X
X
X
— O1
X
X
Port B6
Analog input
6
—
29 25 17 11
PB5/AIN5
I/O
X
X
X
— O1
X
X
Port B5
Analog input
5
I2C_SDA
[AFR6]
30 26 18 12
PB4/AIN4
I/O
X
X
X
— O1
X
X
Port B4
Analog input
4
I2C_SCL
[AFR6]
31 27 19 13
PB3/AIN3
I/O
X
X
X
— O1
X
X
Port B3
Analog input
3
TIM1_ETR
[AFR5]
32 28 20 14
PB2/AIN2
I/O
X
X
X
— O1
X
X
Port B2
Analog input
TIM1_CH3N
[AFR5]
33 29 21 15
PB1/AIN1
I/O
X
X
X
— O1
X
X
Port B1
Analog input
1
TIM1_CH2N
[AFR5]
34 30 22 16
PB0/AIN0
I/O
X
X
X
— O1
X
X
Port B0
Analog input
0
TIM1_CH1N
[AFR5]
PH4/TIM1_ETR I/O
X
X
—
— O1
X
X
Port H4
Timer 1 trigger input
—
LQFP64
-
LQFP80
Pin name
Type
Output
LQFP32/VFQFPN32
Input
LQFP48
Pin number
22 18
23 19 13
Main
function
(after
reset)
Default
alternate
function
Alternate
function
after remap
[option bit]
35
-
-
-
36
-
-
-
PH5/
TIM1_CH3N
I/O
X
X
—
— O1
X
X
Port H5
Timer 1 inverted
channel 3
—
37
-
-
-
PH6/
TIM1_CH2N
I/O
X
X
—
— O1
X
X
Port H6
Timer 1 inverted
channel 2
—
38
-
-
-
PH7/
TIM1_CH1N
I/O
X
X
—
— O1
X
X
Port H7
Timer 1 inverted
channel 2
—
34/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 13.
Pinouts and pin description
STM8A microcontroller family pin description (continued)
Input
wpu
Ext. interrupt
High sink
Speed
OD
PP
I/O
X
X
—
— O1
X
X
Port E7
Analog input
8
—
PE6/AIN9
I/O
X
X
X
— O1
X
X
Port E7
Analog input
9
—
41 33 25 17
PE5/SPI_NSS
I/O
X
X
X
— O1
X
X
Port E5
SPI master/
slave select
—
42
PC0/ADC_ETR
I/O
X
X
X
— O1
X
X
Port C0
ADC trigger
input
—
43 34 26 18 PC1/TIM1_CH1 I/O
X
X
X
HS O3
X
X
Port C1
Timer 1 channel 1
—
44 35 27 19 PC2/TIM1_CH2 I/O
X
X
X
HS O3
X
X
Port C2
Timer 1channel 2
—
45 36 28 20 PC3/TIM1_CH3 I/O
X
X
X
HS O3
X
X
Port C3
Timer 1 channel 3
—
46 37 29 21 PC4/TIM1_CH4 I/O
X
X
X
HS O3
X
X
Port C4
Timer 1 channel 4
—
47 38 30 22
Port C5
SPI clock
—
LQFP48
PE7/AIN8
LQFP64
Main
function
(after
reset)
LQFP80
Pin name
floating
Output
Type
LQFP32/VFQFPN32
Pin number
39 31 23
-
40 32 24
-
-
-
PC5/SPI_SCK
I/O
X
X
X
— O3
X
X
Default
alternate
function
Alternate
function
after remap
[option bit]
48 39 31
-
VSSIO_2
S
—
—
—
—
—
—
—
I/O ground
—
49 40 32
-
VDDIO_2
S
—
—
—
—
—
—
—
I/O power supply
—
50 41 33 23
PC6/SPI_MOSI
I/O
X
X
X
— O3
X
X
Port C6
SPI master
out/
slave in
—
51 42 34 24
PC7/SPI_MISO
I/O
X
X
X
— O3
X
X
Port C7
SPI master
in/ slave out
—
52 43 35
-
PG0/CAN_Tx
I/O
X
X
—
— O1
X
X
Port G0 CAN transmit
—
53 44 36
-
PG1/CAN_Rx
I/O
X
X
—
— O1
X
X
Port G1
CAN receive
—
54 45
-
-
PG2
I/O
X
X
—
— O1
X
X
Port G2
—
—
55 46
-
-
PG3
I/O
X
X
—
— O1
X
X
Port G3
—
—
56 47
-
-
PG4
I/O
X
X
—
— O1
X
X
Port G4
—
—
57 48
-
-
PI0
I/O
X
X
—
— O1
X
X
Port I0
—
—
58
-
-
-
PI1
I/O
X
X
—
— O1
X
X
Port I1
—
—
59
-
-
-
PI2
I/O
X
X
—
— O1
X
X
Port I2
—
—
60
-
-
-
PI3
I/O
X
X
—
— O1
X
X
Port I3
—
—
Doc ID 14395 Rev 9
35/110
Pinouts and pin description
Table 13.
STM8AF52/62xx, STM8AF51/61xx
STM8A microcontroller family pin description (continued)
LQFP32/VFQFPN32
floating
wpu
Ext. interrupt
High sink
Speed
OD
PP
Main
function
(after
reset)
61
-
-
-
PI4
I/O
X
X
—
— O1
X
X
Port I4
—
—
62
-
-
-
PI5
I/O
X
X
—
— O1
X
X
Port I5
—
—
63 49
-
-
PG5
I/O
X
X
—
— O1
X
X
Port G5
—
—
64 50
-
-
PG6
I/O
X
X
—
— O1
X
X
Port G6
—
—
65 51
-
-
PG7
I/O
X
X
—
— O1
X
X
Port G7
—
—
66 52
-
-
PE4
I/O
X
X
X
— O1
X
X
Port E4
—
—
PE3/TIM1_BKIN I/O
X
X
X
— O1
X
X
Port E3
Timer 1 break input
—
X
—
X
— O1 T(2)
-
Port E2
I2C data
—
-
Port E1
I2C
—
Pin name
Type
LQFP48
Output
LQFP64
Input
LQFP80
Pin number
67 53 37
-
68 54 38
-
PE2/I2C_SDA
69 55 39
-
2C_SCL
70 56 40
-
71
-
-
72
-
-
I/O
Default
alternate
function
Alternate
function
after remap
[option bit]
I/O
X
—
X
— O1
T(2)
PE0/CLK_CCO
I/O
X
X
X
— O3
X
X
Port E0
Configurable
clock output
—
-
PI6
I/O
X
X
—
— O1
X
X
Port I6
—
—
-
PI7
I/O
X
X
—
— O1
X
X
Port I7
—
—
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
PE1/I
clock
X
X
X
HS O3
X
X
Port D0
Timer 3 channel 2
I/O
X
X
X
HS O4
X
X
Port D1
SWIM data
interface
—
75 59 43 27 PD2/TIM3_CH1 I/O
X
X
X
HS O3
X
X
Port D2
Timer 3 channel 1
TIM2_CH3
[AFR1]
76 60 44 28 PD3/TIM2_CH2 I/O
X
X
X
HS O3
X
X
Port D3
Timer 2 channel 2
ADC_ETR
[AFR0]
PD4/TIM2_CH1/
I/O
BEEP
X
X
X
HS O3
X
X
Port D4
Timer 2 channel 1
BEEP output
[AFR7]
X
X
X
— O1
X
X
Port D5
LINUART
data transmit
—
Port D6
X
— O1
X
X
LINUART
data receive
—
X
X
X
— O1
X
X
Port D7
Top level
interrupt
—
73 57 41 25 PD0/TIM3_CH2 I/O
74 58 42 26
77 61 45 29
PD1/SWIM(3)
78 62 46 30
PD5/
LINUART_TX
I/O
79 63 47 31
PD6/
LINUART_RX
I/O
X
X
80 64 48 32
36/110
PD7/TLI(4)
I/O
X
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Pinouts and pin description
1. In Halt/Active-halt mode, this pin behaves as follows:
- The input/output path is disabled.
- If the HSE clock is used for wakeup, the internal weak pull-up is disabled.
- If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the
corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in
Halt/Active-halt mode.
2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up and protection diode to VDD are
not implemented)
3. The PD1 pin is in input pull-up during the reset phase and after reset release.
4. If this pin is configured as interrupt pin, it will trigger the TLI.
6.2
Alternate function remapping
As shown in the rightmost column of Table 13, some alternate functions can be remapped at
different I/O ports by programming one of eight AFR (alternate function remap) option bits.
Refer to Section 9: Option bytes on page 51. When the remapping option is active, the
default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the STM8S and STM8A microcontroller families reference manual,
RM0016).
Doc ID 14395 Rev 9
37/110
Memory and register map
STM8AF52/62xx, STM8AF51/61xx
7
Memory and register map
7.1
Memory map
Figure 7.
Register and memory map
00 0000
Up to 6 Kbytes RAM
Stack
RAM end address
Reserved
00 4000
Up to 2 Kbytes data EEPROM
00 4800
Option bytes
00 4900
00 5000
Reserved
HW registers
00 5800
Reserved
00 6000
2 Kbytes boot ROM
00 6800
00 7F00
CPU/SWIM/Debug/ITC registers
00 8000
IT vectors
00 8080
Up to 128 Kbytes
Flash program memory
Memory end address
Table 14.
Memory model 128K
Flash program
memory size
Flash program
memory end
address
128K
0x00 27FFF
96K
0x00 1FFFF
64K
0x00 17FFF
48K
0x00 13FFF
32K
0x00 0FFFF
RAM end
address
Stack roll-over
address
0x00 17FF
0x00 1400
0x00 17FF
0x00 1400
0x00 17FF
0x00 1400
3K
0x00 0BFF
n/a(1)
6K
0x00 17FF
0x00 1400
RAM size
6K
1. If the device contains the super set silicon (salestype contains SSS), the roll-over address is the same as
on the 128K device. For more information on stack handling refer to the “Memory and register map” section
in the reference manual RM0016. For more information on salestype composition, refer to section 13 in the
present document.
38/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
7.2
Memory and register map
Register map
In this section the memory and register map of the devices covered by this datasheet is
described. For a detailed description of the functionality of the registers, refer to the
reference manual RM0016.
Table 15.
I/O port hardware register map
Register label
Register name
Reset
status
0x00 5000
PA_ODR
Port A data output latch register
0x00
0x00 5001
PA_IDR
Port A input pin value register
0xXX(1)
PA_DDR
Port A data direction register
0x00
0x00 5003
PA_CR1
Port A control register 1
0x00
0x00 5004
PA_CR2
Port A control register 2
0x00
0x00 5005
PB_ODR
Port B data output latch register
0x00
0x00 5006
PB_IDR
Port B input pin value register
0xXX(1)
PB_DDR
Port B data direction register
0x00
0x00 5008
PB_CR1
Port B control register 1
0x00
0x00 5009
PB_CR2
Port B control register 2
0x00
0x00 500A
PC_ODR
Port C data output latch register
0x00
0x00 500B
PB_IDR
Port C input pin value register
0xXX(1)
PC_DDR
Port C data direction register
0x00
0x00 500D
PC_CR1
Port C control register 1
0x00
0x00 500E
PC_CR2
Port C control register 2
0x00
0x00 500F
PD_ODR
Port D data output latch register
0x00
0x00 5010
PD_IDR
Port D input pin value register
0xXX(1)
PD_DDR
Port D data direction register
0x00
0x00 5012
PD_CR1
Port D control register 1
0x02
0x00 5013
PD_CR2
Port D control register 2
0x00
0x00 5014
PE_ODR
Port E data output latch register
0x00
0x00 5015
PE_IDR
Port E input pin value register
0xXX(1)
PE_DDR
Port E data direction register
0x00
0x00 5017
PE_CR1
Port E control register 1
0x00
0x00 5018
PE_CR2
Port E control register 2
0x00
0x00 5019
PF_ODR
Port F data output latch register
0x00
0x00 501A
PF_IDR
Port F input pin value register
0xXX(1)
PF_DDR
Port F data direction register
0x00
0x00 501C
PF_CR1
Port F control register 1
0x00
0x00 501D
PF_CR2
Port F control register 2
0x00
Address
0x00 5002
0x00 5007
0x00 500C
0x00 5011
0x00 5016
0x00 501B
Block
Port A
Port B
Port C
Port D
Port E
Port F
Doc ID 14395 Rev 9
39/110
Memory and register map
Table 15.
STM8AF52/62xx, STM8AF51/61xx
I/O port hardware register map (continued)
Register label
Register name
Reset
status
0x00 501E
PG_ODR
Port G data output latch register
0x00
0x00 501F
PG_IDR
Port G input pin value register
0xXX(1)
PG_DDR
Port G data direction register
0x00
0x00 5021
PG_CR1
Port G control register 1
0x00
0x00 5022
PG_CR2
Port G control register 2
0x00
0x00 5023
PH_ODR
Port H data output latch register
0x00
0x00 5024
PH_IDR
Port H input pin value register
0xXX(1)
PH_DDR
Port H data direction register
0x00
0x00 5026
PH_CR1
Port H control register 1
0x00
0x00 5027
PH_CR2
Port H control register 2
0x00
0x00 5028
PI_ODR
Port I data output latch register
0x00
0x00 5029
PI_IDR
Port I input pin value register
0xXX(1)
PI_DDR
Port I data direction register
0x00
0x00 502B
PI_CR1
Port I control register 1
0x00
0x00 502C
PI_CR2
Port I control register 2
0x00
Register label
Register name
Reset
status
0x00 505A
FLASH_CR1
Flash control register 1
0x00
0x00 505B
FLASH_CR2
Flash control register 2
0x00
0x00 505C
FLASH_NCR2
Flash complementary control register 2
0xFF
FLASH_FPR
Flash protection register
0x00
0x00 505E
FLASH_NFPR
Flash complementary protection
register
0xFF
0x00 505F
FLASH_IAPSR
Address
0x00 5020
0x00 5025
0x00 502A
Block
Port G
Port H
Port I
1. Depends on the external circuitry.
Table 16.
Address
0x00 505D
General hardware register map
Block
Flash
0x00 5060 to
0x005061
0x00 5062
0x00 5065 to
0x00 509F
40/110
0x40
Reserved area (2 bytes)
Flash
FLASH_PUKR
0x00 5063
0x00 5064
Flash in-application programming
status register
Flash Program memory unprotection
register
0x00
Reserved area (1 byte)
Flash
FLASH_DUKR
Data EEPROM unprotection register
Reserved area (59 bytes)
Doc ID 14395 Rev 9
0x00
STM8AF52/62xx, STM8AF51/61xx
Table 16.
Address
Memory and register map
General hardware register map (continued)
Block
0x00 50A0
Register label
Register name
Reset
status
EXTI_CR1
External interrupt control register 1
0x00
EXTI_CR2
External interrupt control register 2
0x00
ITC
0x00 50A1
0x00 50A2 to
0x00 50B2
0x00 50B3
Reserved area (17 bytes)
RST
RST_SR
0x00 50B4 to
0x00 50BF
Reset status register
0xXX(1)
Reserved area (12 bytes)
0x00 50C0
CLK_ICKR
Internal clock control register
0x01
CLK_ECKR
External clock control register
0x00
CLK
0x00 50C1
0x00 50C2
Reserved area (1 byte)
0x00 50C3
CLK_CMSR
Clock master status register
0xE1
0x00 50C4
CLK_SWR
Clock master switch register
0xE1
0x00 50C5
CLK_SWCR
Clock switch control register
0xXX
0x00 50C6
CLK_CKDIVR
Clock divider register
0x18
0x00 50C7
CLK_PCKENR1
Peripheral clock gating register 1
0xFF
CLK_CSSR
Clock security system register
0x00
0x00 50C9
CLK_CCOR
Configurable clock control register
0x00
0x00 50CA
CLK_PCKENR2
Peripheral clock gating register 2
0xFF
0x00 50C8
CLK
0x00 50CB
Reserved area (1 byte)
0x00 50CC
CLK_HSITRIMR
HSI clock calibration trimming register
0x00
0x00 50CD
CLK_SWIMCCR
SWIM clock control register
0bXXXX
XXX0
0x00 50CE
to 0x00 50D0
Reserved area (3 bytes)
0x00 50D1
WWDG_CR
WWDG control register
0x7F
WWDG_WR
WWDR window register
0x7F
WWDG
0x00 50D2
0x00 50D3 to
0x00 50DF
Reserved area (13 bytes)
0x00 50E0
0x00 50E1
IWDG
0x00 50E2
IWDG_KR
IWDG key register
0xXX(2)
IWDG_PR
IWDG prescaler register
0x00
IWDG_RLR
IWDG reload register
0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
0x00 50F1
0x00 50F2
AWU
AWU_CSR1
AWU control/status register 1
0x00
AWU_APR
AWU asynchronous prescaler buffer
register
0x3F
AWU_TBR
AWU timebase selection register
0x00
Doc ID 14395 Rev 9
41/110
Memory and register map
Table 16.
STM8AF52/62xx, STM8AF51/61xx
General hardware register map (continued)
Address
Block
Register label
Register name
Reset
status
0x00 50F3
BEEP
BEEP_CSR
BEEP control/status register
0x1F
Reserved area (12 bytes)
0x00 50F4 to
0x00 50FF
0x00 5200
SPI_CR1
SPI control register 1
0x00
0x00 5201
SPI_CR2
SPI control register 2
0x00
0x00 5202
SPI_ICR
SPI interrupt control register
0x00
SPI_SR
SPI status register
0x02
0x00 5204
SPI_DR
SPI data register
0x00
0x00 5205
SPI_CRCPR
SPI CRC polynomial register
0x07
0x00 5206
SPI_RXCRCR
SPI Rx CRC register
0xFF
0x00 5207
SPI_TXCRCR
SPI Tx CRC register
0xFF
0x00 5203
SPI
Reserved area (8 bytes)
0x00 5208 to
0x00 520F
0x00 5210
I2C_CR1
I2C control register 1
0x00
0x00 5211
I2C_CR2
I2C control register 2
0x00
0x00 5212
I2C_FREQR
I2C frequency register
0x00
0x00 5213
I2C_OARL
I2C own address register low
0x00
0x00 5214
I2C_OARH
I2C own address register high
0x00
I2C_DR
I2C data register
0x00
0x00 5217
I2C_SR1
I2C status register 1
0x00
0x00 5218
I2C_SR2
I2C status register 2
0x00
0x00 5219
I2C_SR3
I2C status register 3
0x00
0x00 521A
I2C_ITR
I2C interrupt control register
0x00
0x00 521B
I2C_CCRL
I2C clock control register low
0x00
0x00 521C
I2C_CCRH
I2C clock control register high
0x00
0x00 521D
I2C_TRISER
I2C TRISE register
0x02
0x00 5215
0x00 5216
I2C
0x00 521E to
0x00 522F
42/110
Reserved area (18 bytes)
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 16.
Memory and register map
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5230
UART1_SR
USART status register
0xC0
0x00 5231
UART1_DR
USART data register
0xXX
0x00 5232
UART1_BRR1
USART baud rate register 1
0x00
0x00 5233
UART1_BRR2
USART baud rate register 2
0x00
0x00 5234
UART1_CR1
USART control register 1
0x00
UART1_CR2
USART control register 2
0x00
0x00 5236
UART1_CR3
USART control register 3
0x00
0x00 5237
UART1_CR4
USART control register 4
0x00
0x00 5238
UART1_CR5
USART control register 5
0x00
0x00 5239
UART1_GTR
USART guard time register
0x00
0x00 523A
UART1_PSCR
USART prescaler register
0x00
Address
0x00 5235
Block
USART
0x00 523B to
0x00 523F
Reserved area (5 bytes)
0x00 5240
UART3_SR
LINUART status register
0xC0
0x00 5241
UART3_DR
LINUART data register
0xXX
0x00 5242
UART3_BRR1
LINUART baud rate register 1
0x00
0x00 5243
UART3_BRR2
LINUART baud rate register 2
0x00
UART3_CR1
LINUART control register 1
0x00
0x00 5245
UART3_CR2
LINUART control register 2
0x00
0x00 5246
UART3_CR3
LINUART control register 3
0x00
0x00 5247
UART3_CR4
LINUART control register 4
0x00
0x00 5244
LINUART
0x00 5248
0x00 5249
0x00 524A to
0x00 524F
Reserved
UART3_CR6
LINUART control register 6
0x00
Reserved area (6 bytes)
Doc ID 14395 Rev 9
43/110
Memory and register map
Table 16.
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5250
TIM1_CR1
TIM1 control register 1
0x00
0x00 5251
TIM1_CR2
TIM1 control register 2
0x00
0x00 5252
TIM1_SMCR
TIM1 slave mode control register
0x00
0x00 5253
TIM1_ETR
TIM1 external trigger register
0x00
0x00 5254
TIM1_IER
TIM1 Interrupt enable register
0x00
0x00 5255
TIM1_SR1
TIM1 status register 1
0x00
0x00 5256
TIM1_SR2
TIM1 status register 2
0x00
0x00 5257
TIM1_EGR
TIM1 event generation register
0x00
0x00 5258
TIM1_CCMR1
TIM1 capture/compare mode register 1
0x00
0x00 5259
TIM1_CCMR2
TIM1 capture/compare mode register 2
0x00
0x00 525A
TIM1_CCMR3
TIM1 capture/compare mode register 3
0x00
0x00 525B
TIM1_CCMR4
TIM1 capture/compare mode register 4
0x00
0x00 525C
TIM1_CCER1
TIM1 capture/compare enable register
1
0x00
0x00 525D
TIM1_CCER2
TIM1 capture/compare enable register
2
0x00
0x00 525E
TIM1_CNTRH
TIM1 counter high
0x00
TIM1_CNTRL
TIM1 counter low
0x00
0x00 5260
TIM1_PSCRH
TIM1 prescaler register high
0x00
0x00 5261
TIM1_PSCRL
TIM1 prescaler register low
0x00
0x00 5262
TIM1_ARRH
TIM1 auto-reload register high
0xFF
0x00 5263
TIM1_ARRL
TIM1 auto-reload register low
0xFF
0x00 5264
TIM1_RCR
TIM1 repetition counter register
0x00
0x00 5265
TIM1_CCR1H
TIM1 capture/compare register 1 high
0x00
0x00 5266
TIM1_CCR1L
TIM1 capture/compare register 1 low
0x00
0x00 5267
TIM1_CCR2H
TIM1 capture/compare register 2 high
0x00
0x00 5268
TIM1_CCR2L
TIM1 capture/compare register 2 low
0x00
0x00 5269
TIM1_CCR3H
TIM1 capture/compare register 3 high
0x00
0x00 526A
TIM1_CCR3L
TIM1 capture/compare register 3 low
0x00
0x00 526B
TIM1_CCR4H
TIM1 capture/compare register 4 high
0x00
0x00 526C
TIM1_CCR4L
TIM1 capture/compare register 4 low
0x00
0x00 526D
TIM1_BKR
TIM1 break register
0x00
0x00 526E
TIM1_DTR
TIM1 dead-time register
0x00
0x00 526F
TIM1_OISR
TIM1 output idle state register
0x00
Address
0x00 525F
44/110
STM8AF52/62xx, STM8AF51/61xx
Block
TIM1
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 16.
Address
Memory and register map
General hardware register map (continued)
Block
Register label
0x00 5270 to
0x00 52FF
Register name
Reset
status
Reserved area (147 bytes)
0x00 5300
TIM2_CR1
TIM2 control register 1
0x00
0x00 5301
TIM2_IER
TIM2 interrupt enable register
0x00
0x00 5302
TIM2_SR1
TIM2 status register 1
0x00
0x00 5303
TIM2_SR2
TIM2 status register 2
0x00
0x00 5304
TIM2_EGR
TIM2 event generation register
0x00
0x00 5305
TIM2_CCMR1
TIM2 capture/compare mode register 1
0x00
0x00 5306
TIM2_CCMR2
TIM2 capture/compare mode register 2
0x00
0x00 5307
TIM2_CCMR3
TIM2 capture/compare mode register 3
0x00
0x00 5308
TIM2_CCER1
TIM2 capture/compare enable register
1
0x00
0x00 5309
TIM2_CCER2
TIM2 capture/compare enable register
2
0x00
0x00 530A
TIM2_CNTRH
TIM2 counter high
0x00
0x00 530B
TIM2_CNTRL
TIM2 counter low
0x00
00 530C0x
TIM2_PSCR
TIM2 prescaler register
0x00
0x00 530D
TIM2_ARRH
TIM2 auto-reload register high
0xFF
0x00 530E
TIM2_ARRL
TIM2 auto-reload register low
0xFF
0x00 530F
TIM2_CCR1H
TIM2 capture/compare register 1 high
0x00
0x00 5310
TIM2_CCR1L
TIM2 capture/compare register 1 low
0x00
0x00 5311
TIM2_CCR2H
TIM2 capture/compare reg. 2 high
0x00
0x00 5312
TIM2_CCR2L
TIM2 capture/compare register 2 low
0x00
0x00 5313
TIM2_CCR3H
TIM2 capture/compare register 3 high
0x00
0x00 5314
TIM2_CCR3L
TIM2 capture/compare register 3 low
0x00
TIM2
0x00 5315 to
0x00 531F
Reserved area (11 bytes)
Doc ID 14395 Rev 9
45/110
Memory and register map
Table 16.
STM8AF52/62xx, STM8AF51/61xx
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5320
TIM3_CR1
TIM3 control register 1
0x00
0x00 5321
TIM3_IER
TIM3 interrupt enable register
0x00
0x00 5322
TIM3_SR1
TIM3 status register 1
0x00
0x00 5323
TIM3_SR2
TIM3 status register 2
0x00
0x00 5324
TIM3_EGR
TIM3 event generation register
0x00
0x00 5325
TIM3_CCMR1
TIM3 capture/compare mode register 1
0x00
0x00 5326
TIM3_CCMR2
TIM3 capture/compare mode register 2
0x00
0x00 5327
TIM3_CCER1
TIM3 capture/compare enable register
1
0x00
TIM3_CNTRH
TIM3 counter high
0x00
0x00 5329
TIM3_CNTRL
TIM3 counter low
0x00
0x00 532A
TIM3_PSCR
TIM3 prescaler register
0x00
0x00 532B
TIM3_ARRH
TIM3 auto-reload register high
0xFF
0x00 532C
TIM3_ARRL
TIM3 auto-reload register low
0xFF
0x00 532D
TIM3_CCR1H
TIM3 capture/compare register 1 high
0x00
0x00 532E
TIM3_CCR1L
TIM3 capture/compare register 1 low
0x00
0x00 532F
TIM3_CCR2H
TIM3 capture/compare register 2 high
0x00
0x00 5330
TIM3_CCR2L
TIM3 capture/compare register 2 low
0x00
Address
0x00 5328
Block
TIM3
Reserved area (15 bytes)
0x00 5331 to
0x00 533F
0x00 5340
TIM4_CR1
TIM4 control register 1
0x00
0x00 5341
TIM4_IER
TIM4 interrupt enable register
0x00
0x00 5342
TIM4_SR
TIM4 status register
0x00
TIM4_EGR
TIM4 event generation register
0x00
0x00 5344
TIM4_CNTR
TIM4 counter
0x00
0x00 5345
TIM4_PSCR
TIM4 prescaler register
0x00
0x00 5346
TIM4_ARR
TIM4 auto-reload register
0xFF
0x00 5343
0x00 5347 to
0x00 53FF
46/110
TIM4
Reserved area (185 bytes)
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 16.
Memory and register map
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5400
ADC _CSR
ADC control/status register
0x00
0x00 5401
ADC_CR1
ADC configuration register 1
0x00
0x00 5402
ADC_CR2
ADC configuration register 2
0x00
0x00 5403
ADC_CR3
ADC configuration register 3
0x00
ADC_DRH
ADC data register high
0xXX
0x00 5405
ADC_DRL
ADC data register low
0xXX
0x00 5406
ADC_TDRH
ADC Schmitt trigger disable register
high
0x00
0x00 5407
ADC_TDRL
ADC Schmitt trigger disable register
low
0x00
Address
0x00 5404
Block
ADC
0x00 5408 to
0x00 541F
Reserved area (24 bytes)
0x00 5420
CAN_MCR
CAN master control register
0x02
0x00 5421
CAN_MSR
CAN master status register
0x02
0x00 5422
CAN_TSR
CAN transmit status register
0x00
0x00 5423
CAN_TPR
CAN transmit priority register
0x0C
0x00 5424
CAN_RFR
CAN receive FIFO register
0x00
0x00 5425
CAN_IER
CAN interrupt enable register
0x00
0x00 5426
CAN_DGR
CAN diagnosis register
0x0C
0x00 5427
CAN_FPSR
CAN page selection register
0x00
0x00 5428
CAN_P0
CAN paged register 0
0xXX(3)
0x00 5429
CAN_P1
CAN paged register 1
0xXX(3)
0x00 542A
CAN_P2
CAN paged register 2
0xXX(3)
CAN_P3
CAN paged register 3
0xXX(3)
0x00 542C
CAN_P4
CAN paged register 4
0xXX(3)
0x00 542D
CAN_P5
CAN paged register 5
0xXX(3)
0x00 542E
CAN_P6
CAN paged register 6
0xXX(3)
0x00 542F
CAN_P7
CAN paged register 7
0xXX(3)
0x00 5430
CAN_P8
CAN paged register 8
0xXX(3)
0x00 5431
CAN_P9
CAN paged register 9
0xXX(3)
0x00 5432
CAN_PA
CAN paged register A
0xXX(3)
0x00 5433
CAN_PB
CAN paged register B
0xXX(3)
0x00 5434
CAN_PC
CAN paged register C
0xXX(3)
0x00 5435
CAN_PD
CAN paged register D
0xXX(3)
0x00 5436
CAN_PE
CAN paged register E
0xXX(3)
0x00 542B
beCAN
Doc ID 14395 Rev 9
47/110
Memory and register map
Table 16.
STM8AF52/62xx, STM8AF51/61xx
General hardware register map (continued)
Address
Block
Register label
Register name
Reset
status
0x00 5437
beCAN
CAN_PF
CAN paged register F
0xXX(3)
0x00 5438 to
0x00 57FF
Reserved area (968 bytes)
1. Depends on the previous reset source.
2. Write only register.
3. If the bootloader is enabled, it is initialized to 0x00.
Table 17.
CPU/SWIM/debug module/interrupt controller registers
Register label
Register name
Reset
status
0x00 7F00
A
Accumulator
0x00
0x00 7F01
PCE
Program counter extended
0x00
0x00 7F02
PCH
Program counter high
0x80
0x00 7F03
PCL
Program counter low
0x00
XH
X index register high
0x00
XL
X index register low
0x00
0x00 7F06
YH
Y index register high
0x00
0x00 7F07
YL
Y index register low
0x00
0x00 7F08
SPH
Stack pointer high
0x17(2)
0x00 7F09
SPL
Stack pointer low
0xFF
0x00 7F0A
CC
Condition code register
0x28
Address
Block
0x00 7F04
0x00 7F05
CPU(1)
0x00 7F0B
to 0x00
7F5F
0x00 7F60
Reserved area (85 bytes)
CPU
CFG_GCR
Global configuration register
0x00
0x00 7F70
ITC_SPR1
Interrupt software priority register 1
0xFF
0x00 7F71
ITC_SPR2
Interrupt software priority register 2
0xFF
0x00 7F72
ITC_SPR3
Interrupt software priority register 3
0xFF
ITC_SPR4
Interrupt software priority register 4
0xFF
0x00 7F74
ITC_SPR5
Interrupt software priority register 5
0xFF
0x00 7F75
ITC_SPR6
Interrupt software priority register 6
0xFF
0x00 7F76
ITC_SPR7
Interrupt software priority register 7
0xFF
0x00 7F77
ITC_SPR8
Interrupt software priority register 8
0xFF
0x00 7F73
ITC
0x00 7F78
to
0x00 7F79
0x00 7F80
48/110
Reserved area (2 bytes)
SWIM
SWIM_CSR
SWIM control status register
Doc ID 14395 Rev 9
0x00
STM8AF52/62xx, STM8AF51/61xx
Table 17.
Address
Memory and register map
CPU/SWIM/debug module/interrupt controller registers (continued)
Block
Register label
0x00 7F81
to
0x00 7F8F
Register name
Reset
status
Reserved area (15 bytes)
0x00 7F90
DM_BK1RE
DM breakpoint 1 register extended byte
0xFF
0x00 7F91
DM_BK1RH
DM breakpoint 1 register high byte
0xFF
0x00 7F92
DM_BK1RL
DM breakpoint 1 register low byte
0xFF
0x00 7F93
DM_BK2RE
DM breakpoint 2 register extended byte
0xFF
0x00 7F94
DM_BK2RH
DM breakpoint 2 register high byte
0xFF
DM_BK2RL
DM breakpoint 2 register low byte
0xFF
0x00 7F96
DM_CR1
DM debug module control register 1
0x00
0x00 7F97
DM_CR2
DM debug module control register 2
0x00
0x00 7F98
DM_CSR1
DM debug module control/status register 1
0x10
0x00 7F99
DM_CSR2
DM debug module control/status register 2
0x00
0x00 7F9A
DM_ENFCTR
DM enable function register
0xFF
0x00 7F95
DM
0x00 7F9B
to 0x00
7F9F
Reserved area (5 bytes)
1. Accessible by debug module only
2. Product dependent value, see Figure 7: Register and memory map.
Table 18.
Temporary memory unprotection registers
Register label
Register name
Reset
status
0x00 5800
TMU_K1
Temporary memory unprotection key register 1
0x00
0x00 5801
TMU_K2
Temporary memory unprotection key register 2
0x00
0x00 5802
TMU_K3
Temporary memory unprotection key register 3
0x00
0x00 5803
TMU_K4
Temporary memory unprotection key register 4
0x00
TMU_K5
Temporary memory unprotection key register 5
0x00
0x00 5805
TMU_K6
Temporary memory unprotection key register 6
0x00
0x00 5806
TMU_K7
Temporary memory unprotection key register 7
0x00
0x00 5807
TMU_K8
Temporary memory unprotection key register 8
0x00
0x00 5808
TMU_CSR
Temporary memory unprotection control and status
register
0x00
Address
0x00 5804
Block
TMU
Doc ID 14395 Rev 9
49/110
Interrupt table
STM8AF52/62xx, STM8AF51/61xx
8
Interrupt table
Table 19.
STM8A interrupt table(1)
Priority Source block
Description
Interrupt vector
address
Wakeup
from Halt
Comments
—
Reset
Reset
0x00 6000
Yes
Reset vector in ROM
—
TRAP
SW interrupt
0x00 8004
—
—
0
TLI
External top level interrupt
0x00 8008
—
—
1
AWU
Auto-wakeup from Halt
0x00 800C
Yes
—
2
Clock
controller
Main clock controller
0x00 8010
—
—
3
MISC
External interrupt E0
0x00 8014
Yes
Port A interrupts
4
MISC
External interrupt E1
0x00 8018
Yes
Port B interrupts
5
MISC
External interrupt E2
0x00 801C
Yes
Port C interrupts
6
MISC
External interrupt E3
0x00 8020
Yes
Port D interrupts
7
MISC
External interrupt E4
0x00 8024
Yes
Port E interrupts
8
CAN
CAN interrupt Rx
0x00 8028
Yes
—
9
CAN
CAN interrupt TX/ER/SC
0x00 802C
—
—
10
SPI
End of transfer
0x00 8030
Yes
—
11
Timer 1
Update/overflow/
trigger/break
0x00 8034
—
—
12
Timer 1
Capture/compare
0x00 8038
—
—
13
Timer 2
Update/overflow
0x00 803C
—
—
14
Timer 2
Capture/compare
0x00 8040
—
—
15
Timer 3
Update/overflow
0x00 8044
—
—
16
Timer 3
Capture/compare
0x00 8048
—
—
17
USART
Tx complete
0x00 804C
—
—
18
USART
Receive data full reg.
0x00 8050
—
—
I C interrupts
0x00 8054
Yes
—
2
2
19
I C
20
LINUART
Tx complete/error
0x00 8058
—
—
21
LINUART
Receive data full reg.
0x00 805C
—
—
22
ADC
End of conversion
0x00 8060
—
—
23
Timer 4
Update/overflow
0x00 8064
—
—
24
EEPROM
End of programming/
write in not allowed area
0x00 8068
—
—
1. All unused interrupts must be initialized with ‘IRET’ for robust programming.
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9
Option bytes
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Each option
byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented
one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 20: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be changed in ICP mode (via SWIM).
Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 20.
Addr.
0x00
4800
0x00
4801
0x00
4802
0x00
4803
0x00
4804
0x00
4805
0x00
4806
0x00
4807
0x00
4808
0x00
4809
0x00
480A
Option bytes
Option
name
Option
byte
no.
Read-out
protection
(ROP)
OPT0
ROP[7:0]
0x00
OPT1
UBC[7:0]
0x00
NOPT1
NUBC[7:0]
0xFF
User boot
code
(UBC)
Option bits
7
6
5
4
3
2
Alternate
OPT2
AFR7 AFR6 AFR5 AFR4 AFR3
AFR2
function
remapping
NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2
(AFR)
1
0
Factory
default
setting
AFR1
AFR0
0x00
NAFR1
NAFR0
0xFF
OPT3
Reserved
LSI_
EN
IWDG
_HW
WWD
G _HW
WWDG
_HALT
0x00
NOPT3
Reserved
NLSI_
EN
NIWD
G_HW
NWWD
G_HW
NWWG
_HALT
0xFF
OPT4
Reserved
EXT
CLK
CKAW
USEL
PRSC1
PRSC0
0x00
NOPT4
Reserved
NEXT
CLK
NCKAW
NPRSC
NPRSC1
USEL
0
0xFF
Watchdog
option
Clock
option
OPT5
HSECNT[7:0]
0x00
NOPT5
NHSECNT[7:0]
0xFF
HSE clock
startup
Doc ID 14395 Rev 9
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Option bytes
Table 20.
Addr.
STM8AF52/62xx, STM8AF51/61xx
Option bytes (continued)
Option
name
0x00
480B
Option
byte
no.
Option bits
7
6
5
4
3
2
1
0
Factory
default
setting
OPT6
TMU[3:0]
0x00
NOPT6
NTMU[3:0]
0xFF
TMU
0x00
480C
0x00
480D
0x00
480E
OPT7
Reserved
WAIT
STATE
0x00
NOPT7
Reserved
NWAIT
STATE
0xFF
Flash wait
states
0x00
480F
Reserved
0x00
4810
OPT8
TMU_KEY 1 [7:0]
0x00
0x00
4811
OPT9
TMU_KEY 2 [7:0]
0x00
0x00
4812
OPT10
TMU_KEY 3 [7:0]
0x00
0x00
4813
OPT11
TMU_KEY 4 [7:0]
0x00
OPT12
TMU_KEY 5 [7:0]
0x00
0x00
4815
OPT13
TMU_KEY 6 [7:0]
0x00
0x00
4816
OPT14
TMU_KEY 7 [7:0]
0x00
0x00
4817
OPT15
TMU_KEY 8 [7:0]
0x00
0x00
4818
OPT16
TMU_MAXATT [7:0]
0xC7
0x00
4814
TMU
0x00
4819
to
487D
0x00
487E
0x00
487F
Reserved
Bootloader(1)
OPT17
BL [7:0]
0x00
NOPT
17
NBL [7:0]
0xFF
1. This option consists of two bytes that must have a complementary value in order to be valid. If the option is invalid, it has no
effect on EMC reset.
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Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 21.
Option bytes
Option byte description
Option byte no.
Description
OPT0
ROP[7:0]: Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the STM8A microcontroller family reference manual
(RM0016) section on Flash/EEPROM memory readout protection for
details.
OPT1
UBC[7:0]: User boot code area
0x00: No UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03 to 0xFF: Pages 4 to 255 defined as UBC, memory write-protected
Note: Refer to the STM8A microcontroller family reference manual
(RM0016) section on Flash/EEPROM write protection for more details.
OPT2
AFR7: Alternate function remapping option 7
0: Port D4 alternate function = TIM2_CH1
1: Port D4 alternate function = BEEP
AFR6: Alternate function remapping option 6
0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4
1: Port B5 alternate function = I2C_SDA, port B4 alternate function =
I2C_SCL.
AFR5: Alternate function remapping option 5
0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,
port B1 alternate function = AIN1, port B0 alternate function = AIN0.
1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =
TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate
function = TIM1_CH1N.
AFR4: Alternate function remapping option 4
0: Port D7 alternate function = TLI
1: Reserved
AFR3: Alternate function remapping option 3
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = TIM1_BKIN
AFR2: Alternate function remapping option 2
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = CLK_CCO
Note: AFR2 option has priority over AFR3 if both are activated
AFR1: Alternate function remapping option 1
0: Port A3 alternate function = TIM2_CH3, port D2 alternate function
TIM3_CH1.
1: Port A3 alternate function = TIM3_CH1, port D2 alternate function
TIM2_CH3.
AFR0: Alternate function remapping option 0
0: Port D3 alternate function = TIM2_CH2
1: Port D3 alternate function = ADC_ETR
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Option bytes
STM8AF52/62xx, STM8AF51/61xx
Table 21.
Option byte description (continued)
Option byte no.
Description
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
OPT3
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on Halt
0: No reset generated on Halt if WWDG active
1: Reset generated on Halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
OPT4
CKAWUSEL: Auto-wakeup unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for AWU
PRSC[1:0]: AWU clock prescaler
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
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OPT5
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilization time to 0.5, 8, 128, and 2048 HSE
cycles with corresponding option byte values of 0xE1, 0xD2, 0xB4, and
0x00.
OPT6
TMU[3:0]: Enable temporary memory unprotection
0101: TMU disabled (permanent ROP).
Any other value: TMU enabled.
OPT7
WAIT STATE: Wait state configuration
This option configures the number of wait states inserted when reading
from the Flash/data EEPROM memory.
0: No wait state
1: One wait state
OPT8
TMU_KEY 1 [7:0]: Temporary unprotection key 0
Temporary unprotection key: Must be different from 0x00 or 0xFF
OPT9
TMU_KEY 2 [7:0]: Temporary unprotection key 1
Temporary unprotection key: Must be different from 0x00 or 0xFF
OPT10
TMU_KEY 3 [7:0]: Temporary unprotection key 2
Temporary unprotection key: Must be different from 0x00 or 0xFF
OPT11
TMU_KEY 4 [7:0]: Temporary unprotection key 3
Temporary unprotection key: Must be different from 0x00 or 0xFF
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 21.
Option bytes
Option byte description (continued)
Option byte no.
Description
OPT12
TMU_KEY 5 [7:0]: Temporary unprotection key 4
Temporary unprotection key: Must be different from 0x00 or 0xFF
OPT13
TMU_KEY 6 [7:0]: Temporary unprotection key 5
Temporary unprotection key: Must be different from 0x00 or 0xFF
OPT14
TMU_KEY 7 [7:0]: Temporary unprotection key 6
Temporary unprotection key: Must be different from 0x00 or 0xFF
OPT15
TMU_KEY 8 [7:0]: Temporary unprotection key 7
Temporary unprotection key: Must be different from 0x00 or 0xFF
OPT16
TMU_MAXATT [7:0]: TMU access failure counter
TMU_MAXATT can be initialized with the desired value only if TMU is
disabled (TMU[3:0]=0101 in OPT6 option byte).
When TMU is enabled, any attempt to temporary remove the readout
protection by using wrong key values increments the counter.
When the option byte value reaches 0x08, the Flash memory and data
EEPROM are erased.
OPT17
BL[7:0]: Bootloader enable
If this option byte is set to 0x55 (complementary value 0xAA) the
bootloader program is activated also in case of a programmed code
memory (for more details, see the bootloader user manual, UM0560).
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
10
Electrical characteristics
10.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
10.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = -40 °C, TA = 25 °C, and
TA = TAmax (given by the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production.
10.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5.0 V. They are
given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range.
10.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
10.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
Figure 8.
Pin loading conditions
STM8A pin
50 pF
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10.1.5
Electrical characteristics
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 9.
Pin input voltage
STM8A pin
VIN
10.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 22.
Symbol
Voltage characteristics
Min
Max
Unit
-0.3
6.5
V
VSS - 0.3
6.5
VSS - 0.3
VDD + 0.3
|VDDx - VDD| Variations between different power pins
—
50
|VSSx - VSS| Variations between all the different ground pins
—
50
VDDx - VSS
Ratings
Supply voltage (including VDDA and VDDIO)(1)
Input voltage on true open drain pins (PE1,
VIN
VESD
Input voltage on any other pin
PE2)(2)
(2)
Electrostatic discharge voltage
V
mV
see Absolute maximum ratings
(electrical sensitivity) on
page 85
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
Doc ID 14395 Rev 9
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Electrical characteristics
Table 23.
STM8AF52/62xx, STM8AF51/61xx
Current characteristics
Symbol
Ratings
Max.
IVDDIO
Total current into VDDIO power lines (source)(1)(2)(3)
100
IVSSIO
(1)(2)(3)
100
Total current out of VSS IO ground lines (sink)
IIO
Output current sunk by any I/O and control pin
20
Output current source by any I/Os and control pin
-20
Injected current on any pin
±10
Sum of injected currents
50
Unit
mA
IINJ(PIN)(4)
IINJ(TOT)
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external supply.
2. The total limit applies to the sum of operation and injected currents.
3. VDDIO includes the sum of the positive injection currents. VSSIO includes the sum of the negative injection
currents.
4. This condition is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the
injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN >
VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive
injection current allowed and the corresponding VIN maximum must always be respected.
Table 24.
Thermal characteristics
Symbol
Storage temperature range
TSTG
Ratings
Conforming to AEC-Q100 rev G
1. For detailed mission profile analysis, please contact your local ST Sales Office.
58/110
Unit
-65 to 150
160
Operating lifetime(1)
Symbol
OLF
Value
°C
Maximum junction temperature
TJ
Table 25.
Ratings
Doc ID 14395 Rev 9
Value
Unit
−40 to 125 °C
Grade 1
−40 to 150 °C
Grade 0
STM8AF52/62xx, STM8AF51/61xx
10.3
Electrical characteristics
Operating conditions
Table 26.
General operating conditions
Symbol
Parameter
fCPU
Internal CPU clock frequency
VDD/VDDIO
Conditions
Min
Max
1 wait state
TA = -40 °C to 150 °C
16
24
0 wait state
TA = -40 °C to 150 °C
0
16
-
3.0
5.5
V
470
3300
nF
-
0.3
Ω
-
15
nH
Standard operating voltage
MHz
CEXT: capacitance of external
capacitor
VCAP(1)
ESR of external capacitor
at 1 MHz(2)
ESL of external capacitor
TA
Suffix A
85
Suffix B
105
Suffix C
125
Ambient temperature
Suffix D
150
- 40
TJ
Unit
°C
Suffix A
90
Suffix B
110
Suffix C
130
Suffix D
155
Junction temperature range
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.
2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.
Figure 10. fCPUmax versus VDD
fCPU [MHz]
24
Functionality
not guaranteed
in this area
16
Functionality guaranteed
@ TA -40 to 150 °C at 1 waitstate
12
Functionality guaranteed
@ TA -40 to 150 °C at 0 waitstate
8
4
0
3.0
4.0
5.0
5.5
Supply voltage [V]
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Electrical characteristics
Table 27.
tTEMP
Parameter
Conditions
Min
Typ
Max
—
2(1)
—
—
(1)
2
—
8
tVDD
Operating conditions at power-up/power-down
8
Symbol
STM8AF52/62xx, STM8AF51/61xx
VDD rise time rate
VDD fall time rate
Unit
µs/V
Reset release delay
VDD rising
—
3
—
ms
Reset generation delay
VDD falling
—
3
—
µs
VIT+
Power-on reset
threshold(2)
—
2.65
2.8
2.95
VIT-
Brown-out reset
threshold
—
2.58
2.73
2.88
VHYS(BOR)
Brown-out reset
hysteresis
—
—
70(1)
V
mV
1. Guaranteed by design, not tested in production.
2. If VDD is below 3 V, the code execution is guaranteed above the VIT- and VIT+ thresholds. RAM content is
kept. The EEPROM programming sequence must not be initiated.
10.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in Table 26. Care should be taken to limit the series inductance
to less than 15 nH.
Figure 11. External capacitor CEXT
ESR
C
ESL
Rleak
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.
10.3.2
Supply current characteristics
The current consumption is measured as described in Figure 8 on page 56 and Figure 9 on
page 57.
If not explicitly stated, general conditions of temperature and voltage apply.
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Table 28.
Total current consumption in Run, Wait and Slow mode. General conditions
for VDD apply, TA = −40 °C to 150 °C
Symbol
IDD(RUN)(1)
IDD(RUN)(1)
IDD(WFI)
Electrical characteristics
(1)
IDD(SLOW)
(1)
Parameter
Supply current in
Run mode
Supply current in
Run mode
Supply current in
Wait mode
Supply current in
Slow mode
Conditions
All peripherals
clocked, code
executed from Flash
program memory,
HSE external clock
(without resonator)
All peripherals
clocked, code
executed from RAM,
HSE external clock
(without resonator)
CPU stopped, all
peripherals off, HSE
external clock
fCPU scaled down,
all peripherals off,
code executed from
RAM
Typ
Max
Unit
(2)
fCPU = 24 MHz 1 ws
8.7
16.8
fCPU = 16 MHz
7.4
14
fCPU = 8 MHz
4.0
7.4(2)
fCPU = 4 MHz
2.4
4.1(2)
fCPU = 2 MHz
1.5
2.5
fCPU = 24 MHz
4.4
6.0(2)
fCPU = 16 MHz
3.7
5.0
fCPU = 8 MHz
2.2
3.0(2)
fCPU = 4 MHz
1.4
2.0(2)
fCPU = 2 MHz
1.0
1.5
fCPU = 24 MHz
2.4
3.1(2)
fCPU = 16 MHz
1.65
2.5
fCPU = 8 MHz
1.15
1.9(2)
fCPU = 4 MHz
0.90
1.6(2)
fCPU = 2 MHz
0.80
1.5
External clock 16 MHz
fCPU = 125 kHz
1.50
1.95
LSI internal RC
fCPU = 128 kHz
1.50
1.80(2)
mA
1. The current due to I/O utilization is not taken into account in these values.
2. Values not tested in production. Design guidelines only.
Doc ID 14395 Rev 9
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Electrical characteristics
Table 29.
STM8AF52/62xx, STM8AF51/61xx
Total current consumption in Halt and Active-halt modes. General conditions for VDD
applied. TA = −40 °C to 55 °C unless otherwise stated
Conditions
Main
voltage
regulator
(MVR)(1)
Flash
mode(2)
Supply current in
Halt mode
Off
Powerdown
Supply current in
Active-halt mode
with regulator on
On
Symbol
IDD(H)
Parameter
Powerdown
Typ
Max
Clocks stopped
5
35(3)
Clocks stopped,
TA = 25 °C
5
25
External clock 16 MHz
fMASTER = 125 kHz
770
900(3)
LSI clock 128 kHz
150
230(3)
LSI clock 128 kHz
25
42(3)
LSI clock 128 kHz,
TA = 25 °C
25
30
10
30(3)
Clock source and
temperature condition
IDD(AH)
tWU(AH)
Supply current in
Active-halt mode
with regulator off
Off
Wakeup time from
Active-halt mode
with regulator on
On
Wakeup time from
Active-halt mode
with regulator off
Powerdown
Operating
mode
Unit
µA
TA =−40 to 150 °C
µs
Off
50
80(3)
1. Configured by the REGAH bit in the CLK_ICKR register.
2. Configured by the AHALT bit in the FLASH_CR1 register.
3. Data based on characterization results. Not tested in production.
Current consumption for on-chip peripherals
Table 30.
Oscillator current consumption
Symbol
IDD(OSC)
IDD(OSC)
Parameter
HSE oscillator current
consumption(2)
HSE oscillator current
consumption(2)
Typ
Max(1)
fOSC = 24 MHz
1
2.0(3)
fOSC = 16 MHz
0.6
—
fOSC = 8 MHz
0.57
—
fOSC = 24 MHz
0.5
1.0(3)
fOSC = 16 MHz
0.25
—
fOSC = 8 MHz
0.18
—
Conditions
Quartz or
ceramic
resonator,
CL = 33 pF
VDD = 5 V
Quartz or
ceramic
resonator,
CL = 33 pF
VDD = 3.3 V
Unit
mA
1. During startup, the oscillator current consumption may reach 6 mA.
2. The supply current of the oscillator can be further optimized by selecting a high quality resonator with small Rm value. Refer
to crystal manufacturer for more details
3. Informative data.
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Table 31.
Symbol
IDD(PROG)
Table 32.
Symbol
IDD(TIM1)
Electrical characteristics
Programming current consumption
Parameter
Programming current
Conditions
Typ
Max
Unit
VDD = 5 V, -40 °C to 150 °C, erasing
and programming data or Flash
program memory
1.0
1.7
mA
Typical peripheral current consumption VDD = 5.0 V(1)
Parameter
TIM1 supply current(2)
Typ.
Typ.
0.03
0.23
0.34
0.02
0.12
0.19
IDD(TIM3)
TIM3 supply
current(2)
0.01
0.1
0.16
IDD(TIM4)
TIM4 supply current(2)
0.004
0.03
0.05
0.03
0.09
0.15
IDD(TIM2)
IDD(USART)
IDD(LINUART)
TIM2 supply current
(2)
Typ.
fmaster = 2 MHz fmaster = 16 MHz fmaster =24 MHz
USART supply
current(2)
0.03
0.11
0.18
IDD(SPI)
SPI supply
current(2)
0.01
0.04
0.07
IDD(I2C)
I2C supply current(2)
IDD(CAN)
IDD(AWU)
IDD(TOT_DIG)
IDD(ADC)
LINUART supply
current(2)
0.02
0.06
0.91
CAN supply
current(3)
0.06
0.30
0.40
AWU supply
current(2)
0.003
0.02
0.05
All digital peripherals on
0.22
1
2.4
ADC supply current when
converting(4)
0.93
0.95
0.96
Unit
mA
1. Typical values not tested in production. Since the peripherals are powered by an internally regulated, constant digital
supply voltage, the values are similar in the full supply voltage range.
2. Data based on a differential IDD measurement between no peripheral clocked and a single active peripheral. This
measurement does not include the pad toggling consumption.
3. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data
transmit sequence in loopback mode at 1 MHz. This measurement does not include the pad toggling consumption.
4. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Current consumption curves
Figure 12 to Figure 17 show typical current consumption measured with code executing in
RAM.
Figure 12. Typ. IDD(RUN)HSE vs. VDD
@fCPU = 16 MHz, peripherals = on
10
9
25°C
8
85°C
7
125°C
25°C
9
IDD(RUN)HSE [mA]
IDD(RUN)HSE [mA]
10
Figure 13. Typ. IDD(RUN)HSE vs. fCPU
@ VDD = 5.0 V, peripherals = on
6
5
4
3
2
1
8
85°C
7
125°C
6
5
4
3
2
1
0
0
2.5
3
3.5
4
4.5
5
5.5
0
6
5
10
VDD [V]
3
2
25°C
85°C
125°C
1
0
4.5
5.5
5
4
3
2
25°C
85°C
125°C
1
0
2.5
6.5
3.5
4.5
5.5
6.5
VDD [V]
Figure 16. Typ. IDD(WFI)HSE vs. fCPU
@ VDD = 5.0 V, peripherals = on
Figure 17. Typ. IDD(WFI)HSI vs. VDD
@ fCPU = 16 MHz, peripherals = off
2.5
IDD(WFI)HSI [mA]
6
IDD(WFI)HSE [mA]
30
6
VDD [V]
5
4
3
25°C
2
85°C
1
5
10
15
20
25
1.5
1
25°C
85°C
0.5
0
0
0
2
125°C
125°C
30
2.5
3
3.5
4
4.5
VDD [V]
fcpu [MHz]
64/110
25
Figure 15. Typ. IDD(WFI)HSE vs. VDD
@ fCPU = 16 MHz, peripherals = on
IDD(WFI)HSE [mA]
IDD(RUN)HSI [mA]
4
3.5
20
fcpu [MHz]
Figure 14. Typ. IDD(RUN)HSI vs. VDD
@ fCPU = 16 MHz, peripherals = off
2.5
15
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5.5
6
STM8AF52/62xx, STM8AF51/61xx
10.3.3
Electrical characteristics
External clock sources and timing characteristics
HSE external clock
An HSE clock can be generated by feeding an external clock signal of up to 24 MHz to the
OSCIN pin.
Clock characteristics are subject to general operating conditions for VDD and TA.
Table 33.
Symbol
HSE external clock characteristics
Parameter
Conditions
Min
Typ
Max
Unit
TA = -40 °C to 150 °C
0(1)
—
24
MHz
fHSE_ext
User external clock source
frequency
VHSEdHL
Comparator hysteresis
—
0.1 x VDD
—
—
VHSEH
OSCIN high-level input pin
voltage
—
0.7 x VDD
—
VDD
VHSEL
OSCIN low-level input pin
voltage
—
VSS
—
0.3 x VDD
VSS < VIN < VDD
-1
—
+1
ILEAK_HSE
OSCIN input leakage current
V
µA
1. If CSS is used, the external clock must have a frequency above 500 kHz.
Figure 18. HSE external clock source
VHSEH
VHSEL
fHSE
External clock
source
OSCIN
STM8A
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 24 MHz.
All the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
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Electrical characteristics
Table 34.
HSE oscillator characteristics
Symbol
Parameter
RF
CL1/CL2
STM8AF52/62xx, STM8AF51/61xx
(1)
gm
tSU(HSE)(2)
Conditions
Min
Typ
Max
Unit
Feedback resistor
—
—
220
—
kΩ
Recommended load capacitance
—
—
—
20
pF
Oscillator trans conductance
—
5
—
—
mA/V
VDD is
stabilized
—
2.8
—
ms
Startup time
1. The oscillator needs two load capacitors, CL1 and CL2, to act as load for the crystal. The total load capacitance (CLoad) is
(CL1 * CL2)/(CL1 + CL2). If CL1 = CL2, Cload = CL1/2. Some oscillators have built-in load capacitors, CL1 and CL2.
2. This value is the startup time, measured from the moment it is enabled (by software) until a stabilized 24 MHz oscillation is
reached. It can vary with the crystal type that is used.
Figure 19. HSE oscillator circuit diagram
fHSE to core
Rm
Lm
RF
CO
CL1
OSCIN
Cm
gm
Resonator
Current control
Resonator
STM8A
OSCOUT
CL2
HSE oscillator critical gm formula
The crystal characteristics have to be checked with the following formula:
Equation 1
g m » g mcrit
where gmcrit can be calculated with the crystal parameters as follows:
Equation 2
f
2
g mcrit = ( 2 × Π × HSE ) × R m ( 2Co + C )
Rm: Notional resistance (see crystal specification)
Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1 = CL2 = C: Grounded external capacitance
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STM8AF52/62xx, STM8AF51/61xx
Internal clock sources and timing characteristics
Subject to general operating conditions for VDD and TA.
High-speed internal RC oscillator (HSI)
Table 35.
HSI oscillator characteristics
Symbol
fHSI
Parameter
Conditions
Min
Typ
Max
Unit
—
—
16
—
MHz
HSI oscillator user
trimming accuracy
Trimmed by the application
for any VDD and TA
conditions
-1
—
1
HSI oscillator accuracy
(factory calibrated)
VDD = 3.0 V ≤ VDD ≤ 5.5 V,
-40 °C ≤ TA ≤ 150 °C
-5
—
5
—
—
—
2(1)
Frequency
ACCHS
tsu(HSI)
HSI oscillator wakeup time
%
µs
1. Guaranteed by characterization, not tested in production
Figure 20. Typical HSI frequency vs VDD
3%
-40°C
HSI frequency variation [%]
10.3.4
Electrical characteristics
2%
25°C
85°C
1%
125°C
0%
-1%
-2%
-3%
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Low-speed internal RC oscillator (LSI)
Subject to general operating conditions for VDD and TA.
Table 36.
LSI oscillator characteristics
Symbol
fLSI
tsu(LSI)
Parameter
Conditions
Min
Typ
Max
Unit
Frequency
—
112
128
144
kHz
LSI oscillator wakeup time
—
—
—
7(1)
µs
1. Data based on characterization results, not tested in production.
Figure 21. Typical LSI frequency vs VDD
LSI frequency variation [%]
3%
2%
1%
25°C
0%
-1%
-2%
-3%
2.5
68/110
3
3.5
4
VDD [V]
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4.5
5
5.5
6
STM8AF52/62xx, STM8AF51/61xx
10.3.5
Electrical characteristics
Memory characteristics
Flash program memory/data EEPROM memory
General conditions: TA = -40 °C to 150 °C.
Table 37.
Symbol
VDD
Flash program memory/data EEPROM memory
Parameter
Conditions
Min(1) Typ
Max
Operating voltage
(all modes, execution/write/erase)
fCPU is 16 to 24 MHz
with 1 ws
fCPU is 0 to 16 MHz
with 0 ws
Operating voltage (code execution)
fCPU is 16 to 24 MHz
with 1 ws
fCPU is 0 to 16 MHz
with 0 ws
2.6
—
5.5
Standard programming time
(including erase) for byte/word/block
(1 byte/4 bytes/128 bytes)
—
—
6
6.6
Fast programming time for 1 block
(128 bytes)
—
—
3
3.3
Erase time for 1 block (128 bytes)
—
—
3
3.3
3.0
—
Unit
5.5
V
VDD
tprog
terase
ms
ms
1. Guaranteed by characterization, not tested in production.
Table 38.
Symbol
Flash program memory
Parameter
Condition
Min
Max
Unit
TWE
Temperature for writing and erasing
—
-40
150
°C
NWE
Flash program memory endurance
(erase/write cycles)(1)
TA = 25 °C
1000
—
cycles
—
Data retention time
TA = 25 °C
40
tRET
TA = 55 °C
20
—
years
1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a
write/erase operation addresses a single byte.
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Electrical characteristics
Table 39.
STM8AF52/62xx, STM8AF51/61xx
Data memory
Symbol
Parameter
Condition
Min
Max
Unit
TWE
Temperature for writing and erasing
—
-40
150
°C
Data memory endurance(1)
(erase/write cycles)
TA = 25 °C
300 k
NWE
tRET
Data retention time
—
cycles
(2)
100 k
—
TA = 25 °C
40(2)(3)
—
TA = 55 °C
(2)(3)
—
TA = -40°C to 125 °C
20
years
1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a
write/erase operation addresses a single byte.
2. More information on the relationship between data retention time and number of write/erase cycles is
available in a separate technical document.
3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.
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10.3.6
Electrical characteristics
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 40.
Symbol
I/O static characteristics
Parameter
VIL
Low-level input voltage
VIH
High-level input voltage
Vhys
Hysteresis(1)
VOH
VOL
Rpu
tR, tF
Conditions
—
Min
Typ
Max
-0.3 V
0.3 x VDD
0.7 x VDD
VDD + 0.3 V
—
0.1 x
VDD
—
Unit
—
Standard I/0, VDD = 5 V,
I = 3 mA
VDD - 0.5 V
—
—
Standard I/0, VDD = 3 V,
I = 1.5 mA
VDD - 0.4 V
—
—
High sink and true open
drain I/0, VDD = 5 V
I = 8 mA
—
—
0.5
Standard I/0, VDD = 5 V
I = 3 mA
—
—
0.6
Standard I/0, VDD = 3 V
I = 1.5 mA
—
—
0.4
VDD = 5 V, VIN = VSS
35
50
65
Fast I/Os
Load = 50 pF
—
—
35(2)
Standard and high sink I/Os
Load = 50 pF
—
—
125(2)
High-level output voltage
Low-level output voltage
Pull-up resistor
Rise and fall time
(10% - 90%)
Ilkg
Digital input pad leakage
current
Ilkg ana
Analog input pad leakage
current
Ilkg(inj)
Leakage current in
adjacent I/O(3)
IDDIO
Total current on either
VDDIO or VSSIO
V
kΩ
ns
Fast I/Os
Load = 20 pF
20(2)
Standard and high sink I/Os
Load = 20 pF
50(2)
VSS ≤ VIN ≤ VDD
—
—
±1
VSS ≤ VIN ≤ VDD
-40 °C < TA < 125 °C
—
—
±250
VSS ≤ VIN ≤ VDD
-40 °C < TA < 150 °C
—
—
±500
Injection current ±4 mA
—
—
±1(3)
µA
Including injection currents
—
—
60
mA
µA
nA
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
2. Guaranteed by design.
3. Data based on characterization results, not tested in production.
Figure 22. Typical VIL and VIH vs VDD @ four temperatures
6
-40°C
25°C
5
85°C
VIL / V IH [V]
4
125°C
3
2
1
0
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 23. Typical pull-up resistance RPU vs VDD @ four temperatures
60
Pull-Up resistance [k ohm]
55
50
45
-40°C
40
25°C
85°C
35
125°C
30
2.5
3
3.5
4
4.5
VDD [V]
72/110
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5.5
6
STM8AF52/62xx, STM8AF51/61xx
Electrical characteristics
Figure 24. Typical pull-up current Ipu vs VDD @ four temperatures(1)
140
Pull-Up current [µA]
120
100
80
-40°C
60
25°C
40
85°C
125°C
20
0
0
1
2
3
4
5
6
VDD [V]
1. The pull-up is a pure resistor (slope goes through 0).
Typical output level curves
Figure 25 to Figure 34 show typical output level curves measured with output on a single pin.
Figure 25. Typ. VOL @ VDD = 3.3 V (standard
ports)
Figure 26. Typ. VOL @ VDD = 5.0 V (standard
ports)
-40°C
1.5
-40°C
1.5
25°C
25°C
85°C
1.25
85°C
1.25
125°C
125°C
1
VOL [V]
VOL [V]
1
0.75
0.75
0.5
0.5
0.25
0.25
0
0
0
1
2
3
4
5
6
7
0
2
4
6
IOL [mA]
Figure 27. Typ. VOL @ VDD = 3.3 V (true open
drain ports)
25°C
1.75
85°C
125°C
1.5
85°C
125°C
1.5
1.25
1.25
VOL [V]
VOL [V]
12
-40°C
2
25°C
1.75
10
Figure 28. Typ. VOL @ VDD = 5.0 V (true open
drain ports)
-40°C
2
8
IOL [mA]
1
0.75
1
0.75
0.5
0.5
0.25
0.25
0
0
0
2
4
6
8
10
12
14
IOL [mA]
0
5
10
15
20
25
IOL [mA]
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Figure 29. Typ. VOL @ VDD = 3.3 V (high sink
ports)
Figure 30. Typ. VOL @ VDD = 5.0 V (high sink
ports)
-40°C
1.5
25°C
85°C
1.25
-40°C
1.5
25°C
85°C
1.25
125°C
125°C
1
VOL [V]
VOL [V]
1
0.75
0.75
0.5
0.5
0.25
0.25
0
0
0
2
4
6
8
10
12
14
0
5
10
IOL [mA]
Figure 31. Typ. VDD - VOH @ VDD = 3.3 V
(standard ports)
125°C
85°C
125°C
1.5
1.25
VDD - V OH [V]
VDD - V OH [V]
25°C
1.75
85°C
1.5
1
0.75
1.25
1
0.75
0.5
0.5
0.25
0.25
0
0
0
1
2
3
4
5
6
7
0
2
4
6
IOH [mA]
125°C
85°C
125°C
1.5
1.25
VDD - V OH [V]
VDD - V OH [V]
25°C
1.75
85°C
1.5
12
-40°C
2
25°C
1.75
10
Figure 34. Typ. VDD - VOH @ VDD = 5.0 V (high
sink ports)
-40°C
2
8
IOH [mA]
Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (high
sink ports)
1
0.75
1.25
1
0.75
0.5
0.5
0.25
0.25
0
0
0
2
4
6
8
10
12
14
IOH [mA]
74/110
25
-40°C
2
25°C
1.75
20
Figure 32. Typ. VDD - VOH @ VDD = 5.0 V
(standard ports)
-40°C
2
15
IOL [mA]
0
5
10
15
IOH [mA]
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25
STM8AF52/62xx, STM8AF51/61xx
Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 41.
NRST pin characteristics
Symbol
VIL(NRST)
Parameter
Conditions
Min
Typ
Max
—
VSS
—
0.3 x VDD
—
0.7 x VDD
—
VDD
—
0.6
V
NRST low-level input voltage(1)
(1)
Unit
—
VIH(NRST)
NRST high-level input voltage
VOL(NRST)
NRST low-level output voltage(1)
RPU(NRST)
NRST pull-up resistor
—
30
40
60
kΩ
NRST input filtered pulse(1)
—
85
—
315
ns
tIFP
tIFP(NRST)
IOL = 3 mA
NRST Input not filtered pulse
duration(2)
500
ns
1. Data based on characterization results, not tested in production.
2. Data guaranteed by design, not tested in production.
Figure 35. Typical NRST VIL and VIH vs VDD @ four temperatures
-40°C
6
25°C
85°C
5
125°C
4
VIL / V IH [V]
10.3.7
Electrical characteristics
3
2
1
0
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Figure 36. Typical NRST pull-up resistance RPU vs VDD
-40°C
60
NRST Pull-Up resistance [k ohm]
25°C
55
85°C
125°C
50
45
40
35
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 37. Typical NRST pull-up current Ipu vs VDD
140
NRST Pull-Up current [µA]
120
100
80
60
-40°C
25°C
40
85°C
20
125°C
0
0
1
2
3
VDD [V]
4
5
6
The reset network shown in Figure 38 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 41:
NRST pin characteristics), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external
circuitry, attention must be taken to the charge/discharge time of the external capacitor to
fulfill the external devices reset timing conditions. Minimum recommended capacity is 10 nF.
76/110
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Electrical characteristics
Figure 38. Recommended reset pin protection
STM8A
VDD
RPU
External
reset
circuit
(optional)
NRST
Internal reset
Filter
0.1µF
10.3.8
TIM 1, 2, 3, and 4 electrical specifications
Subject to general operating conditions for VDD, fMASTER and TA.
Table 42.
TIM 1, 2, 3, and 4 electrical specifications
Symbol
fEXT
Parameter
Conditions
Min
Typ
Max
Unit
—
—
—
24
MHz
Timer external clock frequency(1)
1. Not tested in production.
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
SPI interface
10.3.9
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under ambient temperature, fMASTER frequency, and VDD supply voltage
conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 43.
SPI characteristics
Symbol
Parameter
Conditions
Min
Max
0
10
0
6(1)
0
8(1)
—
25(2)
Master mode
fSCK
1/tc(SCK)
SPI clock frequency
Slave mode
VDD < 4.5 V
VDD = 4.5 V to 5.5 V
tr(SCK)
tf(SCK)
tsu(NSS)(3)
SPI clock rise and fall time Capacitive load: C = 30 pF
NSS setup time
Slave mode
4 * tMASTER
—
NSS hold time
Slave mode
70
—
tSCK/2 + 15
tw(SCKH)(3)
tw(SCKL)(3)
Master mode
5
—
Slave mode
5
—
Master mode
7
—
Slave mode
10
—
Slave mode
—
3* tMASTER
Data output disable time
Slave mode
25
tv(SO)(3)
VDD < 4.5 V
Slave mode
(after enable edge) V = 4.5 V to 5.5 V
DD
—
75
Data output valid time
—
53
tv(MO)(3)
Data output valid time
Master mode (after enable edge)
—
30
Slave mode (after enable edge)
31
—
Master mode (after enable edge)
12
—
th(NSS)
(3)
tw(SCKH)(3)
SCK high and low time
tw(SCKL)(3)
tsu(MI)(3)
tsu(SI)(3)
Data input setup time
th(MI)(3)
th(SI)(3)
Data input hold time
ta(SO)(3)(4) Data output access time
tdis(SO)
(3)(5)
th(SO)(3)
th(MO)(3)
Master mode
tSCK/2 - 15
Unit
MHz
ns
Data output hold time
1. fSCK < fMASTER/2.
2. The pad has to be configured accordingly (fast mode).
3. Values based on design simulation and/or characterization results, and not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
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STM8AF52/62xx, STM8AF51/61xx
Electrical characteristics
Figure 39. SPI timing diagram in slave mode and with CPHA = 0
NSS input
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tc(SCK)
th(NSS)
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
M SB IN
LSB IN
B I T1 IN
th(SI)
ai14134
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 40. SPI timing diagram in slave mode and with CPHA = 1
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
B I T1 IN
M SB IN
LSB IN
ai14135
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
Doc ID 14395 Rev 9
79/110
Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Figure 41. SPI timing diagram - master mode
(IGH
.33INPUT
3#+OUTPUT
#0(! #0/,
3#+OUTPUT
TC3#+
#0(!
#0/,
#0(! #0/,
#0(!
#0/,
TSU-)
-)3/
).0 54
TW3#+(
TW3#+,
TR3#+
TF3#+
-3 ").
") 4).
,3").
TH-)
-/3)
/5454
" ) 4/54
- 3"/54
TV-/
,3"/54
TH-/
AI
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
80/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
10.3.10
Electrical characteristics
I2C interface characteristics
Table 44.
I2C characteristics
Standard mode I2C Fast mode I2C(1)
Symbol
Parameter
Min(2)
Max(2)
Min(2)
Max(2)
Unit
tw(SCLL)
SCL clock low time
4.7
—
1.3
—
tw(SCLH)
SCL clock high time
4.0
—
0.6
—
tsu(SDA)
SDA setup time
250
—
100
—
th(SDA)
SDA data hold time
0(3)
—
0(4)
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
(VDD 3 V to 5.5 V)
—
1000
—
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
(VDD 3 V to 5.5 V)
—
300
—
300
th(STA)
START condition hold time
4.0
—
0.6
—
tsu(STA)
Repeated START condition setup time
4.7
—
0.6
—
tsu(STO)
STOP condition setup time
4.0
—
0.6
—
µs
STOP to START condition time
(bus free)
4.7
—
1.3
—
µs
—
400
—
400
pF
tw(STO:STA)
Cb
µs
ns
µs
Capacitive load for each bus line
1. fMASTER, must be at least 8 MHz to achieve max fast
I 2C
speed (400 kHz)
2. Data based on standard I2C protocol requirement, not tested in production
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
Doc ID 14395 Rev 9
81/110
Electrical characteristics
10.3.11
STM8AF52/62xx, STM8AF51/61xx
10-bit ADC characteristics
Subject to general operating conditions for VDDA, fMASTER and TA unless otherwise
specified.
Table 45.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
kHz/MHz
fADC
ADC clock frequency
—
111 kHz
—
4 MHz
VDDA
Analog supply
—
3
—
5.5
VREF+
Positive reference voltage
—
2.75
—
VDDA
VREF-
Negative reference voltage
—
VSSA
—
0.5
—
VSSA
—
VDDA
Devices with
external VREF+/
VREF- pins
VREF-
—
VREF+
—
—
—
3
fADC = 2 MHz
—
1.5
—
fADC = 4 MHz
—
0.75
—
fADC = 2 MHz
—
7
—
VAIN
Csamp
Conversion voltage range(1)
Internal sample and hold capacitor
tS(1)
Sampling time
(3 x 1/fADC)
tSTAB
Wakeup time from standby
tCONV
Total conversion time including
sampling time
(14 x 1/fADC)
Rswitch
Equivalent switch resistance
fADC = 4 MHz
V
pF
µs
3.5
fADC = 2 MHz
—
7
—
fADC = 4 MHz
—
3.5
—
—
—
—
30
kΩ
1. During the sample time, the sampling capacitance, Csamp (3 pF typ), can be charged/discharged by the
external source. The internal resistance of the analog source must allow the capacitance to reach its final
voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no
effect on the conversion result.
Figure 42. Typical application with ADC
VDD
STM8A
VT
0.6V
RAIN
Rswitch
AINx
VAIN
Ts
CAIN
VT
0.6V
IL
10-bit A/D
conversion
Csamp
1. Legend: RAIN = external resistance, CAIN = capacitors, Csamp = internal sample and hold capacitor.
82/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 46.
Electrical characteristics
ADC accuracy for VDDA = 5 V
Symbol
Parameter
Conditions
Typ
Max(1)
|ET|
Total unadjusted error(2)
1.4
3(3)
|EO|
Offset error(2)
0.8
3
0.1
2
0.9
1
0.7
1.5
(2)
|EG|
Gain error
|ED|
Differential linearity error(2)
|EL|
fADC = 2 MHz
Integral linearity error
(2)
(2)
(4)
1.9
4(4)
1.3(4)
4(4)
0.6(4)
3(4)
|ET|
Total unadjusted error
|EO|
Offset error(2)
|EG|
Gain error(2)
|ED|
Differential linearity error(2)
1.5(4)
2(4)
|EL|
Integral linearity error(2)
1.2(4)
1.5(4)
fADC = 4 MHz
Unit
LSB
1. Max value is based on characterization, not tested in production.
2. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for
IINJ(PIN) and ΣIINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy.
3. TUE 2LSB can be reached on specific salestypes on the whole temperature range.
4. Target values.
Figure 43. ADC accuracy characteristics
EG
1023
1022
1021
V
–V
DDA
SSA
1LSB
= ----------------------------------------IDEAL
1024
(2)
ET
7
(3)
(1)
6
5
4
EO
EL
3
ED
2
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
1021102210231024
VDDA
1. Example of an actual transfer curve
2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.
EO = Offset error: Deviation between the first actual transition and the first ideal one.
EG = Gain error: Deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: Maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: Maximum deviation between any actual transition and the end point correlation
line.
Doc ID 14395 Rev 9
83/110
Electrical characteristics
10.3.12
STM8AF52/62xx, STM8AF51/61xx
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 47.
Symbol
84/110
EMS data
Parameter
Conditions
Level/class
VFESD
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VDD = 3.3 V, TA= 25 °C,
fMASTER = 16 MHz (HSI clock),
Conforms to IEC 1000-4-2
3B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD= 3.3 V, TA= 25 °C,
fMASTER = 16 MHz (HSI clock),
Conforms to IEC 1000-4-4
4A
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Electrical characteristics
Electromagnetic interference (EMI)
Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin
loading.
Table 48.
EMI data
Conditions
Symbol
SEMI
Parameter
Max fCPU(1)
General
conditions
VDD = 5 V,
TA = 25 °C,
Peak level
LQFP80 package
conforming to SAE
SAE EMI level J 1752/3
Monitored
frequency band
Unit
8
MHz
16
MHz
24
MHz
0.1 MHz to 30 MHz
15
17
22
30 MHz to 130 MHz
18
22
16
130 MHz to 1 GHz
-1
3
5
—
2
2.5
2.5
dBµV
1. Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard. For more details, refer to the application
note AN1181.
Table 49.
Symbol
ESD absolute maximum ratings
Ratings
Conditions
Class
Maximum
value(1)
VESD(HBM)
Electrostatic discharge voltage
(human body model)
TA = 25 °C, conforming to
JESD22-A114
3A
4000
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
TA = 25 °C, conforming to
JESD22-C101
3
500
VESD(MM)
Electrostatic discharge voltage
(charge device model)
TA = 25 °C, conforming to
JESD22-A115
B
200
Uni
t
V
1. Data based on characterization results, not tested in production
Doc ID 14395 Rev 9
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
●
A supply overvoltage (applied to each power supply pin) and
●
A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 50.
Symbol
Electrical sensitivities
Parameter
Conditions
Class(1)
TA = 25 °C
LU
TA = 85 °C
Static latch-up class
TA = 125 °C
A
TA = 150 °C
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
86/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
10.4
Electrical characteristics
Thermal characteristics
In case the maximum chip junction temperature (TJmax) specified in Table 26: General
operating conditions is exceeded, the functionality of the device cannot be guaranteed.
TJmax, in degrees Celsius, may be calculated using the following equation:
Equation 3
TJmax = TAmax + (PDmax x ΘJA)
where:
TAmax is the maximum ambient temperature in ° C
ΘJA is the package junction-to-ambient thermal resistance in ° C/W
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/Omax represents the maximum power dissipation on output pins
where:
Equation 4
PI/Omax = Σ (VOL * IOL) + Σ((VDD - VOH) * IOH)
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low- and high-level in the
application.
Table 51.
Thermal characteristics(1)
Symbol
Parameter
Value
Unit
ΘJA
Thermal resistance junction-ambient
LQFP 80 - 14 x 14 mm
38
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 64 - 10 x 10 mm
46
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm
57
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm
59
°C/W
ΘJA
Thermal resistance junction-ambient
VFQFPN 32 - 5 x 5 mm
25
°C/W
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
10.4.1
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
Doc ID 14395 Rev 9
87/110
Electrical characteristics
10.4.2
STM8AF52/62xx, STM8AF51/61xx
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
Figure 52: Ordering information scheme(1) on page 98).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
–
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2)
–
IDDmax = 8 mA
–
VDD = 5 V
–
maximum 20 I/Os used at the same time in output at low-level with IOL = 8 mA
–
VOL = 0.4 V
Equation 5
PINTmax = 8 mA x 5 V = 400 mW
Equation 6
PIOmax = 20 x 8 mA x 0.4 V = 64 mW
This gives:
PINTmax = 400 mW and PIOmax 64 mW:
Equation 7
PDmax = 400 mW + 64 mW
Thus:
PDmax = 464 mW.
Using the values obtained in Table 51: Thermal characteristics on page 87 TJmax is
calculated as follows:
For LQFP64 46 °C/W
Equation 8
Tjmax = 82 °C + (46 °C/W x 464 mW) = 82 °C + 21 °C = 103 ° C
This is within the range of the suffix B version parts (-40 °C < Tj < 105 ° C).
Parts must be ordered at least with the temperature range suffix B.
88/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
11
Package characteristics
Package characteristics
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Doc ID 14395 Rev 9
89/110
Package characteristics
11.1
STM8AF52/62xx, STM8AF51/61xx
Package mechanical data
Figure 44. LQFP 80-pin low profile quad flat package (14 x 14)
D
ccc C
D1
A
A2
D3
41
60
40
61
b
L1
E3 E1 E
L
A1
K
80
Pin 1
identification
Table 52.
1
c
1S_ME
LQFP 80-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
A
—
—
1.600
—
—
0.0630
A1
0.050
—
0.150
0.0020
—
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.220
0.320
0.380
0.0087
0.0126
0.0150
c
0.090
—
0.200
0.0035
—
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
—
12.350
—
—
0.4862
—
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
—
12.350
—
—
0.4862
—
e
—
0.650
—
—
0.0256
—
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
—
1.000
—
—
0.0394
—
ccc
—
—
0.100
—
—
0.0039
k
0°
3.5°
7°
0°
3.5°
7°
1. Values in inches are converted from mm and rounded to 4 decimal digits
90/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Package characteristics
Figure 45. LQFP 64-pin low profile quad flat package (10 x 10)
D
ccc C
D1
A
A2
D3
33
48
32
49
b
L1
E3 E1 E
L
A1
K
64
17
Pin 1
identification
16
1
Table 53.
c
5W_ME
LQFP 64-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
A
—
—
1.600
—
—
0.0630
A1
0.050
—
0.150
0.0020
—
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
—
0.200
0.0035
—
0.0079
D
11.800
12.000
12.200
0.4646
0.4724
0.4803
D1
9.800
10.000
10.200
0.3858
0.3937
0.4016
D3
—
7.500
—
—
0.2953
—
E
11.800
12.000
12.200
0.4646
0.4724
0.4803
E1
9.800
10.000
10.200
0.3858
0.3937
0.4016
E3
—
7.500
—
—
0.2953
—
e
—
0.500
—
—
0.0197
—
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
—
1.000
—
—
0.0394
—
ccc
—
—
0.080
—
—
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits
Doc ID 14395 Rev 9
91/110
Package characteristics
STM8AF52/62xx, STM8AF51/61xx
Figure 46. LQFP 64-pin recommended footprint
7?&0
1. Drawing is not to scale. Dimensions are in millimeters.
92/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Package characteristics
Figure 47. LQFP 48-pin low profile quad flat package (7 x 7)
D
ccc C
D1
D3
A
A2
25
36
24
37
L1
b
E3 E1 E
48
Pin 1
identification
13
1
L
A1
K
c
12
5B_ME
Table 54.
LQFP 48-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
A
—
—
1.600
—
—
0.0630
A1
0.050
—
0.150
0.0020
—
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
—
0.200
0.0035
—
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
—
5.500
—
—
0.2165
—
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
—
5.500
—
—
0.2165
—
e
—
0.500
—
—
0.0197
—
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
—
1.000
—
—
0.0394
—
ccc
—
—
0.080
—
—
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits
Doc ID 14395 Rev 9
93/110
Package characteristics
STM8AF52/62xx, STM8AF51/61xx
Figure 48. LQFP 48-pin recommended footprint
"?&0
1. Drawing is not to scale. Dimensions are in millimeters.
94/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Package characteristics
Figure 49. LQFP 32-pin low profile quad flat package (7 x 7)
ccc C
D
D1
D3
24
A
A2
17
16
25
L1
b
E3
32
E1 E
9
Pin 1
identification
L
A1
1
K
c
8
5V_ME
Table 55.
LQFP 32-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
A
—
—
1.600
—
—
0.0630
A1
0.050
—
0.150
0.0020
—
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.300
0.370
0.450
0.0118
0.0146
0.0177
c
0.090
—
0.200
0.0035
—
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
—
5.600
—
—
0.2205
—
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
—
5.600
—
—
0.2205
—
e
—
0.800
—
—
0.0315
—
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
—
1.000
—
—
0.0394
—
ccc
—
—
0.100
—
—
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits
Doc ID 14395 Rev 9
95/110
Package characteristics
STM8AF52/62xx, STM8AF51/61xx
Figure 50. LQFP 32-pin recommended footprint
6?&0
1. Drawing is not to scale. Dimensions are in millimeters.
96/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Package characteristics
Figure 51. VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5)
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
E
b
E2
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
Table 56.
42_ME
VFQFPN 32-lead very thin fine pitch quad flat no-lead package
mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
A
0.800
0.900
1.000
0.0315
0.0354
0.0394
A1
0.000
0.020
0.050
0.000
0.0008
0.0020
A3
—
0.200
—
—
0.0079
—
b
0.180
0.250
0.300
0.0071
0.0098
0.0118
D
4.850
5.000
5.150
0.1909
0.1969
0.2028
D2
3.400
3.450
3.500
0.1339
0.1358
0.1378
E
4.850
5.000
5.150
0.1909
0.1969
0.2028
E2
3.400
3.450
3.500
0.1339
0.1358
0.1378
e
—
0.500
—
—
0.0197
—
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
ddd
—
—
0.080
—
—
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits
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Ordering information
12
STM8AF52/62xx, STM8AF51/61xx
Ordering information
Figure 52. Ordering information scheme(1)
Example:
STM8A
F
62
A
A
T
D
XXX(2)
Y
Product class
8-bit automotive microcontroller
Program memory type
F = Flash + EEPROM
P = FASTROM
H = Flash no EEPROM(3)
Device family
51 = Silicon rev X, CAN/LIN(3)
61 = Silicon rev X, LIN only(3
52 = Silicon rev U and rev T, CAN/LIN
62 = Silicon rev U and rev T, LIN only
Program memory size
6 = 32 Kbytes
7 = 48 Kbytes(3)
8 = 64 Kbytes
9 = 96 Kbytes(3)
A= 128 Kbytes
Pin count
6 = 32 pins
8 = 48 pins
9= 64 pins
A = 80 pins
Package type
T = LQFP
U = VFQFPN
Temperature range
A = -40 to 85 °C
B = -40 to 105 °C(3)
C = -40 to 125 °C
D = -40 to 150 °C(4)
Packing
Y = Tray
U = Tube
X = Tape and reel compliant with EIA 481-C
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest
to you.
2. Customer specific FASTROM code or custom device configuration. This field shows ‘SSS’ if the device
contains a super set silicon, usually equipped with bigger memory and more I/Os. This silicon is supposed
to be replaced later by the target silicon.
3. Not recommended for new design.
4. Available on STM8AFx2xx devices.
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13
STM8 development tools
STM8 development tools
Development tools for the STM8A microcontrollers include the
●
STice emulation system offering tracing and code profiling
●
STVD high-level language debugger including assembler and visual development
environment - seamless integration of third party C compilers
●
STVP Flash programming software
In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
13.1
Emulation and in-circuit debugging tools
The STM8 tool line includes the STice emulation system offering a complete range of
emulation and in-circuit debugging features on a platform that is designed for versatility and
cost-effectiveness. In addition, STM8A application development is supported by a low-cost
in-circuit debugger/programmer.
The STice is the fourth generation of full-featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including tracing, profiling and code coverage
analysis to help detect execution bottlenecks and dead code.
In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers
via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of
an application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
13.1.1
STice key features
●
Program and data trace recording up to 128 K records
●
Advanced breakpoints with up to 4 levels of conditions
●
Data breakpoints
●
Real-time read/write of all device resources during emulation
●
Occurrence and time profiling and code coverage analysis (new features)
●
In-circuit debugging/programming via SWIM protocol
●
8-bit probe analyzer
●
1 input and 2 output triggers
●
USB 2.0 high-speed interface to host PC
●
Power supply follower managing application voltages between 1.62 to 5.5 V
●
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements
●
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
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STM8 development tools
13.2
STM8AF52/62xx, STM8AF51/61xx
Software tools
STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer
(STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8.
13.2.1
STM8 toolset
The STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com. This package includes:
ST visual develop
Full-featured integrated development environment from STMicroelectronics, featuring:
●
Seamless integration of C and ASM toolsets
●
Full-featured debugger
●
Project management
●
Syntax highlighting editor
●
Integrated programming interface
●
Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP)
Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8A
microcontroller’s Flash memory. STVP also offers project mode for saving programming
configurations and automating programming sequences.
13.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface. Available toolchains include:
C compiler for STM8
All compilers are available in free version with a limited code size depending on the
compiler. For more information, refer to www.cosmic-software.com, www.raisonance.com,
and www.iar.com.
STM8 assembler linker
Free assembly toolchain included in the STM8 toolset, which allows you to assemble and
link your application source code.
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13.3
STM8 development tools
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8A Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming your STM8A.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
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Revision history
14
STM8AF52/62xx, STM8AF51/61xx
Revision history
Table 57.
Document revision history
Date
Revision
31-Jan-2008
Rev 1
Initial release
Rev 2
Added ‘H’ products to the datasheet (Flash no EEPROM).
Features on page 1: Updated Memories, Reset and supply
management, Communication interfaces and I/Os; reduced wakeup
pins by 1.
Table 1: Removed STM8AF6168, STM8AF6148, STM8AF6166,
STM8AF6146, STM8AF5168, STM8AF5186, STM8AF5176, and
STM8AF5166.
Section 1, Section 5, Section 6.2, Table 21, and Section 9: Updated
reference documentation: RM0009, PM0047, and UM0470.
Section 2: Added information about peak performance.
Section 3: Removed STM8A common features table.
Table 4: Removed STM8AF5186T, STM8AF5176T, STM8AF5168T,
and STM8AF5166T.
Table 5: Removed STM8AF6168T, STM8AF6166T, STM8AF6148T,
and STM8AF6146T.
Section 5: Made minor content changes and improved readability
and layout.
Section 5.5.3: Major modification, TMU included.
Section 5.5.2: User trimming updated.
Section 5.5.3: LSI as CPU clock added.
Section 5.5.4 , Section 5.5.5: Maximum frequency conditional 32
Kbyte/128 Kbyte.
Section 5.8: Scan for 128 Kbyte removed.
Section 5.9, Section 5.9.3: SPI 10 Mb/s.
Figure 3, Figure 4, and Figure 5: Amended footnote 1.
Table 12: HS output changed from 20 mA to 8 mA.
Section 7: Corrected Figure 7: Register and memory map; removed
address list; added Table 14.
Section 10.3.2 Note on typical/WC values added.
Table 18: Replaced the source blocks ‘simple USART’, ‘very low-end
timer (timer 4)’, and ‘EEPROM’ with ‘LINUART’, ‘timer4’ and
‘reserved’ respectively, added TMU registers.
Table 20: Updated OPT6 and NOPT6, added OPT7 to 17 (TMU, BL)
Table 21: Updated OPT1 UBC[7:0], OPT4 CKAWUSEL, OPT4
PRSC [1:0], and OPT6, added OPT7 to 16 (TMU).
Table 23: Amended footnotes.
Table 26: Added parameter ‘voltage and current operating
conditions’.
Table 27: Amended footnotes.
Table 28: Replaced.
Table 29: Amended maximum data and footnotes.
Table 21: Replaced.
Table 22: Added and amended IDD(RUN) data; amended IDD(WFI)
data; amended footnotes.
Table 32: Filled in, amended maximum data and footnotes.
Figure 12 to Figure 17: info on peripheral activity added.
Table 33: Modified fHSE_ext data and added VHSEdhl data.
22-Aug-2008
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Changes
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Table 57.
Revision history
Document revision history (continued)
Date
22-Aug-2008
16-Sep-2008
Revision
Changes
Rev 2
cont’d
Table 35: Removed ACCHSI parameters and replaced with ACCHS
parameters; amended data and footnotes.
Amended data of ‘RAM and hardware registers’ table.
Table 37: Updated names and data of NRW and tRET parameters.
Table 40: Added VOH and VOL parameters; Updated Ilkg ana
parameter.
Removed: Output driving current (standard ports), Output driving
current (true open drain ports), and Output driving current (high sink
ports).
Table 45: Updated fADC, tS, and tCONV data.
ADC accuracy for VDDA = 3.3 V table: Removed the 4-MHz condition
from all parameters.
Table 46: Removed the 4-MHz condition from all parameters;
updated footnote 1 and removed footnote 2.
Table 50: Added data for TA = 145 °C.
Figure 52: Updated memory size, pin count and package type
information.
Rev 3
Replaced the salestype ‘STM8H61xx’ with ‘STM8AH61xx on the first
page.
Added ‘part numbers’ to heading rows of Table 1: Device summary.
Updated the 80-pin package silhouette on page 1 in line with POA
0062342-revD.
Table 18: Renamed ‘TMU key registers 0-7 [7:0]’ as ‘TMU key
registers 1-8 [7:0]’
Section 9: Updated introductory text concerning option bytes which
do not need to be saved in a complementary form.
Table 18: Renamed the option bits ‘TMU[0:3]’, ‘NTMU[0:3]’, and
‘TMU_KEY 0-7 [7:0]’ as ‘TMU[3:0]’, ‘NTMU[3:0]’, and ‘TMU_KEY 1-8
[7:0]’ respectively.
Table 21: Updated values of option byte 5 (HSECNT[7:0]); inverted
the description of option byte 6 (TMU[3:0]); renamed option bytes 8
to 15 ‘TMU_KEY 0-7 [7:0]’, as ‘TMU_KEY 1-8 [7:0]’.
Updated 80-pin package information in line with POA 0062342-revD
in Figure 44 and Table 52.
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Revision history
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Table 57.
Document revision history (continued)
Date
01-Jul-2009
104/110
Revision
Changes
Rev 4
Added ‘STM8AH61xx’ and ‘STM8AH51xx to document header.
Updated Features on page 1 (memories, timers, operating
temperature, ADC and I/Os).
Updated Table 1: Device summary.
Updated Kbytes value of program memory in Chapter 1: Introduction
Chapter 2: Description
– Changed the first two lines from the top.
Updated Figure 1: STM8A block diagram
Updated Chapter 5: Product overview
In Figure 5: LQFP 48-pin pinout, added USART function to pins 10,
11, and 12; added CAN Tx and CAN Rx functions to pins 35 and 36
respectively.
Section 6.2: Pin description
– Deleted text below the Table 12: Legend/abbreviation for the pin
description table
Table 13: STM8A microcontroller family pin description
– 68th, 69th pin (LQFP80): replaced X with a dash for PP output
– Added a table footnote
Updated Figure 7: Register and memory map
Table 14: Memory model 128K
– Updated footnote
Deleted the table “Stack and RAM partitioning“
Table 19: STM8A interrupt table.
– Updated priorities 13, 15, 17, 20 and 24
– Changed table footnote
Updated Chapter 7.2: Register map
Updated Table 39: Data memory, Table 40: I/O static characteristics,
and Table 41: NRST pin characteristics.
Section 10.1.1: Minimum and maximum values.
– Added ambient temperature TA = -40 °C
Updated Table 22: Voltage characteristics
Updated Table 23: Current characteristics
Updated Table 24: Thermal characteristics
UpdatedTable 26: General operating conditions
UpdatedTable 27: Operating conditions at power-up/power-down.
Figure 10: fCPUmax versus VDD.
– Updated temperature ranges in functional area
– Added a figure footnote
Removed ‘total current consumption’ and ‘note on the run-current
typical values’.
Replaced Table 28: Total current consumption in Run, Wait and Slow
mode. General conditions for VDD apply, TA = -40 °C to 150 °C
Replaced Table 29: Total current consumption in Halt and Active-halt
modes. General conditions for VDD applied. TA = -40 °C to 55 °C
unless otherwise stated.
Removed Table 21: Total current consumption in run, wait and slow
mode. General conditions for VDD apply. TA = -40 °C to 145 °C
Doc ID 14395 Rev 9
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Table 57.
Revision history
Document revision history (continued)
Date
01-Jul-2009
Revision
Changes
Rev 4
Removed Table 22: Total current consumption and timing in halt, fast
active halt and slow active halt modes at VDD = 3.3 V.
Added Table 30: Oscillator current consumption
Added Table 31: Programming current consumption.
Updated Table 32: Typical peripheral current consumption VDD = 5.0
V
Changed Section : HSE external clock title from “HSE user external
clock“
Updated Table 33: HSE external clock characteristics
Updated Table 34: HSE oscillator characteristics.
Figure 19: HSE oscillator circuit diagram.
– Changed ‘consumption control’ to ‘current control’
HSE oscillator critical gm formula.
– Clarified formula
Updated Table 35: HSI oscillator characteristics.
Removed ‘RAM and hardware registers’
Removed Table 29: RAM and hardware registers.
Updated Table 37: Flash program memory/data EEPROM memory.
Added Table 38: Flash program memory
Added Table 39: Data memory.
Updated Table 40: I/O static characteristics
Updated Table 41: NRST pin characteristics
Updated Table 42: TIM 1, 2, 3, and 4 electrical specifications
Section 10.3.9: SPI interface
Changed title from “SPI serial peripheral interface“
Updated Table 43: SPI characteristics.
Figure 39: SPI timing diagram in slave mode and with CPHA = 0
– Changed title
– Added footnote 1.
Figure 40: SPI timing diagram in slave mode and with CPHA = 1
– Changed title
Updated Table 45: ADC characteristics.
Updated Figure 42: Typical application with ADC and added legend.
Removed Table 36: ADC accuracy for VDDA = 3.3 V
Updated Table 46: ADC accuracy for VDDA = 5 V
Updated Table 48: EMI data
Updated Table 50: Electrical sensitivities
Added Section : In order to meet environmental requirements, ST
offers these devices in different grades of ECOPACK® packages,
depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at:
www.st.com. ECOPACK® is an ST trademark..
Figure 45: LQFP 64-pin low profile quad flat package (10 x 10)
– Deleted footnote
Updated Figure 52: Ordering information scheme(1).
Added Chapter 13: STM8 development tools.
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Revision history
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Table 57.
Document revision history (continued)
Date
Revision
22-Oct-2009
Rev 5
Updated Table 1: Device summary:
– Added STM8AF5178, STM8AF519A and STM8AF619A.
Rev 6
Updated title on cover page.
Modified cover page header to clarify the part numbers covered by
the datasheets. Updated Note 1 below Table 1: Device summary to
add ‘P’ order codes.
Changed definition of ‘P’ order codes.
‘Q’ order codes (FASTROM and EEPROM) removed.
Content of Section 5: Product overview reorganized. Table 13:
STM8A microcontroller family pin description: updated PD7/TLI
alternate function, removed caution note for PD6/ LINUART_RX, and
added Note 1 to PA1/OSCIN.
Renamed Section 7 Memory and register map, and content merged
with section 9. Register map. Updated Figure 7: Register and
memory map.
Renamed BL_EN and NBL_EN, BL and NBL, respectively, in
Table 20: Option bytes.
Updated AFR4 definition in Table 21: Option byte description.Added
CEXT in Table 26: General operating conditions, and Section 10.3.1:
VCAP external capacitor.
Update tVDD in Table 27: Operating conditions at power-up/powerdown.
Moved Table 32: Typical peripheral current consumption VDD = 5.0 V
to Section : Current consumption for on-chip peripherals.
Removed VESD(MM) from Table 49: ESD absolute maximum ratings.
Updated Section 12: Ordering information to the devices supported
by the datasheet.
Updated Section 13: STM8 development tools.
Rev 7
Added STM8AF5168 and STM8AF518A part number in Figure 4,
and STM8AF618A in Figure 5. Added STM8AF52xx, STM8AF6269,
STM8AF628x, and STM8AF62Ax.
Updated D temperature range to -40 to 150°C.
Updated number of I/Os on cover page.
Added Table 25: Operating lifetime.
Restored VESD(MM) from Table 49: ESD absolute maximum ratings.
Table 26: General operating conditions: updated VCAP information.
ESL parameter, and range D maximum junction temperature (TJ).
Added STM8AF52xx and STM8AF62xx, and Note 3 in Section 12:
Ordering information.
Updated Section 13: STM8 development tools: added Table 54:
Product evolution summary, and split the beCAN time triggered
communication mode limitation into Section 13.7.3 and
Section 13.7.4.
13-Apr-2010
08-Jul-2010
106/110
Changes
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Table 57.
Revision history
Document revision history (continued)
Date
Revision
Changes
Modified references to reference manual, and Flash programming
manual in the whole document.
Added reference to AEC Q100 standard on cover page.
Renamed timer types as follows:
– Auto-reload timer to general purpose timer
– Multipurpose timer to advanced control timer
– System timer to basic timer
Introduced concept of high density Flash program memory.
Updated number of I/Os for devices in 80-, 64-, and 48-pin packages
in Table 2: STM8AF52xx product line-up with CAN, Table 3:
STM8AF62xx product line-up without CAN, Table 4:
STM8AF/H/P51xx product line-up with CAN, and Table 5:
STM8AF/H/P61xx product line-up without CAN.
Added TMU brief description in Section 5.4: Flash program and data
EEPROM, updated TMU_MAXATT description in Table 21: Option
byte description, and TMU_MAWATT reset value in Table 20: Option
bytes.
3&-Jan-2011
Rev 8
Updated clock sources in clock controller features (Section 5.5.1).
Added Table 7: Peripheral clock gating bits (CLK_PCKENR2) in
Section 5.5.6.
Added calibration using TIM3 in Section 5.7.2: Auto-wakeup counter.
Added Table 10: ADC naming and Table 11: Communication
peripheral naming correspondence.
Updated SPI data rate to fMASTER/2 in Section 5.9.3: Serial
peripheral interface (SPI).
Added reset state in Table 12: Legend/abbreviation for the pin
description table.
Table 13: STM8A microcontroller family pin description: modified
Note 2, added Note 3 related to PD1/SWIM, corrected wpu input for
PE1 and PE2, and renamed TIMn_CCx and TIMn_NCCx to
TIMn_CHx and TIMn_CHxN, respectively.
Section 7.2: Register map: Removed CAN register CLK_CANCCR.
Removed I2C_PECR register.
Added Note 1 for Px_IDR registers in Table 15: I/O port hardware
register map. Updated register reset values for Px_IDR and PD_CR1
registers.
Replaced tables describing register maps and reset values for nonvolatile memory, global configuration, reset status, TMU, clock
controller, interrupt controller, timers, communication interfaces, and
ADC, by Table 16: General hardware register map. Added debug
module register map.
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Revision history
STM8AF52/62xx, STM8AF51/61xx
Table 57.
Document revision history (continued)
Date
3&-Jan-2011
18-Jul-2012
108/110
Revision
Changes
Rev 8
(continued)
Renamed Fast Active Halt mode to Active-halt mode with regulator
on, and Slow Active Halt mode to Active-halt mode with regulator off,
updated Section 5.6: Low-power operating modes, and Table 29:
Total current consumption in Halt and Active-halt modes. General
conditions for VDD applied. TA = -40 °C to 55 °C unless otherwise
stated. IDD(FAH) and IDD(SAH) renamed IDD(AH); tWU(FAH) and tWU(SAH)
renamed tWU(AH).
Removed note 1 in Table 26: General operating conditions, and note
1 below Figure 10: fCPUmax versus VDD.
Removed note 3 in Table 28: Total current consumption in Run, Wait
and Slow mode. General conditions for VDD apply, TA = -40 °C to
150 °C.
Removed note 2 in Table 33: HSE external clock characteristics and
Table 37: Flash program memory/data EEPROM memory.
Removed note 1 in Table 39: Data memory. Modified TWE maximum
value in Table 38: Flash program memory and Table 39: Data
memory.
Added tIFP(NRST) and renamed VF(NRST) tIFP in Table 41: NRST pin
characteristics.
Added recommendation concerning NRST pin level, and power
consumption sensitive applications, above Figure 38:
Recommended reset pin protection, and updated external capacitor
value.
Update Note 1 in Table 42: TIM 1, 2, 3, and 4 electrical
specifications.
Updated Note 1 in Table 43: SPI characteristics.
Moved know limitations to separate errata sheet.
Added “not recommended for new design” note to device family 51,
memory size 7 and 9, and temperature range B, in Figure 52:
Ordering information scheme(1).
Added Raisonance compiler in Section 13.2: Software tools.
Rev 9
Updated wildcards of document part numbers.
Added VFQFPN package.
Added STM8AF62A6 part number.
Table 1: Device summary: updated footnote 1 and added footnote 2.
Table 2: STM8AF52xx product line-up with CAN and Table 3:
STM8AF62xx product line-up without CAN: added “P” version for all
order codes; updated size of data EEPROM for 64K devices to 2K
instead of 1.5K; updated RAM.
Figure 1: STM8A block diagram: updated POR, BOR and WDG;
removed PDR; added legend.
Section 5.4: Flash program and data EEPROM: removed
nonrelevant bullet points and added a sentence about the factory
programme.
Added Table 6: Peripheral clock gating bits (CLK_PCKENR1) and
updated Table 7: Peripheral clock gating bits (CLK_PCKENR2).
ADC features: updated ADC input range.
Table 14: Memory model 128K: updated RAM size, RAM end
addresses, and stack roll-over addresses; updated footnote 1.
Doc ID 14395 Rev 9
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Table 57.
Revision history
Document revision history (continued)
Date
18-Jul-2012
Revision
Changes
Rev 9
(continued)
Table 20: Option bytes: updated factory default setting for NOPT17;
updated footnote 1.
Table 22: Voltage characteristics: updated VDDX - VDD to VDDX - VSS.
Table 26: General operating conditions: updated VCAP.
Table 28: Total current consumption in Run, Wait and Slow mode.
General conditions for VDD apply, TA = -40 °C to 150 °C: updated
conditions for IDD(RUN).
Table 40: I/O static characteristics: added new condition and new
max values for rise and fall time; updated footnote 2.
Section 10.3.7: Reset pin characteristics: updated text below
Figure 37: Typical NRST pull-up current Ipu vs VDD.
Figure 38: Recommended reset pin protection: updated unit of
capacitor.
Table 43: SPI characteristics: updated SCK high and low time
conditions and values.
Figure 41: SPI timing diagram - master mode: replaced ‘SCK input’
signals with ‘SCK output’ signals.
Updated Table 52: LQFP 80-pin low profile quad flat package
mechanical data, Table 53: LQFP 64-pin low profile quad flat
package mechanical data, Table 54: LQFP 48-pin low profile quad
flat package mechanical data, Table 55: LQFP 32-pin low profile
quad flat package mechanical data, and Table 56: VFQFPN 32-lead
very thin fine pitch quad flat no-lead package mechanical data.
Replaced Figure 45: LQFP 64-pin low profile quad flat package (10 x
10), Figure 47: LQFP 48-pin low profile quad flat package (7 x 7),
and Figure 49: LQFP 32-pin low profile quad flat package (7 x 7).
Added Figure 46: LQFP 64-pin recommended footprint, Figure 48:
LQFP 48-pin recommended footprint, and Figure 50: LQFP 32-pin
recommended footprint.
Updated Figure 51: VFQFPN 32-lead very thin fine pitch quad flat
no-lead package (5 x 5).
Updated Figure 52: Ordering information scheme(1).
Section 13.2.2: C and assembly toolchains: added www.iar.com.
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STM8AF52/62xx, STM8AF51/61xx
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