ETC STP2200ABGA

STP2200ABGA
July 1997
USC
Uniprocessor System Controller
DATA SHEET
DESCRIPTION
The Uniprocessor System Controller (USC) has a DRAM memory controller and functions to regulate the
flow of requests and data on the UPA bus. It also controls the resets going to all UPA clients.
Features
Benefits
• Controls up to eight standard SS-10/SS-20-type DRAM
SIMMs
• Standard workstation memory
• Supports various memory SIMM organizations: 16 MB, 64
MB, and 256 MB as well as dual-stacked 128-MB SIMMs
• Flexibility
• Controls and generates a number of resets for the system
• High integration
• Programmed via a standard 8-bit asynchronous interface
(EBus)
• Allows design of low-cost, low-chip-count embedded
systems
• JTAG interface allows full chip scan
• Ease of design and testability
• 225-pin ABGA package
• Low cost
The USC is used as the system controller of a complete Uniprocessor UltraSPARC system.
Note: Instead of using the U2S, the USC can also be used with the UPA to PCI-bus; I/O interface
controller (U2P)
UPA Devices
Abbreviations
Part Number
Description
USC
SC_UP
STP 2200ABGA
Uniprocessor System Controller
RIC
RISC
STP2210QFP
Reset/Interrupt/Clock Controller
U2S
SYSIO
STP2220ABGA
UPA to SBus I/O interface controller
U2P
Psycho
STP2222ABGA
UPA to PCI bus I/O Interface controller
XBI
BMX
STP2230SOP
Crossbar Data Path
Note: This data sheet refers to the UPA to System I/O interface. The UPA to PCI bus Interface controller
(U2P) can be substituted where U2S appears.
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Uniprocessor System Controller
BLOCK AND TYPICAL APPLICATION DIAGRAMS
Chip Boundary
UPA_ADDRBUS0[34:0]
MEMADDR[12:0]
UPA_ADR0_PAR0
RAS[3:0]
UPA_ADDR0_VAL0[1:0]
Memory
Controller
UPA_SC_REQ0
UPA_REQIN0[1:0]
UPA_ADDRBUS1[28:0]
CAS[3:0]
WE
MRB_CTRL[1:0]
Port Interface
MWB_CTRL[1:0]
UPA_ADDR1_VAL1
UPA_PREPLY0[4:0]
UPA_PREPLY1[4:0]
BMX_CMD[3:0] x2
UPA_PREPLY2[4:0]
UPA_SREPLY0[4:0]
UPA_SREPLY1[4:0]
Data Path
Scheduler
SYS_RESET
UPA_SREPLY2[4:0]
UPA_ECC_VAL_0
X_BUTTON_RESET
UPA_DATA_STALL0
P_BUTTON_RESET
UPA_ECC_VAL_1
UPA_DATA_STALL1
UPA_RESET0
UPA_RESET1
UPA_XIR
EBUS_CS
EBus Interface
JTAG_TCK
JTAG_TMS
EBUS_RD
EBUS_WR
JTAG
JTAG_TDI
JTAG_TDO
EBUS_RDY
EBUS_ADDR[2:0]
JTAG_TRST
EBUS_DATA[7:0]
CLK +
CLK –
Clock/PLL
PLL_BYPASS
Figure 1. USC Block Diagram
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July 1997
USC
Uniprocessor System Controller
UPA_ADDRBUS1
STP2200ABGA
UPA_64S
64
UPA_ADDRBUS0
STP2220ABGA
UPA-to-SBus Interface (U2S)
or
STP2xxxABGA
UPA-to-PCI Interface (U2P)
72
CPU
72
I/O Data Bus
144
Processor Data Bus
STP2200ABGA
Uniprocessor
System Controller
(USC)
BMX_CMD0[3:0]
BMX_CMD1[3:0]
MRB_CTRL
MWB_CTRL
STP2230SOP
Crossbar Switch Array (18)
(XB1)
288
Memory Data Bus
144
144
MEMADDR[12:0]
RAS[3:0]
CAS[3:0]
WE
Memory SIMMs
Figure 2. USC Typical Application Diagram
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SIGNAL DESCRIPTIONS
UPA Interface Signals
Signal
I/O
UPA_ADDRBUS0[34:0]
I/O
Address bus 0 (processor/U2S)
Description
UPA_ADR0_PAR
I/O
Parity for address bus 0
UPA_ADDR0_VAL[1:0]
I/O
[0] = processor, [1] = U2S
UPA_SC_REQ0
O
USC request for address bus 0
UPA_REQIN0[1:0]
I
Client address bus 0 arbitration requests: [0] = processor, [1] = U2S
UPA_ADDRBUS1[28:0]
O
Address bus for UPA64S
UPA_ADDR1_VAL1
O
Address valid signal for UPA64S
UPA_SREPLY0_[4:0]
O
S_Reply for processor
UPA_SREPLY1_[4:0]
O
S_Reply for U2S
UPA_SREPLY2_[2:0]
O
S_Reply for UPA64S
UPA_PREPLY0_[4:0]
I
P_Reply from processor
UPA_PREPLY1_[4:0]
I
P_Reply from U2S
UPA_PREPLY2_[1:0]
I
P_Reply from UPA64S
UPA_RESET0
O
Reset for processor, tied to the U2S’s UPA_ARB_RESET
UPA_RESET1
O
Reset for U2S
UPA_XIR
O
XIR reset for processor only
UPA_ECC_VAL_0
O
ECC valid for processor
UPA_ECC_VAL_1
O
ECC valid for U2S
UPA_DATA_STALL0
O
Stall data to processor
UPA_DATA_STALL1
O
Stall data to U2S
Memory Interface Signals
Signal
I/O
Description
MEMADDR[12:0]
O
Row/column address
RAS[3:0]
O
RAS per SIMM pair
CAS[3:0]
O
CAS (four copies)
WE
O
Write enable
Crossbar Interface Signals
Signal
Type
Description
BMX_CMD0[3:0]
O
Command to XB1 crossbar array of 18 devices
MRB_CTRL0
O
Fill the XB1 read buffer
MWB_CTRL0
O
Drain the XB1 write buffer
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STP2200ABGA
Crossbar Interface Signals
Signal
Type
Description
BMX_CMD1[3:0]
O
Duplicate of BMX_CMD0[3:0]
MRB_CTRL1
O
Duplicate of MRB_CTRL0
MWB_CTRL1
O
Duplicate of MWB_CTRL0
EBus Signals
Signal
Type
EBUS_DATA[7:0]
Condition
Description
I/O
5-V tolerant
Data in and data out pins - 3.3 volt output level
EBUS_CS
I
5-V tolerant
Chip select for USC on the EBus
EBUS_ADDR[2:0]
I
5-V tolerant
EBus address
EBUS_RDY
O
EBUS_WR
I
5-V tolerant
Indicates write on EBus
EBUS_RD
I
5-V tolerant
Indicates read on EBus
EBus ready to the STP2001 SLAVIO- 3.3 volt output level
Miscellaneous Signals
Signal
Type
Condition
Description
CLK+
I
PECL
System clock (differential)
CLK–
I
PECL
System clock (differential)
SYS_RESET
I
5-V tolerant
Power-on reset; pulldown
P_BUTTON_RESET
I
5-V tolerant
POR button reset
X_BUTTON_RESET
I
5-V tolerant
XIR button reset
PLL_BYPASS
I
JTAG_TDI
I
JTAG_TDO
O
JTAG_TCK
Bypass internal PLL
5-V tolerant
Test data input
I
5-V tolerant
Scan clock
JTAG_TMS
I
5-V tolerant
Test mode select; pullup
JTAG_TRST
I
5-V tolerant
Reset TAP controller; pullup
Test data output- 3.3 volt output level
DEBUG[3:0]
O
Debug pins
PM_OUT
O
Process monitor output
Power and Ground
Signal
Description
VDD
+3.3 V
VSS
Ground
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Uniprocessor System Controller
STP2200ABGA
Power and Ground
Signal
Description
PLL_VDD
Power for PLL
PLL_GND
Ground for PLL
VCC
5-V reference for 5-V tolerant inputs
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Uniprocessor System Controller
STP2200ABGA
TECHNICAL OVERVIEW
The USC implements three UPA ports on two address buses. It has a programmable memory controller and
an EBus interface. Addresses flow through the USC. Data flows through the crossbar switches.
UPA Port Interface (PIF)
The PIF is responsible for receiving UPA packets, decoding their destinations, and forwarding the packets to
their proper destinations. The PIF also receives all P_Replys from UPA clients.
UPA address bus 0 has two clients: the processor and U2S (UPA-to-SBus Interface), or U2P (UPA-to-PCI Interface). The PIF controls the arbitration on UPA address bus 0, for its two clients and itself. The two other
masters on this bus are the processor and one of the system I/O devices. The PIF arbitration algorithm is
described in the USC User Manual.
Noncached transactions are typically forwarded to a system I/O chip. Cached transactions are typically forwarded to the memory controller. The PIF maintains data coherency in the system between the processor
cache, main memory, and the U2S merge buffer.
The UPA address bus 1 supports a single UPA64S device. This address bus is output only on the USC (for
example: unidirectional), and the USC is always the master. This interface is typically used for a graphic slave
device. The PIF will only generate and receive truncated P_Reply and S_Reply packets going to and coming
from the UPA64s device.
The PIF contains three sets of the following registers (one for each UPA port, processor, U2S, UPA 64S device):
• SC_Port_Config registers
• SC_Port_Status registers
UPA Data Path Scheduler (DPS)
The DPS is responsible for regulating the flow of data throughout the system. It generates the following:
•
•
•
•
STP2230SOP (XB1/BMX) crossbar switch commands;
S_Replys for all clients;
UPA_DATA_STALL signals;
UPA_ECC_VAL signals.
DPS contains no software-visible registers.
Memory Controller (MC)
The MC is responsible for controlling the SIMMs. It performs the following functions:
•
•
•
•
Generates timing for read, write, and refresh;
Converts the physical address in the UPA packet into row and column addresses;
Maintains the refresh timer;
Controls loading and unloading of data from the XB1 read and write buffers.
The PIF forwards memory requests to the MC. The MC communicates with the DPS to schedule delivery of
data.
The MC contains the following registers:
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USC
Uniprocessor System Controller
• MC_Control 0; and
• MC_Control 1
These registers are described in further detail in the USC User Guide.
EBus Interface (EB)
The EB implements an interface to EBus, an asynchronous 8-bit interface controlled by the STP2001 Slave I/O
Controller (SLAVIO). Since the USC contains no UPA data path, all reading and writing of internal registers
has to take place via EBus. Since all internal registers are 32 bits wide, the EB has to perform packing and
unpacking.
The EB block implements reset logic and contains a number of global registers.
• SC_Control register for controlling resets and logging reset status;
• SC_ID register, which contains the USC’s JEDEC ID number, implementation and version numbers, and
the number of UPA ports that the chip supports;
• Performance counters: SC_Perf_Ctrl, SC_Perf0, and SC_Perf1. These counters can be configured to count
various events for performance analysis.
Clock and PLL
The USC will operate at a maximum frequency of 100 MHz (10 nanoseconds cycle time). It is a completely
synchronous, edge-triggered, register-based design which uses only the rising edge of the clock to update the
flip-flops.
The chip also contains a phase-locked loop (PLL) to remove the skew introduced by the internal clock distribution network. This improves I/O timing.
JTAG Interface
The USC provides a JTAG interface for full chip scan which is used only for ATPG and in-system interconnect
testing. The USC’s boundary is shadowed to allow for board-level test.
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Uniprocessor System Controller
STP2200ABGA
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings [1]
Symbol
Parameter
Min
Max
Units
V
VDD
DC supply voltage
0
4.1
VCC
DC reference voltage
0
6.0
V
VIN
Input voltage (any pin)
VSS-0.3
VDD + 0.3
V
PD
Continuous power dissipation
2.5
W
TSTG
Storage temperature range
-40
125
°C
1. Operation of the device at values in excess of those listed above will result in degradation or destruction of the device. All voltages
are defined with respect to ground. Functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
Recommended Operating Conditions
Symbol
Parameter
Min
Typ
Max
Units
3.15
3.3
3.45
V
5.0
5.25
V
VDD
DC supply voltage
VCC
5V reference voltage
VIN
Input voltage
VDD + 0.3
V
TC
Case temperature
70
°C
TJ
Operating junction temperature
105
°C
VSS-0.3
Capacitance [1]
Max
Units
CIN
Symbol
Input capacitance
Parameter
Condition
10
pF
COUT
Output capacitance
10
pF
CIO
I/O capacitance
15
pF
1. The parameter values are not tested, they are provided from simulation.
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STP2200ABGA
=
DC Characteristics
Symbol
Parameter
Conditions
Min
Max
Units
0.8
V
VIL
Input low voltage
VIH
Input high voltage
VIL
Input low voltage, CLK + / –
PECL inputs
VDD-1.81
VDD-1.475
V
VIH
Input high voltage, CLK + / –
PECL inputs
VDD-1.165
VDD-0.88
V
IIN
Input current
10
µA
VOL
Output low voltage
leakage current only
VOH
Output high voltage
leakage current only
IOZ
High Z leakage current
10
µA
IDD
Supply current
758
mA
PD
Power dissipation
2500
mW
10
2.0
V
0.4
2.4
V
V
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STP2200ABGA
AC CHARACTERISTICS
Nearly all inputs and outputs are registered and are referenced to the PECL differential input clock (CLK+
and CLK–). This clock input controls an on-board PLL. These signals are clocked by the rising edge of CLK+
at the crossover between CLK+ and CLK– (where both signals are at the same voltage). All inputs are applied
with a rise and fall time of 1.0 nanosecond (ns).
The JTAG signals, are referenced to JTAG_TCK. They are asynchronous signals with respect to CLK+/CLK–.
The following signals are asynchronous to CLK + and CLK – and the JTAG clock. They include resets and the
EBus Interface signals:
EBUS_ADDR[2:0]
EBUS_CS
EBUS_RD
EBUS_WR
EBUS_DATA[7:0]
P_RESET
X_RESET
SYS_RESET
JTAG_TRST
AC Characteristics, UPA_CLK+ / UPA_CLK –
-83
Parameter
Signal Name
Condition
-100
Min
Max
83.3
Min
Max
Units
40
100.0
MHz
tCYCLE
CLK+ /CLK–
40.0
tWH
CLK+ /CLK–
5.4
tWL
CLK+ /CLK–
tE
CLK+ /CLK–
Rising
600
600
ps
tE
CLK– /CLK–
Falling
600
600
ps
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4.4
5.4
ns
4.4
ns
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STP2200ABGA
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Uniprocessor System Controller
AC Characteristics, Signals Referenced to Rising Edge of UPA_CLK
-83
Parameter
Signal Name
Condition
Min
-100
Max
Min
Max
Units
tSU
UPA signals
2.5
3.0
ns
tH
UPA signals
0.5
0.5
ns
tCO
UPA signals
tVO
UPA signals
tCO
BMX_CMD0[3:0]
70 pF
6.1
4.1
ns
tCO
BMX_CMD1[3:0]
70 pF
6.1
4.1
ns
tCO
MRB_CTRL[1:0]
70 pF
6.1
4.1
ns
tCO
MWB_CTRL[1:0]
70 pF
6.1
4.1
ns
tCO
MEMADDR[12:0]
70 pF
6.1
4.1
ns
tCO
RAS[3:0]
70 pF
6.1
4.1
ns
tCO
CAS[3:0]
70 pF
6.1
4.1
ns
tCO
WE
70 pF
6.1
4.1
ns
tCO
EBUS_RDY
70 pF
11.9
11.9
ns
70 pF
6.1
0.5
4.1
0.5
ns
ns
AC Characteristics, JTAG_TCK and Signals Referenced to JTAG_TCK
-83
Parameter
Signal Name
Condition
Min
-100
Max
Min
Max
Units
MHz
JTAG_TCK
tWH
JTAG_TCK
tWL
JTAG_TCK
tE
JTAG_TCK
Rising
20.0
tE
JTAG_TCK
Falling
20.0
tSU
JTAG_TDI
Wrt rising edge of JTAG_TCK
2.5
2.5
ns
tH
JTAG_TDI
Wrt rising edge of JTAG_TCK
6.5
6.5
ns
tSU
JTAG_TMS
Wrt rising edge of JTAG_TCK
2.5
2.5
ns
tH
JTAG_TMS
Wrt rising edge of JTAG_TCK
6.5
6.5
tCO
JTAG_TDO
70 pF; Wrt falling edge of
JTAG_TCK
12
10.0
10.0
tCYCLE
30.0
70.0
30.0
70.0
ns
30.0
70.0
30.0
70.0
ns
20.0
ns
20.0
ns
16.0
ns
16.0
ns
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Signal Timing Definition
tCYCLE
tWH
tE(RISE)
tWL
3.0V
CLK+
0.0V
tE(FALL)
3.0V
CLK–
0.0V
tsu
tH
Input
VDD/2
tço
tvo
1.5V
Output
Figure 3. Signal Timing Definition
PLL Specifications
PLL and Clock Distribution Circuitry
The schematic below shows the PLL scheme inside the USC.
PLL1XSF
BIED03T
FBIN
CLK+
P
CLK–
N
PLL_BYPASS
FBOUT
Z
Clock
MUX
FBCLK1X
REFCLK
CLK1X
BYPASS
Clock
Buffers
Internal Clock
JTAG_TCK
Clock select from TAP controller
Figure 4. PLL and Clock Distribution Schematic
Power Supply Filter
The PLL power should be filtered with the following part or equivalent to reduce the system noise injected
into the PLL by the system: TDK ACF321825 EMI/RFI filter.
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TIMING DIAGRAMS
Bus Timings
All data transfers have a dead cycle between them, except for back-to-back single writes from the processor to
a graphics slave device.
The following diagrams show some best-case response timing for the USC.
Figure 5 shows the best-case timing for forwarding a PRequest on address bus 0.
UPA_ADDRBUS0
PReq0
PReq0
PReq1
PReq1
UPA_SC_REQ0
Figure 5. Best-Case PRequest-to-PRequest Timing (ABus0 to ABus0)
Figure 6 shows the best-case timing for sending an SRequest that is triggered by a PRequest.
UPA_ADDRBUS0
PReq0
PReq1
SReq0
SReq1
UPA_SC_REQ0
Figure 6. Best-Case PRequest-to-SRequest Timing (ABus0 to ABus0)
Since the USC is always the master of address bus 1 and no arbitration is ever required on that bus, the time it
takes for the USC to forward a packet from address bus 0 to address bus 1 is faster than between two devices
on address bus 0, as shown in Figure 7.
UPA_ADDRBUS0
UPA_ADDRBUS1
PReq0
PReq1
SReq0
SReq1
Figure 7. Best-Case PRequest-to-SRequest Timing (ABus0 to ABus1)
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STP2200ABGA
Figure 8 and Figure 9 show the best-case timing for non-cacheable single and block read from U2S referenced
to the time the P_Reply is issued from the slave. The timing for non-cacheable read from the fast frame buffer
(FFB) (UPA64S) is the same, except that it is referenced to a single-cycle P_RASB instead of the two-cycle
P_RAS/P_RAB.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
18
19
P_RAS
UPA_PREPLY
UPA_SREPLY
to master
S_SRS
UPA_SREPLY
to slave
S_RAS
X_IPS
BMX_CMD
DATA_STALL
UPA_DATA 64
UPA_DATA 128
Figure 8. Best-Case Timing for Noncached Single Read, UPA64 -> UPA128
0
UPA_PREPLY
UPA_SREPLY
to master
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
P_RAB
S_SRB
UPA_SREPLY
to slave
BMX_CMD
S_RBU
X_IPB
DATA_STALL
(CPU)
UPA_DATA 64
UPA_DATA 128
Figure 9. Best-Case Timing for Noncached Block Read, UPA64 -> UPA128
Figure 10 and Figure 11 show the best-case timing for a non-cacheable single and block write to the U2S. A
non-cacheable write to the FFB has similar timing, except that the time it takes to forward the PRequest is
slightly less.
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0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
UPA_ADDRBUS0
UPA_SREPLY
to master
S_WAS
UPA_SREPLY
to slave
S_SWS
BMX_CMD
X_PIS
DATA_STALL
UPA_DATA 64
UPA_DATA 128
Figure 10. Best-Case Timing for Non-Cached Single Write, UPA128 -> UPA64
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
UPA_ADDRBUS0
UPA_SREPLY
to master
S_WAB
UPA_SREPLY
to slave
S_SWB
BMX_CMD
X_PIB
DATA_STALL
UPA_DATA 64
UPA_DATA 128
Figure 11. Best-Case Timing for Non-Cached Block Write, UPA128 -> UPA64
Figure 12 and Figure 13 show a U2S single and block read from the FFB, referenced to the P_Reply from the
FFB.
0
UPA_PREPLY
UPA_SREPLY
to master
UPA_SREPLY
to slave
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
P_RASB
S_RAS
S_SRS
BMX_CMD
DATA_STALL
UPA_DATA 64
UPA_DATA 128
Figure 12. Best-Case Timing for Non-Cached Single Read, UPA64 -> UPA64
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Uniprocessor System Controller
0
UPA_PREPLY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
STP2200ABGA
15
16
17
18
19
P_RASB
UPA_SREPLY
to master
S_RAB
UPA_SREPLY
to slave
S_SRB
BMX_CMD
DATA_STALL
UPA_DATA 64
UPA_DATA 128
Figure 13. Best-Case Timing for Noncached Block Read, UPA64 -> UPA64
Figure 14 and Figure 15 show the best-case timing for a U2S non-cacheable single and block write to FFB.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
18
19
UPA_ADDRBUS
BUS0
UPA_SREPLY
to master
BUS1
S_WAS
UPA_SREPLY
to slave
S_SWS
BMX_CMD
DATA_STALL
UPA_DATA 64
UPA_DATA 128
Figure 14. Best-Case Timing for Noncached Single Write, UPA64 -> UPA64
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
UPA_ADDRBUS
UPA_SREPLY
to master
UPA_SREPLY
to slave
BUS0
BUS1
S_WAB
S_SWB
BMX_CMD
DATA_STALL
UPA_DATA 64
UPA_DATA 128
Figure 15. Best-Case Timing for Noncached Block Write, UPA64 -> UPA64
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Figure 16 and Figure 17 show the nominal timing for a U2S non-cacheable single and block read from the
processor.
0
UPA_PREPLY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
18
19
P_RASB
UPA_SREPLY
to master
S_RAS
UPA_SREPLY
to slave
S_SRS
BMX_CMD
X_PIS
DATA_STALL
UPA_DATA 64
UPA_DATA 128
Figure 16. Best-Case Timing for Noncached Single Read, UPA128 -> UPA64
0
UPA_PREPLY
1
2
3
4
5
6
7
UPA_SREPLY
to master
UPA_SREPLY
to slave
BMX_CMD
8
9
10
11
12
13
14
15
16
17
P_RASB
S_RAB
S_SRB
X_PIB
DATA_STALL
UPA_DATA 64
UPA_DATA 128
Figure 17. Best-Case Timing for Noncached Block Read, UPA128 -> UPA64
Note: Timing diagrams for U2S non-cacheable single and block write to the processor are not shown
because such transactions are dropped by the USC.
Figure 18 shows the “fast path” timing for memory reads issued from the processor. Fast paths are characterized by row address valid one cycle earlier than that of normal paths. The fast path is only available for reads
issued from the processor’s master class 0. It is not available for writes or for any accesses from the U2S. Normal paths are used for all transactions that are not processor reads from memory, for example, DMA, memory
writes, etc. See Figure 22 and Figure 23 for a graphic representation of fast paths and normal paths. Fast path
is not implemented for processor writes because for processor transaction type P_WRI_REQ (described in the
UPA specification) we need to examine the IVA bit (state bit embedded in the transaction packet, as described
in the UPA specification) before launching the request to memory, and the IVA bit is in the second half of the
PRequest packet. P_WRB_REQ (described in the UPA specification) almost always follows a victimizing read,
and this can be overlapped with the read. Accesses from the U2S are less latency sensitive. Since the fast path
is very timing critical and adds additional complexity to the logic, it is not implemented for the U2S.
18
July 1997
USC
Uniprocessor System Controller
STP2200ABGA
)
UPA_ADDRBUS0
PReq0
PReq1
MEMADDR[12:0]
Row Address
RAS
Figure 18. Best-Case PRequest-to-Memory Request Timing, Read (Fast Path)
Figure 19 shows a read or write issued through the “normal path.”
UPA_ADDRBUS0
MEMADDR[12:0]
PReq0
PReq1
Row Address
RAS
Figure 19. Best-Case PRequest-to-Memory Request Timing (Normal Path)
July 1997
19
STP2200ABGA
20
USC
Uniprocessor System Controller
USC
Uniprocessor System Controller
RAS
STP2200ABGA
RP
RAS
CAS
Fixed at Two Clocks
Fixed at One Clock
Figure 21. Basic Refresh Timing
1. RAS is the minimum RAS timing.
2. RP is the RAS-precharge timing.
UPA-to-Memory Timing
Figure 22 and Figure 23 show the minimum time for a UPA memory request packet issued on the UPA address
bus pins to traverse the USC and appear on the USC’s memory outputs, assuming that the USC is idle.
UPA_ADDRBUS0
MEMADDR[12:0]
Row Address
RAS
Figure 22. Best-Case UPA-to-Memory Timing (Fast Path)
July 1997
21
USC
Uniprocessor System Controller
STP2200ABGA
UPA_ADDRBUS0
Row Address
MEMADDR[12:0]
RAS
Figure 23. Best-Case UPA-to-Memory Timing (Normal Path)
Note: Fast path timing is only applicable for memory reads issued from the processor. All other memory
accesses use the normal path.
Default Memory Timing
Figure 24 through Figure 28 show the default timing after power on. These are the slowest, most conservative
timings possible and are guaranteed to work at any frequency.
0
MEMADDR
1
2
Row
3
4
5
6
Column 0
7
8
9
10
11
12
13
14
15
16
17
18
19
Column 1
RAS
CAS
WE
MRB_CTRL
UPA_SREPLY
BMX_CMD
MEMDATA
UPA_DATA
UPA_DATA_STALL
Figure 24. Default Memory CPU Read Timing
22
July 1997
USC
Uniprocessor System Controller
0
1
2
3
MEMADDR
4
5
6
7
Row
8
9
10
11
12
Column 0
13
14
STP2200ABGA
15
16
17
18
19
Column 1
RAS High for Five Clocks
Before Next Transaction
RAS
CAS
WE
MRB_CTRL
UPA_SREPLY
BMX_CMD
UPA_DATA
(CPU)
MEMDATA
UPA_DATA_STALL
Figure 25. Default Memory CPU Write Timing
0
MEMADDR
1
2
Row
3
4
5
6
Column 0
7
8
9
10
11
12
13
14
15
16
17
18
19
Column 1
RAS
CAS
WE
MRB_CTRL
UPA_SREPLY
BMX_CMD
MEMDATA
UPA_DATA
UPA_DATA_STALL
Figure 26. Default Memory U2S Read Timing
July 1997
23
USC
Uniprocessor System Controller
STP2200ABGA
0
1
2
3
4
MEMADDR
5
6
7
8
9
Row
10
11
12
13
Column 0
14
15
16
17
18
19
18
19
Column 1
RAS
CAS
WE
MRB_CTRL
UPA_SREPLY
BMX_CMD
UPA_DATA
(U2S)
MEMDATA
UPA_DATA_STALL
Figure 27. Default Memory U2S Write Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
MEMADDR
RAS
CAS
WE
MWB_CTRL
MRB_CTRL
MEMDATA
Figure 28. Default Refresh Timing
24
July 1997
USC
Uniprocessor System Controller
STP2200ABGA
83.3 MHz (12 ns) Timings
0
1
2
3
4
Row
MEMADDR
5
6
7
8
9
Column 0
10
11
12
13
14
15
16
17
18
19
13
14
15
16
17
18
19
Column 1
RAS
CAS
WE
MRB_CTRL
UPA_SREPLY
BMX_CMD
MEMDATA
UPA_DATA
UPA_DATA_STALL
Figure 29. 83.3 MHz CPU Read Timing
0
MEMADDR
1
2
3
4
Row
5
6
7
8
9
Column 0
10
11
12
Column 1
RAS
CAS
WE
MWB_CTRL
UPA_SREPLY
BMX_CMD
UPA_DATA
(CPU)
MEMDATA
UPA_DATA_STALL
Figure 30. 83.3 MHz CPU Write Timing
July 1997
25
USC
Uniprocessor System Controller
STP2200ABGA
0
1
2
3
4
Row
MEMADDR
5
6
7
8
9
Column 0
10
11
12
13
14
15
16
17
18
19
Column 1
RAS
CAS
WE
MRB_CTRL
UPA_SREPLY
BMX_CMD
MEMDATA
UPA_DATA
UPA_DATA_STALL
Figure 31. 83.3 MHz U2S Read Timing
0
MEMADDR
1
2
3
4
5
Row
6
7
8
9
10
11
12
Column 0
13
14
15
16
17
18
19
Column 1
RAS
CAS
WE
MWB_CTRL
UPA_SREPLY
BMX_CMD
UPA_DATA
(U2S)
MEMDATA
UPA_DATA_STALL
Figure 32. 83.3 MHz U2S Write Timing
26
July 1997
USC
Uniprocessor System Controller
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
STP2200ABGA
15
16
17
18
19
MEMADDR
RAS
CAS
WE
MWB_CTRL
MRB_CTRL
MEMDATA
Figure 33. 83.3 MHz Refresh Timing
71.4 MHz (14 nanoseconds) Timings
0
MEMADDR
1
2
Row
3
4
5
Column 0
6
7
8
9
10
11
12
Column 1
13
14
15
16
17
18
19
Next Row
RAS
CAS
WE
MRB_CTRL
UPA_SREPLY
BMX_CMD
MEMDATA
UPA_DATA
UPA_DATA_STALL
Figure 34. 71.4 MHz CPU Read Timing
July 1997
27
USC
Uniprocessor System Controller
STP2200ABGA
0
1
2
MEMADDR
3
4
5
6
7
Row
8
9
10
Column 0
11
12
13
14
15
13
14
15
16
17
18
19
16
17
18
19
Column 1
RAS
CAS
WE
MWB_CTRL
UPA_SREPLY
BMX_CMD
UPA_DATA
(CPU)
MEMDATA
UPA_DATA_STALL
Figure 35. 71.4 MHz CPU Write Timing
0
MEMADDR
1
2
Row
3
4
5
Column 0
6
7
8
9
10
11
12
Column 1
Next Row
RAS
CAS
WE
MRB_CTRL
UPA_SREPLY
BMX_CMD
MEMDATA
UPA_DATA
UPA_DATA_STALL
Figure 36. 71.4 MHz U2S Read Timing
28
July 1997
USC
Uniprocessor System Controller
0
1
2
3
MEMADDR
4
5
6
7
8
9
Row
10
11
12
13
Column 0
14
STP2200ABGA
15
16
17
18
19
Column 1
RAS
CAS
WE
MWB_CTRL
UPA_SREPLY
BMX_CMD
UPA_DATA
(U2S)
MEMDATA
UPA_DATA_STALL
Figure 37. 71.4 MHz U2S Write Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
MEMADDR
RAS
CAS
WE
MWB_CTRL
MRB_CTRL
MEMDATA
Figure 38. 71.4 MHz Refresh Timing
July 1997
29
USC
Uniprocessor System Controller
STP2200ABGA
Minimum Timings
Figure 39 through Figure 43 show the absolute minimum timing that the memory controller is capable of
generating.
0
MEMADDR
1
2
3
Row
4
5
6
Column 0
7
8
9
10
11
12
Column 1
13
14
15
16
17
18
19
15
16
17
18
19
Next Row
RAS
CAS
WE
MWB_CTRL
UPA_SREPLY
BMX_CMD
MEMDATA
UPA_DATA
(CPU)
UPA_DATA_STALL
Figure 39. Minimum CPU Read Timing
0
MEMADDR
1
2
3
4
Row
5
6
7
8
Column 0
9
10
11
12
13
14
Column 1
RAS
CAS
WE
MWB_CTRL
UPA_SREPLY
BMX_CMD
UPA_DATA
(CPU)
MEMDATA
UPA_DATA_STALL
Figure 40. Minimum CPU Write Timing
30
July 1997
USC
Uniprocessor System Controller
0
MEMADDR
1
2
3
Row
4
5
6
Column 0
7
8
9
10
11
12
13
Column 1
14
STP2200ABGA
15
16
17
18
19
15
16
17
18
19
Next Row
RAS
CAS
WE
MRB_CTRL
UPA_SREPLY
BMX_CMD
MEMDATA
UPA_DATA
UPA_DATA_STALL
Figure 41. Minimum U2S Read Timing
0
MEMADDR
1
2
3
4
Row
5
6
7
8
9
10
11
12
Column 0
13
14
Column 1
RAS
CAS
WE
MWB_CTRL
UPA_SREPLY
BMX_CMD
UPA_DATA
(CPU)
MEMDATA
UPA_DATA_STALL
Figure 42. Minimum U2S Write Timing
July 1997
31
USC
Uniprocessor System Controller
STP2200ABGA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
MEMADDR
RAS
CAS
WE
MWB_CTRL
MRB_CTRL
MEMDATA
Figure 43. Minimum Refresh Timing
32
July 1997
USC
Uniprocessor System Controller
STP2200ABGA
EBus Timing
Figure 44 and Figure 45 show external timing for EBus accesses.
EBUS_CS
EBUS_ADDR[2:0]
EBUS_RD
EBUS_WR
EBUS_RDY
EBUS_DATA[7:0]
Figure 44. External EBus Read Timing
EBUS_CS
EBUS_ADDR[2:0]
EBUS_WR
EBUS_RD
EBUS_DATA[7:0]
EBUS_RDY
Figure 45. External EBus Write Timing
July 1997
33
USC
Uniprocessor System Controller
STP2200ABGA
PACKAGE INFORMATION
225-Pin Plastic Ball Grid Array (ABGA) Pin Assignments
Pin
A1
Signal Name
Pin
Signal Name
Pin
VSS
D1
VDD
G1
Signal Name
VSS
Pin
K1
Signal Name
Pin
Signal Name
DEBUG_2 [1]
N1
MEMADDR_5
MEMADDR_7
A2
UPA_PREPLY1_1
D2
BMX_CMD0_2
G2
WE
K2
MEMADDR_12
N2
A3
JTAG_TRST
D3
UPA_SREPLY0_0
G3
BMX_CMD1_0
K3
DEBUG_1 [1]
N3
MEMADDR_1
A4
VDD
D4
UPA_PREPLY1_4
G4
CAS2
K4
MEMADDR_10
N4
DEBUG_3 [1]
A5
JTAG_TDI
D5
UPA_PREPLY1_0
G5
VDD
K5
MEMADDR_4
N5
UPA_ADDRBUS0_31
A6
X_RESET
D6
PLL_BYPASS
G6
VSS
K6
UPA_ADR0_PAR0
N6
UPA_ADDRBUS0_24
A7
VSS
D7
CLK+
G7
VSS
K7
VSS
N7
UPA_ADDRBUS0_21
A8
PLL_VDD
D8
UPA_ECC_VAL_0
G8
VSS
K8
VSS
N8
UPA_ADDRBUS0_18
A9
VDD
D9
UPA_SREPLY1_1
G9
VSS
K9
VSS
N9
UPA_ADDRBUS0_17
A10
UPA_SREPLY1_2
D10
EBUS_RDY
G10 VSS
K10
UPA_ADDRBUS0_00
N10
UPA_ADDRBUS0_10
A11
UPA_SREPLY1_0
D11
EBUS_DATA_4
G11 VDD
K11
UPA_ADDRBUS1_27
N11
UPA_ADDRBUS0_06
A12
VSS
D12
EBUS_ADDR_0
G12 UPA_ADDRBUS1_05
K12
UPA_ADDRBUS1_19
N12
UPA_ADDRBUS0_05
A13
EBUS_RD
D13
UPA_ADDR1_VAL1
G13 UPA_ADDRBUS1_09
K13
UPA_ADDRBUS1_21
N13
UPA_REQIN0_1
A14
EBUS_DATA_6
D14
5V_REF
G14 UPA_ADDRBUS1_07
K14
UPA_ADDRBUS1_16
N14
UPA_ADDRBUS1_26
A15
VDD
D15
VSS
G15 VDD
K15
UPA_ADDRBUS1_14
N15
UPA_ADDRBUS1_23
B1
UPA_SREPLY0_1
E1
BMX_CMD0_1
H1
CAS0
L1
MEMADDR_11
P1
MEMADDR_2
B2
UPA_SREPLY0_4
E2
BMX_CMD1_1
H2
RAS3
L2
MEMADDR_9
P2
UPA_PREPLY0_4
B3
UPA_SREPLY0_3
E3
BMX_CMD0_3
H3
CAS1
L3
MEMADDR_6
P3
UPA_PREPLY0_3
B4
JTAG_TMS
E4
MRB_CTRL0
H4
DEBUG_0 [1]
L4
MEMADDR_0
P4
UPA_ADDRBUS0_34
B5
JTAG_TDO
E5
UPA_PREPLY1_3
H5
VDD
L5
UPA_PREPLY0_2
P5
UPA_ADDRBUS0_29
B6
UPA_DATA_STALL1
E6
P_RESET
H6
VSS
L6
UPA_ADDRBUS0_33
P6
UPA_ADDRBUS0_28
B7
PLL_VSS
E7
VDD
H7
VSS
L7
VDD
P7
UPA_ADDRBUS0_23
B8
UPA_DATA_STALL0
E8
VDD
H8
VSS
L8
VDD
P8
UPA_ADDRBUS0_20
B9
UPA_SREPLY1_4
E9
VDD
H9
VSS
L9
VDD
P9
UPA_ADDRBUS0_15
B10
UPA_RESET_1
E10
EBUS_CS
H10
VSS
L10
UPA_ADDRBUS0_04
P10
UPA_ADDRBUS0_13
B11
EBUS_WR
E11
EBUS_ADDR_1
H11
VDD
L11
UPA_ADDR0_VAL0_0
P11
UPA_ADDRBUS0_09
B12
UPA_RESET_0
E12
UPA_SREPLY2_1
H12
UPA_ADDRBUS1_13
L12
UPA_ADDRBUS1_22
P12
UPA_ADDRBUS0_07
B13
EBUS_DATA_1
E13
UPA_PREPLY2_1
H13
UPA_ADDRBUS1_12
L13
UPA_ADDRBUS1_24
P13
UPA_ADDRBUS0_01
B14
EBUS_DATA_3
E14
UPA_ADDRBUS1_00
H14
UPA_ADDRBUS1_08
L14
UPA_ADDRBUS1_20
P14
UPA_REQIN0_0
B15
EBUS_DATA_0
E15
UPA_ADDRBUS1_02
H15
UPA_ADDRBUS1_10
L15
UPA_ADDRBUS1_18
P15
UPA_SC_REQ0
C1
BMX_CMD1_3
F1
BMX_CMD0_0
J1
VDD
M1
VSS
R1
VDD
C2
MWB_CTRL0
F2
CAS3
J2
RAS1
M2
MEMADDR_8
R2
UPA_PREPLY0_1
C3
MRB_CTRL1
F3
BMX_CMD1_2
J3
RAS2
M3
MEMADDR_3
R3
UPA_ADDRBUS0_32
C4
UPA_PREPLY1_2
F4
MWB_CTRL1
J4
RAS0
M4
NC
R4
VSS
C5
JTAG_TCK
F5
UPA_SREPLY0_2
J5
VDD
M5
UPA_PREPLY0_0
R5
UPA_ADDRBUS0_27
C6
UPA_XIR
F6
PM_OUT
J6
VSS
M6
UPA_ADDRBUS0_30
R6
UPA_ADDRBUS0_25
C7
SYS_RESET
F7
VSS
J7
VSS
M7
UPA_ADDRBUS0_26
R7
VDD
C8
CLK–
F8
VSS
J8
VSS
M8
UPA_ADDRBUS0_22
R8
UPA_ADDRBUS0_19
C9
UPA_ECC_VAL_1
F9
VSS
J9
VSS
M9
UPA_ADDRBUS0_14
R9
VSS
C10
UPA_SREPLY1_3
F10
EBUS_DATA_2
J10
VSS
M10 UPA_ADDRBUS0_12
R10
UPA_ADDRBUS0_16
C11
EBUS_DATA_5
F11
UPA_SREPLY2_2
J11
VDD
M11 UPA_ADDRBUS0_03
R11
UPA_ADDRBUS0_11
C12
EBUS_DATA_7
F12
UPA_ADDRBUS1_01
J12
UPA_ADDRBUS1_15
M12 UPA_ADDR0_VAL0_1
R12
VDD
C13
EBUS_ADDR_2
F13
UPA_ADDRBUS1_06
J13
UPA_ADDRBUS1_17
M13 UPA_ADDRBUS1_28
R13
UPA_ADDRBUS0_08
C14
UPA_SREPLY2_0
F14
UPA_ADDRBUS1_03
J14
UPA_ADDRBUS1_11
M14 UPA_ADDRBUS1_25
R14
UPA_ADDRBUS0_02
C15
UPA_PREPLY2_0
F15
UPA_ADDRBUS1_04
J15
VSS
M15 VDD
R15
VSS
1. DEBUG pins are used for internal debug only and are not used in a system implementation.
34
July 1997
USC
Uniprocessor System Controller
STP2200ABGA
225-Pin Plastic ABGA Package Dimensions
0.35
27.00 ± 0.10
Square
13.50 ± 0.10
TYP
-C0.60 ± 0.05
TYP
Seating Plane
12.00 ± 0.10
TYP
14 Spaces @ 1.50 = 21.00
3.00
TYP
3.00
TYP
24.00 ± 0.10
Square
C
1.73 ± 0.10
0.56 ± 0.06
15
14
13
12
14 Spaces @ 1.50 = 21.00
11
10
9
8
7
6
5
4
3
25°
Appro
x.
2
Position A1
Indicator
0.78 DIA
Approx.
(Gold plated)
1
0.15
C
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Solder ball grid
array coordinates
are for reference only
Notes:
1. Drawing is not to scale.
2. Unless otherwise specified, all dimensions are in millimeters. Nonlimited
dimensions other than size of raw material shall be held as follows when
expressed:
10-2 decimal places,
± 0.13 as angles,
10-3 decimal places
3. It is imperative that measures be taken during assembly, handling, etc. to
prevent the possibility of damage to devices by static electric discharge.
4. The flatness of the overmold surface in the center 10.16 mm DIA area, shall
be within 0.076 mm.
July 1997
35
STP2200ABGA
36
USC
Uniprocessor System Controller