Micrel, Inc. 2.5V/3.3V 1.5GHz PRECISION LVPECL PROGRAMMABLE DELAY WITH FINE TUNE CONTROL Precision Edge® ® SY89296U Precision Edge SY89296U FEATURES ■ Precision LVPECL programmable delay line ■ Guaranteed AC performance over temperature and voltage: • > 1.5GHz fMAX • < 160ps rise/fall times ■ Low jitter design: • < 10psPP total jitter • < 2psRMS cycle-to-cycle jitter • < 1psRMS random jitter ■ Programmable delay range: 3.2ns to 14.8ns in 10ps increments ■ Increased monotonicity over the MC100EP195 ■ ±10% of LSB INL ■ VBB output reference voltage ■ Parallel inputs accepts LVPECL or CMOS/LVTTL ■ 40ps/V fine tuning range ■ Low voltage operation: 2.5V ±5% and 3.3V ±10% ■ Industrial –40°C to +85°C temperature range ■ Available in 32-pin (5mm × 5mm) MLF® package or 32-pin TQFP package Precision Edge® DESCRIPTION The SY89296U is a programmable delay line that delays the input signal using a digital control signal. The delay can vary from 3.2ns to 14.8ns in 10ps increments. Further, the delay may be varied continuously in about 40ps range by setting the voltage at the FTUNE pin. In addition, the input signal is LVPECL, uses either a 2.5V ±5% or 3.3V ±10% power supply, and is guaranteed over the full industrial temperature range (–40°C to +85°C). The delay varies in discrete steps based on a control word. The control word is 10-bits long and controls the delay in 10ps increments. The eleventh bit is D[10] and is used to simultaneously cascade the SY89296U for a larger delay range. In addition, the input pins IN and /IN default to an equivalent low state when left floating. Further, for maximum flexibility, the control register interface accepts CMOS or TTL level signals. For applications that do not require an analog delay input, see the SY89295U. The SY89295U and SY89296U are part of Micrel’s high-speed, Precision Edge® product line. All support documentation can be found on Micrel’s website at www.micrel.com. APPLICATIONS ■ Clock de-skewing ■ Timing adjustments ■ Aperture centering Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-072706 [email protected] or (408) 955-1690 Rev.: D 1 Amendment: /0 Issue Date: July 2006 Precision Edge® SY89296U Micrel, Inc. PACKAGE/ORDERING INFORMATION D7 D6 D5 D4 GND D3 D2 D1 Ordering Information(1) 32 31 30 29 28 27 26 25 D8 D9 D10 IN /IN VBB VEF VCF 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 GND D0 VCC Q /Q VCC VCC FTUNE 17 Part Number Package Type Operating Range Package Marking Lead Finish SY89296UMI MLF-32 Industrial SY89296U Sn-Pb SY89296UMITR(2) MLF-32 Industrial SY89296U Sn-Pb T32-1 Industrial SY89296U Sn-Pb SY89296UTI SY89296UTITR(2) T32-1 Industrial SY89296U Sn-Pb MLF-32 Industrial SY89296U with Pb-Free bar-line indicator Pb-Free NiPdAu SY89296UMGTR(2, 3) MLF-32 Industrial SY89296U with Pb-Free bar-line indicator Pb-Free NiPdAu SY89296UTG(3) T32-1 Industrial SY89296U with Pb-Free bar-line indicator Pb-Free NiPdAu SY89296UTGTR(2, 3) T32-1 Industrial SY89296U with Pb-Free bar-line indicator Pb-Free NiPdAu SY89296UMG(3) GND LEN SETMIN SETMAX VCC /CASCADE CASCADE /EN 9 10 11 12 13 14 15 16 D7 D6 D5 D4 GND D3 D2 D1 32-Pin MLF™ (MLF-32) 32 31 30 29 28 27 26 25 D8 D9 D10 IN /IN VBB VEF VCF 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 GND D0 VCC Q /Q VCC VCC FTUNE Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs. GND LEN SETMIN SETMAX VCC /CASCADE CASCADE /EN 9 10 11 12 13 14 15 16 32-Pin TQFP (T32-1) TRUTH TABLES Input/Output Digital Control Latch Inputs Outputs LEN Latch Action IN /IN OUT /OUT 0 Pass Through D[10:0] 0 1 0 1 1 Latched D[10:0] 1 0 1 0 Input Enable /EN Q, /Q 0 IN, /IN Delayed 1 Latched D[10:0] M9999-072706 [email protected] or (408) 955-1690 2 Precision Edge® SY89296U Micrel, Inc. FUNCTIONAL BLOCK DIAGRAM IN 0 0 0 0 /IN 1 1 1 1 512 GD /EN 16 GD 256 GD 128 GD 64 GD 0 0 0 1 1 1 1 4 GD 2 GD 1 32 GD 0 8 GD 0 0 1 1 GD FTUNE D[9:0] LEN SETMIN 10-bit Latch SETMAX 0 Q 1 /Q 1 GD D[10] CASCADE Latch /CASCADE VBB VCF VEF M9999-072706 [email protected] or (408) 955-1690 3 Precision Edge® SY89296U Micrel, Inc. PIN DESCRIPTION Pin Number Pin Name Pin Function 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 D[9:0] CMOS, ECL, or TTL Control Bits: These control signals adjust the delay from IN to Q. See “AC Electrical Characteristics” for delay values. In addition, see “Interface Applications” section which illustrates the proper interfacing techniques for different logic standards. D[9:0] contains pull-downs and defaults LOW when left floating. D0 (LSB), and D9 (MSB). See “Typical Operating Characteristics” for delay information. 3 D10 CMOS, ECL, or TTL Control Bit: This bit is used to cascade devices for an extended delay range. In addition, it drives CASCADE and /CASCADE. Further, D[10] contains a pulldown and defaults LOW when left floating. 4, 5 IN, /IN LVPECL/ECL Signal Input: Input signal to be delayed. IN contains a 75kΩ pull-down and will default to a logic LOW if left floating. 6 VBB(1) Reference Voltage Output: When using a single-ended input signal source to IN or /IN, connect the unused input of the differential pair to this pin. This pin can also be used to rebias AC-coupled inputs to IN and /IN. When used, de-couple to VCC using a 0.01µF capacitor, otherwise leave floating if not used. Maximum sink/source is ±0.5mA. 7 VEF Reference Voltage Output: Connect this pin to VCF when D[9:0], and D[10] is ECL. Logic Standard VCF Connects to LVPECL VEF(1) CMOS No Connect TTL 1.5V Source 8 VCF Reference Voltage Input: The voltage driven on VCF sets the logic transition threshold for D[9:0], and D[10]. 9, 24, 28 GND, Exposed Pad(2) Negative Supply: For MLF™ package, exposed pad must be connected to a ground plane that is the same potential as the ground pin. 10 LEN ECL Control Input: When HIGH latches the D[9:0] and D[10] bits. When LOW, the D[9:0] and D[10] latches are transparent. 11 SETMIN ECL Control Input: When HIGH, D[9:0] registers are reset. When LOW, the delay is set by SETMAX or D[9:0] and D[10]. SETMIN contains a pull-down and defaults LOW when left floating. 12 SETMAX ECL Control Input: When SETMAX is set HIGH and SETMIN is set LOW, D[9:0] = 1111111111. When SETMAX is LOW, the delay is set by SETMIN or D[9:0] and D[10]. SETMAX contains a pull-down and defaults LOW when left floating. 13, 18, 19, 22 VCC 14, 15 /Cascade, Cascade 16 /EN 20, 21 /Q, Q 17 FTUNE Positive Power Supply: Bypass with 0.1µF and 0.01µF low ESR capacitors. LVPECL Differential Output: The outputs are used when cascading two or more SY89296U to extend the delay range. LVPECL Single-Ended Control Input: When LOW, Q is delayed from IN. When HIGH, Q is a differential LOW. /EN contains a pull-down and defaults LOW when left floating. LVPECL Differential Output: Q is a delayed version of IN. Always terminate the output with 50Ω to VCC – 2V. See “Output Interface Applications” section. Voltage Control Input: By varying the voltage, the delay is fine tuned, see the graph, “Propagation Delay vs. FTUNE Voltage.” Leave pin floating if not used. Notes: 1. Single-ended operation is only functional at 3.3V. 2. MLF™ package only. M9999-072706 [email protected] or (408) 955-1690 4 Precision Edge® SY89296U Micrel, Inc. Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) .................................. –0.5V to +4.0V Input Voltage (VIN) ......................................... –0.5V to VCC LVPECL Output Current (IOUT) Continuous ......................................................... 50mA Surge ................................................................ 100mA Lead Temperature (soldering, 20 sec.) ................... +260°C Storage Temperature Range (TS) ............ –65°C to +150°C Supply Voltage (VCC) .............................. +2.375V to +3.6V Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance(3) MLF™ (θJA) Still-Air ............................................................. 35°C/W MLF™ (ψJB) Junction-to-Board ............................................ 28°C/W TQFP (θJA) Still-Air ............................................................. 28°C/W TQFP (ψJB) Junction-to-Board ............................................ 20°C/W DC ELECTRICAL CHARACTERISTICS(4) TA = –40°C to 85°C, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VCC Power Supply VCC = 2.5V VCC = 3.3V 2.375 3 2.5 3.3 2.625 3.6 V V IEE Power Supply Current No load, max VCC 220 mA VIN Input Voltage Swing (IN, /IN) See Figure 1a. 150 1200 mV VDIFF_IN Differential Input Voltage Swing (IN, /IN) See Figure 1b. 300 2400 mV VIHCMR Input High Common Mode Range IN, /IN VEE+1.2 VCC V Max Units VCC = 3.3V, TA = –40°C to 85°C, unless otherwise stated. Symbol Parameter Condition Min Typ VIH Input High Voltage (IN, /IN) 2.075 2.420 V VIL Input Low High Voltage (IN, /IN) 1.355 1.675 V VBB Output Voltage Reference 1.775 1.875 1.975 V VEF Mode Connection 1.9 2.0 2.1 V VCF Input Select Voltage 1.55 1.65 1.75 V Min Typ Max Units VCC = 2.5V, TA = –40°C to 85°C, unless otherwise stated. Symbol Parameter Condition VIH Input High Voltage (IN, /IN) 1.275 1.62 V VIL Input Low High Voltage (IN, /IN) 0.555 0.875 V VBB Output Voltage Reference 0.925 1.075 1.175 V VEF Mode Connection 1.10 1.20 1.30 V VCF Input Select Voltage 1.15 1.25 1.35 V Notes: 1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Rating” conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Thermal performance on MLF™ packages assumes exposed pad is soldered (or equivalent) to the device most negative potential (GND). 4. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established. Input and output parameters vary 1:1 with VCC, wtih the exception of VCF. M9999-072706 [email protected] or (408) 955-1690 5 Precision Edge® SY89296U Micrel, Inc. LVPECL OUTPUTS DC ELECTRICAL CHARACTERISTICS(5) VCC = 3.3V; TA = –40°C to +85°C; RLOAD = 50Ω to VCC–2V; unless noted. Symbol Parameter VOH Condition Min Typ Max Units Output HIGH Voltage (Q, /Q) 2.155 2.280 2.405 V VOL Output LOW Voltage (Q, /Q) 1.355 1.480 1.605 V VOUT Output Voltage Swing (Q, /Q) See Figure 1a. 550 800 mV VDIFF_OUT Differential Output Voltage Swing (Q, /Q) See Figure 1b. 1.1 1.6 V Min Typ Max Units LVPECL OUTPUTS DC ELECTRICAL CHARACTERISTICS(5) VCC = 2.5V; TA = –40°C to +85°C; RLOAD = 50Ω to VCC–2V; unless noted. Symbol Parameter Condition VOH Output HIGH Voltage (Q, /Q) 1.355 1.48 1.605 V VOL Output LOW Voltage (Q, /Q) 0.555 0.680 0.805 V VOUT Output Voltage Swing (Q, /Q) See Figure 1a. 550 800 mV VDIFF_OUT Differential Output Voltage Swing (Q, /Q) See Figure 1b. 1.1 1.6 V Min Typ LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(6) VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to +85°C; unless noted. Symbol Parameter Condition Max VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V IIH Input HIGH Current 40 µA IIL Input LOW Current 2.0 V –300 Notes: 5. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established. VOH and VOL parameters vary 1:1 with VCC. 6. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established. M9999-072706 [email protected] or (408) 955-1690 6 Units µA Precision Edge® SY89296U Micrel, Inc. AC ELECTRICAL CHARACTERISTICS(7) TA = –40°C to +85°C; unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Operating Frequency Clock 1.5 tpd Propagation Delay IN to Q; D[0–10]=0 IN to Q; D[0–10]=1023 /EN to Q: D[0–10]=0 D10 to CASCADE 3200 11500 3400 350 Programmable Range tpd (max) – tpd (min) 8300 tRANGE tSKEW Duty Cycle Skew ∆t Step Delay INL Integral Non-Linearity tS Setup Time tH tPHL – tPLH Units ps ps ps ps ps 25 ps ps ps ps ps ps ps ps ps ps ps ps Note 9 –10 D t+o LEN D to IN /EN to IN Note 10 Note 11 200 350 300 ps ps ps LEN to D IN to /EN Note 12 200 400 ps ps 500 500 450 ps ps ps Release Time /EN to IN SETMAX to LEN SETMIN to LEN tJITTER Cycle-to-Cycle Jitter Total Jitter Random Jitter Note 13 Note 14 Note 15 tr, tf Output Rise/Fall Time 20% to 80% (Q) 20% to 80% (CASCADE) Duty Cycle FTUNE 4200 14800 4400 670 10 15 35 70 145 290 575 1150 2300 4610 9220 tR fT Max GHz Note 8 D0 High D1 High D2 High D3 High D4 High D5 High D6 High D7 High D8 High D9 High D0-D9 High Hold Time Typ 50 90 +10 2 10 1 psRMS psPP psRMS 85 160 300 ps ps 55 % 47 52 ps/V 45 0 ≤ FTUNE ≤ 1.25V %LSB Notes: 7. High frequency AC electricals are guaranteed by design and characterization 8. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of the output. 9. INL (Integral Non-Linearity) is defined from its corresponding point on the ideal delay versus D[9:0] curve as the deviation from its ideal delay. The maximum difference is the INL. Theoretical Ideal Linearity (TIL) = (measured maximum delay – measured minimum delay) ÷ 1024. INL = measured delay – measured minimum delay + (step number × TIL). 10. This setup time defines the amount of time prior to the input signal. The delay tap of the device must be set. 11. This setup time defines the amount of the time that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than ±75mV to the IN, /IN transition. 12. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater than ±75mV to that IN, /IN transition. 13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc = Tn – Tn+1, where T is the time between rising edges of the output signal. 14. Total jitter definition: with an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peak-topeak jitter value. 15. Random jitter definition: jitter that is characterized by a Gaussian distribution, unbounded and is quantified by its standard deviation and mean. Random jitter is measured with a K28.7 comma defect pattern, measured at 1.5Gbps. M9999-072706 [email protected] or (408) 955-1690 7 Precision Edge® SY89296U Micrel, Inc. TYPICAL OPERATING CHARACTERISTICS VCC = 3.3V, GND = 0, DIN = 100mV, TA = 25°C, unless otherwise stated. Delay vs. D[9:0] 50 800 3000 2000 AMPLITUDE (mV) 6000 5000 4000 1000 0 0 Amplitude vs. Frequency 900 40 8000 7000 DELAY (ps) DELAY (ps) 10000 9000 Propagation Delay Delayvs. vs.FTUNE FTUNE 30 20 10 0 700 600 500 400 300 200 100 500 D[9:0] M9999-072706 [email protected] or (408) 955-1690 1000 -10 0 0.5 1 FTUNE(V) 8 1.5 0 0 500 1000 1500 2000 2500 FREQUENCY (MHz) Precision Edge® SY89296U Micrel, Inc. TIMING DIAGRAM /IN IN tpd /Q Q SINGLE-ENDED AND DIFFERENTIAL SWINGS VDIFF_IN, VDIFF_OUT 1.6V (Typ.) VIN, VOUT 800mV (Typ.) Figure 1b. Differential Voltage Swing Figure 1a. Single-Ended Voltage Swing INPUT AND OUTPUT STAGES VCC 75k9 /EN LEN SETMIN SETMAX D[0:10] IN /IN 75k9 VCC 75k9 Figure 2a. Differential Input Stage M9999-072706 [email protected] or (408) 955-1690 VCC VBB Q, CASCADE /Q, /CASCADE 75k9 Figure 2b. Single-Ended Input Stage 9 Figure 3. LVPECL Output Stage Precision Edge® SY89296U Micrel, Inc. OUTPUT INTERFACE APPLICATIONS +3.3V +3.3V Q Z0 = 50Ω R1 130Ω R1 130Ω +3.3V Q +3.3V +3.3V Z0 = 50Ω Z0 = 50Ω Z0 = 50Ω /Q /Q 50Ω R2 82Ω R2 82Ω VCC VT = VCC –2V For +2.5V systems R1 = 250Ω, R2 = 62.5Ω C (optional) 0.01µF Figure 4. Parallel Termination +3.3V R1 130Ω R1 1kΩ R3 1kΩ +3.3V R2 82Ω R4 1.6kΩ Q Z0 = 50Ω /Q R2 82Ω For +2.5V systems R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ Figure 6. Terminating Unused I/O M9999-072706 [email protected] or (408) 955-1690 R1 50Ω For +2.5V systems R1 = 19Ω Figure 5. Y-Termination +3.3V +3.3V 50Ω 10 Precision Edge® SY89296U Micrel, Inc. APPLICATIONS INFORMATION For best performance, use good high frequency layout techniques, filter VCC supplies, and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the SY89296U data inputs and outputs. VBB Reference The VBB pin is an internally generated reference and is available for use only by the SY89296U. When unused, this pin should be left unconnected. The two common uses for VBB are to handle a single-ended PECL input, and to rebias inputs for AC-coupling applications. If either IN or /IN is driven by a single-ended output, VBB is used to bias the unused input. Please refer to Figure 10. The PECL signal driving the SY89296U may optionally be inverted in this case. When the signal is AC-coupled, VBB is used, as shown in Figure 13, to re-bias IN and/or /IN. This ensures that SY89296U inputs are within acceptable common mode range. In all cases, VBB current sinking or sourcing must be limited to 0.5mA or less. Setting D Input Logic Thresholds In all designs where the SY89296U GND supply is at zero volts, the D inputs can accommodate CMOS and TTL level signals, as well as PECL or LVPECL. Figures 11, 12, and 14 show how to connect VCF and VEF for all possible cases. Cascading Two or more SY89296U may be cascaded in order to extend the range of delays permitted. Each additional SY89296U adds about 3.2ns to the minimum delay and adds another 10240ps to the delay range. Internal cascade circuitry has been included in the SY89296U. Using this internal circuitry, the SY89296U may be cascaded without any external gating. Examples of cascading 2, 3, or 4 SY89296U appear in Figures 7, 8, and 9. Control Word (11bits) DAC C[10] FTUNE C[9:0] D[10] FTUNE D[9:0] #1 #2 IN Q IN Q /IN /Q /IN /Q SETMIN /CASCADE SETMAX CASCADE Figure 7. Cascading Two SY89296U Control Word (12bits) DAC C[11] D[10] FTUNE C[10] C[9:0] #1 D[10] D[9:0] #2 IN Q IN /IN /Q /IN SETMIN SETMAX #3 Q /Q SETMIN /CASCADE SETMAX CASCADE IN Q /IN /CASCADE /Q CASCADE Figure 8. Cascading Three SY89296U M9999-072706 [email protected] or (408) 955-1690 11 FTUNE Precision Edge® SY89296U Micrel, Inc. Control Word (12bits) C[11] D[10] FTUNE DAC C[10] C[9:0] #1 #2 #3 IN Q IN Q IN /IN /Q /IN /Q /IN SETMIN SETMIN SETMAX SETMAX Q /Q SETMIN /CASCADE SETMAX CASCADE Figure 9. Cascading Four SY89296U M9999-072706 [email protected] or (408) 955-1690 12 D[10] D[9:0] FTUNE #4 IN Q /IN /CASCADE /Q CASCADE Precision Edge® SY89296U Micrel, Inc. INTERFACE APPLICATIONS VCC = +3.3V m LVPECL Signals D[0:10] VCF VEF !"# Figure 10. Interfacing to a Single-Ended LVPECL Signal Figure 11. VCF/VEF Biasing for LVPECL Control (D) Input To invert the signal, connect the LVPECL input to /IN and connect VCC to IN. VCC = +3.3V VCC = +3.3V CMOS Inputs TTL Inputs D[0:10] D[0:10] IN VCF NC VCF /IN VCC NC VEF 50Ω 0.01µF 0.01µF 50Ω NC VEF VBB 0V Figure 12. VCF/VEF Biasing for CMOS Control (D) Input 1.5k Figure 13. Re-Biasing an AC-Coupled Signal 0V Figure 14. VCF/VEF Biasing for LVTTL Control (D) Input RELATED PRODUCT AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY89295U 2.5/3.3V 1.5GHz Precision LVPECL Programmable Delay www.micrel.com/product-info/products/sy89295u.shtml SY89296U 2.5/3.3V 1.5GHz Precision LVPECL Programmable Delay with Fine Tune Control www.micrel.com/product-info/products/sy89296u.shtml 16-MLF Manufacturing Guidelines Exposed Pad Application Note www.amkor.com/products/notes_papers/MLF_appnote_0902.pdf HBW Solutions http://www.micrel.com/product-info/as/solutions.shtml M9999-072706 [email protected] or (408) 955-1690 13 Precision Edge® SY89296U Micrel, Inc. 32-PIN MicroLeadFrame® (MLF-32) Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 32-Pin MLF® Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 qualification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management. M9999-072706 [email protected] or (408) 955-1690 14 Precision Edge® SY89296U Micrel, Inc. 32-PIN TQFP (T32-1) Rev. 01 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-072706 [email protected] or (408) 955-1690 15