SY89853U Precision Low-Power Dual 2:1 LVPECL MUX with Internal Termination General Description The SY89853U features two, low jitter 2:1 differential multiplexers with 100K LVPECL (800mV) compatible outputs, capable of handling clocks up to 2.5GHz and data streams up to 2.5Gbps. The SY89853U differential inputs include Micrel’s unique, 3-input termination architecture that allows users to interface to any differential signal (AC- or DCCoupled) as small as 100mV without any level shifting or termination resistors networks in the signal path. The result is a clean, stub-free, low jitter interface solution. The differential 800mV LVPECL outputs have fast rise/fall times guaranteed to be less than 180ps. The SY89853U operates from a 2.5V ±5% or a 3.3V ±10% supply, and is guaranteed over the full industrial temperature range (–40°C to +85°C). For applications that require higher performance, consider the SY58026U. The SY89853U is part of Micrel's Precision ® Edge product family. All support documentation can be found on Micrel’s web site at www.micrel.com. ® Precision Edge Features • Dual 2:1 MUX, each channel selects from inputs • Unique, patent-pending input isolation design minimizes crosstalk • Low power 210mW (VCC = 2.5V) • Guaranteed AC performance over temperature and voltage: - DC-to->2.5Gbps data rate throughput - <360ps IN-to-Q tpd - <180ps tr/tf times • Ultra-low jitter design: - <1psRMS random jitter - <10psPP deterministic jitter - <10psPP total jitter (clock) - <0.7psRMS crosstalk-induced jitter • Unique, patent-pending 50Ω input termination and VT pin accepts DC- and AC-coupled inputs (CML, LVDS, PECL) • 800mV LVPECL output swing • Power supply 2.5V ±5% or 3.3V ±10% • –40°C to +85°C temperature range • Available in 32-pin (5mm x 5mm) MLF® package Applications • • • • Data communication systems All SONET OC-3 to OC-48 applications All Fibre Channel applications All GigE applications Markets • • • • LAN/WAN communication Enterprise servers ATE Test and measurement Precision Edge is a registered trademark of Micrel, Inc MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com February 2007 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U Functional Block Diagram Truth Table SEL Q 0 IN0 Input Select 1 IN1 Input Select February 2007 2 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY89853UMG MLF-32 Industrial SY89853U with Pb-Free bar-line indicator NiPdAu Pb-Free SY89853UMGTR(2) MLF-32 Industrial SY89853U with Pb-Free bar-line indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25ºC, DC Electricals only. 2. Tape and Reel. Pin Configuration 32-Pin MLF® (MLF-32) Pin Description Pin Number Pin Name 25, 28, 29, 32 1, 4 5, 8 INA0, /INA0, INA1, /INA1, INB0, /INB0, INB1, /INB1 10, 13, 16, 17, 20, 23 VCC 14, 19 NC 18 15 SELA, SELB 22, 21 12, 11 QA, /QA, QB, /QB Differential Outputs: These LVPECL output pairs are the outputs of the device. They are a logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to the “Truth Table” below for details. 26, 30 2, 6 VTA0, VTA1 VTB0, VTB1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VTA0, VTA1, VTB0, VTB1 pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for details. 27 31 3 7 VREF-ACA0, VREF-ACA1, VREF-ACB0, VREF-ACB1 Reference Voltages: These reference voltage outputs are equivalent to VCC-1.2V. They are used for AC-coupled inputs. Connect VREF-AC directly to the VT pin and bypass with 0.01µF low ESR capacitor to VCC. See “Input Interface Applications” section. Maximum sink/source current is ±1.5mA. 9, 24 GND, Exposed Pad Ground: Ground pins and exposed pad must be connected to the same ground plane. February 2007 Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. Connecting one input to VCC and the complementary input-to-GND through 1kΩ resistor can terminate unused differential input pairs. The VT pin is to be left open in this configuration. Please refer to the “Input Interface Applications” section for more details. Positive power supply. Bypass with 0.1µF//0.01µF low ESR capacitors. The 0.01µF capacitor should be as close to VCC pin as possible. Not connected. Bank A and Bank B Input Channel Select (TTL/CMOS): These TTL/CMOS-compatible inputs select the inputs to the multiplexers. These inputs are internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. 3 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) ............................–0.5V to +4.0V Input Voltage (VIN) ....................................–0.5V to VCC LVPECL Output Current (IOUT) Continuous................................................. ±50mA Surge ....................................................... ±100mA Termination Current Source or Sink Current on VT .................... ±50mA Input Current Source or Sink Current on IN, /IN.............. ±50mA Current (VREF-AC) Source or Sink Current on VREF-AC ............... ±2mA Lead Temperature (soldering, 20sec.) ...............260°C Storage Temperature (Ts) ................ –65°C to +150°C Supply Voltage (VCC) .....................+2.375V to +2.625V .....................................................+3.0V to +3.6V Ambient Temperature (TA)....................–40°C to +85°C Package Thermal Resistance(3) MLF® (θJA) Still-Air......................................................35°C/W 500lfpm ....................................................28°C/W MLF® (ψJB) Junction-to-Board.....................................16°C/W DC Electrical Characteristics(4) TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter Condition Min Typ Max Units VCC Power Supply VCC = 2.5V VCC = 3.3V 2.375 3.0 2.5 3.3 2.625 3.6 V V ICC Power Supply Current No load, max. VCC. 65 85 mA RIN Input Resistance (IN-to-VT) 45 50 55 Ω RDIFF_IN Differential Input Resistance (IN-to-/IN) 90 100 110 Ω VIH Input High Voltage (IN, /IN) VCC– 1.2 VCC V VIL Input Low Voltage (IN, /IN) 0 VIH– 0.1 V VIN Input Voltage Swing (IN-to-/IN) See Figure 1a. 100 1700 mV VDIFF_IN Differential Input Voltage Swing |IN - /IN| See Figure 1b. 200 VT_IN Maximum Input Voltage (IN-to-VT) VREF-AC Output Reference Voltage VCC– 1.3 mV VCC– 1.2 1.28 V VCC– 1.1 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and ψJB values are determined for a 4-layer board in still-air, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. February 2007 4 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U LVPECL Outputs DC Electrical Characteristics(5) VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC–2V; TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter Condition Min Typ Max Units VOH Output High Voltage (Q, /Q) VCC–1.145 VCC–0.895 V VOL Output Low Voltage (Q, /Q) VCC–1.945 VCC–1.695 V VOUT Output Voltage Swing (Q, /Q) See Figure 1a. 400 800 mV VDIFF-OUT Differential Output Voltage Swing (Q, /Q) See Figure 1b. 800 1600 mV Min Typ LVTTL/CMOS DC Electrical Characteristics(5) VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter VIH Input High Voltage VIL Input Low Voltage Condition Max 2.0 V 0.8 IIH Input High Current VIN = VCC IIL Input Low Current VIN = 0.5V Units 75 –300 V µA µA Notes: 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. February 2007 5 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U AC Electrical Characteristics(6) VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C, RL = 50Ω to VCC–2V, unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Operating Frequency NRZ Data 2.5 Gbps Clock, VOUT > 400mV 2.5 GHz tpd Typ Max Units Propagation Delay IN-to-Q 160 250 360 ps SEL-to-Q 100 260 400 ps tpd Tempco Differential Propagation Delay Temperature Coefficient tSKEW Input-to-Input Skew (Within-bank) Note 7 10 20 ps Bank-to-Bank Skew Note 8 12 25 ps tJITTER 143 fs/ ºC Data Random Jitter (RJ) Note 9 1 psRMS Deterministic Jitter (DJ) Note 10 10 psPP Clock Cycle-to-Cycle Jitter Note 11 1 psRMS Total Jitter (TJ) Note 12 10 psPP 0.7 psRMS 180 ps Crosstalk-Induced Jitter Channel-to-Channel (Within-bank) tr, tf Output Rise/Fall Time (20% to 80%) Note 13, within-bank At full output swing. 50 100 Notes: 6. High-speed AC parameters are guaranteed by design and characterization. VIN swing ≥ 100mV, unless otherwise stated. 7. Input-to-input skew is the difference in time between two inputs to the output within a bank. 8. Bank-to-bank skew is the difference in time from input to the output between banks. 9. Random jitter is measured with a K28.7 character pattern, measured at <fMAX. 23 10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 -1 PRBS pattern. 11. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the output signal. 12 12. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value. 13. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs. February 2007 6 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U Typical Operating Characteristics VCC = 3.3V ±10%; TA = –40°C to + 85°C, RL = 50Ω to VCC–2V, unless otherwise stated. February 2007 7 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U Functional Characteristics VCC = 3.3V ±10%; TA = –40°C to + 85°C, RL = 50Ω to VCC–2V, unless otherwise stated. February 2007 8 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U Single-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing Timing Diagram February 2007 9 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U Input and Output Stages Figure 2b. Simplified LVPECL Output Stage Figure 2a. Simplified Differential Input Stage Input Interface Applications Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3c. LVDS Interface option: may connect VT to VCC. Figure 3d. CML Interface (DC-Coupled) February 2007 Figure 3e. CML Interface (AC-Coupled) 10 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U Output Interface Applications LVPECL has high input impedance, very low output (open emitter) impedance, and small signal swing, which result in low EMI. LVPECL is ideal for driving 50Ω and 100Ω controlled impedance transmission lines. There are different techniques for terminating LVPECL outputs: Parallel Termination TheveninEquivalent, Parallel Termination (3-resistor), and ACcoupled termination. Unused output pairs may be left floating; however, single-ended outputs must be terminated or balanced. Note: Note: 1. For a 2.5V system, R1 = 250Ω, R2 = 62.5 Ω. 1. For a 2.5V system, Rb = 19Ω. 2. For a 3.3V system, R1 = 130Ω, R2 = 82Ω. 2. For a 3.3V system, Rb = 50Ω. Figure 4b. Parallel Termination (3-Resistor) Figure 4a. Parallel Thevenin-Equivalent Termination Note: Note: For a 2.5V system, R = 50Ω. For a 2.5V system, R1 = 250Ω, R2 = 62.5 Ω. Figure 4d. Parallel Thevenin-Equivalent Termination Figure 4c. AC-Coupled Termination Related Product and Support Documentation Part Number Function Data Sheet Link SY58026U 5Gbps Dual 2 :1 400mV LVPECL MUX with Internal Termination www.micrel.com/product-info/products/sy58026u.shtml. HBW Solutions February 2007 MLF® Application Note www.amkor.com/products/notes_papers/MLFAppNote.pdf New Products and Applications www.micrel.com/product-info/products/solutions.shtml 11 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U Package Information 32-Pin MLF® (MLF-32) PCB Thermal Consideration for 32-Pin MLF® Package (Always solder, or equivalent, the exposed pad to the PCB) Packages Notes: February 2007 1. Package meets Level 2 Moisture Sensitivity Classification. 2. All parts are dry-packed before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management. 12 M9999-022007-B [email protected] or (408) 955-1690 Micrel, Inc. SY89853U MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. February 2007 13 M9999-022007-B [email protected] or (408) 955-1690