TDA1180P TV HORIZONTAL PROCESSOR ■ ■ ■ ■ ■ ■ ■ ■ ■ NOISE GATED HORIZONTAL SYNC SEPARATOR NOISE GATED VERTICAL SYNC SEPARATOR HORIZONTAL OSCILLATOR WITH FREQUENCY RANGE LIMITER PHASE COMPARATOR BETWEEN SYNC PULSES AND OSCILLATOR PULSES (PLL) PHASE COMPARATOR BETWEEN FLYBACK PULSES AND OSCILLATOR PULSES (PLL) LOOP GAIN AND TIME CONSTANT SWITCHING ( VCR) COMPOSITE BLANKING AND KEY PULSE GENERATOR PROTECTION CIRCUITS OUTPUT STAGES WITH HIGH CURRENT CAPABILITY DIP16 (Plastic Package) ORDER CODE : TDA1180P DESCRIPTION The TDA1180P is a horizontal processor circuit for b.w. and colour monitors. It is a monolithic integrated circuit encapsulated in 16-lead dual in-line plastic package. PIN CONNECTIONS SUPPLY VOLTAGE 1 16 GROUND NEGATIVE OUTPUT 2 15 OSCILLATOR CONTROL CURRENT POSITIVE OUTPUT 3 14 OSCILLATOR PROTECTION CIRCUIT INPUT 4 13 CONTROL CURRENT OUTPUT PHASE SHIFTER FILTER 5 12 TIME CONSTANT SWITCH FLYBACK INPUT 6 11 COINCIDENCE DETECTOR KEY AND BLANKING PULSE OUTPUT 7 10 VERTICAL SYNC. OUTPUT SYNC. SEPARATOR INPUT 8 9 1180P-01.EPS VERTICAL SYNC. SEPARATOR INPUT May 1993 1/12 2/12 1180P-02.EPS Video Signal AAAA AAAA VS AAAA AAAA VS 8 9 AAAA AAAA AAAA AAAA 12 11 VCR Time Constant and Control Current Switch AAAA AAAA 13 Phase Comparator (Oscillator Sync.) Pulse Shaper Composite Key and Blanking Pulse Generator Vertical Sync. Blanking 6 7 Coincidence Detector Sync. Gate Sync. Separator Gate Pulse Shaper Vertical Sync. Output Stage Noise Vertical Sync. Separator 10 Voltage Limiter AAAA AAAA 15 Frequency AAAA AAAA VS AAAA AAAA 14 Phase Shifter and Pulse Shaper Phase Comparator (Oscillator Flyback) Oscillator 5 1 VS AAAA AAAA AAAA AAAA 16 Output Stage Under Voltage Protection Protection Switch 4 3 2 VS TDA1180P BLOCK DIAGRAM TDA1180P ABSOLUTE MAXIMUM RATINGS Value Unit VS Supply voltage (Pin 1) 15 V V2 Voltage at Pin 2 18 V V4 Voltage at Pin 4 VS V8 Voltage at Pin 8 - 6 , VS V V9 Voltage at Pin 9 ±6 V V11 Voltage at Pin 11 VS I2 Pin 2 peak current 1 A I3 Pin 3 peak current 0.5 A I6 Pin 6 current 30 mA I7 Pin 7 current 20 mA I10 Pin 10 current 30 mA Ptot Tstg , Tj o Total power dissipation at Tamb ≤ 70 C 1 Storage and junction temperature W o - 40 , + 150 C THERMAL DATA Symbol Rth (j-a) Parameter Value Thermal Resistance Junction-Ambient Max Unit o 80 C/W 1180P-01.TBL Parameter 1180P-02.TBL Symbol ELECTRICAL CHARACTERISTICS (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified) Symbol Parameter VS Supply voltage range IS Supply current VS Supply voltage at which the output pulses (at pin 2 and 3) are switched off Test conditions Min. Typ. Max. Unit 9.5 12 13.2 V 42 52 mA 4 V I3 = 0 HORIZONTAL SYNC. SEPARATOR VI Peak to peak input signal V8 Input switching voltage I8 = 80 µA 1 1.5 3 I8 Input switching current V8 = 1.4V 10 I8 Leakage current V8 = -5V 6 V V µA 1 µA VERTICAL SYNC. SEPARATOR VI Peak to Peak Input Signal V9 Input Switching Voltage I9= 80µA 1.5 3 6 V I9 Input Switching Current V9 = 1.4V 5 µA I9 1 V µA Leakage Current V9 = -5V V10 Vertical Sync. Pulse Output Voltage No Load Pin10 R10 Output Resistance 10 kΩ tLV Delay between Leading Edge of Input and Output Signals 17 µs tLV Delay between Trailing Edge of Input and Output Signals 50 µs tV Vertical Sync Pulse Duration 190 µs 11 V 3/12 1180P-03.TBL 1 TDA1180P ELECTRICAL CHARACTERISTICS (continued) (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit 0.5 V PROTECTION CIRCUIT V4 Input Voltage for Switching off the Output Pulses R4 Input Resistance I4 Input Current Output Pulses OFF Output Pulses ON 1 200 kΩ µA 5 FLYBACK PULSE V6 Input Threshold Voltage of Blanking Generator 1.8 V V6 Input Threshold Voltage of Phase Comparator 7.6 V I6 Input Switching Current 0.45 mA V6 ≥ 1.7V OUTPUT PULSE V3 Peak-to-Peak Output Voltage I3 = 150 mApp 10 V I3 Output Current V3 = 5V 500 mA R3 Output Resistance At Leading Edge of output pulse At Training Edge of Output Pulse 3 Ω 20 Ω tp Output Pulse Duration 20 22 26 µs COMPOSITE BLANKING AND KEY PULSE V7k Key Pulse Output Peak Voltage 9 11 V7B Blanking Pulse Output Voltage 4.2 4.5 R7 Output Resistance 100 Ω tsk Phase Relation Between Trailing Edge of Key Pulse and Middle of Sync. Input Pulse 2.7 µs tk Key Pulse Duration tfb Delay between Flyback Pulse and Blanking Pulse 3.5 V 4.8 µs 3.8 V6 = 1.7V V 0.2 µs INTERNAL GATING PULSE tg Gating Pulse Duration 7.5 µs t Phase Relation between Middle of Sync. Pulse and Trailing and Leading Edge of Gating Pulse 3.75 µs COINCIDENCE DETECTOR V11 I11 Output Voltage With Coincidence Without Coincidence 6.8 4 Peak Output Current 0.5 V V mA VCR SWITCH V11 Input Voltage 0 to 4 or 8.5 to 12 - I11 Output Current 35 µA V I11 Output Current 0.4 mA V12 Output Voltage R12 Output Resistance 4/12 4.5V < V11 < 8V V11 > 8.5V or V11 < 4V 3 V 100 40 Ω kΩ 1180P-04.TBL TIME CONSTANT SWITCH TDA1180P ELECTRICAL CHARACTERISTICS (continued) (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit OSCILLATOR V14 Low Level Threshold Voltage 5.4 V V14 High Level Threshold Voltage 8.2 V I14 Charge Current 0.6 mA I14 Discharge Current 0.3 mA V15 Current Source Supply Voltage 3 V I15 Current Source Supply Current 0.3 mA fO Free Running Frequency 15625 Hz ∆fO fO Adjustment Range ± 10 % ∆fO ∆I15 Frequency Control Sensitivity 52 Hz µA ∆fO Frequency Change when VS Drops to 4V ± 10 % +0.6 mA 5 µA OSCILLATOR-FLYBACK PULSE PHASE COMPARATOR V5 Control Voltage Range I5 Peak Control Current I5 Input Current (blocked Phase Detector) tD Permissible Delay between Output Pulse Leading Edge and Flyback Pulse Leading Edge ∆t ∆tD 9.4 to 8.2 -0.6 V µs tp - tf Static Control Error 0.2 % SYNC PULSE-OSCILLATOR PHASE COMPARATOR V13 Control Voltage Range 4.6 to 1.4 I13 Control Peak Current +2 ∆f ∆t Phase Lock Loop Gain V -2.2 -2 mA 2 kHz µs ± 700 Hz Phase Relation between Middle of Flyback Pulse and Middle of Sync. Pulse 2.2 µs ∆V5 ∆tO Adjustment Sensitivity 65 mV µs ∆I5 ∆tO Adjustment Sensitivity 16 µA µs f Catching and Holding Range tO 5/12 1180P-05.TBL OVERALL PHASE RELATIONSHIP TDA1180P TEST CIRCUIT Sandcastle Output Flyback Input (100V) Vert. Sync. Output +V S +V S R8 47kΩ R3 2.2MΩ 10 7 C8 220nF 6 5 4 1 C1 470nF 9 2 R1 2.2kΩ TDA1180P Video Signal Input R2 2.7kΩ 8 3 Output Pulse C3 220nF R4 1.5MΩ +V S C4 100nF 11 12 13 R7 R6 3.6kΩ R5 820kΩ C5 680nF 15 14 16 R9 1.2kΩ C6 4.7µF 100kΩ R10 10kΩ R11 82kΩ C7 10nF C9 4.3nF R12 P2 +V S 22kΩ 22kΩ Frequency 1180P-03.EPS C2 100pF t LV t TV tV 6/12 1180P-04.EPS Figure 1 : Vertical Sync. Output Pulse TDA1180P Figure 2 : Relation Ship of Main Waveform Phases Flyback Input Pulse to tf Video Input Signal Phase Comparator Driving Pulse Separated Sync. Pulse tg Gate Pulse t t td Sandcastle Output Pulse V7K t SK tK V7B 1180P-05.EPS tp Output Pulse Pin 3 7/12 TDA1180P Figure 3 : Free Running Frequency versus Supply Voltage Figure 4 : Loop Gain f O (kHz) 1 16 f O (kHz) 15.625 0 2 4 6 8 10 12 14 16 APPLICATION INFORMATION Pin 1 - Positive supply The operating supply voltage of the device ranges from 10V to 13.2V Pin 2 and 3 - Output The outputs of TDA1180P are suitable for driving transistor output stages, they deliver positive pulse at Pin 3 and negative pulse at Pin 2. The negative pulse is used for direct driving of the output stage, while positive pulse is useful when a driver stage is required. The rise and fall times of the output pulses are about 150 ns so that interference due to radiation are avoided. Furthermore the output stages are internally protected against short circuit. Pin 4 - Protection circuit input By connecting Pin 4 of the IC to earth the output pulses at Pin 2 and 3 are shut off ; this function has been introduced to produced to protect the final stages from overloads. The same pulses are also shut off when the supply voltage falls below 4V. Pin 5 - Phase shifter filter To compensate for the delay introduced by the line final stages, the flyback pulses to Pin 6 and the oscillator waveform are compared in the oscillatorflyback pulse phase comparator. The result of the comparison is a control current which, after it has been filtered by the external capacitor connected to Pin 5, is sent to a phase shifter which adequately regulates the phase of the output pulses. 8/12 1180P-06.EPS VS (V) 15 ϕ (µs) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 The maximum phase shift allowed is: td = tp - tf where tf is the flyback pulse duration. Pin 5 has high input and output resistance (current generator). Pin 6 - Flyback input The flyback pulse drives the high impedance input through a resistor in order to limit the input current to suitable maximum values. The flyback input pulses are processed by a double threshold circuit; this generates the blanking pulses by sensing low level flyback voltage and the pulses to drive the phase comparator by sensing high level flyback voltage, therefore phase jitter caused by ringing normally associated with the flyback pulse, is avoided. Pin 7 - Key and blanking pulse output The key pulse for taking out the burst from the chrominance signal is generated from the oscillator ramp and has therefore a fixed phase position with respect to the sync. The key pulse is then added internally to the blanking pulse obtained by correctly forming the flyback pulse present at Pin 6. The sum of the two signals (sandcastle pulse) is available on low impedance at output Pin 7. Pin 8 and 9 - Sync separators inputs The video signal is applied by means of two distinct biasing networks to pins 8 and 9 of the IC and therefore to the respective vertical and horizontal sync separators. The latter take the sync pulses out of the video signal and make them available to the rest of the circuit for further processing. 1180P-07.EPS 0 15.5 TDA1180P Pin 10 - Vertical sync output The vertical sync pulse, obtained by internal integration of the synchronizing signal, is available at this pin. The output impedance is typically 10kΩ and the lowest amplitude without load is 11V. Pin 11 - Coincidence detector From the oscillator waveform a gate pulse 7 µs wide is taken whose phase position is centered on the horizontal synchronism. The gate pulse not only controls a logic block which permits the sync to reach the oscillator-sync phase comparator only for as long as its duration, but also allows the latching and de-latching conditions of the oscillator to be established.This function is obtained by a coincidence detector which compares the phase of the gate pulses with that of the sync. When the two signals are not accurately aligned in time it means that the oscillator is not synchronized. In this case the detector acts on the logic block to eliminate its filtering effect and on the time constant switching block to establish a high impedance on Pin 12 (small time constant of low-pass filter). This latter block also acts on the oscillator-sync phase detector to increase its sensitivity and with it the loop gain of the synchronizing system. In this conditions the phase lock has low noise immunity (wide equivalent noise bandwidth) and rapid pull-in time which allows fairly short synchronization times. Once locking has taken place the coincidence detector enables the logic block, causes a low impedance on Pin 12 and reduces the sensitivity of the phase comparator. In these conditions the phase lock has high noise immunity ( narrow equivalent noise bandwidth) due to the complete elimination of interference which occurs during the scanning period and the greater inertia with which the oscillator can change its frequency. To optimize the behaviour of the IC if a video recorder is used, the state of the detector can be forced by connecting Pin 11 to earth or to + VS. The characteristics of the phase lock thus correspond to the lack of synchronization. Pin 12 - Time constant switch, (see Pin 11) Pin 13 - Control current output The oscillator is synchronized by comparing the phase of its waveform with that of the sync pulses in the oscillator-sync phase comparator and sending its output current I13 (proportional to the phase difference between the two signals) to Pin 15 of the oscillator after it has been filtered properly with an external low-pass circuit. The time constant of the filter can be switched between two values according to the impedance presented by Pin 12. The voltage limiter at the output of the phase comparator limits the voltage excursion on Pin 13 and therefore the frequency range in which the oscillator remains held-in. The output resistance of Pin 13 is: ● low when V13 > 4.3 or V13 < 1.6V ● high when 1.6V < V13 < 4.3V To prevent the vertical sync from reaching the oscillator-sync phase comparator along with the horizontal sync,a signal which inhibits the phase detector during the vertical interval is taken from the vertical output stage; inhibition remain even if the video signal is not present. The free running frequenc of the oscillator is determined by the values of the capacitor and of the resistor connected to Pins 14 and 15 respectively. To generate the line frequency output pulses, two theresholds are fixed along the fall ramp of the triangular waveform of the oscillator. Pin14 - Oscillator (see Pin 13) Pin 15 - Oscillator control current input (see Pin 13) Pin 16 - Ground 9/12 TDA1180P Figure 5 : Application Circuit for Large Screen Black & White and Colour TV Sandcastle Output +V S +32V Phase Flyback Input (100V) Vert. Sync. Output P1 220kΩ +V S R8 47kΩ R3 2.2MΩ 10 C8 220nF 7 6 220Ω R13 220kΩ 5 C10 4 10µF 1 BU406D C1 470nF 9 2 R1 2.2kΩ 120Ω TDA1180P 6.8nF R2 2.7kΩ Video Signal Input R14 8 BC440 3 560Ω C3 220nF R4 1.5MΩ +V S C4 100nF 11 12 13 R7 R6 3.6kΩ R5 820kΩ C5 680nF 15 14 Q1 16 R9 1.2kΩ C6 4.7µF 100kΩ R10 10kΩ R11 82kΩ C7 10nF C9 4.3nF R12 P2 1180P-08.EPS C2 100pF +V S 22kΩ Frequency 22kΩ Figure 6 : P.C. Board and Component Layout for the Circuit in Figure 6 (1:1 scale) P1 R1 VIDEO SIGNAL INPUT R8 C2 R13 SANDCASTLE OUTPUT R2 C8 FLYBACK INPUT (100V) C1 VS C3 C10 R4 C9 TDA1180P R12 VERTICAL SYNC. OUTPUT R14 OUTPUT PULSE R7 R3 R10 R11 R6 C4 R5 P2 C7 C5 1180P-09.EPS C6 Q1 10/12 R9 TDA1180P Figure 7 : Application Circuit for Small Screen b.w. TV +10.8V 15Ω Sandcastle Output Flyback Input (100V) Vert. Sync. Output 10µF BU407D +V S +V S R8 47kΩ R3 2.2MΩ 10 C8 220nF 7 6 68Ω 100µF 5 4 1 15nF C1 470nF 9 2 R1 2.2kΩ TDA1180P Video Signal Input R2 2.7kΩ 8 3 C3 220nF R4 1.5MΩ 11 12 13 15 R7 +V S 1.2kΩ C6 4.7µF R6 3.6kΩ R5 820kΩ C5 680nF C4 100nF 14 16 R9 100kΩ R10 10kΩ R11 82kΩ C7 10nF C9 4.3nF R12 1180P-10.EPS C2 100pF P2 +V S 22kΩ 22kΩ Frequency Figure 8 : Application Circuit for Darlington Output Stage Sandcastle Output Flyback Input (100V) Vert. Sync. Output +V S +V S R8 47kΩ R3 2.2MΩ 10 C8 220nF 7 6 5 BU806 or BU807 100µF 4 82Ω 1 C1 470nF 4.7µF 9 2 R1 2.2kΩ TDA1180P Video Signal Input 33Ω R2 2.7kΩ 8 3 C3 220nF R4 1.5MΩ +V S C4 100nF 11 12 13 R7 R6 3.6kΩ R5 820kΩ C5 680nF 15 14 16 R9 1.2kΩ C6 4.7µF 100kΩ R10 10kΩ R11 82kΩ C7 10nF C9 4.3nF R12 +V S 22k Ω P2 22k Ω 1180P-11.EPS C2 100pF Frequency 11/12 TDA1180P I b1 L a1 PACKAGE MECHANICAL DATA 16 PINS - PLASTIC DIP b Z B e E e3 D 9 1 8 a1 B b b1 D E e e3 F i L Z Min. 0.51 0.77 Millimeters Typ. Max. 1.65 Min. 0.020 0.030 0.5 0.25 Inches Typ. Max. 0.065 0.020 0.010 20 8.5 2.54 17.78 0.787 0.335 0.100 0.700 7.1 5.1 3.3 0.280 0.201 0.130 1.27 0.050 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 12/12 DIP16.TBL Dimensions PM-DIP16.EPS F 16