Order this document by MC13001X/D
MONOMAX
BLACK AND WHITE TV
SUBSYSTEM
The MONOMAX is a single chip IC that will perform the electronic
functions of a monochrome TV receiver, with the exception of the tuner,
sound channel, and power output stages. The MC13001XP and
MC13007XP will function as a drop–in replacement for the MC13001P and
MC13007P, but some external IF components can be removed for maximum
benefit. IF AGC range has been increased, video output impedance lowered,
and horizontal driver output current capability increased.
• Full Performance Monochrome Receiver with Noise and Video
Processing (Black Level Clamp, DC Contrast, Beam Limiter)
• Video IF Detection On–Chip (No Coils, No Pins, except Inputs)
•
•
•
•
•
•
•
•
SEMICONDUCTOR
TECHNICAL DATA
Noise Filtering On–Chip (Minimum Pins and Externals)
Oscillator Components On–Chip (No Precision Capacitors Required)
MC13001XP for 525 Line NTSC and MC13007XP for 625 Line CCIR
Low Dissipation in All Circuit Sections
P SUFFIX
PLASTIC PACKAGE
CASE 710
High Performance Vertical Countdown
2–Loop Horizontal System with Low Power Startup Mode
ORDERING INFORMATION
Noise Protected Sync and Gated AGC System
Operating
Temperature Range
Device
MC13001XP
TA = 0° to +70°C
MC13007XP
Designed to work with TDA1190P or TDA3190P Sound IF and Audio
Output Devices
Package
Plastic DIP
Figure 1. Basic Elements of the System
Black
Clamp
Contrast
Beam Limit
26 25 27
Sound
IF
28
VIF IF Decoupling
4 2
6
Video Process
Video IF
IF In 3
IF In 5
VIF
Video
Process
Detector
24 Video Out
Blank
Buffer
8 AGC Filter
RF AGC 11
RF AGC Delay 10
AGC 9
Flyback 15
AGC Sync
RF
AGC
AGC
Feed Forward
Flyback
Buffer
AGC
23 Vertical Sync
Sync
Separator
Noise
Process
Horizontal Sync
Separator 7
Vertical
Horizontal
VCC 18
Vertical
Integrator
22 Vertical Out
Vertical
Sync
Separator
Window
Control
& Reset
Vertical
Preamp
Clock
B525
Vertical
Ramp
21
Vertical
Feedback
Regulator
Phase
Detector 2
+8.0V Out 19
Phase
Detector 1
13
Horizontal Phase
Detector 1
B2
31.5 kHz
Oscillator
Variable
Slicer
12
Horizontal Frequency
14
Horizontal Phase
Detector 2
B2
Horizontal
Buffer
20 Vertical Size
17 Horizontal Out
Motorola, Inc. 1995
MOTOROLA ANALOG IC DEVICE DATA
1
MC13001X MC13007X
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Symbol
Value
Unit
VCC
+16
Vdc
Power Dissipation
PD
1.0
W
Horizontal Driver Current – Pin 17
Ihor
–20
mA
IRFAGC
20
mA
Video Detector Current – Pin 24
IVID
5.0
mA
Vertical Driver Current – Pin 22
Ivert
5.0
mA
Auxiliary Regulator Current – Pin 19
Ireg
35
mA
RθJC
60
°C/W
TJ
150
°C
Tstg
–65 to + 150
°C
TA
0° to + 70
°C
Rating
Power Supply Voltage – Pin 18
RF AGC Current – Pin 11
Thermal Resistance Junction–to–Case
Maximum Junction Temperature
Storage Temperature Range
Operating Temperature Range
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Value
Unit
Ihor
≤10
mA
RF AGC Current
IRFAGC
≤10
mA
Regulator Current
Ireg
≤20
mA
Horizontal Output Drive Current
ELECTRICAL CHARACTERISTICS (VCC = 11.3 V, TA = 25°C)
Symbol
Min
Typ
Max
Unit
Power Supply Current (Pins 18, 19)
ICC
44
–
76
mA
Regulator Voltage (Pin 19)
Vreg
7.2
8.2
8.8
Vdc
fhor(NOM)
13
–
19
kHz
–
230
–
Hz/µA
fhor
–10
–
+10
%
Oscillator Temperature Stability (0 ≤ TA ≤ 75°C)
–
–
50
–
Hz
Phase Detector 1 (Charge/Discharge Current)
(Non–Standard Frame)
(Standard Frame)
Iφ1
–
–
±900
±400
–
–
µA
Phase Detector 2
(Charge/Discharge Current)
Vφ2
–
+1.0
–0.6
–
mA
Phase Detector 1
(Output Voltage Limits)
Vφ1
–
7.5 (max)
2.5 (min)
–
Vdc
Phase Detector 2
(Output Voltage Limits)
Vφ1
–
7.7 (max)
1.5 (min)
–
Phase Detector 1
(Leakage Current)
–
–
2.0
Phase Detector 2
(Leakage Current)
–
–
3.0
Horizontal Delay Range
(Sync to Flyback)
–
–
18 (max)
5.0 (min)
–
–
µs
–
–
0.3
Vdc
–
–
5.0
10
–
–
±500
±750
–
Characteristics
HORIZONTAL SPECIFICATIONS
Oscillator Frequency (Nominal) (Pin 12)
Oscillator Sensitivity
Startup Frequency (I18 = 4.0 mA)
Horizontal Output Saturation Voltage
(I17 = 15 mA)
Phase–Detector 1 (Gain Constant)
(Out–of–Lock)
(In–Lock)
Horizontal Pull–In Range
2
V17(sat)
µA
µA/µs
Hz
MOTOROLA ANALOG IC DEVICE DATA
MC13001X MC13007X
ELECTRICAL CHARACTERISTICS (continued) (VCC = 11.3 V, TA = 25°C)
Symbol
Min
Typ
Max
Unit
Output Current (Pin 22)
I22
–0.6
–
–
mA
Feedback Leakage Current (Pin 21)
I21
–
–
6.0
µA
Feedback Maximum Voltage
V21
–
5.1
–
Vdc
Ramp Retrace Current (Pin 20)
I20
500
–
900
µA
–
–
0.3
µA
Characteristics
VERTICAL SPECIFICATIONS
Ramp Leakage Current (Pin 20)
IF SPECIFICATIONS
Regulator Voltage
Input Bias Voltage
V4
V2,6
–
–
7.5
4.2
–
–
Vdc
Input Resistance
Input Capacitance (VAGC Pin 8 = 4.0 V)
Rin
Cin
–
–
6.0
2.0
–
–
kΩ
pF
–
80
–
µVrms
–
75
–
MHz
Zero Carrier Voltage (See Figure 5) (Pin 28)
–
7.0
–
Vdc
Output Voltage (See Figure 6) (Pin 24)
White to Back Porch
–
1.4
–
V
Differential Gain
Differential Phase (IRE Test Method)
–
6
4
–
%
Degrees
–
10
–
µA
–
14:1
–
V27
–
1.0
–
Vdc
RF (Turner AGC Output Current (V11 = 5.5 V)
I11
5.0
–
–
mA
AGC Delay Bias Current
I10
–
–10
–
µA
AGC Feedforward Current
I9
–
1.0
–
mA
AGC Threshold (Sync Tip at Pin 28)
V28
4.7
–
5.1
Vdc
Sync Separator Operating Point
V7
–
4.2
–
Vdc
Sync Separator Charge Current
I7
–
5.0
–
mA
Sensitivity
(V8 = 0 V, 400 Hz 30% MOD, V28 = 0.8 Vpp)
Bandwidth
BW
VIDEO SPECIFICATIONS
Contrast Bias Current (Pin 26)
I26
Contrast Control Range
Beam Limiting Voltage (Pin 27)
AGC & SYNC
–10
4.0
(Pin 9)
–20
3.0
–30
2.0
–40
1.0
RELATIVE ATTENUATION (dB)
Figure 3. Video Output Response
5.0
AGC FEEDFORWARD, Pin 9 (V)
IF GAIN REDUCTION (dB)
Figure 2. Monomax AGC Characteristics
0
3
Video Out (Pin 24) with Max Contrast
2
Sound IF Out (Pin 28)
1
0
–1
–2
–3
–4
–5
–50
0
1.0
2.0
3.0
AGC VOLTAGE, Pin 8 (V)
MOTOROLA ANALOG IC DEVICE DATA
4.0
0
5.0
–6
0
2.0
4.0
6.0
8.0
VIDEO OUTPUT RESPONSE (MHz)
10
3
MC13001X MC13007X
GENERAL DESCRIPTION
The Video IF Amplifier is a four–stage design with 80 µV,
sensitivity. It uses a 6.2 V supply decoupled at Pin 4. The first
two stages are gain controlled, and to ensure optimum noise
performance, the first stage control is delayed until the
second stage has been gain reduced by 15 dB. To bias the
amplifier, balanced dc feedback is used which is decoupled
at Pins 2 and 6 and then fed to the input Pins 3 and 5 by
internal 3.9 k resistors. The nominal bias voltage at these
input pins is approximately 4.2 Vdc. The input, because of the
high IF gain, should be driven from a balanced differential
source. For the same reason, care must be taken with the IF
decoupling.
The IF output is rectified in a full wave envelope detector
and detector nonlinearity is compensated by using a similar
nonlinear element in a feedback output buffer amplifier. The
detected 1.9 Vpp video at Pin 28 contains the sound
intercarrier signal, and Pin 28 is normally used as the sound
takeoff point. The video frequency response, detector to Pin
28, is shown in Figure 3 and the detector intermodulation
performance can be seen by reference to Figure 4. Typical
Pin 28 video waveforms and voltage levels are shown in
Figure 5.
The video processing section of Monomax contains a
contrast control, black level clamp, a beam current limiter and
composite blanking. The video signal first passes through the
contrast control. This has a range of 14:1 for a 0 V to 5.0 V
change of voltage on Pin 26, which corresponds to a change
of video amplitude at Pin 24 of 1.4 V to 0.1 V (black to white
level). The beam current limiter operates on the contrast
control, reducing the video signal when the beam current
exceeds the limit set by external components. As the beam
current increases, the voltage at Pin 27 moves negatively
from its normal value of 1.5 V, and at 1.0 V operates the
contrast control, thus initiating beam limiting action. After the
contrast control, the video is passed through a buffer amplifier
and dc is restored by the black level clamp circuit before
being fed to Pin 24 where it is blanked. The black level clamp,
which is gated “on” during the second half of the flyback,
maintains the video black level at 2.4 V ± 0.1 V under all
conditions, including changes in contrast, temperature and
power supply. The loop integrating capacitor is at Pin 25 and
is normally at a voltage of 3.3 V. The frequency response of
the video at Pin 24 is shown in Figure 3 and it is blanked to
within 0.5 V of ground.
RELATIVE PRODUCT ATTENUATION (dB)
Figure 4. Detector Products
10
0
–10
45.74 MHz = 25 mVrms
42.17 MHz = 12.5 mVrms
41.25 MHz = Relative to
41.25 MHz = 45.75 MHz
–20
–30
–40
4.5 MHz
920 kHz
–50
2.66 MHz
–60
–10
4
– Reference = 3.58 MHz
–20
–30
–40
–50
RELATIVE 41.25 MHz INPUT LEVEL (dB)
Figure 5. Pin 28 Sound Output
7.0 V
Zero Carrier
87.5%
25%
Back Porch
5.1 V
AGC Threshold
3.6 V
Noise Threshold
Figure 6. Pin 24 Video Output
3.8V
Max. Contrast
2.4V
Min. Contrast
Back Porch
1.7V
Max. Blanking Level
The AGC loop is a gated system, and for all normal
variations of the IF input signal, maintains the sync tip of a
noise filtered video signal at a reference voltage (5.1 V
Pin 28). The strobe for the AGC error amplifier is formed by
gating together the flyback pulse with the separated sync
pulse. Integration of the error signal is performed by the
capacitor at Pin 8, which forms the dominant AGC time
constant. Improved noise performance is obtained by the use
of a gated AGC system, noise protected by a dc coupled
noise canceling circuit. The false AGC lock conditions, which
can result from this combination, are prevented by an
anti–lockout circuit connected to the sync separator at Pin 7.
AGC lockout conditions, which occur due to large rapid
changes of signal level are detected at Pin 7 and recovery is
ensured under these conditions by changing the AGC into a
mean level system. The voltage at Pin 10 sets the point at
which tuner AGC takeover occurs and positive going tuner
control, suitable for an NPN RF transistor, is available at
Pin 11. The maximum output is 5.5 V at 5.0 mA. A
feed–forward output is provided at Pin 9. This enables the
AGC control voltage to be ac coupled into the tuner takeover
control at Pin 10. The coupling allows additional IF gain
reduction during signal transient conditions, thus
compensating for variations of AGC loop gain at the tuner
AGC takeover point. In this way the AGC system stability and
response are not degraded.
The previously mentioned noise protection is effected by
detecting negative–going noise spikes at the video detector
output. A dc coupled detector is used which turns on when a
noise spike exceeds the video sync tip by 1.4 V. This pulse is
then stretched and used to cancel the noise present on the
delayed video at the input to the sync separator. Cancellation
is performed by blanking the video to ground. Complete
cancellation of the noise spike results from the stretching of
the blanking pulse and the delay of the noise spike at the
input to the sync separator. Protection of both the horizontal
PLL and the AGC stems from the fact that both circuits use
the noise cancelled sync for gating.
MOTOROLA ANALOG IC DEVICE DATA
MC13001X MC13007X
The composite sync is stripped from a delayed and filtered
video in a peak detecting type of sync separator. The
components connected to Pin 7 determine the slice and tilt
levels of the sync separator. For ideal horizontal sync
separation and to ensure correct operating of AGC anti–
lockup circuit, a relatively short time constant is required at
Pin 7. This time constant is less than optimum for good noise
free vertical separation, giving rise to a vertical slice level
near sync tip. An additional longer time–constant is therefore
coupled to the first via a diode. With the correct choice of time
constants, the diode is non–conducting during the horizontal
sync period, but conducts during the longer vertical period.
This connects the longer time constant to the sync separator
for the vertical period and stops the slice level from moving up
the sync tip. The separated composite sync is integrated
internally, and the time constant is such that only the longer
period vertical pulses produce a significant output pulse. The
output is then fed to the vertical sync separator, which further
processes the vertical pulse and provides increased noise
protection. The selection of the external components
connected to the vertical separator at Pin 23 permits a wide
range of performance options. A simple resistor divider from
the 8.2 V regulated supply gives adequate performance for
most conditions. The addition of an RC network will make the
slice level adapt to varying sync amplitude and give improved
weak signal performance. A resistor to the AGC voltage on
Pin 9 enables the sync slice level to be changed as a function
of signal level. This further improves the low signal level
separation while at the same time giving increased impulse
noise protection on strong signals.
Horizontal Oscillator
The horizontal PLL (see Figure 7) is a two–loop system
using a 31.5 kHz oscillator which after a divider stage is
locked to the sync pulse using Phase Detector 1. The control
signal derived from this phase detector on Pin 13 is fed via a
high–value resistor to the frequency–control point on Pin 12.
The same divided oscillator frequency is also fed to Phase
Detector 2, where the flyback pulse is compared with it and
the resulting error used to change a variable slice level on the
oscillator ramp waveform. This therefore changes the timing
of the output square wave from the slicer and hence the
timing of the buffered horizontal output on Pin 17 (see
Figure 8). The error on Phase Detector 2 is reduced until the
phasing of the flyback pulse is correct with respect to the
divided oscillator waveform, and hence with respect to the
sync pulse.
Figure 8. Horizontal Waveforms
200 mVpp
4.5 V
7
6.0 V
13
2.0 V
17
50 mVpp
0V
+0.9 V 15
0V
–0.7 V
To improve the pull–in and noise characteristics of the first
PLL, the phase detector current is increased when the
vertical lock indicator signals an unlocked condition and is
decreased when locked. This increases the loop bandwidth
and pull–in range when out of lock, and decreases the loop
bandwidth when in lock, thus improving the noise
performance. In addition, the phase detector current during
the vertical period is reduced in order to minimize the
disturbance to the horizontal caused by the longer period
vertical phase detector pulses.
Figure 7. Horizontal Oscillator Systems
31.5kHz
Oscillator
Vary
Frequency
SLICE
12
13
Divide
by 2
Phase
Detector 1
Output
Divide
by 2
SLICE
Phase
Detector 2
15
17
Vary
SLICE
Level
(Phase)
14
Deflection
Flyback
Sync
MOTOROLA ANALOG IC DEVICE DATA
5
MC13001X MC13007X
The flyback gating input is on Pin 15 which is internally
clamped to 0.7 V in both directions and requires a negative
input current of 0.6 mA to operate the gate circuit. This input
can be a raw flyback pulse simply fed via a suitable resistor.
The oscillator itself is a novel design using an on–chip
50 pF silicon nitride capacitor which has a temperature drift
of only 70 ppm/°C and negligible long term drift. This, in
conjunction with an external resistor, gives a drift of horizontal
frequency of less than 1.0 Hz/°C – i.e., less than 100 Hz over
the full operating temperature range of the chip. The pull–in
range of the PLL is about ±750 Hz, so normally this would
eliminate the need for any customer adjustment of the
frequency.
The second significant feature of this design is the use of a
virtual ground at the frequency control point which floats at a
potential derived from a divider across the power supply and
this is the same divider which determines the end–points of
the oscillator ramp. The frequency adjustment which is
necessary to take up tolerances in the on–chip capacitor is
fed in as a current to this virtual ground, and when this
adjustment current is derived from an external potentiometer
across the same supply there is no frequency variation with
supply voltage. Moreover, using the voltage from a
potentiometer for the adjustment instead of the simple
variable resistor normally used in RC oscillators makes the
frequency independent of the value of the potentiometer and
hence its temperature coefficient. The frequency control
current from the first phase detector is fed into this same
virtual ground, and as the sensitivity of the control is about
230 Hz/µA, a high value resistor can be used (680 kΩ) which
can be directly connected to the phase detector filter without
significant loading.
This oscillator operates with almost constant frequency
to below 4.0 V and as the total PLL system consumes
less than 4.0 mA at this voltage, this gives an ideal
startup characteristic for receivers using deflection–derived
power supplies.
Vertical System
An output switching signal is taken from the 31.5 kHz
oscillator to clock the vertical counter which is used in place
of a conventional vertical oscillator circuit. The counter is
reset by the vertical sync pulse, but the period during which it
is permitted to reset is controlled by the window control.
Normally, when the counter is running synchronously, the
window is narrow to give some protection against spurious
noise pulses in the sync signal. If the counter output is not
coincident with sync however, after a short period the window
opens to five reset over a much wider count range, leading to
a fast picture roll towards lock. At weak signal, i.e., less than
200 µV IF input, the vertical system is forced to narrow mode
to give a steadier picture for commonly occurring types of
noise. The vertical sync, gated by the counter, then resets a
ramp generator on Pin 20 and the 1.5 Vpp ramp is
buffered to Pin 22 by the vertical preamplifier. A differential
input to the preamp on Pin 21 compares the signal generated
across the resistor in series with the deflection coils with the
generated ramp and thus controls shape and amplitude of
the coil current.
The basic block diagram of the countdown system is
shown in Figure 9. The 31.5 kHz (2FH) clock from the
horizontal oscillator drives a 10–stage counter circuit which is
normally reset by the vertical sync pulse via the sync gate,
‘‘OR’’ gate and D flip–flop. This D input is also used to initiate
discharge of the ramp capacitor and hence causes picture
flyback.
Figure 9. Monomax Vertical Countdown
0
20
Blanking
Pulse
Blanking
Latch
2FH
Clock
Counter Reset
10 Stage Counter
514–526
‘‘Narrow’’
384–544
‘‘Wide’’
H/4
Delay
COINC
To
‘‘Wide’’
8H/2 Delay
Window
Control
Coincidence
Detector
2H/2 Delay
COINC
Vertical
Sync
To
‘‘Narrow’’
Define
Window
for Sync
D Flip–Flop
(Delay)
Sync Gate/
Ramp Latch
To Ramp
Pull–Down
6
D
Clock
MOTOROLA ANALOG IC DEVICE DATA
MC13001X MC13007X
The period during which sync can reset the counter and
cause flyback is determined by the window control which
defines a count range during which the gate is open. One of
two ranges is selected according to the condition of the
signal. The normal “narrow” range is 514 to 526 counts for a
525 line system and is selected after the coincidence
detector indicates that the reset is coincident, twice in
succession, with the 525 count from the counter. When the
detector indicates non–coincidence 8 times in succession,
then the window control switches to the “wide” mode (384 to
544 counts) to achieve rapid re–synchronization. For the 625
line version the counts are 614 to 626 for narrow mode and
484 to 644 for wide mode. Note that the OR gate after the
sync gate is used to terminate the count at the end of the
respective window if a sync pulse has not appeared.
This method accepts nonstandard signals almost in the
same way as a conventional triggered RC oscillator and has
a similar fast lock–in time. However, the use of a window
control on the counter reset ensures that when locked with a
normal standard broadcast signal the counter will reject most
spurious noise pulse.
The blanking output is provided from a latch which is set by
the counter reset pulse and terminated by count 20 from the
counter chain.
Figure 10. Vertical Waveforms
7.0 V
23
6.0 V
–2.5 V 20
1.0 V pp
2.0 V
22
0V
21
–4.0 V
500 mV pp
Power Supply
The power supply regulator, although of simple design,
provides two independent power supplies – one for the
horizontal PLL section and the other for the remainder of the
chip. The supplies share the same reference voltage but
the design of the main regulator is such that it can be
switched on independently to give minimum loading on the
“bleed” voltage source during startup phase of a
defection–derived supply system.
Figure 11. Power Supply Circuit
RBL =
VBL – 8
4 x 10–3
Main
12 V Supply
Horizontal
Startup Bleed
+ VBL
8.2 V to
External
Circuits
IEXT
RBL
R6
18
19
R1
8.2 V to
Horizontal
System
Q5
Q3
Q6
8.2V to
All Monomax
Circuits Except
Horizontal
R2
D1
D2
Z1
Q2
Q1
R3
Q4
Q7
R5
MOTOROLA ANALOG IC DEVICE DATA
R4
IEXT (mA)
R6 (Ω)
< 5.0
150
20
82
35
68
7
MC13001X MC13007X
Figure 12. Test Circuit Diagram
6.6k
Detected
Video
1
100
28
V28
40
V2
2
10k
36k
1.0k
27
2.7k
3.9k
12k
8.0k
I26
3.5k
10nF
V4
22k
26
3
10nF
Pin 19
Regulated
Supply
4
0.1nF
25
0.1nF
10nF
250
V6
500
Blanking
2.5k
24
5
Same as Pin 3
Video
6
Same as Pin 2
Vertical Sync
Integrated
Sync
2.2k
23
10nF
Sync
470
8.2k
220
I22
Video
I7
470k
50nF
22
7
Vreg
12k
100
V7
820
180k
8
10nF
27k
I20
+
–
I9
5.0k
0.1µF
10k
I10
100
Vreg Source
8.2V
ICC
19
10
220
Horizontal
Supply
12V
120V
18
11
I11
0.1nF
3.0k
22k
330
17
12
10nF
I12
3.0V
13
AGC
Gate
14
10nF
16
5.0k
I01
V02
5.0V
V17
V01
8
12V
0.1µF
35k
Regulated Supply
82k
12V
750k
20
Vertical
Countdown
9
470
21
6.2V
V8
47k
12V
V21
2.2nF
4.7k
91k
Vreg
56k
V27
300
15
Flyback Pulse
I02
MOTOROLA ANALOG IC DEVICE DATA
MC13001X MC13007X
Figure 13. Simplified Application
Video
Out
1.2k
39k
High Voltage
Winding
82k
Contrast
+8.2V
1
10
27
26
+24V
+12V
+120V
1.0M
+120V +120V
33k
27k
Flyback
Black
47k Level
Clamp
4.7µF
28
Vert
Feedback
Vert
Size
470 k
Sound IF
24
Horiz
Drive
0.1
RFB
23
22
Vreg
21
20
Vpk
Vpk
kΩ
RFB =
2
+8.2V
Vert
Drive
25
150
0.1
3.3M
0.05
2.2k
1.0µ F
To TDA1190P
+8.2V
Vert
Sync{
50nF
220
Startup
Resistor
+8.2V
VCC
19
18
17
16
15
MC13001X MONOMAX
2
3
4
5
6
7
8
VRF 10nF
9
10
12
RF
AGC
0.33µF
1.0µF
10nF
11
50nF
13
Horiz
Freq
680
14
Horiz
Phase
Det. 1
8.2V
39k
1
Horiz
Phase
Det. 2
10nF
680k
8.2k
0.47µ F
91k
Horiz
Freq
100pF 20%
Video IF In
+8.2V
360k
RF
AGC
Delay
100k
20k
0.1nF
10nF
2% Metal Film
or Metal Oxide
+8.2V
120k
22nF
1.0µF
470k
2.7M
Sync Separator Components
Pin 9
1.8M
Tuner
50nF
2.2k
23
{Vertical Sync, optional components
{for extra performance with low signal strength.
MOTOROLA ANALOG IC DEVICE DATA
See Application Note AN879 for further information.
9
MC13001X MC13007X
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 710–02
ISSUE C
28
15
B
14
1
L
C
A
N
H
G
F
D
K
SEATING
PLANE
M
J
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
36.45
37.21
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
0_
15_
0.51
1.02
INCHES
MIN
MAX
1.435
1.465
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.085
0.008
0.015
0.115
0.135
0.600 BSC
0_
15_
0.020
0.040
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA / EUROPE: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: [email protected] – TOUCHTONE (602) 244–6609
INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
10
◊
*MC13001X/D*
MC13001X/D
MOTOROLA ANALOG IC DEVICE
DATA