TDA9108 MONITOR HORIZONTAL PROCESSOR .. .. .. .. . POS/NEG SYNC INPUT SYNC POLARITY DETECTION 2 PLLs CONCEPT 2 COMPLEMENTARY OUTPUTS DC ADJUSTABLE FREQUENCY DC ADJUSTABLE DUTY CYCLE X-RAY PROT INPUT BACK PORCH CLAMPING PULSE GENERATOR H-DRIVE INHIBITION WHEN VS < VS START DIP14 (Plastic Package) ORDER CODE : TDA9108 DESCRIPTION The TDA9108 is a horizontal deflection processor specially designed for monitor applications. The H-drive output duty cycle, the horizontal frequency and the horizontal position are DC adjustable ; it accepts both POS/NEG polarity on sync input and delivers polarity information on a dedicated pin. All these features make the device a good choice for multifrequency application.In addition to this, X-ray protection, 2 complementary H-drive output , and a back porch clamping pulse generator are also included. It is a monolithic integrated circuit encapsulated in a 14 lead dual line plastic package. 1 14 GR OUN D NEGATIVE H-DRIVE 2 13 H-FREQUENCY SETTING POSITIVE H-DRIVE 3 12 H-OSCILLATOR CAPACITOR DUTY CYCLE ADJUSTMENT 4 11 1st PLL LOOP FILTER 2nd PLL LOOP FILTER 5 10 SYNC POLARITY FLYBACK INPUT 6 9 SYN C INPUT 7 8 X-RAY PROTECTION INPUT SU PP LY VOLTAGE BACK PORCH CLAMPING PULSE OUTPUT October 1993 9108-01.EPS PIN CONNECTIONS 1/9 TDA9108 BLOCK DIAGRAM HOR IZONTAL LOOP FLYBACK IN FILTER 6 5 7 BACK PORCH CLAMP PULSE GENERATOR SUPPLY 1 HORIZONTAL PULSE SHAPER 2nd PHASE COMPARATOR 4 HORIZONTAL DUTY CYCLE GROUND 14 INPUT 9 SYNC EXTRACTOR H-Sync SYNC 10 POLARITY DETECTION 1st PHASE COMPARATOR OSCILLATOR 11 13 12 LOOP FILTER R C 3 POSIT IVE OUTPUT THYRISTOR FUNCTION 8 X-RAY PROT INPUT 9108-02.EPS POLARITY 2 NEGATIVE OUTPUT OUTPUT STAGE Symbol Parameter VS Supply Voltage (Pin 1) Value Unit 15 V V2 Voltage at Pin 2 18 V V4 Voltage at Pin 4 0, VS V V8 Voltage at Pin 8 0 , VS V V9 Voltage at Pin 9 0 , VS V V10 Voltage at Pin 10 0, VS V A I2 Pin 2 Peak Current 1 I3 Pin 3 Peak Current 0.5 A I6 Pin 6 Input Current 30 mA I7 Pin 7 Input Current 10 mA Ptot Tstg , Tj o Total Power Dissipation at Tamb ≤ 70 C 0.9 Storage and Junction Temperature W o - 40 , + 150 C 9108-01.TBL ABSOLUTE MAXIMUM RATINGS Symbol R th (j-a) Parameter Value Thermal Resistance Junction-ambient Max. Unit o 90 C/W 9108-02.TBL THERMAL DATA ELECTRICAL CHARACTERISTICS (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified) 2/9 Parameter VS Supply Voltage Range IS Supply Current (Pin 1) VS Supply voltage at which the output pulses (at Pin 2 and 3) are switched off Test conditions Min. 10 I3 = 0 Typ. Max. Unit 12 13.2 V 38 55 mA 4 V 9108-03.TBL Symbol TDA9108 ELECTRICAL CHARACTERISTICS (continued) (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit VS 0.8 1 V V µA µA 2.7 V 1 12 µA µA V 3.2 V 0.5 µA µA HORIZONTAL SYNC. INPUT V9SW Sync Input Threshold Sync high Sync Low ● Sync high ● Sync Low 2 ● ● I9SW Sync Input Current -20 -7 2.3 2.5 SYNC POLARITY SELECTION V10th Polarity Selection Threshold Positive sync on Pin 9 for V 10 < V10th Negative sync on Pin 9 for V10 > V10th I10 V10ZL Input Current Low Impedance (2kΩ) Threshold V10 = 2V V10 = 3V (see note 1) 6.3 X-RAY PROTECTION CIRCUIT V8th I8 X-ray Prot Input Threshold Voltage (when V8 > V8th Pin 2 and 3 are inhibited until VS is switched off/on) Input Current 2.6 V8 ≤ 2.5 V8 ≥ 3.3 2.9 -0.5 FLYBACK INPUT V6 I6 Phase Comparator Input Threshold Input Switching Current 10 V mA 3.2 150 10.8 2.7 150 100 3 V mA V V mA mA Ω 20 Ω 0.1 OUTPUT PULSE V2 I2 V3 I3 R3 Saturation Voltage (Pin 3 grounded) I2 = 150mA Output Current (Pin 3 grounded) V2 = 5V Output Voltage (Pin 2 connected to supply) ● High level (I3 = 150mA) ● Low level (I3 = 100mA) Output Current Capability ● Source ● Sink Output Resistance ● At leading edge of output pulse ● At falling edge of output pulse 2.2 8.8 9.8 1.5 DUTY CYCLE ADJUSTMENT f = 31.5kHz Pin 4 not connected Pin 4 not connected Pin 4 not connected 26 30 0.178 VS 0.19 VS 0.202 VS 1.7 2.3 2.9 Note 1 : The voltage on the polarity detection comparator is clamped by an internal Zener diode (VZ). VPin 10 − VZ When voltage on Pin 10 reaches VZ, then IPIn 10 = . 2kΩ Note 2 : Pin 4 internal schematic % V kΩ VS 2kΩ 10 To Duty Cyc le 34 2.5V Adjustment DZ 2.3kΩ 9108-04.EPS 4 0.19 VS 9108-04.TBL V4 R4 Horizontal Output Pulse Duty Cycle on Pin 3 (high level, line transistor off time) Voltage on Pin 4 (see note 2) Serial Equivalent Resistor on Pin 4 (see note 2) 9108-03.EPS tp 3/9 TDA9108 ELECTRICAL CHARACTERISTICS (continued) (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit DUTY CYCLE ADJUSTMENT (continued) tpADJ K4 Max. Horizontal Output Duty Cycle Range V4 (function of V 4) tp = K4 ⋅ (see note 3) VS Duty Cycle Adjustment Coefficient f = 31.5kHz 50 % 1.6 1.8 2 4 1.1 5 0.2 1.5 0.5 1.9 V V µs 1.25 1.7 2.15 µs 2.6 27 5.4 8.2 0.6 0.3 2.9 30 3.2 33 V V mA mA V kHz KEY PULSE OUTPUT V7k V7L tSK tK Key Pulse Output Peak Voltage (emitter follower) Low Level (outside the key pulse) Phase Relation between Trailing Edge of Key Pulse and Middle of Sync. Input Pulse Key Pulse Duration I7 = 5mA f = 31.5kHz Sync width = 2µs OSCILLATOR V12 V12 I12 I12 V13 fO Low Level Threshold Voltage High Level Threshold Voltage Charge Current Discharge Current Reference Voltage on Pin 13 Free Running Frequency fMax. Maximum Oscillator Frequency Jitt. ∆fO ∆I13 Horizontal Jitter Frequency Control Sensitivity ∆fO Frequency Change when VS Drops to 7.5V R13 = 10kΩ R13 = 10kΩ R13 = 10kΩ C12 = 2.2nF R13 = 47kΩ C12 = 2.2nF f = 31.5kHz R13 = 10kΩ C12 = 2.2nF 66 kHz 5 100 ns Hz µA -6 % PHASE COMPARATOR V5 I5 I5 tD ∆t ∆tD Control Voltage Range Peak Control Current Input Current (blocked Phase Detector) Permissible Delay between Output Pulse Leading Edge and Flyback Pulse Leading Edge Static Control Error During flyback pulse Outside flyback pulse 9.4 to 8.2 ± 0.85 5 tp - tf 0.2 V mA µA µs % SYNC PULSE-OSCILLATOR PHASE COMPARATOR V11 I11 ∆f ∆t f Control Voltage Range Control Peak Current Phase Lock Loop Gain During Sync Pulse R11-13 = 100kΩ Catching and Holding Range See Typical Application 4.6 to 1.4 ± 2.3 4 ± 700 V mA kHz µs Hz 1.1 µs tO Phase Relation between Middle of Flyback Pulse and Middle of Sync. Pulse R13 = 10kΩ C12 = 2.2nF ∆V5 ∆tO Adjustment Sensitivity 130 mV µs ∆I5 ∆tO Adjustment Sensitivity 50 µA µs tp tfly Note 3 : td must be ≥ (Hperiod − 0.25 − ) in order to have ± 5% horizontal phase adjustment range. 100 2 4/9 9108-05.TBL OVERALL PHASE RELATIONSHIP TDA9108 Figure 1 : Relation Ship of Main Waveform Phases Flyback Input Pulse tO tf Sync Input Signal Phase Comparator Driving Pulse td Back Porch Clamping Pulse V7K t SK tK tp Hp 100 9108-05.EPS Output Pulse Pin 3 5/9 6/9 or 9108-06.EPS 5 0 0 5 10nF 33kΩ Line sync input : TTL level VCC 10 9 14 1 680nF POLARITY DETECTION SEPARATOR 10nF 4.7kΩ 11 1st PHASE COMPARATOR H-Sync 10kΩ 100kΩ 12 22kΩ 47kΩ Frequency 13 OSCILLATOR INHIBITION VCC min. 2nd PHASE COMPARATOR LINE PULSE DETECTION LINE PULSE GENERATOR SYNC 5 220nF 6 47kΩ 7 Flyback Input LINE 2.2nF THYRISTOR PROTECTION FUNCTION LINE OUT STAGE MONOSTABLE 8 3 2 4 X-Ray Protection 3V Line Output VCC Duty Cycle Adjustment VCC TDA9108 TYPICAL APPLICATION TDA9108 APPLICATION INFORMATION Figure 3 Sync Extractor and Polarity Detection This circuit is able to handle both positive or negative TTL input signal on Pin 9. The voltage on Pin 10 drives an internal inverter providing a constant sync polarity to the 1st phase comparator. When using a RC network between Pin 9 and 10 (see Typical Application), the IC will adapt itself automatically to positive or negative sync. On an other hand, and in order to simplified the application, the Pin 10 can be connected to ground or supply (through a resistor), in this case the IC will work only with one sync polarity. VREF 1/3T T 2nd Phase Locked Loop To compensate the delay introduced by the horizontal final stage, the flyback pulse (Pin 6) and the oscillator waveform (Pin 12) are compared in the 2nd phase comparator. The result of the comparison is a control current which, after it has been filtered by the external capacitor on Pin 5, is sent to a phase shifter which adequately regulates the horizontal output pulses phase. The maximum phase shift allowed is td = tp - tf where tf is the flyback duration (see Figure 4). If td > tp - tf, then the horizontal output transistor will be tunned on during flyback distroying it. Figure 2 PHASE COMPARATOR 9108-08.EPS Pin 12 1st PLL It is composed by a phase comparator, the oscillator and an external loop filter (see Figure 2) - The phase comparator receives the H-sync signal (with positive polarity) and a signal coming from the internal current controlled oscillator. The loop is closed through an external resistor between Pin 11 and 13. - The oscillatorgenerates a sawtooth waveform on Pin 12 by charging and discharging the external capacitor. The capacitor is discharging by the current flowing Pin 13 and charged by two times this latter (see Figure 3). The sawtooth is used internally to generate all the required timings. It is possible to DC control the frequency by adding or substracting a DC current on Pin 13 (see Figure 2). VCO Figure 4 tf 11 13 12 td HORIZONTAL FLYBACK HORIZONTAL BU OFF DRIVE R1 P1 BU ON tp 9108-09.EPS LOOP FILTER 9108-07.EPS H-sync 12 13 HP 7/9 TDA9108 X-Ray Protection Input (Pin 8) When the voltage on this pin becomes higher then 2.9V (typ.), the horizontal outputs are inhibited (Pins 2 and 3) and will remains in this condition until a reset is made on supply voltage (poweroff/power-on). tfly tp (1) Hperiod − 0.25 − ≤ td 100 2 (2) td ≤ 0.36 Hp - tfly - 2µs 2 H-Duty Cycle (see Figure 5) The output duty cycle is variable between 0 and 50% by varying the voltage on Pin 4. In order to maintain ± 5% horizontal phase adjustment possibilities the following equation must be respected. ⇒ If not, tp will decrease because of H-drive trailing edge wrong position (phase shifter saturation) ⇒ If not, tp will decrease because of H-drive leading edge wrong position (phase shifter saturation) Figure 5 VPin 13 H-drive leading edge limit H-drive trailing edge limit Equation (1) HORIZONTAL DRIVE BU OFF Equation (2) HORIZONTAL FLYBACK 8/9 BU OFF 9108-10.EPS HORIZONTAL DRIVE TDA9108 I b1 L a1 PACKAGE MECHANICAL DATA 14 PINS - PLASTIC DIP b B e E Z Z e3 D 8 1 7 a1 B b b1 D E e e3 F i L Z Min. 0.51 1.39 Millimeters Typ. Max. 1.65 Min. 0.020 0.055 0.5 0.25 Inches Typ. 0.065 0.020 0.010 20 0.787 8.5 2.54 15.24 0.335 0.100 0.600 7.1 5.1 0.280 0.201 3.3 1.27 Max. DIP14.TBL Dimensions PM-DIP14.EPS F 14 0.130 2.54 0.050 0.100 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. 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