AGERE TDAT161G2-BA23

Data Sheet
August 18, 2004
MARS®2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Features
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One of the next-generation, system-on-a-chip
devices of Agere Systems’ multiservice access &
rate solutions MARSTM family of framers.
Transmission convergence and SONET/SDH terminal functionality for linear networks.
Versatile IC supports 155/622/2488 Mbits/s
SONET/SDH interface solutions for packet over
SONET (POS), packet over fiber (POF), or asynchronous transfer mode (ATM) applications.
Low-power 1.6 V/3.3 V operation.
SONET/SDH Interface
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Termination of quad STS-3/STM-1,
quad STS-12/STM-4, or single STS-48/STM-16.
Supports overhead processing for transport and
path overhead bytes.
Optional insertion and extraction of overhead bytes
via serial overhead interface.
STS pointer processing to align the receive frame
to the system frame.
Support for 1 + 1 and 1:1 linear networks.
Full path termination and SPE extraction/insertion.
SONET/SDH compliant condition and alarm
reporting.
Handles all concatenation levels of STS-3c to
STS-48c (in multiples of 3: e.g., 3c, 6c, 9c, etc.).
Built-in diagnostic loopback modes.
Compliant with the following Telcordia Technologies®, ANSI®, and ITU standards:
— GR-253 CORE: SONET Transport Systems:
Common Generic Criteria.
— ITU-T G.707: Network Node Interface for the
Synchronous Digital Hierarchy.
— ITU-T G.803: Architecture of Transport Networks Based on the Synchronous Digital Hierarchy.
— T1.105: SONET-Basic Description including
Multiplex Structure, Rates, and Formats.
— T1.105.02 SONET-Payload Mappings.
— T1.105.03 SONET-Jitter at Network Interfaces.
— T1.105.06 SONET Physical Layer Specifications.
— T1.105.07 SONET-Sub-STS-1 Interface Rates
and Formats Specification.
— ITU-T I.432: B-ISDN User-Network InterfacePhysical Layer Specification.
— IETF RFC 2615: PPP over SONET/SDH.
— IETF RFC 1661: The Point-to-Point Protocol
(PPP).
— IETF RFC 1662: PPP in HDLC-like Framing.
Data Processing
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Provisionable data engine supports payload insertion/extraction for PPP, ATM, or HDLC streams.
Extraction and insertion of DS3 frames containing
HDLC or ATM data streams for up to 16 channels.
Integrated UTOPIA Level 2 and Level 3 compatible
physical layer interface for packets or ATM cells.
Provides/supports internal E3 mapping.
Supports DS3/PLCP and clear channel DS3 mapping.
Insertion and extraction of up to 16 separate data
channels.
Direct cell/packet over fiber interface device.
Compliant with ATM forum, ITU standards, and
IETF standards.
Supports generic framing procedure (GFP) protocol.
Interfaces
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Enhanced UTOPIA interface for cell and packet
transfer.
IEEE® 1149.1 port with BIST, scan, and boundry
scan.
Microprocessor Interface
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Up to 66 MHz synchronous.
16-bit address and 16-bit data interface.
Synchronous or asynchronous modes available.
Configurable to operate with most commercial
microprocessors.
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Table of Contents
Contents
Page
Features ................................................................................................................................................................... 1
SONET/SDH Interface ....................................................................................................................................... 1
Data Processing................................................................................................................................................. 1
Interfaces ........................................................................................................................................................... 1
Microprocessor Interface ................................................................................................................................... 1
Description.............................................................................................................................................................. 27
Generic Framing Procedure (GFP) .................................................................................................................. 28
Target Applications Supported ............................................................................................................................... 29
MARS2G5 P-Pro (600-Pin LBGA and 792-Pin PBGA) .................................................................................... 29
MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA) ........................................................................................... 30
MARS622 P-Pro (TDAT12622) (792-Pin PBGA) ............................................................................................. 31
Overview................................................................................................................................................................. 32
Clocking ........................................................................................................................................................... 34
MARS2G5 P-Pro (792-Pin PBGA) Low-Speed Devices Available......................................................................... 36
MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA) ........................................................................................... 36
MARS622 P-Pro (TDAT12622) (792-Pin PBGA) ............................................................................................. 36
MARS2G5 P-Pro Device Product Line Table Summaries...................................................................................... 37
Pin Information ....................................................................................................................................................... 38
792-Pin PBGA Pin Assignments ...................................................................................................................... 38
600-Pin LBGA Pin Assignments ...................................................................................................................... 87
Pin Descriptions...................................................................................................................................................... 97
Microprocessor (MPU) Interface........................................................................................................................... 123
Device Address Space Assignments ............................................................................................................. 123
Microprocessor Interface Modes.................................................................................................................... 124
Microprocessor Interface Timing.................................................................................................................... 125
Necessary Register Provisioning Sequence and Clocks ............................................................................... 133
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers....................................................... 134
Performance Monitor (PM) Reset .................................................................................................................. 158
General-Purpose Input/Output Interface ........................................................................................................ 160
Interrupts ........................................................................................................................................................ 162
Loopback Operation....................................................................................................................................... 163
MPU Register Descriptions ............................................................................................................................ 164
MPU Register Map......................................................................................................................................... 173
Functional Description .......................................................................................................................................... 175
Line Interface........................................................................................................................................................ 176
LVPECL I/O Termination and Load Specifications ........................................................................................ 178
Line Interface I/O Timing................................................................................................................................ 180
Transport Overhead Processor (TOHP-48) Block................................................................................................ 184
Introduction .................................................................................................................................................... 184
TOHP-48 Functional Block Diagram .............................................................................................................. 184
Enhancements ............................................................................................................................................... 186
APSMON and K2MON Processing (Including K1K2 Validation and Pass Through) ..................................... 186
TOHP-48 Receive Direction........................................................................................................................... 187
Transmit Direction (to SONET/SDH line) ....................................................................................................... 197
Receive/Transmit TOHP-48 Interface ............................................................................................................ 204
TOHP-48 Register Descriptions..................................................................................................................... 208
TOHP-48 Register Map ................................................................................................................................. 237
Pointer Processor (PP)......................................................................................................................................... 247
Introduction .................................................................................................................................................... 247
Detailed Description ....................................................................................................................................... 250
PP Register Map Overview ............................................................................................................................ 257
PP Register Descriptions ............................................................................................................................... 258
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Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Table of Contents (continued)
Contents
Page
PP Register Map ............................................................................................................................................ 317
Path Terminator (PT)............................................................................................................................................ 345
Introduction .................................................................................................................................................... 345
SPE Mapper................................................................................................................................................... 346
Supported SPE Formats ................................................................................................................................ 349
SPE Mapper Architecture............................................................................................................................... 352
Transpose Block ............................................................................................................................................ 356
PT Register Descriptions ............................................................................................................................... 357
PT Register Map (Entire PT Except RXT Block)............................................................................................ 385
STS Receive Terminator (RXT) Block.................................................................................................................. 391
Introduction .................................................................................................................................................... 391
Receive Timing Functions.............................................................................................................................. 393
Pointer Interpreter Functions.......................................................................................................................... 394
Concatenation ................................................................................................................................................ 398
RXT Register Descriptions............................................................................................................................. 414
RXT Register Map.......................................................................................................................................... 460
DS3/E3 Block ....................................................................................................................................................... 486
DS3 Functional Description............................................................................................................................ 486
DS3 Transmit Direction .................................................................................................................................. 494
FIFO Block ..................................................................................................................................................... 494
DS3 PLCP Frame/Data Insert........................................................................................................................ 495
DS3 Frame Generate/OH Bit Inserter ............................................................................................................ 497
Transparent Payload Mode (Used in Conjunction with DS3 Mapping) .......................................................... 498
E3 Functional Description .............................................................................................................................. 499
DS3 Register Descriptions ............................................................................................................................. 518
E3 Register Descriptions................................................................................................................................ 550
DS3 Register Map.......................................................................................................................................... 582
E3 Register Map ............................................................................................................................................ 595
Appendix: DS3 to STS-1 Mapping ................................................................................................................. 609
Receive Sequencer (RXS) Block.......................................................................................................................... 611
Introduction .................................................................................................................................................... 611
RXS PRBS Monitor ........................................................................................................................................ 612
RXS Register Descriptions............................................................................................................................. 613
RXS Register Maps........................................................................................................................................ 618
Data Engine Block ................................................................................................................................................ 623
Data Engine Block—Subblocks ..................................................................................................................... 623
Data Engine Block—ATM Framer/Frame Inserter Subblock................................................................................ 624
Overview ........................................................................................................................................................ 624
Capabilities..................................................................................................................................................... 624
Architecture .................................................................................................................................................... 626
Data Engine Block—HDLC Framer and Escaper Subblock ................................................................................. 627
Introduction .................................................................................................................................................... 627
Features ......................................................................................................................................................... 627
Byte-Synchronous Mode................................................................................................................................ 628
Examples of Byte-Synchronous Mode Escaper Operation ............................................................................ 629
Examples of Byte-Synchronous Mode Framer Operation.............................................................................. 631
Bit-Synchronous Mode................................................................................................................................... 632
Examples of Bit-Synchronous Mode Framer Operation................................................................................. 634
Examples of Bit-Synchronous Mode Escaper Operation ............................................................................... 635
Data Engine Block—CRC Generator/Checker Subblock ..................................................................................... 636
Overview ........................................................................................................................................................ 636
Agere Systems Inc.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Table of Contents (continued)
Contents
Page
Receive .......................................................................................................................................................... 636
Transmit ......................................................................................................................................................... 639
Examples of CRC Insertion/Testing ............................................................................................................... 641
Data Engine Block—PPP Detach Subblock ......................................................................................................... 645
PPP Header Detach....................................................................................................................................... 645
Data Engine Block—Data Engine Counter Subblock ........................................................................................... 648
Introduction .................................................................................................................................................... 648
Overview ........................................................................................................................................................ 648
Implementation .............................................................................................................................................. 648
Data Engine Block—Channel Distribution and Allocation Subblock..................................................................... 651
Channel Distribution and Allocation Subblock Description ............................................................................ 651
Operation and Programming of the CDA Maps ............................................................................................. 652
Data Engine Block—GFP General Framing Procedure Subblock........................................................................ 668
Introduction .................................................................................................................................................... 668
Overview ........................................................................................................................................................ 668
GFP Control Messages.................................................................................................................................. 670
GFP Frame Delineation/Frame Insertion ....................................................................................................... 671
GFP Scrambling/Descrambling...................................................................................................................... 673
Packet-Over-Wavelength Mode ..................................................................................................................... 676
Data Engine Block Registers................................................................................................................................ 677
DE Register Descriptions ............................................................................................................................... 677
DE Register Map............................................................................................................................................ 703
UTOPIA (UT) Block .............................................................................................................................................. 716
UTOPIA Interface Features ........................................................................................................................... 716
UTOPIA Modes .............................................................................................................................................. 718
32-Bit Mode Configuration (Necessary Configuration for Proper Operation)................................................. 718
UT Receive Path (Ingress)............................................................................................................................. 721
UT Transmit Path (Egress) ............................................................................................................................ 724
Address Modes and Pin Assignments of MPHY Interfaces ........................................................................... 726
UTOPIA Loopbacks ....................................................................................................................................... 729
Basic Modes of Operations ............................................................................................................................ 730
Mixed Modes of Operations ........................................................................................................................... 739
Reference Configurations .............................................................................................................................. 741
UTOPIA Interface Pin Description ................................................................................................................. 742
FIFO Ganging ................................................................................................................................................ 744
Packet Packing .............................................................................................................................................. 744
Default Channel Configuration ....................................................................................................................... 744
UTOPIA Interface Timing ............................................................................................................................... 745
UT Global Registers....................................................................................................................................... 748
UT Per-Interface Registers ............................................................................................................................ 750
UT Register Map ............................................................................................................................................ 764
System Interface................................................................................................................................................... 772
ATM Interfaces............................................................................................................................................... 772
POS Interfaces............................................................................................................................................... 775
Test....................................................................................................................................................................... 778
Scan ............................................................................................................................................................... 778
Boundary Scan .............................................................................................................................................. 778
RAM BIST ...................................................................................................................................................... 778
GFP Payload Area CRC-32 Insertion (Version 2.2 and 2.3 Only) ................................................................. 786
Introduction .................................................................................................................................................... 793
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Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Figures
Figure
Page
Figure 1. MARS2G5 P-Pro Block Diagram ............................................................................................................ 27
Figure 2. GFP Relationship to Transport Payloads ............................................................................................... 28
Figure 3. MARS2G5 P-Pro Device Interface Speed/Rate Diagram ...................................................................... 29
Figure 4. MARS1G2 P-Pro Device Interface Speed/Rate Diagram ...................................................................... 30
Figure 5. MARS622 P-Pro Device Interface Speed/Rate Diagram ....................................................................... 31
Figure 6. MARS2G5 P-Pro External Interfaces ..................................................................................................... 33
Figure 7. Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode ................................................................ 34
Figure 8. Clock Domains in the Packet-Over-Fiber (POF) Mode .......................................................................... 35
Figure 9. PLL Outputs Lock-In Process ............................................................................................................... 122
Figure 10. Microprocessor Interface Synchronous Write Cycle (MPU_MPMODE (Pin D8) = 1) ......................... 125
Figure 11. Microprocessor Interface Synchronous Read Cycle (MPU_MPMODE (Pin D8) = 1) ........................ 127
Figure 12. Microprocessor Interface Asynchronous Write Cycle Description (MPU_MPMODE (Pin D8) = 0) .... 129
Figure 13. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0) ................................. 131
Figure 14. PM Reset Signal Generation .............................................................................................................. 159
Figure 15. General Input/Output (GPIO) ............................................................................................................. 161
Figure 16. Interrupt Functionality ......................................................................................................................... 162
Figure 17. Loopback Operation ........................................................................................................................... 163
Figure 18. MARS2G5 P-Pro Block Diagram Indicating the Signal Pins per Block .............................................. 175
Figure 19. Line Interface ...................................................................................................................................... 177
Figure 20. LVPECL Load Connections ................................................................................................................ 179
Figure 21. Receive Line-Side Timing Waveform ................................................................................................. 180
Figure 22. Transmit Line-Side Timing Waveform—OC-48 Contraclocking ......................................................... 181
Figure 23. Transmit Line-Side Timing Waveform—OC-48 Forward Clocking ..................................................... 181
Figure 24. Transmit Line-Side Timing Waveform—Frame Sync ......................................................................... 181
Figure 25. High-Level Block Interconnect ............................................................................................................ 184
Figure 26. TOHP-48 Block Diagram (One Channel) ........................................................................................... 185
Figure 27. Time-Slot Assignments ...................................................................................................................... 194
Figure 28. REI-L (MS-REI) Location .................................................................................................................... 202
Figure 29. RTOH Interface .................................................................................................................................. 205
Figure 30. TTOH Interface ................................................................................................................................... 205
Figure 31. STS-3/STM1, STS-12/STM-4, and STS-48/STM-16 Transmit TOAC Interface Timing ..................... 206
Figure 32. STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing .............................................. 206
Figure 33. STS-3/STM-1 Receive TOAC Interface Timing .................................................................................. 207
Figure 34. Signal Degrade and Failure Parameters for BER .............................................................................. 228
Figure 35. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of Pointer Processor ........................ 250
Figure 36. Top Level Block Diagram of the Pointer Processor Block .................................................................. 251
Figure 37. Overview of Pointer Processor Register Map .................................................................................... 257
Figure 38. Path Terminator Block Diagram ......................................................................................................... 345
Figure 39. Block Diagram of SPE Mapper Block ................................................................................................. 346
Figure 40. Direct Mapping into STS SPE ............................................................................................................ 349
Figure 41. STS-Nc SPE ....................................................................................................................................... 349
Figure 42. Asynchronous Mapping of DS3 into STS-1 SPE ................................................................................ 350
Figure 43. Asynchronous Mapping of E3 into STS-1 SPE .................................................................................. 351
Figure 44. STS-48 Frame Structure .................................................................................................................... 352
Figure 45. STS-12 Frame Structure .................................................................................................................... 353
Figure 46. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of STS Receive Terminator ............. 391
Figure 47. STS Receive Terminator (RXT) Functional Block Diagram ............................................................... 392
Figure 48. Interpreter State Machine ................................................................................................................... 394
Figure 49. STS-12 RXT Concatenated Offset Passing ....................................................................................... 398
Figure 50. STS-6 RXT Concatenated Offset Passing ......................................................................................... 398
Figure 51. STS-3 and STS-1 RXT Concatenated Offset Passing ....................................................................... 399
Agere Systems Inc.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
List of Figures (continued)
Figure
Page
Figure 52. STS-6c Offset Passing in an STS-12 RXT ......................................................................................... 399
Figure 53. Concatenated Offset Passing ............................................................................................................. 400
Figure 54. Overview of RXT Register Map .......................................................................................................... 414
Figure 55. DS3 Block Interface Diagram ............................................................................................................. 486
Figure 56. DS3 Receive Subblock ....................................................................................................................... 487
Figure 57. DS3/E3 Mappings .............................................................................................................................. 499
Figure 58. VC-3 Into an AU-3 .............................................................................................................................. 500
Figure 59. Asynchronous Mapping of 34,368 kbits/s Tributary Into VC-3 ........................................................... 501
Figure 60. G.832 E3 Frame Structure at 34,368 kbits/s ...................................................................................... 502
Figure 61. DS3 Multiframe Format ...................................................................................................................... 609
Figure 62. PLCP Mapping of ATM Cells .............................................................................................................. 610
Figure 63. MARS2G5 P-Pro PRBS Monitor/Generator Locations ....................................................................... 612
Figure 64. ATM Cell Format ................................................................................................................................ 624
Figure 65. Alpha-Delta Framer State Machine .................................................................................................... 626
Figure 66. Legend for Escaper Examples ........................................................................................................... 629
Figure 67. Escaping and EOP ............................................................................................................................. 629
Figure 68. Escaping Dry and Abort ..................................................................................................................... 630
Figure 69. Aborting a Dry .................................................................................................................................... 630
Figure 70. Framing and EOP ............................................................................................................................... 631
Figure 71. Framing Dry and Abort ....................................................................................................................... 631
Figure 72. Aborting a Dry .................................................................................................................................... 631
Figure 73. Bit-Synchronous HDLC Framer Operation ......................................................................................... 634
Figure 74. Bit-Synchronous HDLC Abort ............................................................................................................. 634
Figure 75. Bit-Synchronous HDLC Escaper Operation ....................................................................................... 635
Figure 76. Bit-Synchronous HDLC Escaper Abort .............................................................................................. 635
Figure 77. CRC-16 Checker Data Arriving Across Two Words ........................................................................... 636
Figure 78. CRC-32 Check Arriving Across Two Words ....................................................................................... 637
Figure 79. A CRC-16/32 Checker Circuit ............................................................................................................ 638
Figure 80. Normal CRC-16 and CRC-32 Cases .................................................................................................. 639
Figure 81. CRC Generator Block Diagram .......................................................................................................... 640
Figure 82. Assorted CRC Generator Cases ........................................................................................................ 641
Figure 83. Assorted CRC Generator Cases ........................................................................................................ 642
Figure 84. Assorted CRC Checker Cases ........................................................................................................... 643
Figure 85. Assorted CRC Checker Cases ........................................................................................................... 644
Figure 86. DE Counter Block ............................................................................................................................... 649
Figure 87. GFP Encapsulations of Packet Data .................................................................................................. 669
Figure 88. Special-Purpose GFP Header Definitions .......................................................................................... 669
Figure 89. Special-Purpose GFP Header Definitions .......................................................................................... 672
Figure 90. X43 Self-Synchronous Scrambler/Descrambler ................................................................................. 674
Figure 91. X48 Set-Reset Scrambler ................................................................................................................... 675
Figure 92. X48 Scrambler Synchronization State Machine ................................................................................. 676
Figure 93. UT48: Generic Structure of UTOPIA Block ........................................................................................ 717
Figure 94. Receive-Side Interface Handshaking in Point-to-Point Mode (RXPPA as Single Cycle) ................... 723
Figure 95. Transmit-Side Interface Handshaking in Point-to-Point Mode (TXPPA as Single Cycle) .................. 725
Figure 96. Near-End Loopback for Slice D .......................................................................................................... 729
Figure 97. Overall Structure for Receive Direction .............................................................................................. 731
Figure 98. Overall Structure for Transmit Direction ............................................................................................. 732
Figure 99. Four Groups of Multi-PHY Devices of Four Channels for Receive Direction ..................................... 733
Figure 100. Four Groups of Multi-PHY Devices of Four Channels for Transmit Direction .................................. 734
Figure 101. Two Groups of Multi-PHY Devices of Eight Channels for Receive Direction ................................... 735
Figure 102. Two Groups of Multi-PHY Devices of Eight Channels for Transmit Direction .................................. 736
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Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Figures (continued)
Figure
Page
Figure 103. A Multi-PHY Device of 16 Channels for Receive 16-Bit or 8-Bit Modes ........................................... 737
Figure 104. A Multi-PHY Device of 16 Channels of Receive 32-Bit Mode .......................................................... 738
Figure 105. Mixed Modes of Operations for Receive Direction ........................................................................... 739
Figure 106. Mixed Modes of Operation of the Receive Side and the Transmit Side ........................................... 740
Figure 107. Reference Configurations ................................................................................................................. 741
Figure 108. Transmit UTOPIA Interface Timing .................................................................................................. 745
Figure 109. Receive UTOPIA Interface Timing ................................................................................................... 746
Figure 110. Quad 16-Bit ATM Level 2 ................................................................................................................. 772
Figure 111. Quad 8-Bit ATM Level 3 ................................................................................................................... 773
Figure 112. Single 32-Bit ATM Level 3 ................................................................................................................ 774
Figure 113. Quad 16-Bit POS Level 2 ................................................................................................................. 775
Figure 114. Quad 8-Bit POS Level 3 ................................................................................................................... 776
Figure 115. Single 32-Bit POS Level 3 ................................................................................................................ 777
Agere Systems Inc.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
List of Tables
Table
Page
Table 1. List of the Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode.................................................. 34
Table 2. MARS2G5 P-Pro Device Product Line—Data Port Summary.................................................................. 37
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order ....................................... 38
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name............................................................................... 62
Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order....................................................................... 87
Table 6. Pin Assignments for 600-Pin LBGA by Signal Name ............................................................................... 92
Table 7. Pin Descriptions—Line Interface Signals ................................................................................................. 97
Table 8. Pin Descriptions—TOH Interface Signals............................................................................................... 102
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals........................................................................ 104
Table 10. Pin Descriptions—Microprocessor Interface Signals............................................................................ 117
Table 11. Pin Descriptions—General-Purpose I/O Signals: Interface Signals ..................................................... 118
Table 12. Pin Descriptions—JTAG Interface Signals ........................................................................................... 119
Table 13. Pin Descriptions—Power Signals ......................................................................................................... 120
Table 14. PLL Test Outputs.................................................................................................................................. 122
Table 15. Pin Descriptions—No-Connect Pins..................................................................................................... 122
Table 16. Leakage Test Pin.................................................................................................................................. 122
Table 17. Device Address Space Assignment ..................................................................................................... 123
Table 18. MPU Modes.......................................................................................................................................... 124
Table 19. Microprocessor Interface Synchronous Write Cycle Specifications ..................................................... 126
Table 20. Microprocessor Interface Synchronous Read Cycle Specifications ..................................................... 128
Table 21. Microprocessor Interface Asynchronous Write Cycle Specifications.................................................... 130
Table 22. Microprocessor Interface Asynchronous Read Cycle Specifications ................................................... 132
Table 23. PM Reset Signal Provisioning .............................................................................................................. 158
Table 24. MPU_VERR[0—5], Version Control Registers (RO) ............................................................................ 164
Table 25. MPU_ISR, Interrupt Status Register (RO or COR/W) .......................................................................... 165
Table 26. MPU_CNDR, Condition Register (RO)................................................................................................. 166
Table 27. MPU_IMR, Interrupt Mask Register (R/W) ........................................................................................... 166
Table 28. MPU_ICLRR, Interrupt Clear Register (R/W) ....................................................................................... 167
Table 29. MPU_SWRSR, Software Reset Register (R/W)................................................................................... 167
Table 30. MPU_GPIO_CTLR, GPIO Output Value (R/W).................................................................................... 168
Table 31. MPU_PROVISION0, Provisioning Register 0 (R/W) ............................................................................ 168
Table 32. MPU_PROVISION1, Provisioning Register 1 (R/W) ............................................................................ 168
Table 33. MPU_LPBKCTLR, Loopback Control Register (R/W) .......................................................................... 169
Table 34. MPU_GPIOCFG, GPIO Configuration Register (R/W)......................................................................... 169
Table 35. MPU_GPIO_OER[1—2], GPIO Output Enable (R/W).......................................................................... 170
Table 36. MPU_PDN1, Powerdown Register 1 (R/W) ......................................................................................... 171
Table 37. MPU_PDN2, Powerdown Register 2 (R/W) ......................................................................................... 171
Table 38. MPU_PDN3, Powerdown Register 3 (R/W) ......................................................................................... 171
Table 39. MPU_SCRATCHR, Scratch Register (R/W)......................................................................................... 171
Table 40. MPU_TDAT16_MODER, MARS2G5 P-Pro Mode Selection Register (R/W)....................................... 171
Table 41. MPU_LI_MODER, Register (R/W) ....................................................................................................... 172
Table 42. MPU_HSI_TST_CTL, High-Speed Interface Control ........................................................................... 172
Table 43. MPU_HSI_LPBKR, High-Speed Interface Loopback Register............................................................. 172
Table 44. MPU Register Map ............................................................................................................................... 173
Table 45. Line Interface Modes ............................................................................................................................ 177
Table 46. Nominal dc Power for Suggested Terminations ................................................................................... 179
Table 47. Receive Line-Side Timing Specifications ............................................................................................. 182
Table 48. Transmit Line-Side Timing Specifications ............................................................................................ 183
Table 49. Framing Bytes Observed for Framing Integrity..................................................................................... 188
Table 50. TOAC Channel Output Versus Time-Slot Assignment ......................................................................... 195
Table 51. Transport Overhead Bytes Received Via RxTOAC Interface............................................................... 196
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Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Tables (continued)
Table
Page
Table 52. TOAC Channel Input Versus Time-Slot Assignments .......................................................................... 198
Table 53. TTOAC OC-3 Signal Definition............................................................................................................. 198
Table 54. TTOAC OC-12 Signal Definition........................................................................................................... 199
Table 55. TTOAC OC-48 Signal Definition........................................................................................................... 200
Table 56. TTOAC Control Bits.............................................................................................................................. 201
Table 57. Rx/Tx TOHP-48 Interface Rates........................................................................................................... 204
Table 58. Transmit TOAC Interface Timing Specifications................................................................................... 206
Table 59. Receive TOAC Interface Timing Specifications.................................................................................... 207
Table 60. TOHP_MODE_VERR, Mode (R/W) and Block Version (RO)............................................................... 208
Table 61. TOHP_CH_INT, Channel Interrupt (R/W, RO) ..................................................................................... 208
Table 62. TOHP_DLT_EVT[A—D][1—2], 0x0802—0x0809, Delta/Event Registers (COR/COW-RO) ................ 209
Table 63. TOHP_RX_TX_STATE[A—D], 0x080A—0x080D, Receive/Transmit State Registers (RO) ............... 211
Table 64. TOHP_MSK[A—D][1—2], 0x080E—0x0815, Mask Bit Registers (R/W).............................................. 212
Table 65. TOHP_TRG[A—D], 0x0816—0x0819, Trigger Register 0 Æ 1 (R/W) ................................................. 213
Table 66. TOHP_CNTD[A—D][1—2], 0x081A—0x0821, Continuous N-Times Detect (CNTD) Values (R/W) .... 214
Table 67. TOHP_RCTL[A—D][1—2], 0x0822—0x0829, Receive Control [1—2] (R/W) ...................................... 215
Table 68. TOHP_RCTL[A—D][3], 0x082A—0x082D, Receive Control 3 (R/W) .................................................. 218
Table 69. TOHP_TCTL[A—D][1—2], 0x082E—0x0835, Transmit Control [1—2] (R/W) ..................................... 219
Table 70. TOHP_TCTL[A—D][3], 0x0836—0x0839, Transmit Control 3 (R/W) ................................................... 223
Table 71. TOHP_SD_SETR[A—D][1—2], 0x083A—0x0841, Signal Degrade BER Algorithm Set Control
Registers [1—2] (R/W)....................................................................................................................................... 224
Table 72. TOHP_SD_SETR[A—D][3], 0x0842—0x0845, Signal Degrade BER Algorithm Set Control
Register [3] (R/W) .............................................................................................................................................. 224
Table 73. TOHP_SD_CLEARR[A—D][1—2], 0x0846—0x084D, Signal Degrade BER Algorithm Clear
Control Registers [1—2] (R/W) .......................................................................................................................... 225
Table 74. TOHP_SD_CLEARR[A—D][3], 0x084E—0x0851, Signal Degrade BER Algorithm Clear Control
Register [3] (R/W) .............................................................................................................................................. 225
Table 75. TOHP_SF_SETR[A—D][1—2], 0x0852—0x0859, Signal Fail Set BER Algorithm Control
Registers [1—2] (R/W)....................................................................................................................................... 226
Table 76. TOHP_SF_SETR[A—D][3], 0x085A—0x085D, Signal Fail BER Algorithm Set Control
Register [3] (R/W) .............................................................................................................................................. 226
Table 77. TOHP_SF_CLEARR[A—D][1—2], 0x085E—0x0865, Signal Fail BER Algorithm Clear
Control Registers [1—2] (R/W) .......................................................................................................................... 227
Table 78. TOHP_SF_CLEARR[A—D][3], 0x0866—0x0869, Signal Fail BER Algorithm Clear
Control Register [3] (R/W).................................................................................................................................. 227
Table 79. Ns, L, M, and B Values to Set the BER Indicator ................................................................................. 229
Table 80. Ns, L, M, and B Values to Clear the BER Indicator .............................................................................. 230
Table 81. TOHP_B1ECNTR[A—D], 0x086A—0x086D, B1 Error Count (RO) ..................................................... 231
Table 82. TOHP_B2ECNTR[A—D][1—2], 0x086E—0x0875, B2 Error Count (RO) ............................................ 231
Table 83. TOHP_M1ECNTR[A—D][1—2], 0x0876—0x087D, M1 Error Count (RO) ........................................... 231
Table 84. TOHP_TOH_INSR[A—D][1—2], 0x087E—0x0885, Transmit OH Insert Value (R/W)......................... 232
Table 85. TOHP_RMONR[A—D][1—3], 0x0886—0x0891, Receive Monitor Value (RO).................................... 232
Table 86. TOHP_RJ0DMONR[A—D][1—32], 0x0892—0x0911, Receive J0/Z0 Monitor Value Registers (RO) . 233
Table 87. TOHP_TJ0DINSR[A—D][1—32], 0x0912—0x09A9, Transmit J0/Z0 Insert Value Registers (R/W) .... 234
Table 88. TOHP_TZ0DINSR[A—D][1—6], 0x09AA—0x09C1, Transmit Z0 Insert Value Registers (R/W) ......... 235
Table 89. Z0 Byte Ordering STS-48 Mode for Z0-1—Z0-47 ................................................................................ 236
Table 90. Z0 Byte Ordering STS-12 Mode for Z0-1—Z0-11 ................................................................................ 236
Table 91. Z0 Byte Ordering STS-3 Mode for Z0-1—Z0-2 .................................................................................... 236
Table 92. TOHP_SCRATCHR, 0x09C2, TOHP-48 Scratch Register (R/W) ........................................................ 236
Table 93. TOHP-48 Register Map ........................................................................................................................ 237
Table 94. E1/F1 Path Status Definition ................................................................................................................ 249
Agere Systems Inc.
9
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
List of Tables (continued)
Table
Page
Table 95. RDI-P Codes and Interpretation ........................................................................................................... 256
Table 96. PP_IDR, PP Identification Register (RO, Fixed Value) ........................................................................ 258
Table 97. PP_CORWR, PP Clear on Read/Write Register (R/W, Control) .......................................................... 258
Table 98. PP_POH_ALMBNR[1—2], Path Overhead Alarm Status Binning Register (RO) ................................ 259
Table 99. PP_ES_ALMBNBSR, Elastic Store Overrun/Underrun Alarm Status Binning Bytestream A—D (RO) 263
Table 100. PP_TSES_ALMBSR[A—D], Time Slots 1—12 Elastic Store Overrun/Underrun Alarm
Bytestream A—D (RO, COR/COW)................................................................................................................... 263
Table 101. PP_SF_ALMBNBSR, Signal Fail Alarm Status Binning Bytestream A—D (RO) ............................... 263
Table 102. PP_TSSF_ALMBSR[A—D], Time Slots 1—12 Signal Fail Alarm Bytestream
A—D (RO, COR/COW)...................................................................................................................................... 263
Table 103. PP_RDI_ALMBNBSR, Remote Defect Indicator Alarm Status Binning Bytestream A—D (RO)........ 264
Table 104. PP_TSRDI_ALMBSR[A—D], Time Slots 1—12 Remote Defect Indicator Alarm
Bytestream A—D (RO, COR/COW)................................................................................................................... 264
Table 105. PP_PLM_ALMBNBSR, Payload Label Mismatch Alarm Status Binning Bytestream A—D (RO) ...... 264
Table 106. PP_TSPLM_ALMBSR[A—D], Time Slots 1—12 Payload Label Mismatch Alarm
Bytestream A—D (RO, COR/COW)................................................................................................................... 264
Table 107. PP_UNEQR_ALMBNBSR, Unequipped Received Alarm Status Binning Bytestream A—D (RO) .... 265
Table 108. PP_TSUNEQR_ALMBSR[A—D], Time Slots 1—12 Unequipped Received Alarm
Bytestream A—D (RO, COR/COW)................................................................................................................... 265
Table 109. PP_AIS_ALMBNBSR, Alarms Indicator Signal Alarm Status Binning Bytestream A—D (RO) .......... 265
Table 110. PP_TSAIS_ALMBSR[A—D], Time Slots 1—12 Alarms Indicator Signal Alarm Bytestream
A—D (RO, COR/COW)...................................................................................................................................... 265
Table 111. PP_LOP_ALMBNBSR, Loss of Pointer Alarm Status Binning Bytestream A—D (RO)...................... 266
Table 112. PP_TSLOP_ALMBSR[A—D], Time Slots 1—12 Loss of Pointer Alarm Bytestream A—D
(RO, COR/COW) ............................................................................................................................................... 266
Table 113. PP_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning
Bytestream A—D (RO, COR/COW)................................................................................................................... 267
Table 114. PP_USCNCTM_ALMBNBSR, Channel Path Unsupported Concatenation Map Alarm Binning
Bytestream A—D (RO, COR/COW)................................................................................................................... 267
Table 115. PP_J1NVLDMSG_ALMBNBSR, Channel Path J1 New Validated Message Alarm Binning Bytestream
A—D (RO, COR/COW)...................................................................................................................................... 267
Table 116. PP_J1MSGMM_ALMBNBSR, Channel Path J1 Message Mismatch Alarm Status Binning Bytestream
A—D (RO, COR/COW)...................................................................................................................................... 267
Table 117. PP_PDI_ALMBNBSR, Payload Defect Indicator Alarm Status Binning Bytestream A—D (RO)........ 268
Table 118. PP_TSPDI_ALMBSR[A—D], Time Slots 1—12 Payload Defect Indicator Alarm Bytestream
A—D (RO, COR/COW)...................................................................................................................................... 268
Table 119. PP_RDI_ALMDBNBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 268
Table 120. PP_TSRDI_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Remote Defect Indicator Alarm
Delta Bytestream A—D (RO, COR/COW) ......................................................................................................... 268
Table 121. PP_PLM_ALMDBNBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 269
Table 122. PP_TSPLM_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Label
Mismatch Alarm Delta Bytestream A—D (RO, COR/COW) .............................................................................. 269
Table 123. PP_UNEQR_ALMDBNBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 269
Table 124. PP_TSUNEQR_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Unequipped Received
Alarm Delta Bytestream A—D (RO, COR/COW)............................................................................................... 269
Table 125. PP_AIS_ALMDBNBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 270
10
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Tables (continued)
Table
Page
Table 126. PP_TSAIS_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Alarm Indicator Signal Alarm
Delta Bytestream A—D (RO, COR/COW) ......................................................................................................... 270
Table 127. PP_LOP_ALMDBNBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 270
Table 128. PP_TSLOP_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Loss of Pointer Alarm Delta
Bytestream A—D (RO, COR/COW)................................................................................................................... 270
Table 129. PP_PTRACCMPIR, Path Trace Access Complete Interrupt (RO, COR/COW) ................................. 271
Table 130. PP_PDI_ALMDBNBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 271
Table 131. PP_TSPDI_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Defect
Indicator Alarm Delta Bytestream A—D (RO, COR/COW) ................................................................................ 271
Table 132. STS-1 #12 Channel Path Alarm Binning Status Registers (RO) ........................................................ 272
Table 133. STS-1 Channel Path SS New Validated Bits Alarm Status Binning Bytestream A—D (RO) ............. 273
Table 134. STS-1 Channel Path Time Slots 1—12 SS New Validated Bits Alarm Status Bytestream
A—D (RO, COR/COW)...................................................................................................................................... 273
Table 135. STS-1 Channel Path SS Bits Mismatch Alarm Status Binning Bytestream A—D (RO) ..................... 273
Table 136. STS-1 Channel Path Time Slots 1—12 SS Bits Mismatch Alarm Status Bytestream A—D
(RO, COR/COW) ............................................................................................................................................... 273
Table 137. PP_POH_ALMBNMR[1—2], Path Overhead Alarm Status Binning Masks (R/W) ............................. 274
Table 138. PP_ES_ALMBNMBSR, Elastic Store Overrun/Underrun Alarm Status Binning Masks
Bytestream A—D (R/W)..................................................................................................................................... 277
Table 139. PP_TSES_ALMMBSR[A—D], Time Slots 1—12 Elastic Store Overrun/Underrun Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 277
Table 140. PP_SF_ALMBNMBSR, Signal Fail Alarm Status Binning Masks Bytestream A—D (R/W) ............... 277
Table 141. PP_TSSF_ALMMBSR[A—D], Time Slots 1—12 Signal Fail Alarm Masks Bytestream A—D (R/W) . 277
Table 142. PP_RDI_ALMBNMBSR, Remote Defect Indicator Alarm Status Binning Masks Bytestream
A—D (R/W) ........................................................................................................................................................ 278
Table 143. PP_TSRDI_ALMMBSR[A—D], Time Slots 1—12 Remote Defect Indicator Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 278
Table 144. PP_PLM_ALMBNMBSR, Payload Label Mismatch Alarm Status Binning Masks Bytestream
A—D (R/W) ........................................................................................................................................................ 278
Table 145. PP_TSPLM_ALMMBSR[A—D], Time Slots 1—12 Payload Label Mismatch Alarm Masks Bytestream
A—D (R/W) ........................................................................................................................................................ 278
Table 146. PP_UNEQR_ALMBNMBSR, Unequipped Received Alarm Status Binning Masks
Bytestream A—D (R/W)..................................................................................................................................... 279
Table 147. PP_TSUNEQR_ALMMBSR[A—D], Time Slots 1—12 Unequipped Received Alarm Masks Bytestream
A—D (R/W) ........................................................................................................................................................ 279
Table 148. PP_AIS_ALMBNMBSR, Alarms Indicator Signal Alarm Status Binning Masks
Bytestream A—D (R/W)..................................................................................................................................... 279
Table 149. PP_TSAIS_ALMMBSR[A—D], Time Slots 1—12 Alarms Indicator Signal Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 279
Table 150. PP_LOP_ALMBNMBSR, Loss of Pointer Alarm Status Binning Masks Bytestream A—D (R/W)...... 280
Table 151. PP_TSLOP_ALMMBSR[A—D], Time Slots 1—12 Loss of Pointer Alarm Masks Bytestream
A—D (R/W) ........................................................................................................................................................ 280
Table 152. PP_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks
Bytestream A—D (R/W)..................................................................................................................................... 281
Table 153. PP_USCNCTM_ALMMBSR, Channel Path Unsupported Concatenation Map Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 281
Table 154. PP_J1NVLDMSG_ALMMBSR, Channel Path J1 New Validated Message Alarm Masks
Bytestream A—D(R/W)...................................................................................................................................... 281
Agere Systems Inc.
11
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
List of Tables (continued)
Table
Page
Table 155. PP_J1MSGMM_ALMMBSR, Channel Path J1 Message Mismatch Alarm Status Masks
Bytestream A—D (R/W)..................................................................................................................................... 281
Table 156. PP_PDI_ALMBNMBSR, Payload Defect Indicator Alarm Status Binning Masks
Bytestream A—D (R/W)..................................................................................................................................... 282
Table 157. PP_TSPDI_ALMMBSR[A—D], Time Slots 1—12 Payload Defect Indicator Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 282
Table 158. PP_RDI_ALMDBNMBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status Binning
Masks Bytestream A—D (R/W) ......................................................................................................................... 283
Table 159. PP_TSRDI_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Remote Defect Indicator
Alarm Delta Masks Bytestream A—D (R/W)...................................................................................................... 283
Table 160. PP_PLM_ALMDBNMBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status Binning
Masks Bytestream A—D (R/W) ......................................................................................................................... 283
Table 161. PP_TSPLM_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Label Mismatch
Alarm Delta Masks Bytestream A—D (R/W)...................................................................................................... 283
Table 162. PP_UNEQR_ALMDBNMBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status Binning
Masks Bytestream A—D (R/W) ......................................................................................................................... 284
Table 163. PP_TSUNEQR_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Unequipped Received
Alarm Delta Masks Bytestream A—D (R/W)...................................................................................................... 284
Table 164. PP_AIS_ALMDBNMBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning
Masks Bytestream A—D (R/W) ......................................................................................................................... 285
Table 165. PP_TSAIS_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Alarm Indicator Signal Alarm
Delta Masks Bytestream A—D (R/W) ................................................................................................................ 285
Table 166. PP_LOP_ALMDBNMBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning Masks
Bytestream A—D (R/W)..................................................................................................................................... 285
Table 167. PP_TSLOP_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Loss of Pointer Alarm Delta
Masks Bytestream A—D (R/W) ......................................................................................................................... 285
Table 168. PP_PTRACCMPIR, Path Trace Access Complete Interrupt Mask (R/W) .......................................... 286
Table 169. STS-1 Channel Path SS Bits Mismatch Alarm Status Binning Masks Bytestream A—D (R/W) ........ 286
Table 170. STS-1 Channel Path Time Slots 1—12 SS Bits Mismatch Alarm Status Binning Masks
Bytestream A—D (R/W)..................................................................................................................................... 286
Table 171. PP_PDI_ALMDBNMBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning
Masks Bytestream A—D (R/W) ......................................................................................................................... 287
Table 172. PP_TSPDI_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Defect Indicator
Alarm Delta Masks Bytestream A—D (R/W)...................................................................................................... 287
Table 173. STS-1 #12 Channel Path Alarm Binning Mask Status Registers (R/W)............................................. 288
Table 174. STS-1 Channel Path SS New Validated Bits Alarm Binning Masks Bytestream A—D (R/W)............ 289
Table 175. STS-1 Channel Path Time Slots 1—12 SS New Validated Bits Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 289
Table 176. PP_PTRBFR[1—32], Path Trace Buffer Registers 1—32 (R/W) ....................................................... 290
Table 177. PP_PTRACCTLR1, Path Trace Access Control Register 1 (R/W)..................................................... 290
Table 178. PP_PTRACCTLR2, Path Trace Access Control Register 2 (R/W)..................................................... 290
Table 179. PP_PTRACCTLR3, Path Trace Access Control Register 3 (R/W)..................................................... 290
Table 180. PP_PTRACBGR, Path Trace Access Begin (WO)............................................................................. 290
Table 181. PP_STS12PTRCTLR[1—6], STS-12 Channel Path Trace Control Registers 1—6 (R/W)................. 291
Table 182. STS-12 F2, H4, Z3, Z4, and Z5 Status (RO) ...................................................................................... 292
Table 183. Path F2, H4, Z3, Z4, and Z5 Provisioning Bytestream A—D (R/W, Control) ..................................... 293
Table 184. STS-12 SS Bits Status (RO)............................................................................................................... 294
Table 185. PP_TSRDI_ALMPSBSR[A—D], Time Slots 1—12 RDI Alarm Persistency Bytestream A—D (RO) . 296
Table 186. PP_TSPLM_ALMPSBSR[A—D], Time Slots 1—12 PLM Alarm Persistency Bytestream A—D (RO) 296
Table 187. PP_TSPUNEQ_ALMPSBSR[A—D], Time Slots 1—12 Path Unequipped Alarm Persistency
Bytestream A—D (RO) ...................................................................................................................................... 296
12
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Tables (continued)
Table
Page
Table 188. PP_TSAIS_ALMPSBSR[A—D], Time Slots 1—12 AIS Alarm Persistency Bytestream A—D (RO) .. 297
Table 189. PP_TSLOP_ALMPSBSR[A—D], Time Slots 1—12 LOP Alarm Persistency Bytestream A—D (RO) 297
Table 190. PP_TSPDI_ALMPSBSR[A—D], Time Slots 1—12 PDI Alarm Persistency Bytestream A—D (RO) .. 297
Table 191. PP_TSRDI_STBSR[A—D], Time Slots 1—12 RDI State Bytestream A—D (RO).............................. 298
Table 192. PP_TSPLM_STBSR[A—D], Time Slots 1—12 PLM State Bytestream A—D (RO) ........................... 298
Table 193. PP_TSPUNEQ_STBSR[A—D], Time Slots 1—12 Path Unequipped State Bytestream A—D (RO) . 298
Table 194. PP_TSAIS_STBSR[A—D], Time Slots 1—12 AIS State Bytestream A—D (RO) .............................. 299
Table 195. PP_TSLOP_STBSR[A—D], Time Slots 1—12 LOP State Bytestream A—D (RO)............................ 299
Table 196. PP_TSPDI_STBSR[A—D], Time Slots 1—12 PDI State Bytestream A—D (RO) .............................. 299
Table 197. PP_SFWSZ_SELR[1—2], Signal Fail Window Size Select Registers 1—2 (R/W, Control) ............... 300
Table 198. PP_SFDR[0—7], Signal Fail Detect Threshold Registers 0—7 (R/W, Control) ................................. 301
Table 199. PP_SFCLRR[0—7], Signal Fail Clear Threshold Registers 0—7 (R/W, Control)............................... 302
Table 200. PP_SFWSZR[0—3], Signal Fail Window Size 0/1/2/3 Registers (R/W, Control) ............................... 302
Table 201. PP_ECNCTM_TSBSR[A—D], Expected Concatenation Map Time Slots 1—12 in
Bytestream A—D (R/W)..................................................................................................................................... 303
Table 202. PP_CNCTCPREN_TSBSR[A—D], Concatenation Compare Enable Time Slots 1—12 in
Bytestream A—D (R/W)..................................................................................................................................... 303
Table 203. PP_RCNCTM_TSBSR[A—D], Received Concatenation Map Time Slots 1—12 in
Bytestream A—D (RO) ...................................................................................................................................... 303
Table 204. PP_SWAIS_ISRTR, Software AIS Insert (R/W) ................................................................................. 304
Table 205. PP_STS12_PINCDECR, STS-12 Pointer Increment/Decrement (R/W) ............................................ 304
Table 206. PP_TSSS_ISRTBSR[A—D], Time Slot 1—Time Slot 12 SS Bits Insert Bytestream A—D (R/W) ..... 304
Table 207. PP_TSE1F1_ISRTBSR[A—D], Time Slot 1—Time Slot 12 E1/F1 Insert Bytestream A—D (R/W).... 304
Table 208. PP_E2_ISRTCTLR[A—D], E2 Insert Control Bytestream A—D (R/W) .............................................. 305
Table 209. PP_TS_INCDECBNR[A—D], Time Slots 1—12 Increment/Decrement Binning Select
Bytestream A—D (R/W)..................................................................................................................................... 305
Table 210. PP_AISONTIM_ISRTR[A—D], STS-12 Pointer Processor Control (R/W) ......................................... 305
Table 211. PP_TSPDIVLD_CTLBSR[A—D], Time Slot 1—Time Slot 12 PDI Validate Control Bytestream
A—D (R/W) ........................................................................................................................................................ 306
Table 212. PP_EXPC2_PVSNR[1—24], Expected C2 Byte Provisioning (R/W) ................................................. 306
Table 213. PP_TSCBB_ERRBSR[A—D], Time Slot 1—Time Slot 12 Count Block/Bit Errors Bytestream A—D 306
Table 214. PP_TS1_6_SSBSRA, PP_TS7_12_SSBSRA, Time Slots 1—12 SS Bits Insertion Value
Bytestream A (R/W) ........................................................................................................................................... 307
Table 215. PP_TS1_6_SSBSRB, PP_TS7_12_SSBSRB, Time Slots 1—12 SS Bits Insertion Value
Bytestream B (R/W) ........................................................................................................................................... 307
Table 216. PP_TS1_6_SSBSRC, PP_TS7_12_SSBSRC, Time Slots 1—12 SS Bits Insertion Value
Bytestream C (R/W)........................................................................................................................................... 308
Table 217. PP_TS1_6_SSBSRD, PP_TS7_12_SSBSRD, Time Slots 1—12 SS Bits Insertion Value
Bytestream D (R/W)........................................................................................................................................... 308
Table 218. SS Bits Provisioning (R/W)................................................................................................................. 309
Table 219. SS Bits Validation/Compare Period (R/W) ......................................................................................... 309
Table 220. Elastic Store Decrement and Increment (R/W) .................................................................................. 309
Table 221. Elastic Store Overflow Region (R/W) ................................................................................................. 309
Table 222. PP_TS_E1F1ISRTR[1—24], Time Slots 1—48 E1/F1 Insert ............................................................. 309
Table 223. PP_E2_ISRTBSR[A—D], E2 Byte Insert Bytestream A—D............................................................... 309
Table 224. PP_TSMNTR[1—48], Time Slots 1—48 Maintenance (R/W)............................................................. 310
Table 225. PP_PI_LSECINCR[A—D], Pointer Interpreter Last Second Increments Bytestream A—D (RO) ...... 310
Table 226. PP_PI_LSECDECR[A—D], Pointer Interpreter Last Second Decrements Bytestream A—D (RO) ... 310
Table 227. PP_PG_LSECINCR[A—D], Pointer Generator Last Second Increments Bytestream A—D (RO) ..... 310
Table 228. PP_PG_LSECDECR[A—D], Pointer Generator Last Second Decrements Bytestream A—D (RO) .. 310
Table 229. PP_POH_ALMPMR, Path Overhead Alarm Performance Monitoring (RO) ....................................... 311
Agere Systems Inc.
13
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
List of Tables (continued)
Table
Page
Table 230. PP_1BRDI_DPMBSR, Path Overhead One-Bit RDI Defect PM Bytestream A—D (RO)................... 312
Table 231. PP_TS1BRDI_DPMBSR[A—D], Path Overhead Time Slots 1—12 One-Bit RDI Defect PM Bytestream
A—D (RO).......................................................................................................................................................... 312
Table 232. PP_ERDI_PDPMBSR, Path Overhead ERDI Payload Defect PM Bytestream A—D (RO) ............... 312
Table 233. PP_TSERDI_PDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Payload Defect PM Bytestream
A—D (RO).......................................................................................................................................................... 312
Table 234. PP_ERDI_CDPMBSR, Path Overhead ERDI Connectivity Defect PM Bytestream A—D (RO) ........ 313
Table 235. PP_TSERDI_CDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Connectivity Defect PM
Bytestream A—D (RO) ...................................................................................................................................... 313
Table 236. PP_ERDI_SDPMBSR, Path Overhead ERDI Server Defect PM Bytestream A—D (RO).................. 313
Table 237. PP_TSERDI_SDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Server Defect PM Bytestream
A—D (RO).......................................................................................................................................................... 313
Table 238. PP_UNEQR_PMBSR, Path Overhead Unequipped Received PM Bytestream A—D (RO) .............. 314
Table 239. PP_TSUNEQR_PMBSR[A—D], Path Overhead Time Slots 1—12 Unequipped Received PM
Bytestream A—D (RO) ...................................................................................................................................... 314
Table 240. PP_AIS_PMBSR, Path Overhead Alarm Indicator Signal PM Bytestream A—D (RO)...................... 314
Table 241. PP_TSAIS_PMBSR[A—D], Path Overhead Time Slots 1—12 Alarm Indicator Signal PM
Bytestream A—D (RO) ...................................................................................................................................... 314
Table 242. PP_LOP_PMBSR, Path Overhead Loss of Pointer PM Bytestream A—D (RO)................................ 315
Table 243. PP_TSLOP_PMBSR[A—D], Path Overhead Time Slots 1—12 Loss of Pointer PM
Bytestream A—D (RO) ...................................................................................................................................... 315
Table 244. PP_LSECCVP_CPMR[1—48], Last Second CV-P Count Time Slot 1—Time Slot 48 PM (RO) ....... 315
Table 245. PP_LSECREIP_CPMR[1—48], Last Second REI-P Count Time Slot 1—Time Slot 48 PM (RO) ..... 315
Table 246. PP_TSRDIPR[1—48], Time Slots 1—48 Path RDI Status (RO) ........................................................ 316
Table 247. PP_TSC2R[1—24], Time Slots 1—48 Path C2 Status (RO).............................................................. 316
Table 248. PP_TSPDIR[1—24], Time Slots 1—48 Path PDI Status (RO) ........................................................... 316
Table 249. Pointer Processor Register Map......................................................................................................... 317
Table 250. STS-48 Time-Slot Assignments ......................................................................................................... 346
Table 251. STS-12 Time-Slot Assignments ................................................................................................. 347
Table 252. STS-3 Time-Slot Assignments ........................................................................................................... 347
Table 253. Sequence Register Map TS[0—23]_PM_[A—D]................................................................................ 348
Table 254. Logical 16-Channel Configuration Concatenation Register Map CH[0—15]_NC............................... 348
Table 255. C2 Path Signal Label.......................................................................................................................... 354
Table 256. G1 RDI-P Codes................................................................................................................................. 355
Table 257. STS-48 Time-Slot Internal Ordering ................................................................................................... 356
Table 258. (PT_TX_VERSION), Version Control (RO) ........................................................................................ 357
Table 259. (PT_TX_CH_INT), Tx Channel Composite Interrupt (RO) ................................................................. 357
Table 260. (PT_TX_TS_[A—D]_INT), Tx Time-Slot Composite Interrupt (RO) ................................................... 357
Table 261. (PT_TX_CH_INTMASK), Tx Channel Composite Interrupt Mask (R/W)............................................ 357
Table 262. (PT_TX_TS[A—D]_INTMASK), Tx Time-Slot Composite Interrupt Mask (R/W)................................ 357
Table 263. (PT_TX_MODE), Mode (R/W)............................................................................................................ 358
Table 264. (PT_TX_BANKAorB), Tx_BANKAorB (R/W) ...................................................................................... 359
Table 265. (PT_TX_SCRATCH), SCRATCH (R/W)............................................................................................. 359
Table 266. (PT_TX_SOFTRST), Tx Channel FIFO Reset (R/W)......................................................................... 359
Table 267. (PT_TX_CH_DELTA [0—15]), Tx Channel Delta/Event (COR/W)..................................................... 360
Table 268. (PT_Tx_TS_[A—D]_Delta), Tx Delta/Event Register (COR/W) ......................................................... 360
Table 269. (PT_Tx_CH_Status_[0—15]), Transmit Status Register (RO) ........................................................... 360
Table 270. (PT_TX_TS_[A—D]0_Status), Transmit Status Register (RO) .......................................................... 361
Table 271. (PT_TX_TS_[A—D]1_Status), Transmit Status Register (RO) .......................................................... 361
Table 272. (PT_TX_TS_[A—D]2_Status), Transmit Status Register (RO) .......................................................... 361
Table 273. (PT_Tx_CH_Mask_[0—15]), Tx Channel Mask Register (R/W) ........................................................ 362
14
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Tables (continued)
Table
Page
Table 274. (PT_Tx_TS_[A—D]_Mask), Tx Mask Register (COR/W) ................................................................... 362
Table 275. (PT_Tx_Mask_A_[1—6]), Transmit Provisioning Register (R/W)....................................................... 363
Table 276. (PT_Tx_Mask_B_[1—6]), Transmit Provisioning Register (R/W)....................................................... 364
Table 277. (PT_Tx_Mask_C_[1—6]), Transmit Provisioning Register (R/W) ...................................................... 365
Table 278. (PT_Tx_Mask_D_[1—6]), Transmit Provisioning Register (R/W) ...................................................... 366
Table 279. (PT_Tx_RW4_[0—15]), Transmit Provisioning Register 4 (R/W)....................................................... 367
Table 280. (PT_Tx_RW1_[0—47]), Transmit Provisioning Register, Per Time Slot (R/W) .................................. 367
Table 281. (PT_Tx_RW2_[0—15]), Transmit Provisioning Register, Per Channel (R/W).................................... 367
Table 282. (PT_Tx_RW3_[0—15]), Transmit Provisioning Register 3 (R/W)....................................................... 367
Table 283. (PT_Tx_alarm_[A—D]_[1]]), TX Alarm Mapper Register 1 (R/W) ...................................................... 368
Table 284. (PT_Tx_alarm_[A—D]_[2]]), TX Alarm Mapper Register 2 (R/W) ...................................................... 368
Table 285. (PT_Tx_alarm_[A—D]_[3]]), TX Alarm Mapper Register 3 (R/W) ...................................................... 369
Table 286. (PT_Tx_alarm_[A—D]_[4]]), TX Alarm Mapper Register 4 (R/W) ...................................................... 369
Table 287. (PT_Tx_alarm_[A—D]_[5]]), TX Alarm Mapper Register 5 (R/W) ...................................................... 370
Table 288. (PT_Tx_alarm_[A—D]_[6]]), TX Alarm Mapper Register 6 (R/W) ...................................................... 370
Table 289. (PT_Tx_RW5_[0—15]), Transmit Provisioning Register 5 (R/W)....................................................... 371
Table 290. (PT_Tx_TIMP_[A—D]), TX TIMP Alarm Register, Per Time Slot (R/W) ............................................ 371
Table 291. (PT_Tx_DS3E3_[A—B]), Transmit Provisioning Register (R/W) ....................................................... 372
Table 292. (PT_Tx_STS1_[A—D]), Transmit Provisioning Register (R/W).......................................................... 372
Table 293. (PT_Tx_Cnfg_Alow), Transmit STS Configuration, Time Slots 0—5 (R/W) ....................................... 373
Table 294. (PT_Tx_Cnfg_Ahigh), Transmit STS Configuration, Time Slots 6—11 (R/W) ................................... 373
Table 295. (PT_Tx_Cnfg_Blow), Transmit STS Configuration, Time Slots 0—5 (R/W) ....................................... 374
Table 296. (PT_Tx_Cnfg_Bhigh), Transmit STS Configuration, Time Slots 6—11 (R/W) ................................... 374
Table 297. (PT_Tx_Cnfg_Clow), Transmit STS Configuration, Time Slots 0—5 (R/W)....................................... 375
Table 298. (PT_Tx_Cnfg_Chigh), Transmit STS Configuration, Time Slots 6—11 (R/W) ................................... 375
Table 299. (PT_Tx_Cnfg_Dlow), Transmit STS Configuration, Time Slots 0—5 (R/W)....................................... 376
Table 300. (PT_Tx_Cnfg_Dhigh), Transmit STS Configuration, Time Slots 6—11 (R/W) ................................... 376
Table 301. (PT_Tx_Stuffbyte_cnfg]), Tx Stuff Byte Configuration Register (R/W)............................................... 377
Table 302. (PT_TX_SEQMAP_A_AB[0—11]), Sequence Map, Bank A, Slices A and B, Per Time Slot (R/W) .. 378
Table 303. (PT_TX_SEQMAP_B_AB[0—11]), Sequence Map, Bank B, Slices A and B, Per Time Slot (R/W) .. 379
Table 304. (PT_TX_SEQMAP_A_CD[0—11]), Sequence Map, Bank A, Slices C and D, Per Time Slot (R/W).. 380
Table 305. (PT_TX_SEQMAP_B_CD[0—11]), Sequence Map, Bank B, Slices C and D, Per Time Slot (R/W).. 381
Table 306. (PT_Tx_J1Byte_start_0_[0—31]), Transmit J1 Byte Message Channel 0 (R/W)............................... 382
Table 307. (PT_Tx_J1Byte_start_1_[0—31]), Transmit J1 Byte Message Channel 1 (R/W)............................... 382
Table 308. (PT_Tx_J1Byte_start_2_[0—31]), Transmit J1 Byte Message Channel 2 (R/W)............................... 382
Table 309. (PT_Tx_J1Byte_start_3_[0—31]), Transmit J1 Byte Message Channel 3 (R/W)............................... 382
Table 310. (PT_Tx_J1Byte_start_4_[0—31]), Transmit J1 Byte Message Channel 4 (R/W)............................... 382
Table 311. (PT_Tx_J1Byte_start_5_[0—31]), Transmit J1 Byte Message Channel 5 (R/W)............................... 383
Table 312. (PT_Tx_J1Byte_start_6_[0—31]), Transmit J1 Byte Message Channel 6 (R/W)............................... 383
Table 313. (PT_Tx_J1Byte_start_7_[0—31]), Transmit J1 Byte Message Channel 7 (R/W)............................... 383
Table 314. (PT_Tx_J1Byte_start_8_[0—31]), Transmit J1 Byte Message Channel 8 (R/W)............................... 383
Table 315. (PT_Tx_J1Byte_start_9_[0—31]), Transmit J1 Byte Message Channel 9 (R/W)............................... 383
Table 316. (PT_Tx_J1Byte_start_10_[0—31]), Transmit J1 Byte Message Channel 10 (R/W)........................... 383
Table 317. (PT_Tx_J1Byte_start_11_[0—31]), Transmit J1 Byte Message Channel 11 (R/W)........................... 384
Table 318. (PT_Tx_J1Byte_start_12_[0—31]), Transmit J1 Byte Message Channel 12 (R/W)........................... 384
Table 319. (PT_Tx_J1Byte_start_13_[0—31]), Transmit J1 Byte Message Channel 13 (R/W)........................... 384
Table 320. (PT_Tx_J1Byte_start_14_[0—31]), Transmit J1 Byte Message Channel 14 (R/W)........................... 384
Table 321. (PT_Tx_J1Byte_start_15_[0—31]), Transmit J1 Byte Message Channel 15 (R/W)........................... 384
Table 322. PT Register Map................................................................................................................................. 385
Table 323. Path Overhead Extraction Compare Values....................................................................................... 393
Table 324. Set/Clear Threshold and Window Settings......................................................................................... 403
Agere Systems Inc.
15
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
List of Tables (continued)
Table
Page
Table 325. Default Signal Fail Window Size Settings........................................................................................... 408
Table 326. STS Path Signal Label Assignments.................................................................................................. 410
Table 327. Payload Label Conditions................................................................................................................... 411
Table 328. RDI-P Codes and Interpretation ......................................................................................................... 412
Table 329. RXT_IDR, RXT Identification Register (RO, Fixed Value).................................................................. 415
Table 330. PP_CORWR, PP Clear on Read/Write Register (R/W, Control) ........................................................ 415
Table 331. RXT_POH_ALMBNR[1—2], Path Overhead Alarm Status Binning Register (RO) ............................ 416
Table 332. RXT_SF_ALMBNBSR, Signal Fail Alarm Status Binning Bytestream A—D (RO) ............................. 419
Table 333. RXT_TSSF_ALMBSR[A—D], Time Slots 1—12 Signal Fail Alarm Bytestream A—D
(RO, COR/COW) ............................................................................................................................................... 419
Table 334. RXT_RDI_ALMBNBSR, Remote Defect Indicator Alarm Status Binning Bytestream A—D (RO) ..... 419
Table 335. RXT_TSRDI_ALMBSR[A—D], Time Slots 1—12 Remote Defect Indicator Alarm
Bytestream A—D (RO, COR/COW)................................................................................................................... 419
Table 336. RXT_PLM_ALMBNBSR, Payload Label Mismatch Alarm Status Binning Bytestream A—D (RO).... 420
Table 337. RXT_TSPLM_ALMBSR[A—D], Time Slots 1—12 Payload Label Mismatch Alarm
Bytestream A—D (RO, COR/COW)................................................................................................................... 420
Table 338. RXT_UNEQR_ALMBNBSR, Unequipped Received Alarm Status Binning Bytestream A—D (RO) .. 420
Table 339. RXT_TSUNEQR_ALMBSR[A—D], Time Slots 1—12 Unequipped Received Alarm Bytestream A—D
(RO, COR/COW) ............................................................................................................................................... 420
Table 340. RXT_AIS_ALMBNBSR, Alarms Indicator Signal Alarm Status Binning Bytestream A—D (RO)........ 421
Table 341. PP_TSAIS_ALMBSR[A—D], Time Slots 1—12 Alarms Indicator Signal Alarm Bytestream
A—D (RO, COR/COW)...................................................................................................................................... 421
Table 342. RXT_LOP_ALMBNBSR, Loss of Pointer Alarm Status Binning Bytestream A—D (RO) ................... 421
Table 343. RXT_TSLOP_ALMBSR[A—D], Time Slots 1—12 Loss of Pointer Alarm Bytestream A—D
(RO, COR/COW) ............................................................................................................................................... 421
Table 344. RXT_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning
Bytestream A—D (RO, COR/COW)................................................................................................................... 422
Table 345. RXT_USCNCTM_ALMBNBSR, Channel Path Unsupported Concatenation Map Alarm Binning
Bytestream A—D (RO, COR/COW)................................................................................................................... 422
Table 346. RXT_J1NVLDMSG_ALMBNBSR, Channel Path J1 New Validated Message Alarm Binning
Bytestream A—D (RO, COR/COW)................................................................................................................... 422
Table 347. RXT_J1MSGMM_ALMBNBSR, Channel Path J1 Message Mismatch Alarm Status Binning
Bytestream A—D (RO, COR/COW)................................................................................................................... 422
Table 348. RXT_PDI_ALMBNBSR, Payload Defect Indicator Alarm Status Binning Bytestream A—D (RO) ..... 423
Table 349. RXT_TSPDI_ALMBSR[A—D], Time Slots 1—12 Payload Defect Indicator Alarm Bytestream
A—D (RO, COR/COW)...................................................................................................................................... 423
Table 350. RXT_RDI_ALMDBNBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 423
Table 351. RXT_TSRDI_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Remote Defect
Indicator Alarm Delta Bytestream A—D (RO, COR/COW) ................................................................................ 423
Table 352. RXT_PLM_ALMDBNBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 424
Table 353. RXT_TSPLM_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Label Mismatch
Alarm Delta Bytestream A—D (RO, COR/COW)............................................................................................... 424
Table 354. RXT_UNEQR_ALMDBNBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 424
Table 355. RXT_TSUNEQR_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Unequipped Received
Alarm Delta Bytestream A—D (RO, COR/COW)............................................................................................... 424
Table 356. RXT_AIS_ALMDBNBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 425
16
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Tables (continued)
Table
Page
Table 357. RXT_TSAIS_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Alarm Indicator Signal Alarm
Delta Bytestream A—D (RO, COR/COW) ......................................................................................................... 425
Table 358. RXT_LOP_ALMDBNBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 425
Table 359. RXT_TSLOP_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Loss of Pointer Alarm Delta
Bytestream A—D (RO, COR/COW)................................................................................................................... 425
Table 360. RXT_PTRACCMPIR, Path Trace Access Complete Interrupt (RO, COR/COW) ............................... 426
Table 361. RXT_PDI_ALMDBNBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning
Bytestream A—D (RO) ...................................................................................................................................... 426
Table 362. RXT_TSPDI_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Defect
Indicator Alarm Delta Bytestream A—D (RO, COR/COW) ................................................................................ 426
Table 363. RXT_POH_ALMBNMR[1—2], Path Overhead Alarm Status Binning Masks (R/W) .......................... 427
Table 364. RXT_SF_ALMBNMBSR, Signal Fail Alarm Status Binning Masks Bytestream A—D (R/W) ............. 429
Table 365. RXT_TSSF_ALMMBSR[A—D], Time Slots 1—12 Signal Fail Alarm Masks Bytestream A—D (R/W)429
Table 366. RXT_RDI_ALMBNMBSR, Remote Defect Indicator Alarm Status Binning Masks
Bytestream A—D (R/W)..................................................................................................................................... 430
Table 367. RXT_TSRDI_ALMMBSR[A—D], Time Slots 1—12 Remote Defect Indicator Alarm Masks Bytestream
A—D (R/W) ........................................................................................................................................................ 430
Table 368. RXT_PLM_ALMBNMBSR, Payload Label Mismatch Alarm Status Binning Masks
Bytestream A—D (R/W)..................................................................................................................................... 430
Table 369. RXT_TSPLM_ALMMBSR[A—D], Time Slots 1—12 Payload Label Mismatch Alarm Masks Bytestream
A—D (R/W) ........................................................................................................................................................ 430
Table 370. RXT_UNEQR_ALMBNMBSR, Unequipped Received Alarm Status Binning Masks
Bytestream A—D (R/W)..................................................................................................................................... 431
Table 371. RXT_TSUNEQR_ALMMBSR[A—D], Time Slots 1—12 Unequipped Received Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 431
Table 372. RXT_AIS_ALMBNMBSR, Alarms Indicator Signal Alarm Status Binning Masks
Bytestream A—D (R/W)..................................................................................................................................... 431
Table 373. RXT_TSAIS_ALMMBSR[A—D], Time Slots 1—12 Alarms Indicator Signal Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 431
Table 374. RXT_LOP_ALMBNMBSR, Loss of Pointer Alarm Status Binning Masks Bytestream A—D (R/W) ... 432
Table 375. RXT_TSLOP_ALMMBSR[A—D], Time Slots 1—12 Loss of Pointer Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 432
Table 376. RXT_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks
Bytestream A—D (R/W)..................................................................................................................................... 432
Table 377. RXT_USCNCTM_ALMMBSR, Channel Path Unsupported Concatenation Map Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 432
Table 378. RXT_J1NVLDMSG_ALMMBSR, Channel Path J1 New Validated Message Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 433
Table 379. RXT_J1MSGMM_ALMMBSR, Channel Path J1 Message Mismatch Alarm Status Masks
Bytestream A—D (R/W)..................................................................................................................................... 433
Table 380. RXT_PDI_ALMBNMBSR, Payload Defect Indicator Alarm Status Binning Masks
Bytestream A—D (R/W)..................................................................................................................................... 433
Table 381. RXT_TSPDI_ALMMBSR[A—D], Time Slots 1—12 Payload Defect Indicator Alarm Masks
Bytestream A—D (R/W)..................................................................................................................................... 433
Table 382. RXT_RDI_ALMDBNMBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status
Binning Masks Bytestream A—D (R/W) ............................................................................................................ 434
Table 383. RXT_TSRDI_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Remote Defect Indicator
Alarm Delta Masks Bytestream A—D (R/W)...................................................................................................... 434
Table 384. RXT_PLM_ALMDBNMBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta
Status Binning Masks Bytestream A—D (R/W) ................................................................................................. 434
Agere Systems Inc.
17
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
List of Tables (continued)
Table
Page
Table 385. RXT_TSPLM_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Label Mismatch
Alarm Delta Masks Bytestream A—D (R/W)...................................................................................................... 434
Table 386. RXT_UNEQR_ALMDBNMBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status
Binning Masks Bytestream A—D (R/W) ............................................................................................................ 435
Table 387. RXT_TSUNEQR_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Unequipped Received
Alarm Delta Masks Bytestream A—D (R/W)...................................................................................................... 435
Table 388. RXT_AIS_ALMDBNMBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning
Masks Bytestream A—D (R/W) ......................................................................................................................... 435
Table 389. RXT_TSAIS_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Alarm Indicator
Signal Alarm Delta Masks Bytestream A—D (R/W)........................................................................................... 435
Table 390. RXT_LOP_ALMDBNMBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning
Masks Bytestream A—D (R/W) ......................................................................................................................... 436
Table 391. RXT_TSLOP_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Loss of Pointer
Alarm Delta Masks Bytestream A—D (R/W)...................................................................................................... 436
Table 392. RXT_PTRACCMPIR, Path Trace Access Complete Interrupt Mask (R/W)........................................ 436
Table 393. RXT_PDI_ALMDBNMBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status Binning
Masks Bytestream A—D (R/W) ......................................................................................................................... 437
Table 394. RXT_TSPDI_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Defect Indicator
Alarm Delta Masks Bytestream A—D (R/W)...................................................................................................... 437
Table 395. RXT_PTRBFR[1—32], Path Trace Buffer Registers 1—32 (R/W) ..................................................... 438
Table 396. RXT_PTRACCTLR1, Path Trace Access Control Register 1 (R/W) .................................................. 438
Table 397. RXT_PTRACCTLR2, Path Trace Access Control Register 2 (R/W) .................................................. 438
Table 398. RXT_PTRACCTLR3, Path Trace Access Control Register 3 (R/W) .................................................. 438
Table 399. RXT_PTRACBGR, Path Trace Access Begin (WO) .......................................................................... 438
Table 400. RXT_STS12PTRCTLR[1—6], STS-12 Channel Path Trace Control Registers 1—6 (R/W) .............. 439
Table 401. RXT_TSRDI_ALMPSBSR[A—D], Time Slots 1—12 RDI Alarm Persistency Bytestream A—D (RO)440
Table 402. RXT_TSPLM_ALMPSBSR[A—D], Time Slots 1—12 PLM Alarm Persistency Bytestream
A—D (RO).......................................................................................................................................................... 440
Table 403. RXT_TSPUNEQ_ALMPSBSR[A—D], Time Slots 1—12 Path Unequipped Alarm Persistency
Bytestream A—D (RO) ...................................................................................................................................... 440
Table 404. RXT_TSAIS_ALMPSBSR[A—D], Time Slots 1—12 AIS Alarm Persistency Bytestream A—D (RO) 441
Table 405. RXT_TSLOP_ALMPSBSR[A—D], Time Slots 1—12 LOP Alarm Persistency Bytestream
A—D (RO).......................................................................................................................................................... 441
Table 406. RXT_TSPDI_ALMPSBSR[A—D], Time Slots 1—12 PDI Alarm Persistency Bytestream A—D (RO) 441
Table 407. RXT_TSRDI_STBSR[A—D], Time Slots 1—12 RDI State Bytestream A—D (RO) ........................... 442
Table 408. RXT_TSPLM_STBSR[A—D], Time Slots 1—12 PLM State Bytestream A—D (RO)......................... 442
Table 409. RXT_TSPUNEQ_STBSR[A—D], Time Slots 1—12 Path Unequipped State Bytestream A—D (RO) 442
Table 410. RXT_TSAIS_STBSR[A—D], Time Slots 1—12 AIS State Bytestream A—D (RO) ............................ 443
Table 411. RXT_TSLOP_STBSR[A—D], Time Slots 1—12 LOP State Bytestream A—D (RO) ......................... 443
Table 412. RXT_TSPDI_STBSR[A—D], Time Slots 1—12 PDI State Bytestream A—D (RO)............................ 443
Table 413. RXT_SFWSZ_SELR[1—2], Signal Fail Window Size Select Registers 1—2 (R/W, Control) ............ 444
Table 414. RXT_SFDR[0—7], Signal Fail Detect Threshold Registers 0—7 (R/W, Control) ............................... 445
Table 415. RXT_SFCLRR[0—7], Signal Fail Clear Threshold Registers 0—7 (R/W, Control) ............................ 446
Table 416. RXT_SFWSZR[0—3], Signal Fail Window Size 0—3 Registers (R/W, Control) ................................ 447
Table 417. RXT_ECNCTM_TSBSR[A—D], Expected Concatenation Map Time Slots 1—12 in Bytestream
A—D (R/W, Control) .......................................................................................................................................... 448
Table 418. RXT_CNCTCPREN_TSBSR[A—D], Concatenation Compare Enable Time Slots 1—12 in Bytestream
A—D (R/W, Control) .......................................................................................................................................... 448
Table 419. RXT_RCNCTM_TSBSR[A—D], Received Concatenation Map Time Slots 1—12 in Bytestream
A—D (RO).......................................................................................................................................................... 448
Table 420. RXT_SWAIS_ISRTR, Software AIS Insert (R/W, Control) ................................................................. 449
18
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Tables (continued)
Table
Page
Table 421. RXT_AISONUNEQ_PR[A—D], Time Slot 1—Time Slot 12 AIS Insert on UNEQ-P Bytestream
A—D (R/W, Control) .......................................................................................................................................... 449
Table 422. RXT_AISONPLM_PR[A—D], Time Slot 1—Time Slot 12 AIS Insert on PLM-P Bytestream A—D
(R/W, Control) .................................................................................................................................................... 449
Table 423. RXT_AISONTIM_PR[A—D], Time Slot 1—Time Slot 12 Software AIS Insert on TIM-P Bytestream
A—D (R/W, Control) .......................................................................................................................................... 449
Table 424. RXT_STS12_PINCDECR, STS-12 Pointer Increment/Decrement (R/W, Control) ............................ 450
Table 425. RXT_TS_INCDECBNR[A—D], Time Slots 1—12 Increment/Decrement Binning Select
Bytestream A—D (R/W, Control) ....................................................................................................................... 450
Table 426. RXT_TSPDIVLD_CTLBSR[A—D], Time Slot 1—Time Slot 12 PDI Validate Control Bytestream
A—D (R/W, Control) .......................................................................................................................................... 451
Table 427. RXT_EXPC2_PVSNR[1—24], Expected C2 Byte Provisioning (R/W, Control) ................................. 452
Table 428. RXT_TSCBB_ERRBSR[A—D], Time Slot 1—Time Slot 12 Count Block/Bit Errors
Bytestream A—D ............................................................................................................................................... 452
Table 429. RXT_TSMNTR[1—48], Time Slots 1—48 Maintenance (R/W, Control)............................................. 453
Table 430. RXT_PI_LSECINCR[A—D], Pointer Interpreter Last Second Increments Bytestream A—D (RO) .... 453
Table 431. RXT_PI_LSECDECR[A—D], Pointer Interpreter Last Second Decrements Bytestream A—D (RO) . 453
Table 432. RXT_POH_ALMPMR, Path Overhead Alarm Performance Monitoring (RO) .................................... 454
Table 433. RXT_1BRDI_DPMBSR, Path Overhead One-Bit RDI Defect PM Bytestream A—D (RO) ................ 455
Table 434. RXT_TS1BRDI_DPMBSR[A—D], Path Overhead Time Slots 1—12 One-Bit RDI Defect
PM Bytestream A—D (RO) ................................................................................................................................ 455
Table 435. RXT_ERDI_PDPMBSR, Path Overhead ERDI Payload Defect PM Bytestream A—D (RO) ............. 455
Table 436. RXT_TSERDI_PDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Payload Defect PM
Bytestream A—D (RO) ...................................................................................................................................... 455
Table 437. RXT_ERDI_CDPMBSR, Path Overhead ERDI Connectivity Defect PM Bytestream A—D (RO) ...... 456
Table 438. RXT_TSERDI_CDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Connectivity Defect PM
Bytestream A—D (RO) ...................................................................................................................................... 456
Table 439. RXT_ERDI_SDPMBSR, Path Overhead ERDI Server Defect PM Bytestream A—D (RO) ............... 456
Table 440. RXT_TSERDI_SDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Server Defect PM
Bytestream A—D (RO) ...................................................................................................................................... 456
Table 441. RXT_UNEQR_PMBSR, Path Overhead Unequipped Received PM Bytestream A—D (RO) ............ 457
Table 442. RXT_TSUNEQR_PMBSR[A—D], Path Overhead Time Slots 1—12 Unequipped Received PM
Bytestream A—D (RO) ...................................................................................................................................... 457
Table 443. RXT_AIS_PMBSR, Path Overhead Alarm Indicator Signal PM Bytestream A—D (RO) ................... 457
Table 444. RXT_TSAIS_PMBSR[A—D], Path Overhead Time Slots 1—12 Alarm Indicator Signal PM
Bytestream A—D (RO) ...................................................................................................................................... 457
Table 445. RXT_LOP_PMBSR, Path Overhead Loss of Pointer PM Bytestream A—D (RO) ............................. 458
Table 446. RXT_TSLOP_PMBSR[A—D], Path Overhead Time Slots 1—12 Loss of Pointer PM
Bytestream A—D (RO) ...................................................................................................................................... 458
Table 447. RXT_LSECCVP_CPMR[1—48], Last Second CV-P Count Time Slot 1—Time Slot 48 PM (RO) ..... 458
Table 448. RXT_LSECREIP_CPMR[1—48], Last Second REI-P Count Time Slot 1—Time Slot 48 PM (RO) ... 458
Table 449. RXT_TSRDIPR[1—48], Time Slots 1—48 Path RDI Status (RO)...................................................... 459
Table 450. RXT_TSC2R[1—24], Time Slots 1—48 Path C2 Status (RO) ........................................................... 459
Table 451. RXT_TSPDIR[1—24], Time Slots 1—48 Path PDI Status (RO)......................................................... 459
Table 452. RXT Register Map .............................................................................................................................. 460
Table 453. Overhead Bits Defined in a 44.736 Mbits/s Multiframe Structure....................................................... 490
Table 454. RAI Code Words................................................................................................................................. 492
Table 455. POI Values ......................................................................................................................................... 495
Table 456. G1 Byte Definition............................................................................................................................... 496
Table 457. Trailer Length ..................................................................................................................................... 496
Table 458. PLCP Nibble Stuff Sequence ............................................................................................................. 496
Agere Systems Inc.
19
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
List of Tables (continued)
Table
Page
Table 459. C-Bit Insert.......................................................................................................................................... 497
Table 460. Overhead Allocation at 34,368 kbits/s ................................................................................................ 502
Table 461. MA Byte Description ........................................................................................................................... 504
Table 462. G.751 E3 Frame Format..................................................................................................................... 505
Table 463. E3-PLCP Mapping of ATM Cells ........................................................................................................ 505
Table 464. Path Overhead Identifier Codes (POI)................................................................................................ 506
Table 465. PLCP G1 byte..................................................................................................................................... 507
Table 466. C1 Values and Transmit Insert Sequence.......................................................................................... 508
Table 467. Receive Mode Control Signals ........................................................................................................... 509
Table 468. Transmit Mode Control Signals .......................................................................................................... 509
Table 469. G.751 E3 Frame Transmit Overhead Operation ................................................................................ 510
Table 470. G.751 E3 Frame Receive Overhead Operation ................................................................................. 510
Table 471. G.751 E3-PLCP Transmit Overhead Operation ................................................................................. 512
Table 472. G.751 E3-PLCP Receive Overhead Operation .................................................................................. 513
Table 473. G.832 E3 Transmit Frame Overhead Operation ................................................................................ 514
Table 474. G.832 E3 Receive Frame Overhead Operation ................................................................................. 515
Table 475. PRBS Receive (Monitor) Pattern Control Signals .............................................................................. 517
Table 476. PRBS Transmit Pattern Control Signals............................................................................................. 517
Table 477. DS3E3_VERR, Version Control (RO)................................................................................................. 518
Table 478. DS3_SCRATCHR, Scratch Register (R/W)........................................................................................ 518
Table 479. DS3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/Event
Registers (R/W) ................................................................................................................................................. 518
Table 480. DS3FRMD_A, DS3 Out-of-Frame Delta (COR/COW)........................................................................ 521
Table 481. DS3LOFD_A, DS3 Loss-of-Frame Delta (COR/COW)....................................................................... 521
Table 482. DS3SEFD_A, DS3 Severely Errored Frame (SEF) Delta (COR/COW) ............................................. 522
Table 483. DS3AISD_A, DS3 AIS Detection Delta (COR/COW) ......................................................................... 522
Table 484. DS3IDLED_A, DS3 Idle Detection Delta (COR/COW) ....................................................................... 522
Table 485. DS3CBD_A, DS3 C-Bit Detect Delta (COR/COW)............................................................................. 522
Table 486. DS3RAID_A, DS3 X-Bit Detect Delta (COR/COW)............................................................................ 522
Table 487. DS3FEACALMD_A, DS3 Far-End Alarm and Control (FEAC) RAI Delta (COR/COW) ..................... 523
Table 488. DS3FEACCTLD_A, DS3 Far-End Alarm and Control (FEAC) Control Delta (COR/COW) ................ 523
Table 489. DS3_PLCPOOFD_A, PLCP Out-of-Frame Monitor Delta (COR/COW)............................................. 523
Table 490. DS3_PLCPRAID_A, PLCP RAI (G1[3]) Monitoring Delta (COR/COW) ............................................. 523
Table 491. DS3_RXPRBS_SYNCD_A, PRBS Detector Sync Delta (COR/COW)............................................... 523
Table 492. DS3FRMD_B, DS3 Out-of-Frame Delta (COR/COW)........................................................................ 524
Table 493. DS3LOFD_B, DS3 Loss-of-Frame Delta (COR/COW)....................................................................... 524
Table 494. DS3SEFD_B, DS3 Severely Errored Frame (SEF) Delta (COR/COW) ............................................. 524
Table 495. DS3AISD_B, DS3 AIS Detection Delta (COR/COW) ......................................................................... 524
Table 496. DS3IDLED_B, DS3 Idle Detection Delta (COR/COW) ....................................................................... 524
Table 497. DS3CBD_B, DS3 C-Bit Detect Delta (COR/COW)............................................................................. 525
Table 498. DS3RAID_B, DS3 X-Bit Detect Delta (COR/COW)............................................................................ 525
Table 499. DS3FEACALMD_B, DS3 Far-End Alarm and Control (FEAC) RAI Delta (COR/COW) ..................... 525
Table 500. DS3FEACCTLD_B, DS3 Far-End Alarm and Control (FEAC) Control Delta (COR/COW) ................ 525
Table 501. DS3_PLCPOOFD_B, PLCP Out-of-Frame Monitor Delta (COR/COW)............................................. 525
Table 502. DS3_PLCPRAID_B, PLCP RAI (G1[3]) Monitoring Delta (COR/COW) ............................................. 526
Table 503. DS3_RXPRBS_SYNCD_B, PRBS Detector Sync Delta (COR/COW)............................................... 526
Table 504. DS3_TXFIFOERRE, FIFO Overflow Indicator Event (COR/COW) .................................................... 526
Table 505. DS3_TXEOPERRER, EOP Marker Error Event (COR/COW)............................................................ 526
Table 506. DS3FRMM_A, DS3 Out-of-Frame Mask (R/W).................................................................................. 527
Table 507. DS3LOFM_A, DS3 Loss-of-Frame Mask (R/W)................................................................................. 527
Table 508. DS3SEFM_A, DS3 Severely Errored Frame (SEF) Mask (R/W) ....................................................... 527
20
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Tables (continued)
Table
Page
Table 509. DS3AISM_A, DS3 AIS Detection Mask (R/W) ................................................................................... 527
Table 510. DS3IDLEM_A, DS3 Idle Detection Mask (R/W) ................................................................................. 527
Table 511. DS3CBM_A, DS3 C-Bit Detect Mask (R/W)....................................................................................... 528
Table 512. DS3RAIM_A, DS3 X-Bit Detect Mask (R/W) ...................................................................................... 528
Table 513. DS3FEACALMM_A, DS3 Far-End Alarm and Control (FEAC) Alarm Mask (R/W) ............................ 528
Table 514. DS3FEACCTLM_A, DS3 Far-End Alarm and Control (FEAC) Control Mask (R/W) .......................... 528
Table 515. DS3_PLCPOOFM_A, PLCP Out-of-Frame Monitor Mask (R/W) ....................................................... 528
Table 516. DS3_PLCPRAIM_A, PLCP RAI (G1[3]) Monitoring Mask (R/W) ....................................................... 529
Table 517. DS3_RXPRBS_SYNCM_A, PRBS Detector Sync Mask (R/W) ......................................................... 529
Table 518. DS3_DS3FRMM_B, DS3 Out-of-Frame Mask (R/W)......................................................................... 529
Table 519. DS3LOFM_B, DS3 Loss-of-Frame Mask (R/W)................................................................................. 529
Table 520. DS3SEFM_B, DS3 Severely Errored Frame (SEF) Mask (R/W) ....................................................... 529
Table 521. DS3AISM_B, DS3 AIS Detection Mask (R/W) ................................................................................... 530
Table 522. DS3IDLEM_B, DS3 Idle Detection Mask (R/W) ................................................................................. 530
Table 523. DS3CBM_B, DS3 C-Bit Detect Mask (R/W)....................................................................................... 530
Table 524. DS3RAIM_B, DS3 X-Bit Detect Mask (R/W) ...................................................................................... 530
Table 525. DS3FEACALMM_B, DS3 Far-End Alarm and Control (FEAC) Alarm Mask (R/W) ............................ 530
Table 526. DS3FEACCTLM_B, DS3 Far-End Alarm and Control (FEAC) Control Mask (R/W) .......................... 531
Table 527. DS3_PLCPOOFM_B, PLCP Out-of-Frame Monitor Mask (R/W) ....................................................... 531
Table 528. DS3_PLCPRAIM_B, PLCP RAI (G1[3]) Monitoring Mask (R/W) ....................................................... 531
Table 529. DS3_RXPRBS_SYNCM_B, PRBS Detector Sync Mask (R/W) ......................................................... 531
Table 530. DS3_TXFIFOERRM, FIFO Overflow Indicator Mask (R/W) ............................................................... 532
Table 531. DS3_TXEOPERRM, EOP Marker Error Mask (R/W) ......................................................................... 532
Table 532. DS3FRM_A, DS3 Out-of-Frame State (RO)....................................................................................... 533
Table 533. DS3LOF_A, DS3 Loss-of-Frame State (RO)...................................................................................... 533
Table 534. DS3SEF_A, DS3 Severely Errored Frame (SEF) (RO)...................................................................... 533
Table 535. DS3AIS_A, DS3 AIS Detection (RO).................................................................................................. 533
Table 536. DS3IDLE_A, DS3 Idle Detection (RO) ............................................................................................... 534
Table 537. DS3CB_A, DS3 C-Bit Detect (RO) ..................................................................................................... 534
Table 538. DS3RAI_A, DS3 X-Bit Detect (RO) .................................................................................................... 534
Table 539. DS3FEACALM_A, DS3 Far-End Alarm and Control (FEAC) (RO) .................................................... 534
Table 540. DS3FEACCTL_A, DS3 Far-End Alarm and Control (FEAC) (RO) ..................................................... 535
Table 541. DS3_PLCPOOF_A, PLCP Out-of-Frame Monitor (RO) ..................................................................... 535
Table 542. DS3_PLCPRAI_A, PLCP RAI (G1[3]) Monitoring (RO)...................................................................... 535
Table 543. DS3_RXPRBS_SYNC_A, PRBS Detector Sync State (RO).............................................................. 535
Table 544. DS3FEACCODE_A[1—6], DS3 Far-End Alarm and Control (FEAC) (RO) ........................................ 536
Table 545. DS3_RXPRBSERRCNT_A, PRBS Error Counter (RO) ..................................................................... 536
Table 546. DS3FRM_B, DS3 Out-of-Frame State (RO)....................................................................................... 536
Table 547. DS3LOF_B, DS3 Loss-of-Frame State (RO)...................................................................................... 536
Table 548. DS3SEF_B, DS3 Severely Errored Frame (SEF) (RO)...................................................................... 537
Table 549. DS3AIS_B, DS3 AIS Detection (RO).................................................................................................. 537
Table 550. DS3IDLE_B, DS3 Idle Detection (RO) ............................................................................................... 537
Table 551. DS3CB_B, DS3 C-Bit Detect (RO) ..................................................................................................... 537
Table 552. DS3RAI_B, DS3 X-Bit Detect (RO) .................................................................................................... 538
Table 553. DS3FEACALM_B, DS3 Far-End Alarm and Control (FEAC) (RO) .................................................... 538
Table 554. DS3FEACCTL_B, DS3 Far-End Alarm and Control (FEAC) (RO) ..................................................... 538
Table 555. DS3_PLCPOOF_B, PLCP Out-of-Frame Monitor (RO) ..................................................................... 538
Table 556. DS3_PLCPRAI_B, PLCP RAI (G1[3]) Monitoring (RO)...................................................................... 539
Table 557. DS3_RXPRBS_SYNC_B, PRBS Detector Sync State (RO).............................................................. 539
Table 558. DS3FEACCODE_B[1—6], DS3 Far-End Alarm and Control (FEAC) (RO)........................................ 539
Table 559. DS3_RXPRBSERRCNT_B, PRBS Error Counter (RO) ..................................................................... 539
Agere Systems Inc.
21
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
List of Tables (continued)
Table
Page
Table 560. DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W)................................................. 540
Table 561. DS3_RXMODE_A_2, Receive Interface A Control Register 2 (R/W)................................................. 540
Table 562. DS3_RXPRBS_A, Receive PRBS (R/W) ........................................................................................... 541
Table 563. DS3_RXMODE_B_1, Receive Interface B Control Register 1 (R/W)................................................. 541
Table 564. DS3_RXMODE_B_2, Receive Interface B Control Register 2 (R/W)................................................. 542
Table 565. DS3_RXPRBS_B, Receive PRBS (R/W) ........................................................................................... 542
Table 566. DS3_RXDS3FBIT_A[1—12], DS3 F-Bit and M-Bit Error Count (RO) ................................................ 543
Table 567. DS3_RXDS3_CVP_P_A[1—12], DS3 P-Bit CVP-P Error Counter (CVP-P) (RO) ............................. 543
Table 568. DS3_RXDS3_CVCP_P_A[1—12], DS3 CP-Bit Error Counter (CVCP-P) (RO) ................................. 543
Table 569. DS3_RXDS3FEBE_A[1—12], DS3 FEBE Error Counter (CVCP-PFE) (RO)..................................... 544
Table 570. DS3_RXPLCPB1ECNT_A[1—12], PLCP B1 Error Count (RO)......................................................... 544
Table 571. DS3_PLCPFEBECNT_A[1—12], PLCP FEBE (G1[7:4]) Error Count (RO) ....................................... 544
Table 572. DS3_RXDS3FBIT_B[1—12], DS3 F-Bit and M-Bit Error Count (RO) ................................................ 545
Table 573. DS3_RDS3_CVP_P_B[1—12], DS3 P-Bit CVP-P Error Counter (CVP-P) ........................................ 545
Table 574. DS3_RXDS3_CVCP_P_B[1—12], DS3 CP-Bit Error Counter (CVCP-P) (RO) ................................. 545
Table 575. DS3_RXDS3FEBE_B[1—12], DS3 FEBE Error Counter (CVCP-PFE) (RO)..................................... 546
Table 576. DS3_RXPLCPB1ECNT_B[1—12], PLCP B1 Error Count (RO)......................................................... 546
Table 577. DS3_PLCPFEBECNT_B[1—12], PLCP FEBE (G1[7:4]) Error Count (RO) ....................................... 546
Table 578. DS3_TDS3PLCPCTL1_CHD[1—16], Transmit PLCP (R/W) ............................................................. 547
Table 579. DS3_TDS3CTL_CHD[1—16], Transmit DS3 (R/W)........................................................................... 548
Table 580. DS3_TXPRBSCTL_[1—2], Transmit PRBS Control (R/W) ................................................................ 549
Table 581. DS3_TXFEBEDINS, Transmit Blank Request Counter Reset (R/W) ................................................. 549
Table 582. DS3_TXFIFO, Transmit FIFO Min/Max Thresholds (R/W)................................................................. 549
Table 583. DS3E3_VERR, Version Control (RO)................................................................................................. 550
Table 584. E3_SCRATCHR, Scratch Register (R/W) .......................................................................................... 550
Table 585. E3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/Event
Registers (R/W) ................................................................................................................................................. 550
Table 586. E3FRMD_A, E3 Out-of-Frame Delta (COR/COW)............................................................................. 553
Table 587. E3LOFD_A, E3 Loss-of-Frame Delta (COR/COW)............................................................................ 553
Table 588. E3_TR_MISMATCHD_A, E3 Delta (COR/COW) ............................................................................... 553
Table 589. E3AISD_A, E3 AIS Detection Delta (COR/COW) .............................................................................. 553
Table 590. E3_D_A, E3 Delta (COR/COW) ......................................................................................................... 554
Table 591. E3_MA_SSMD_A, E3 Delta (COR/COW) .......................................................................................... 554
Table 592. E3_D_A, E3 Delta (COR/COW) ......................................................................................................... 554
Table 593. E3_MA_PTD_A, E3 Delta (COR/COW) ............................................................................................. 554
Table 594. E3_PLCP_LOFD_A, E3 Delta (COR/COW)....................................................................................... 555
Table 595. E3_PLCPOOFD_A, PLCP Out-of-Frame Monitor Delta (COR/COW) ............................................... 555
Table 596. E3_PLCPASD_A, PLCP (G1[3]) Monitoring Delta (COR/COW) ........................................................ 555
Table 597. E3FRMD_B, E3 Out-of-Frame Delta (COR/COW)............................................................................. 556
Table 598. E3LOFD_B, E3 Loss-of-Frame Delta (COR/COW)............................................................................ 556
Table 599. E3_TR_MISMATCHD_B, E3 Delta (COR/COW) ............................................................................... 556
Table 600. E3AISD_B, E3 AIS Detection Delta (COR/COW) .............................................................................. 556
Table 601. E3_D_B, E3 Delta (COR/COW) ......................................................................................................... 557
Table 602. E3_MA_SSMD_B, E3 Delta (COR/COW) .......................................................................................... 557
Table 603. E3_D_B, E3 Delta (COR/COW) ......................................................................................................... 557
Table 604. E3_MA_PTD_B, E3 Delta (COR/COW) ............................................................................................. 557
Table 605. E3_PLCP_LOFD_B, E3 Delta (COR/COW)....................................................................................... 558
Table 606. E3_PLCPOOFD_B, PLCP Out-of-Frame Monitor Delta (COR/COW) ............................................... 558
Table 607. E3_PLCP_G1_ASD_B, PLCP (G1[3]) Monitoring Delta (COR/COW) ............................................... 558
Table 608. E3FRMM_A, E3 Out-of-Frame Mask (R/W) ....................................................................................... 559
Table 609. E3LOFM_A, E3 Loss-of-Frame Mask (R/W) ...................................................................................... 559
22
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Tables (continued)
Table
Page
Table 610. E3SEFM_A, E3 Severely Errored Frame (SEF) Mask (R/W)............................................................. 559
Table 611. E3AISM_A, E3 AIS Detection Mask (R/W)......................................................................................... 559
Table 612. E3_M_A, E3 Mask (R/W) ................................................................................................................... 560
Table 613. E3MAM_A, E3 MA-Bit Detect Mask (R/W)......................................................................................... 560
Table 614. E3_M_A, E3 Detect Mask (R/W) ........................................................................................................ 560
Table 615. E3_MA_PTM_A, E3 Mask (R/W) ....................................................................................................... 560
Table 616. E3_PLCP_LOFM_A, E3 Mask (R/W) ................................................................................................. 561
Table 617. E3_PLCPOOFM_A, PLCP Out-of-Frame Monitor Mask (R/W).......................................................... 561
Table 618. DS3_PLCPASM_A, PLCP (G1[3]) Monitoring Mask (R/W)................................................................ 561
Table 619. E3FRMM_B, E3 Out-of-Frame Mask (R/W) ....................................................................................... 562
Table 620. E3LOFM_B, E3 Loss-of-Frame Mask (R/W) ...................................................................................... 562
Table 621. E3SEFM_B, E3 Severely Errored Frame (SEF) Mask (R/W)............................................................. 562
Table 622. E3AISM_B, E3 AIS Detection Mask (R/W)......................................................................................... 562
Table 623. E3_M_B, E3 Mask (R/W) ................................................................................................................... 563
Table 624. E3MAM_B, E3 MA-Bit Detect Mask (R/W)......................................................................................... 563
Table 625. E3_M_B, E3 Detect Mask (R/W) ........................................................................................................ 563
Table 626. E3_MA_PTM_B, E3 Mask (R/W) ....................................................................................................... 563
Table 627. E3_PLCP_LOFM_B, E3 Mask (R/W) ................................................................................................. 564
Table 628. E3_PLCPOOFM_B, PLCP Out-of-Frame Monitor Mask (R/W).......................................................... 564
Table 629. E3_PLCPASM_B, PLCP (G1[3]) Monitoring Mask (R/W) .................................................................. 564
Table 630. E3FRM_A, E3 Out-of-Frame State (RO)............................................................................................ 565
Table 631. E3LOF_A, E3 Loss-of-Frame State (RO)........................................................................................... 565
Table 632. E3SEF_A, E3 Severely Errored Frame (SEF) (RO)........................................................................... 565
Table 633. E3AIS_A, E3 AIS Detection (RO)....................................................................................................... 565
Table 634. E3E3_A, E3 Detect (RO).................................................................................................................... 566
Table 635. E3_PLCP_LOF_A, E3 PLCP Loss-of-Frame Monitor (RO) ............................................................... 566
Table 636. E3_PLCPOOF_A, PLCP Out-of-Frame Monitor (RO)........................................................................ 566
Table 637. E3_PLCPAS_A, PLCP (G1[3]) Monitoring (RO) ................................................................................ 567
Table 638. E3SSMCODE_A[1—6], E3 (RO)........................................................................................................ 567
Table 639. E3FRM_B, E3 Out-of-Frame State (RO)............................................................................................ 568
Table 640. E3LOF_B, E3 Loss-of-Frame State (RO)........................................................................................... 568
Table 641. E3SEF_B, E3 Severely Errored Frame (SEF) (RO)........................................................................... 568
Table 642. E3AIS_B, E3 AIS Detection (RO)....................................................................................................... 568
Table 643. E3_B, E3 Detect (RO) ........................................................................................................................ 569
Table 644. E3_PLCP_LOF_B, E3 PLCP Loss-of-Frame Monitor (RO) ............................................................... 569
Table 645. E3_PLCPOOF_B, PLCP Out-of-Frame Monitor (RO)........................................................................ 569
Table 646. E3_PLCPAS_B, PLCP (G1[3]) Monitoring (RO) ................................................................................ 570
Table 647. E3SSMCODE_B[1—6], E3 (RO)........................................................................................................ 570
Table 648. E3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W) ................................................... 571
Table 649. E3_RXMODE_A_2, Receive Interface A Control Register 2 (R/W) ................................................... 571
Table 650. RDS3E3_A, Receive Mode Control (R/W) ......................................................................................... 571
Table 651. E3_RXMODE_B_1, Receive Interface B Control Register 1 (R/W) ................................................... 572
Table 652. E3_RXMODE_B_2, Receive Interface B Control Register 2 (R/W) ................................................... 572
Table 653. RDS3E3_B, Receive Mode Control.................................................................................................... 572
Table 654. E3PROV_1, E3 Provisioning Parameters (Per Block) (R/W) ............................................................. 573
Table 655. E3PROV_2, E3 PLCP Provisioning Parameters (Per Block) (R/W)................................................... 573
Table 656. E3PROV_3, E3 AIS Provisioning Parameters (Per Block) (R/W) ...................................................... 573
Table 657. E3PROV_4, E3 Provisioning Parameters (Per Block) (R/W) ............................................................. 574
Table 658. E3PROV_5, E3 Provisioning Parameters (Per Block) (R/W) ............................................................. 574
Table 659. E3_MA_MF_[A—B], E3 Provisioning Parameters.............................................................................. 574
Table 660. E3_TR_NMODE_[A—B][1—2], (R/W)................................................................................................ 575
Agere Systems Inc.
23
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
List of Tables (continued)
Table
Page
Table 661. E3PLCP_MON[A—B][1—2], (RO)...................................................................................................... 575
Table 662. E3_MA_REI_ERRCNT_A[1—12], E3 MA REI Error Count (RO)....................................................... 576
Table 663. E3_B1_ERRCNT_A[1—12], E3 B1 Error Counter (RO) .................................................................... 576
Table 664. E3_RXPLCPB1ECNT_A[1—12], PLCP B1 Error Count (RO) ........................................................... 576
Table 665. E3_PLCPFEBECNT_A[1—12], PLCP FEBE (G1[7:4]) Error Count (RO).......................................... 576
Table 666. E3_MA_REI_ERRCNT_B[1—12], E3 MA REI Error Count (RO)....................................................... 577
Table 667. E3_B1_ERRCNT_B[1—12], E3 B1 Error Counter (RO) .................................................................... 577
Table 668. E3_RXPLCPB1ECNT_B[1—12], PLCP B1 Error Count (RO) ........................................................... 577
Table 669. E3_PLCPFEBECNT_B[1—12], PLCP FEBE (G1[7:4]) Error Count (RO).......................................... 577
Table 670. E3_TE3PLCPCTL1_CHD[1—16], Transmit PLCP (R/W) .................................................................. 578
Table 671. E3_TE3CTL_CHD[1—16], Transmit E3 (R/W)................................................................................... 579
Table 672. E3_TXFEBEDINS, Transmit PLCP FEBE Insert Data Value for All Channel (R/W) .......................... 580
Table 673. TXE3PLCP_P[1—3], Transmit G.751 E3 PLCP Z1—Z3, F1 Insert Control (R/W) ............................ 580
Table 674. TXTRACE[1—16]_B[1—8], Transmit E3 G.832 Trail Trace (TR) Insert Registers
(128 Locations) (R/W)........................................................................................................................................ 580
Table 675. Receive E3 (G.832) Trail Trace Expected/Captured Value—Expected/Capture Format Same as
Transmit Insert Format....................................................................................................................................... 581
Table 676. DS3 Register Map .............................................................................................................................. 582
Table 677. E3 Register Map................................................................................................................................. 595
Table 678. STS-1 Mapping of DS3 Information.................................................................................................... 609
Table 679. (RXSVERSION) Version Control (RO) ............................................................................................... 613
Table 680. RXS_CONTROL, Receive Sequencer Control Register (R/W).......................................................... 613
Table 681. RXS_TS[0—11][A—D], X Sequence Map Register (R/W) ................................................................. 614
Table 682. RYS_TS[0—11][A—D], Y Sequence Map Register (R/W) ................................................................. 614
Table 683. DS3 Support Registers....................................................................................................................... 615
Table 684. RXS PRBS Control Register for Monitor 1 (R/W)............................................................................... 616
Table 685. RXS PRBS Control Register for Monitor 2 (R/W)............................................................................... 616
Table 686. RXS PRBS Status Register for Monitor 1 (Mixed).............................................................................. 617
Table 687. RXS PRBS Status Register for Monitor 2 (Mixed).............................................................................. 617
Table 688. Sequencer Register Map 1 Field Definition ........................................................................................ 618
Table 689. Sequencer Register Map 2 Field Definition ........................................................................................ 622
Table 690. General Registers (RO)...................................................................................................................... 677
Table 691. CORWN Register (R/W)..................................................................................................................... 677
Table 692. TXMUX Mask Register (R/W)............................................................................................................. 677
Table 693. RXMUX Mask Register (R/W) ............................................................................................................ 677
Table 694. FIFO Control (FC) Bandwidth Register (R/W) .................................................................................... 678
Table 695. DE Scratch Register (R/W)................................................................................................................. 678
Table 696. Counter Interrupts (COR/COW) ......................................................................................................... 678
Table 697. GFP Message Interrupts (COR/COW) ............................................................................................... 678
Table 698. Composite Interrupt Register for GFP Interrupts at the Channel Level (COR/COW)......................... 679
Table 699. ATM Frame State Interrupts (COR/COW).......................................................................................... 680
Table 700. ATM Cool Interrupts (COR/COW) ...................................................................................................... 680
Table 701. CDA MAP0 Register (R/W) ................................................................................................................ 681
Table 702. CDA MAP Control Register (R/W)...................................................................................................... 681
Table 703. CDA MAP1 Register (R/W) ................................................................................................................ 681
Table 704. ATM Framer Idle Cell Match Mask (R/W)........................................................................................... 681
Table 705. ATM_LCD[0—15] (R/W)..................................................................................................................... 682
Table 706. ATM_LCDCLK (R/W) ......................................................................................................................... 682
Table 707. ATM_IN_LCD_MASK (R/W)............................................................................................................... 682
Table 708. ATM_OUT_LCD_MASK (R/W)........................................................................................................... 682
Table 709. ATM_IN_LCD (COR/COW) ................................................................................................................ 682
24
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
List of Tables (continued)
Table
Page
Table 710. ATM_OUT_LCD (COR/COW) ............................................................................................................ 682
Table 711. ATM Framer Idle Cell (R/W) ............................................................................................................... 683
Table 712. ATM Unassigned Cell Match/Register (R/W) ..................................................................................... 683
Table 713. ATM Unassigned Cell (R/W) .............................................................................................................. 684
Table 714. ATM Frame State Channel [0—15] Registers (RO) ........................................................................... 684
Table 715. ATM Configuration Registers (R/W) ................................................................................................... 685
Table 716. Rx Channel [0—15] Payload Type and Control (R/W) ....................................................................... 686
Table 717. Rx Payload Type and Payload Control Summary Table .................................................................... 687
Table 718. GFP State Register (R/W, RO)........................................................................................................... 688
Table 719. Registers 0x6470—0x6473 A Message Mailbox Registers (RO)....................................................... 688
Table 720. A Message Mailbox Registers (RO) ................................................................................................... 688
Table 721. Registers 1168—1171 A Message Mailbox Registers (RO) .............................................................. 689
Table 722. Registers 1184—1187 B Message Mailbox Registers (RO) .............................................................. 689
Table 723. B Message Mailbox Registers (RO) ................................................................................................... 689
Table 724. B Message Mailbox Registers (RO) ................................................................................................... 689
Table 725. GFP Interrupt Masks R/W .................................................................................................................. 690
Table 726. Per-Channel Framer State ................................................................................................................. 690
Table 727. GFP Interrupts (COW)........................................................................................................................ 691
Table 728. GFP Receive Configuration Registers (R/W) ..................................................................................... 691
Table 729. PPP Detach Channel 0—15 PPP Protocol Check (R/W) ................................................................... 692
Table 730. PPP Detach Programmable PPP Protocol Register 0—11 (R/W)...................................................... 692
Table 731. PPP Detach Channel 0—15 PPP Header Search (R/W) ................................................................... 693
Table 732. ATM Null Cell Register in TX (R/W) ................................................................................................... 694
Table 733. ATM Header Error Register in Tx (R/W)............................................................................................. 695
Table 734. CRC Transmit Registers (R/W) .......................................................................................................... 695
Table 735. GFP Transmit Registers (R/W)........................................................................................................... 696
Table 736. GFP Transmit Registers (RO) ............................................................................................................ 697
Table 737. GFP Transmit Registers (R/W)........................................................................................................... 697
Table 738. HDLC-Tx Dry Character ..................................................................................................................... 698
Table 739. HDLC-Tx FIFO Threshold .................................................................................................................. 698
Table 740. Tx Payload Type and Control (R/W)................................................................................................... 698
Table 741. Tx Payload Type and Payload Control Summary Table..................................................................... 699
Table 742. ATM/HDLC/GFP Framer—Condition Counter 1 (PMRST Update) (RO) ........................................... 700
Table 743. ATM/HDLC/GFP Framer—Condition Counter 2 (PMRST Update) (RO ............................................ 700
Table 744. CRC Checker—Bad Packet Counter (PMRST Update) (RO) ............................................................ 701
Table 745. PPP Detach—Bad Header Counter (PMRST Update) (RO) .............................................................. 701
Table 746. Interrupts and Interrupt Masks for Packet Counters (R/W) ................................................................ 701
Table 747. Interrupts for Packet Counters (COR/COW) ...................................................................................... 702
Table 748. Transmit (Tx) Good Packet Counter (PMRST Update) (RO) ............................................................. 702
Table 749. DE Register Map ................................................................................................................................ 703
Table 750. Slices, Channels, and Channel IDs .................................................................................................... 717
Table 751. UTOPIA Traffic Types ........................................................................................................................ 719
Table 752. Interface Configurations Supported ................................................................................................... 720
Table 753. UTOPIA Address Modes .................................................................................................................... 727
Table 754. MARS2G5 P-ProLT/MARS2G5 P-Pro UTOPIA (Virtual) Address Pin Mappings............................... 728
Table 755. PHY Channel Address Allocation Related to Status Signal ............................................................... 730
Table 756. UTOPIA Tx Interface Pins that Have Different Meanings in Different Modes .................................... 742
Table 757. UTOPIA Rx Interface Pins that Have Different Meanings in Different Modes .................................... 743
Table 758. Channel B0/B1 Ganging Settings for ATM Cells ................................................................................ 744
Table 759. Transmit UTOPIA Interface Timing Specifications ............................................................................. 745
Table 760. Receive UTOPIA Interface Timing Specifications .............................................................................. 746
Agere Systems Inc.
25
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
List of Tables (continued)
Table
Page
Table 761. UTOPIA Interface Clock Specifications .............................................................................................. 747
Table 762. (UTVER) Version Control (RO) .......................................................................................................... 748
Table 763. (XBARCFGRX) Cross-Bar Configuration Register for Rx (R/W)........................................................ 748
Table 764. (XBARCFGTX) Cross-Bar Configuration Register for Tx (R/W)......................................................... 748
Table 765. (INTSTATUS) Interrupts (RO) ............................................................................................................ 748
Table 766. (INTMASK) Interrupt Masks (R/W) .................................................................................................... 748
Table 767. (ARST) ARST Register (R/W) ............................................................................................................ 749
Table 768. (CORWN) Clear-On-Read or Clear-On-Write Select Register (R/W)................................................. 749
Table 769. UTOPIA Provisioning Field Description.............................................................................................. 750
Table 770. Rx/Tx UTOPIA Interface A—D Provisioning Registers ...................................................................... 752
Table 771. (PARERRA_PM) Interface A Error Count in PMRST Mode (RO) ...................................................... 753
Table 772. (PARERRA) Interface A Error Count (RO/COR) ................................................................................ 753
Table 773. (RXMODEA) Rx Interface A Provisioning Registers (R/W) ................................................................ 753
Table 774. (TXMODEA) Tx Interface A Provisioning Registers (R/W)................................................................. 757
Table 775. (TxWC[A—D]) Channel A—D Transmit Wait Register (R/W)............................................................. 758
Table 776. UTOPIA Channel [A—D](0—3) Provisioning Registers ..................................................................... 759
Table 777. (INTA0) Channel A0—Overflow/Underflow (COR/COW) ................................................................... 760
Table 778. (INTA0m) Channel A0—Overflow/Underflow Mask (R/W) ................................................................. 760
Table 779. (RxProvA0) Channel A0—Provisioning Registers (R/W) ................................................................... 761
Table 780. (TxProvA0) Channel A0—Provisioning Registers (R/W).................................................................... 761
Table 781. (RxThA0) Channel A0—Provisioning Registers (R/W)....................................................................... 762
Table 782. (TxThA0) Channel A0—Provisioning Registers (R/W) ....................................................................... 762
Table 783. (RxThMinA0) Channel A0—Provisioning Registers (R/W)................................................................. 763
Table 784. (TxThMaxA0) Channel A0—Provisioning Registers (R/W) ................................................................ 763
Table 785. UT Register Map ................................................................................................................................ 764
Table 786. JTAG ID Register Codings ................................................................................................................. 778
Table 787. ESD Threshold Voltage ...................................................................................................................... 779
Table 788. LVTTL 3.3 V Logic Interface Characteristics ...................................................................................... 781
Table 789. LVPECL 3.3 V Logic Interface Characteristics ................................................................................... 782
Table 790. Substrate Thickness ........................................................................................................................... 784
Table 791. Loopback Mode .................................................................................................................................. 793
Table 792. Connection Memory Map (WO).......................................................................................................... 795
26
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Description
The MARS2G5 P-Pro SONET/SDH interface device provides a versatile solution for quad OC-3, quad OC-12, and
for single OC-48 linear datacom/telecom applications. Constructed using COM2 CMOS modular process, this
device incorporates integrated SONET/SDH framing, section/line/path termination, pointer processing, and data
engine blocks.
The device provides complete encapsulation and de-encapsulation for packet and ATM streams into and out of
SONET/SDH payloads.
Communication with the MARS2G5 P-Pro device is accomplished through a generic microprocessor interface. The
device supports separate address and data buses.
With the MARS2G5 P-Pro device, support for different types of applications for OC-3/OC-12/OC-48 data equipment is possible, enabling dramatic system cost reduction and the ease of development of extremely competitive
solutions.
This device integrates the SONET/SDH network termination functions with a generic cell/packet delineation circuit.
The interface rates supported are STS-48/STM-16, quad STS-12/STM-4, and quad STS-3/STM-1. The UTOPIA
interface can process and hand off up to 16 channels transported within an STS-N payload. The concatenation levels supported by this device are STS-1, STS-3c, STS-6c, STS-9c, STS-12c, STS-15c, . . . , STS-45c, and STS48c. The data formats processed by this device are ATM cells or HDLC framed packets such as PPP or GFP
framed packets.
DIRECT CELL/PACKET OVER FIBER
SINGLE
STM-16/STS-48
OR QUAD
STM-4/STS-12
OR QUAD
STM-1/STS-3
TXB
PT
DS3
(SPE
MPR)
DE*
OVERHEAD
PROCESSOR
MONITOR
TXC
TXD
TRANSPORT
OVERHEAD
TERMINATION
PACKET/CELL
FIFOs
POINTER
PROCESSOR
TXCLK
TXA
OVERHEAD
PROCESSOR
INSERT
INTERFACE BLOCK
SINGLE
STM-16/STS-48
OR QUAD
STM-4/STS-12
OR QUAD
STM-1/STS-3
UTOPIA
INTERFACE
RXA
PT
(PTR
INTER)
DS3
RXS
RXB
DE†
RXC
RXD
CONTROL
MISCELLANEOUS
DIRECT CELL/PACKET OVER FIBER
TXTOAC RXTOAC
MPU INTERFACE
GPIO
TOAC INTERFACE
5-7393(F).dTDAT16
Note: PT = path terminator, RXS = receive sequencer, and DE = data engine.
* In the transmit path, the data engine performs packet/cell processing (encapsulation, scrambling).
† In the receive path, the data engine performs packet/cell processing (delineation, descrambling, de-encapsulation).
Figure 1. MARS2G5 P-Pro Block Diagram
Agere Systems Inc.
27
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Description (continued)
Generic Framing Procedure (GFP)
GFP is an emerging new global standard for data encapsulation over SONET/SDH or G.709 (ITU-T G.gfp draft new
standard). It is a generic mechanism for adapting variable length client signals onto an octet synchronous transport
network.
Client signals may be PDU oriented, such as IP/PPP or ethernet MAC (frame-mapped GFP), or block-code oriented, such as fiber channel or ESCON (transparent GFP).
Frame-mapped GFP adaptation may operate at the physical or data-link layer of the client signal. Client PDU visibility is required.
Transparent-mapped GFP operates on the coded 8B/10B character stream, rather than on the incoming client
PDUs.
Figure 2 illustrates the relationship between the higher-layer payloads, GFP, and SDH/OTN paths.
GFP benefits include:
■
■
■
■
■
■
Equips SONET/SDH with flexible/efficient data transport capabilities.
More robust frame delineation than flag-based mechanisms such as HDLC.
No payload dependent frame expansion (no HDLC type byte stuffing).
Flexibility of extension headers. This allows for topology/application specific fields to be defined without affecting
frame delineation functions.
Ability to identify the encapsulated client protocol separately from the extension header. This allows frame forwarding based on extension header fields without requiring recognition of the encapsulated client protocol.
Optional GFP 16-bit or 32-bit frame check sequence (FCS). This allows for fault location on a GFP frame basis
without requiring recognition of the encapsulated client protocol. It also provides a data integrity mechanism for
the encapsulation of protocols that may not have such a mechanism.
ETHERNET
PPP/HDLC
OTHER PACKET ORIENTED
BEARER SERVICES
GFP – PAYLOAD DEPENDENT
(CLIENT SPECIFIC ASPECTS)
GFP—PAYLOAD INDEPENDENT
(COMMON GFP ASPECTS)
SDH PATH
OTN OPU
2682(F)s
Figure 2. GFP Relationship to Transport Payloads
GFP Payload Area CRC-32 Insertion (Version 2.2 and 2.3 Only)
GFP block upgrade on transmit and receive to calculate the CRC-32 over only the payload information area.
■
■
■
■
■
MARS2G5 P-Pro (version 2.0/2.1) calculated CRC-32 over everything except the PLI field.
Two modes are supported for CRC-32 insertion/checking:
1. Null-extension headers:
❏ 4-byte header.
❏ Calculation starts after PLI field and 4 bytes of TYPE field.
2. Linear-extension headers:
❏ 8-byte header.
❏ Calculation starts after PLI field and 4 bytes of TYPE field and 4 bytes of EXT header field.
PLI field value will be modified on transmit by +4 to include CRC-32 bytes.
PLI field value will be modified on receive by –4 when CRC-32 is stripped.
MARS2G5 P-Pro (version 2.2 and 2.3) does not touch PFI field value because it will corrupt tHEC.
28
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Target Applications Supported
MARS2G5 P-Pro (600-Pin LBGA and 792-Pin PBGA)
This multirate/multiprotocol/multimode SONET/SDH data interface device targets the following applications (see
Figure 3 for device interface speed/rate information):
■
Mixed ATM/POS-TDM.
■
Access router and aggregation.
■
Wireless, DSLAM, and gateway.
LINE
INTERFACE
SINGLE
(16 x 155 Mbits/s
LVPECL)
or
QUAD
(1 x 622 Mbits/s
LVPECL)
or
QUAD
(1 x 155 Mbits/s
LVPECL)
PT
DS3
(SPE
MPR)
OVERHEAD
PROCESSOR
MONITOR
SEE TABLE 2
DE
TRANSPORT
OVERHEAD
TERMINATION
PACKET/CELL
FIFOs
POINTER
PROCESSOR
TXCLK
OVERHEAD
PROCESSOR
INSERT
INTERFACE BLOCK
SINGLE
(16 x 155 Mbits/s
LVPECL)
or
QUAD
(1 x 622 Mbits/s
LVPECL)
or
QUAD
(1 x 155 Mbits/s
LVPECL)
DIRECT CELL/PACKET OVER FIBER
UTOPIA/DATA
INTERFACE
PT
(PTR
INTER)
CONTROL
DS3
RXS
DE
SEE TABLE 2
MISCELLANEOUS
DIRECT CELL/PACKET OVER FIBER
TXTOAC RXTOAC
MPU INTERFACE
GPIO
TOAC INTERFACE
Figure 3. MARS2G5 P-Pro Device Interface Speed/Rate Diagram
Agere Systems Inc.
29
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Target Applications Supported (continued)
MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA)
This multirate/multiprotocol/multimode SONET/SDH data interface device targets the following applications (see
Figure 4 for device interface speed/rate information):
■
Mixed ATM/POS-TDM.
■
Access router and aggregation.
■
Wireless, DSLAM, and gateway.
LINE
INTERFACE
DUAL
(1 x 622 Mbits/s
LVPECL)
or
QUAD
(1 x 155 Mbits/s
LVPECL)
PT
DS3
(SPE
MPR)
OVERHEAD
PROCESSOR
MONITOR
SEE TABLE 2
DE
TRANSPORT
OVERHEAD
TERMINATION
PACKET/CELL
FIFOs
POINTER
PROCESSOR
TXCLK
OVERHEAD
PROCESSOR
INSERT
INTERFACE BLOCK
DUAL
(1 x 622 Mbits/s
LVPECL)
or
QUAD
(1 x 155 Mbits/s
LVPECL)
DIRECT CELL/PACKET OVER FIBER
UTOPIA/DATA
INTERFACE
PT
(PTR
INTER)
CONTROL
DS3
RXS
DE
SEE TABLE 2
MISCELLANEOUS
DIRECT CELL/PACKET OVER FIBER
TXTOAC RXTOAC
MPU INTERFACE
GPIO
TOAC INTERFACE
Figure 4. MARS1G2 P-Pro Device Interface Speed/Rate Diagram
30
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Target Applications Supported (continued)
MARS622 P-Pro (TDAT12622) (792-Pin PBGA)
This multirate/multiprotocol/multimode SONET/SDH data interface device targets the following applications (see
Figure 5 for device interface speed/rate information):
■
Mixed ATM/POS-TDM.
■
Access router and aggregation.
■
Wireless, DSLAM, and gateway.
LINE
INTERFACE
SINGLE
(1 x 622 Mbits/s
LVPECL)
or
QUAD
(1 x 155 Mbits/s
LVPECL)
PT
DS3
(SPE
MPR)
OVERHEAD
PROCESSOR
MONITOR
SEE TABLE 2
DE
TRANSPORT
OVERHEAD
TERMINATION
PACKET/CELL
FIFOs
POINTER
PROCESSOR
TXCLK
OVERHEAD
PROCESSOR
INSERT
INTERFACE BLOCK
SINGLE
(1 x 622 Mbits/s
LVPECL)
or
QUAD
(1 x 155 Mbits/s
LVPECL)
DIRECT CELL/PACKET OVER FIBER
UTOPIA/DATA
INTERFACE
PT
(PTR
INTER)
CONTROL
DS3
RXS
DE
SEE TABLE 2
MISCELLANEOUS
DIRECT CELL/PACKET OVER FIBER
TXTOAC RXTOAC
MPU INTERFACE
GPIO
TOAC INTERFACE
Figure 5. MARS622 P-Pro Device Interface Speed/Rate Diagram
Agere Systems Inc.
31
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Overview
This SONET line interface integrated circuit (IC) implements a four-port, sixteen-channel SONET/SDH interface for
asynchronous transfer mode (ATM) and packet over SONET (POS) mappings at the STS-3 (STM-1), STS-12
(STM-4), or STS-48 (STM-12) rate. This device also supports direct cell/packet over fiber at up to 2.488 Gbits/s.
The receive path terminates and processes section, line, and path overhead. It performs framing (A1, A2) and
descrambling, detects alarm conditions, and monitors section, line, and path BIP-8s (B1, B2, and B3), accumulating error counts for each level for performance-monitoring purposes. Line and path remote error indications (M1,
G1) are also accumulated. The payload pointers (H1, H2) are interpreted and the synchronous payload envelope
(SPE) is extracted.
When used to implement an ATM UNI, the device performs cell delineation on the SPE. HCS error correction is
provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon
detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled before being
passed to a 32-cell FIFO buffer. The received cells are read from the FIFO using one of four generic 8-/16-/32-bit
wide UTOPIA level 2 and level 3 compliant interface. Counts of received ATM cells, uncorrectable HCS errors, correctable HCS errors, and idle/unassigned ATM cells are accumulated independently for performance-monitoring
purposes.
When used to implement a POS UNI, the device descrambles the SPE before extracting HDLC frames. The control escape characters are removed. Descrambling can be performed after control escape byte destuffing (or
before to control malicious HDLC expansion). The optional 16- or 32-bit error check sequence is verified for correctness. The packets are placed into a 256-byte FIFO buffer. The received packets are read from the FIFO using
a generic 8-/16-/32-bit wide enhanced UTOPIA level 2 and level 3 compliant interface. Counts of errored/dropped
packets are accumulated independently for performance-monitoring purposes. The device POS implementation
also allows the optional detach of a per-channel provisionable PPP header.
The transmit path inserts section, line, and path overhead. It inserts the framing pattern (A1, A2), performs scrambling, inserts AIS (optionally), and calculates and inserts section, line, and path BIP-8s (B1, B2, B3). Line and path
remote failure indications (M1, G1) are inserted based on received BIP-8 errors. The payload pointers (H1, H2) are
generated, and the SPE is inserted.
When used to implement an ATM UNI, ATM cells are written into an internal four-cell (per channel) FIFO buffer
using a generic 8-/16-/32-bit wide UTOPIA level 2 and level 3 compliant interface. Idle/unassigned cells are automatically inserted when the internal FIFO is empty. The device provides generation of the header check sequence
and scrambles the ATM payload. Also supports cell-based UNI per I.432 (i.e., ATM over fiber).
When used to implement a POS UNI, the device writes packets into an internal 256-byte (per channel) FIFO buffer
using a generic 8/16/32-bit wide enhanced UTOPIA level 2 and level 3 compliant interface. HDLC framing performs
the insertion of flags, control escape characters and the FCS fields. Either the CRC-CCITT or CRC-32 (in regular
or reversed mode) can be computed and added to the frame. Counts of transmitted packets and errored/dropped
packets are accumulated for performance-monitoring purposes.
The device is provisioned, controlled, and monitored using a generic 16-bit microprocessor interface. A standard
five-signal IEEE® 1149.1 compliant JTAG test port is also provided for scan, boundary scan, and BIST purposes.
A 4-bit general-purpose input/output (GPIO) interface is provided to control and/or monitor other onboard devices.
32
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Overview (continued)
Figure 6 shows the external interfaces.
PLL
TEST
TXFSYNC
TXCLKQ
TXCLK
2
2
2
TXTOH
4
3
ATM
FRAME
INSERTION
TOH
SOH
POH
LOH
HDLC
ECLREF
STS-3/12
STS-48 RXD
RXCLK
32
SCRM
SCRM
ATM
CD
2
32
FRMR
UTOPIA INTERFACE
STS-48 TXQ
STS-3/12
POINTER
PROCESSOR
DSCRM
HDLC
DSCRM
110
110
TXUTOPIA
RXUTOPIA
2
SOH
LOH
12
RXREF
RXTOH
POH
CONTROL
43
MPU
INTERFACE
4
GPIO
6
JTAG
5-7395(F).aTDAT162
Figure 6. MARS2G5 P-Pro External Interfaces
Agere Systems Inc.
33
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Overview (continued)
Clocking
The following diagram shows a somewhat simplified picture of the major clock domains within the MARS2G5 P-Pro
in the normal SONET/SDH operating mode. There are a total of 16 different clock domains as shown in the following table.
Table 1. List of the Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode
Clock Domain Name
Number of Clocks
Core
1
PLL
2
MPU
1
Receive Line Interface
4
(one each for A, B, C, and D)
UTOPIA Interface
8
(one each for A, B, C, and D);
(one each for Rx and Tx on interface A;
one each for Rx and Tx on interface B)
78 MHz
CORE
CLOCK
PLL
A
A
B
B
C
C
D
D
CORE
CLOCK
DOMAIN
MPU
PATH FOR POF SUPPORT
A
RXLINE RXOHP
PECL I/O
A
A
B
A
B
B
B
C
C
C
D
D
POINTER
PROCESSOR
(PP)
PT/DS3
DATA
ENGINE
(DE)
PT/DS3
RXS/DE
UT TX
C
D
A
UT I/O
PECL I/O
TXLINE TXOHP
B
UT RX C
D
D
PATH FOR POF SUPPORT
5-8701(F)r.3TDAT16
Figure 7. Clock Domains in the MARS2G5 P-Pro, SONET/SDH Mode
34
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Overview (continued)
Clocking (continued)
The following diagram shows a somewhat simplified picture of the clock domains within the MARS2G5 P-Pro when
it is configured into the packet over fiber (POF) mode. In this mode, large subsections of the device are unused.
78 MHz
CORE
CLOCK
PLL
TXLINE
MPU
PECL I/O
A
B
C
D
CORE
CLOCK
DOMAIN
PATH FOR POF SUPPORT
RXLINE
PECL I/O
PT/DS3
B
C
DATA
ENGINE
(DE)
UT TX
RXS/DE
UT RX
UT I/O
A
PATH FOR POF SUPPORT
D
5-8702(F)
Figure 8. Clock Domains in the Packet-Over-Fiber (POF) Mode
Agere Systems Inc.
35
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
MARS2G5 P-Pro (792-Pin PBGA) Low-Speed Devices Available
The functionality of the MARS2G5 P-Pro (792-Pin PBGA) is available in lower-speed devices which are indicated
below with the limitations noted.
MARS1G2 P-Pro (TDAT161G2) (792-Pin PBGA)
MARS1G2 P-Pro is intended for use in quad OC-3 or dual OC-12 TDAT applications. It has the following limitations
with respect to MARS2G5 P-Pro (TDAT162G52):
■
Supports quad OC-3 or dual OC-12 rate line ports.
■
The UTOPIA interface for the device can be operated as follows:
— 4 x 16-bit interfaces (A, B, C, and D) operating up to 26 MHz (2 x 16-bit interface (UT ports A and B only) operating up to 52 MHz (U2/U2+)).
— 4 x 8-bit interfaces (A, B, C, and D) operating up to 52 MHz (U2/U2+).
— 1 x 32-bit interface (UT ports A and B) operating up to 52 MHz (U3/U3+).
— 2 x 8-bit interfaces (A and B) operating up to 104 MHz (U3/U3+).
MPHY is possible in all UTOPIA interfacing modes, (i.e., channels addressed from any interface in MPHY
mode). For example, when connecting to an APP550 (Agere’s network processor), the 2 x 8 (UT ports A and B)
mode at 104 MHz can be used.
MARS622 P-Pro (TDAT12622) (792-Pin PBGA)
MARS622 P-Pro is intended for use in quad OC-3 or single OC-12 TDAT applications. The minimum channel size
is one STS-1, and the device is limited to 12 channels. In addition to the 12-channel limitation, the MARS622 P-Pro
(TDAT12622) also has the following limitations with respect to MARS2G5 P-Pro (TDAT162G52):
■
Supports quad OC-3 rate line ports or a single OC-12 rate line port.
■
The UTOPIA interface for this device can be operated as follows:
— 4 x 16-bit interfaces (UT ports A, B, C, and D) operating up to 26 MHz, (1 x 16-bit interface (UT port A only)
operating up to 52 MHz (U2/U2+)).
— 4 x 8-bit interfaces (UT ports A, B, C, and D) operating up to 52 MHz (U2/U2+).
— 1 x 8-bit interfaces (UT port A only) operating up to 104 MHz (U3/U3+).
MPHY is possible in all UTOPIA interfacing modes, (i.e., channels can be addressed from any interface in MPHY
mode). For example, when connecting to APP550 (Agere’s network processor), the 1 x 8 (UT port A only) mode
at 104 MHz can be used.
36
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
MARS2G5 P-Pro Device Product Line Table Summaries
Table 2 highlights which ports are supported for the line and UTOPIA interfaces for the MARS2G5 P-Pro. Letters in parentheses indicate which ports are
available for that particular interface.
Table 2. MARS2G5 P-Pro Device Product Line—Data Port Summary
Device
Line Ports
OC-3
OC-12
MARS2G5 P
4*
4*
(TADM042G52) (A, B, C, D) (A, B, C, D)
(792-Pin PBGA
and 600-Pin LBGA)
MARS1G2 P
(TADM021G2)
(792-Pin PBGA)
MARS622 P
(TADM04622)
(792-Pin PBGA)
4*
(A, B, C, D)
4
(A, B, C, D)
2
(A,B)
1
(A)
UTOPIA MPHY/Data Interface
OC-48
1
(A)
NA
NA
UTOPIA Level
Interface
UTOPIA
Ports
Max Frequency
See the UTOPIA (UT) Block section and the MARS2G5
P-VC (TADMVC2G52) Device Advisory for Version 2.2
and Version 2.3 of the Device (AY03-015SONT) item
UT27. Limitations in UTOPIA Clock Frequency.
4
(A, B, C, D)
U2/U2+
4 x 16-bit
26 MHz
4
(A, B, C, D)
U2/U2+
2 x 16-bit
52 MHz
2
(A, B)
U2/U2+
4 x 8-bit
52 MHz
4
(A, B, C, D)
U3/U3+
1 x 32-bit
52 MHz
2
(A, B)
U3/U3+
2 x 8-bit
104 MHz
2
(A, B)
U2/U2+
4 x 16-bit
26 MHz
4
(A, B, C, D)
U2/U2+
1 x 16-bit
52 MHz
1
(A)
U2/U2+
4 x 8-bit
52 MHz
4
(A, B, C, D)
U3/U3+
1 x 8-bit
104 MHz
1
(A)
* No support for DS3 and E3 framing on ports C and D.
Note: NA = not available.
Agere Systems Inc.
37
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information
792-Pin PBGA Pin Assignments
A pin assignment conversion between the 792-pin and 600-pin devices is shown in Table 3.
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
792-Pin Signal Name
VDDD2
VDDD2
VDDD2
GNDD
GNDD
VDDD2
VDDD2
NC
GNDD
NC
VDDD2
VDDD2
NC
NC
GNDD
GNDD
NC
NC
VDDD2
VDDD2
VDDD2
MPU_ADDR8
MPU_ADDR2
GNDD
GNDD
GNDD
GNDD
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
GNDD
GNDD
GNDD
VDDD2
VDDD2
VDDD2
600-Pin Signal Name
VDDD
VDDD
GNDD
GNDD
VDDD2
VDDD2
GNDD
GNDD
MPU_DATA1
MPU_DATA6
MPU_DATA10
MPU_DATA15
GNDD
MPU_ADDR8
MPU_ADDR12
GNDD
VDDD
VDDD
NC
GNDD
NC
NC
GNDD
NC
NC
NC
GNDD
GNDD
GNDD
VDDD2
VDDD2
GNDD
GNDD
VDDD
VDDD
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
38
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
792-Pin Signal Name
VDDD2
VDDD2
VDDD2
GNDD
GNDD
VDDD2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
MPU_ADDR12
MPU_ADDR9
MPU_ADDR3
MPU_DATA13
MPU_DATA9
MPU_DATA8
MPU_DATA4
MPU_DSN
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
GNDD
GNDD
GNDD
VDDD2
VDDD2
VDDD2
600-Pin Signal Name
VDDD
VDDD
GNDD
GNDD
NC
PLL_VDDD2
MPU_INTN
MPU_CSN
MPU_DATA0
MPU_DATA5
MPU_DATA9
MPU_DATA14
MPU_ADDR3
MPU_ADDR7
MPU_ADDR11
MPU_ADDR15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GNDD
GNDD
VDDD
VDDD
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
39
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
792-Pin Signal Name
VDDD2
VDDD2
VDDD2
GNDD
GNDD
VDDD2
NC
NC
NC
GNDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
MPU_ADDR13
NC
MPU_ADDR4
MPU_DATA14
MPU_DATA12
MPU_DATA7
MPU_DATA3
MPU_RWN
MPU_MPCLK
RSTN
PLL_VDDD2
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD2
VDDD2
VDDD2
600-Pin Signal Name
GNDD
GNDD
VDDD
GNDD
PLLREF
PLL_GND
RSTN
MPU_MPCLK
MPU_DSN
MPU_DATA4
MPU_DATA8
MPU_DATA13
MPU_ADDR2
MPU_ADDR6
MPU_ADDR10
MPU_ADDR14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GNDD
VDDD
GNDD
GNDD
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
40
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
792-Pin Signal Name
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD2
NC
NC
NC
VDDD2
NC
NC
NC
NC
NC
NC
NC
NC
NC
MPU_ADDR14
MPU_ADDR10
MPU_ADDR5
MPU_DATA15
MPU_DATA10
MPU_DATA6
MPU_DATA2
MPU_ADSN
MPU_DTN
PMRST
PLL_GND
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
600-Pin Signal Name
GNDD
GNDD
GNDD
VDDD2
PLLFB
NC
PMRST
MPU_MPMODE
MPU_RWN
MPU_DATA3
MPU_DATA7
MPU_DATA12
MPU_ADDR1
MPU_ADDR5
NC
MPU_ADDR13
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDDD2
NC
NC
NC
NC
VDDD2
GNDD
GNDD
GNDD
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
41
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
792-Pin Signal Name
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD
VDDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
MPU_ADDR15
MPU_ADDR11
MPU_ADDR6
MPU_ADDR0
MPU_DATA11
MPU_DATA5
MPU_DATA1
MPU_CSN
MPU_INTN
ICTN
NC
NC
GNDD
VDDD
VDDD
GNDD
GNDD
GNDD
GNDD
GNDD
600-Pin Signal Name
VDDD2
IDDQMODE
PLL_VDDD2
PLL_GNDD
VDDD2
NC
ICTN
MPU_DTN
MPU_ADSN
MPU_DATA2
VDDD
MPU_DATA11
MPU_ADDR0
MPU_ADDR4
MPU_ADDR9
VDDD2
NC
NC
NC
VDDD2
NC
NC
NC
NC
VDDD
NC
NC
NC
NC
NC
VDDD2
NC
NC
NC
VDDD2
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
42
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
792-Pin Signal Name
GNDD
GNDD
GNDD
GNDD
VDDD
VDDD
VDDD
NC
NC
NC
GNDD
GNDD
NC
NC
VDDD
VDDD
NC
NC
GNDD
GNDD
GNDD
MPU_ADDR7
MPU_ADDR1
VDDD
VDDD
MPU_DATA0
MPU_MPMODE
GNDD
GNDD
NC
PLLREF
PLLFB
VDDD
VDDD
VDDD
GNDD
GNDD
GNDD
GNDD
600-Pin Signal Name
VDDD2
TCLK
GNDD
TMS
NC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXSPAA
RXSPAB
RXSPAC
RXSPAD
VDDD2
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
43
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
G1
G2
G3
G4
G5
G6
G31
G32
G33
G34
G35
G36
G37
G38
G39
H1
H2
H3
H4
H5
H6
H31
H32
H33
H34
H35
H36
H37
H38
H39
J1
J2
J3
J4
J5
J6
J31
J32
J33
J34
792-Pin Signal Name
VDDD2
VDDD2
GNDD
GNDD
VDDD
VDDD
—
—
—
VDDD
PLL_GNDD
GNDD
GNDD
VDDD2
VDDD2
VDDD2
VDDD2
GNDD
GNDD
NC
NC
—
—
—
PLL_VDDD2
GNDD
IDDQMODE
GNDD
VDDD2
VDDD2
VDDD2
VDDD2
GNDD
RXSPAC
RXSPAB
NC
—
—
—
GNDD
600-Pin Signal Name
GNDD
TDO
TRSTN
NC
TDI
—
TXSPAA
TXADDRA0
TXADDRA1
TXCLKA
GNDD
—
—
—
—
GNDD
TXCLKQP
GNDD
CLKDIV
GNDD
—
TXSZA
TXERRA
TXPPAA
TXENBA
GNDD
—
—
—
—
TXD14N
TXD14P
TXD15N
TXD15P
TXCLKQN
—
TXEOPA
TXSOPA
TXPRTYA
TXDATAA15
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
44
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
J35
J36
J37
J38
J39
K1
K2
K3
K4
K5
K6
K31
K32
K33
K34
K35
K36
K37
K38
K39
L1
L2
L3
L4
L5
L6
L31
L32
L33
L34
L35
L36
L37
L38
L39
M1
M2
M3
M4
M5
792-Pin Signal Name
NC
GNDD
GNDD
GNDD
VDDD2
VDDD2
VDDD2
TXADDRA1
TXSPAA
RXSPAD
RXSPAA
—
—
—
TMS
TCLK
TDI
NC
VDDD2
VDDD2
VDDD2
TXEOPA
TXERRA
TXCLKA
TXADDRA0
GNDD
—
—
—
GNDD
TRSTN
TDO
CLKDIV
VDDD2
VDDD2
VDDD2
TXDATAA15
TXSOPA
TXPPAA
TXSZA
600-Pin Signal Name
TXDATAA14
—
—
—
—
TXD12N
TXD12P
TXD13N
TXD13P
VDDD
—
TXDATAA13
TXDATAA12
TXDATAA11
TXDATAA10
TXDATAA9
—
—
—
—
TXD10N
TXD10P
TXD11N
TXD11P
VDDD
—
VDDD
TXDATAA8
TXDATAA7
TXDATAA6
TXDATAA5
—
—
—
—
TXD8N
TXD8P
TXD9N
TXD9P
VDDD
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
45
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
M6
M31
M32
M33
M34
M35
M36
M37
M38
M39
N1
N2
N3
N4
N5
N6
N31
N32
N33
N34
N35
N36
N37
N38
N39
P1
P2
P3
P4
P5
P6
P31
P32
P33
P34
P35
P36
P37
P38
P39
792-Pin Signal Name
GNDD
—
—
—
GNDD
TXCLKQP
TXCLKQN
TXD15P
TXD15N
VDDD2
TXDATAA7
TXDATAA10
TXDATAA12
TXDATAA13
TXPRTYA
TXENBA
—
—
—
TXD14P
TXD14N
TXD13P
TXD13N
TXD12P
TXD12N
TXDATAA2
TXDATAA5
TXDATAA8
TXDATAA9
TXDATAA11
TXDATAA14
—
—
—
TXD11P
TXD11N
TXD10P
TXD10N
TXD8P
TXD8N
600-Pin Signal Name
—
TXDATAA4
TXDATAA3
TXDATAA2
TXDATAA1
TXDATAA0
—
—
—
—
GNDD
TXD6N
TXD6P
TXD7N
TXD7P
—
RXDATAA15
RXDATAA14
RXDATAA13
RXDATAA12
GNDD
—
—
—
—
TXD4N
TXD4P
TXD5N
VDDD
TXD5P
—
RXDATAA11
RXDATAA10
RXDATAA9
RXDATAA8
RXDATAA7
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
46
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
R1
R2
R3
R4
R5
R6
R31
R32
R33
R34
R35
R36
R37
R38
R39
T1
T2
T3
T4
T5
T6
T31
T32
T33
T34
T35
T36
T37
T38
T39
U1
U2
U3
U4
U5
U6
U31
U32
U33
U34
U35
792-Pin Signal Name
GNDD
TXDATAA0
TXDATAA3
TXDATAA4
TXDATAA6
VDDD
—
—
—
VDDD
TXD9P
TXD9N
TXD7P
TXD7N
GNDD
GNDD
RXDATAA11
RXDATAA13
RXDATAA15
TXDATAA1
VDDD
—
—
—
VDDD
TXD6P
TXD6N
TXD5P
TXD5N
GNDD
RXDATAA4
RXDATAA6
RXDATAA8
RXDATAA10
RXDATAA12
RXDATAA14
—
—
—
TXD4P
TXD4N
600-Pin Signal Name
VDDD
TXD2N_TXDBN
TXD2P_TXDBP
TXD3P_TXDAP
TXD3N_TXDAN
—
RXDATAA6
RXDATAA5
RXDATAA4
RXDATAA3
RXDATAA2
—
—
—
—
GNDD
TXD0P_TXDDP
TXD1N_TXDCN
TXD1P_TXDCP
VDDD2
—
VDDD2
RXDATAA1
RXDATAA0
RXPRTYA
GNDD
—
—
—
—
TXFSYNCN
TXD0N_TXDDN
TXFSYNCP
TXCLKP
TXCLKN
—
RXSOPA
RXEOPA
TXADDRA2
RXENBA
VDDD
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
47
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
U36
U37
U38
U39
V1
V2
V3
V4
V5
V6
V31
V32
V33
V34
V35
V36
V37
V38
V39
W1
W2
W3
W4
W5
W6
W31
W32
W33
W34
W35
W36
W37
W38
W39
Y1
Y2
Y3
Y4
Y5
Y6
792-Pin Signal Name
TXD3P_TXDAP
TXD3N_TXDAN
TXD2P_TXDBP
TXD2N_TXDBN
RXPRTYA
RXDATAA2
RXDATAA3
RXDATAA5
RXDATAA7
RXDATAA9
—
—
—
TXD1P_TXDCP
TXD1N_TXDCN
TXD0P_TXDDP
TXD0N_TXDDN
TXCLKP
TXCLKN
VDDD2
RXEOPA
RXSOPA
RXDATAA0
RXDATAA1
GNDD
—
—
—
GNDD
GNDD
TXFSYNCN
TXFSYNCP
RXCLKN_RXDAN
VDDD2
VDDD2
RXERRA
RXPPAA
RXENBA
TXADDRA2
GNDD
600-Pin Signal Name
—
—
—
—
VDDD
VDDD
GNDD
RXCLKN_RXDAN
RXCLKP_RXDAP
—
GNDD
RXERRA
RXPPAA
RXADDRA2
VDDD
—
—
—
—
VDDD
RXD14N_RXCLKAN
RXD14P_RXCLKAP
RXD15N_RXDBN
RXD15P_RXDBP
—
RXADDRA0
RXADDRA1
RXCLKA
TXADDRB0
RXSZA
—
—
—
—
GNDD
RXD13N_RXCLKBN
RXD13P_RXCLKBP
GNDD
VDDD2
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
48
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
AA1
AA2
AA3
AA4
AA5
AA6
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AA39
AB1
AB2
AB3
AB4
AB5
AB6
AB31
AB32
AB33
AB34
AB35
AB36
AB37
AB38
AB39
792-Pin Signal Name
—
—
—
GNDD
RXD13N_RXCLKBN
RXD14P_RXCLKAP
RXD14N_RXCLKAN
RXCLKP_RXDAP
VDDD2
RXADDRA2
RXADDRA1
RXSZA
RXADDRA0
RXCLKA
GNDD
—
—
—
GNDD
RXD13P_RXCLKBP
RXD15P_RXDBP
RXD15N_RXDBN
VDDD2
VDDD2
TXADDRB0
TXPPAB
TXERRB
TXSZB
TXCLKB
TXADDRB1
—
—
—
RXD9P_RXCLKDP
RXD9N_RXCLKDN
RXD12P_RXDCP
RXD12N_RXDCN
RXD11P_RXCLKCP
RXD11N_RXCLKCN
600-Pin Signal Name
VDDD2
TXSZB
TXCLKB
TXADDRB1
GNDD
—
—
—
—
RXD11N_RXCLKCN
RXD11P_RXCLKCP
RXD12N_RXDCN
RXD12P_RXDCP
GNDD
—
TXEOPB
TXSOPB
TXENBB
TXPPAB
TXERRB
—
—
—
—
RXD9N_RXCLKDN
RXD9P_RXCLKDP
RXD10N_RXDDN
RXD10P_RXDDP
VDDD
—
TXDATAB13
TXDATAB12
TXDATAB14
TXDATAB15
TXPRTYB
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
49
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AC1
AC2
AC3
AC4
AC5
AC6
AC31
AC32
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AD1
AD2
AD3
AD4
AD5
AD6
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AE1
AE2
AE3
AE4
AE5
AE6
AE31
AE32
AE33
AE34
AE35
792-Pin Signal Name
TXENBB
TXDATAB14
TXDATAB15
TXPRTYB
TXSOPB
TXEOPB
—
—
—
RXD8P
RXD8N
RXD7P
RXD7N
RXD10P_RXDDP
RXD10N_RXDDN
GNDD
TXDATAB10
TXDATAB11
TXDATAB13
TXDATAB12
VDDD
—
—
—
VDDD
RXD6P
RXD6N
RXD5P
RXD5N
GNDD
GNDD
TXDATAB9
TXDATAB8
TXDATAB7
TXDATAB6
VDDD
—
—
—
VDDD
RXD4P
600-Pin Signal Name
GNDD
RXD7N
RXD7P
RXD8N
RXD8P
—
TXDATAB8
TXDATAB9
TXDATAB10
TXDATAB11
GNDD
—
—
—
—
RXD5N
RXD5P
RXD6N
RXD6P
VDDD
—
TXDATAB3
TXDATAB4
TXDATAB5
TXDATAB6
TXDATAB7
—
—
—
—
RXD3N
RXD3P
RXD4N
RXD4P
VDDD
—
VDDD
RXDATAB15
TXDATAB0
TXDATAB1
TXDATAB2
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
50
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AE36
AE37
AE38
AE39
AF1
AF2
AF3
AF4
AF5
AF6
AF31
AF32
AF33
AF34
AF35
AF36
AF37
AF38
AF39
AG1
AG2
AG3
AG4
AG5
AG6
AG31
AG32
AG33
AG34
AG35
AG36
AG37
AG38
AG39
AH1
AH2
AH3
AH4
AH5
AH6
792-Pin Signal Name
RXD4N
RXD3P
RXD3N
GNDD
TXDATAB5
TXDATAB4
TXDATAB3
TXDATAB2
TXDATAB1
TXDATAB0
—
—
—
RXD0P
RXD0N
RXD2P
RXD2N
RXD1P
RXD1N
RXDATAB15
RXDATAB14
RXDATAB13
RXDATAB12
RXDATAB10
RXDATAB11
—
—
—
GPIO2
GPIO3
ECLREFHI
ECLREFLO
VDDD2
VDDD2
VDDD2
RXDATAB9
RXDATAB8
RXDATAB7
RXDATAB6
GNDD
600-Pin Signal Name
—
—
—
—
RXD1N
RXD1P
RXD2N
RXD2P
VDDD
—
RXDATAB10
RXDATAB11
RXDATAB12
RXDATAB13
RXDATAB14
—
—
—
—
RXD0N
RXD0P
ECLREFLO
ECLREFHI
GPIO3
—
RXDATAB5
RXDATAB6
RXDATAB7
RXDATAB8
RXDATAB9
—
—
—
—
GNDD
GPIO2
GPIO1
GPIO0
TXTOHF
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
51
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AH31
AH32
AH33
AH34
AH35
AH36
AH37
AH38
AH39
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AJ37
AJ38
AJ39
AK1
AK2
AK3
AK4
AK5
AK6
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AK39
792-Pin Signal Name
—
—
—
GNDD
TXTOHF
GPIO0
GPIO1
VDDD2
VDDD2
VDDD2
RXDATAB5
RXDATAB4
RXDATAB3
RXDATAB2
GNDD
—
—
—
GNDD
TXSPAD
TXTOHD
TXTOHCLK
VDDD2
VDDD2
VDDD2
VDDD2
RXDATAB1
RXDATAB0
RXPRTYB
RXEOPB
—
—
—
RXREF
TXSPAB
TXSPAC
GNDD
VDDD2
VDDD2
600-Pin Signal Name
RXDATAB1
RXDATAB2
RXDATAB3
RXDATAB4
GNDD
—
—
—
—
GNDD
TXTOHCLK
TXTOHD
TXSPAD
TXSPAC
—
RXEOPB
RXSOPB
RXPRTYB
RXDATAB0
GNDD
—
—
—
—
VDDD2
TXSPAB
RXREF
RXTOHFA
RXTOHCLKA
—
RXSZB
RXERRB
RXPPAB
RXENBB
VDDD2
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
52
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AL1
AL2
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL35
AL36
AL37
AL38
AL39
792-Pin Signal Name
VDDD2
VDDD2
RXSOPB
RXENBB
RXPPAB
RXERRB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXTOHDA
RXTOHCLKA
RXTOHFA
GNDD
VDDD2
VDDD2
600-Pin Signal Name
VDDD2
RXTOHDA
RXTOHFB
RXTOHCLKB
VDDD2
RXTOHCLKC
RXTOHCLKD
RXADDRD0
RXPPAD
RXDATAD0
VDDD
RXDATAD9
RXDATAD14
TXDATAD3
TXDATAD8
VDDD2
TXSOPD
VDDD
RXADDRC1
VDDD2
RXSOPC
RXDATAC3
RXDATAC7
RXDATAC12
VDDD
TXDATAC5
TXDATAC10
TXDATAC14
TXEOPC
TXSZC
VDDD2
RXADDRB1
RXADDRB0
RXCLKB
VDDD2
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
53
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AM1
AM2
AM3
AM4
AM5
AM6
AM7
AM8
AM9
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM37
AM38
AM39
792-Pin Signal Name
VDDD2
VDDD2
GNDD
RXSZB
RXCLKB
RXADDRB0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXTOHCLKB
RXTOHFB
GNDD
GNDD
VDDD2
VDDD2
600-Pin Signal Name
GNDD
GNDD
GNDD
VDDD2
RXTOHDB
RXTOHDC
TXADDRD0
RXCLKD
RXENBD
RXDATAD1
RXDATAD5
RXDATAD10
RXDATAD15
TXDATAD2
TXDATAD7
TXDATAD12
TXPRTYD
TXERRD
TXADDRC2
RXSZC
RXEOPC
RXDATAC2
RXDATAC6
RXDATAC11
TXDATAC0
TXDATAC4
TXDATAC9
TXDATAC13
TXSOPC
TXERRC
TXADDRC0
VDDD2
GNDD
GNDD
GNDD
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
54
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AN39
792-Pin Signal Name
VDDD2
VDDD2
GNDD
GNDD
RXADDRB1
VDDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDD
VDDD
GNDD
GNDD
VDDD2
VDDD2
600-Pin Signal Name
GNDD
GNDD
VDDD
GNDD
RXTOHFC
GNDD
RXTOHDD
RXSZD
RXEOPD
RXDATAD2
RXDATAD6
RXDATAD11
TXDATAD0
TXDATAD4
TXDATAD9
TXDATAD13
TXEOPD
TXSZD
RXADDRC2
RXCLKC
RXENBC
RXDATAC1
RXDATAC5
RXDATAC10
RXDATAC15
TXDATAC3
TXDATAC8
TXDATAC12
TXPRTYC
TXPPAC
TXADDRC1
GNDD
VDDD
GNDD
GNDD
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
55
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AP1
AP2
AP3
AP4
AP5
AP6
AP7
AP8
AP9
AP10
AP11
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AP38
AP39
792-Pin Signal Name
GNDD
GNDD
GNDD
GNDD
VDDD
VDDD
VDDD
TXADDRC1
TXERRC
TXSOPC
GNDD
GNDD
TXDATAC4
RXDATAC14
VDDD
VDDD
RXEOPC
RXADDRC0
GNDD
GNDD
GNDD
TXDATAD7
TXDATAD1
VDDD
VDDD
RXDATAD1
RXENBD
GNDD
GNDD
RXTOHFD
TXADDRD1
RXTOHDB
VDDD
VDDD
VDDD
GNDD
GNDD
GNDD
GNDD
600-Pin Signal Name
VDDD
VDDD
GNDD
GNDD
TXADDRD1
RXTOHFD
RXADDRD1
RXERRD
RXSOPD
RXDATAD3
RXDATAD7
RXDATAD12
TXDATAD1
TXDATAD5
TXDATAD10
TXDATAD14
TXDATAD15
TXPPAD
TXCLKD
RXADDRC0
RXPPAC
RXDATAC0
RXDATAC4
RXDATAC9
RXDATAC14
TXDATAC2
TXDATAC7
TXDATAC11
TXDATAC15
TXENBC
TXCLKC
GNDD
GNDD
VDDD
VDDD
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
56
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AR1
AR2
AR3
AR4
AR5
AR6
AR7
AR8
AR9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR25
AR26
AR27
AR28
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR39
792-Pin Signal Name
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD
TXADDRC0
TXCLKC
TXPPAC
TXPRTYC
TXDATAC13
TXDATAC9
TXDATAC3
RXDATAC15
RXDATAC8
RXDATAC3
RXSOPC
RXCLKC
RXADDRC2
TXERRD
TXDATAD14
TXDATAD9
TXDATAD3
RXDATAD14
RXDATAD9
RXDATAD3
RXSOPD
RXSZD
RXADDRD1
RXTOHCLKD
RXTOHCLKC
RXTOHFC
VDDD
VDDD
GNDD
GNDD
GNDD
GNDD
GNDD
600-Pin Signal Name
VDDD
VDDD
GNDD
GNDD
VDDD2
VDDD2
GNDD
GNDD
RXPRTYD
RXDATAD4
RXDATAD8
RXDATAD13
GNDD
TXDATAD6
TXDATAD11
GNDD
TXENBD
VDDD
VDDD
GNDD
RXERRC
RXPRTYC
GNDD
RXDATAC8
RXDATAC13
TXDATAC1
TXDATAC6
GNDD
GNDD
VDDD2
VDDD2
GNDD
GNDD
VDDD
VDDD
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
57
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AT1
AT2
AT3
AT4
AT5
AT6
AT7
AT8
AT9
AT10
AT11
AT12
AT13
AT14
AT15
AT16
AT17
AT18
AT19
AT20
AT21
AT22
AT23
AT24
AT25
AT26
AT27
AT28
AT29
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
792-Pin Signal Name
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
TXSZC
TXENBC
TXDATAC15
TXDATAC12
TXDATAC8
TXDATAC5
RXDATAC13
RXDATAC9
RXDATAC4
RXPRTYC
RXSZC
TXCLKD
TXPPAD
TXDATAD15
TXDATAD10
TXDATAD5
TXDATAD0
RXDATAD11
RXDATAD6
RXDATAD0
RXPPAD
RXADDRD0
TXADDRD0
RXTOHDC
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
600-Pin Signal Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
58
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AU1
AU2
AU3
AU4
AU5
AU6
AU7
AU8
AU9
AU10
AU11
AU12
AU13
AU14
AU15
AU16
AU17
AU18
AU19
AU20
AU21
AU22
AU23
AU24
AU25
AU26
AU27
AU28
AU29
AU30
AU31
AU32
AU33
AU34
AU35
AU36
AU37
AU38
AU39
792-Pin Signal Name
VDDD2
VDDD2
VDDD2
GNDD
GNDD
GNDD
GNDD
GNDD
TXEOPC
TXDATAC14
TXDATAC11
TXDATAC7
TXDATAC2
TXDATAC0
RXDATAC7
RXDATAC5
RXDATAC0
RXPPAC
TXADDRC2
TXSZD
TXSOPD
TXDATAD12
TXDATAD6
TXDATAD2
RXDATAD12
RXDATAD7
RXDATAD2
RXEOPD
RXCLKD
RXTOHDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD2
VDDD2
VDDD2
600-Pin Signal Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
59
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AV1
AV2
AV3
AV4
AV5
AV6
AV7
AV8
AV9
AV10
AV11
AV12
AV13
AV14
AV15
AV16
AV17
AV18
AV19
AV20
AV21
AV22
AV23
AV24
AV25
AV26
AV27
AV28
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AV37
AV38
AV39
792-Pin Signal Name
VDDD2
VDDD2
VDDD2
GNDD
GNDD
GNDD
VDDD2
VDDD2
VDDD2
VDDD2
TXDATAC10
TXDATAC6
TXDATAC1
RXDATAC12
RXDATAC10
RXDATAC6
RXDATAC2
RXENBC
RXADDRC1
TXENBD
TXEOPD
TXDATAD13
TXDATAD8
TXDATAD4
RXDATAD15
RXDATAD10
RXDATAD5
RXPRTYD
RXERRD
VDDD2
VDDD2
VDDD2
VDDD2
GNDD
GNDD
GNDD
VDDD2
VDDD2
VDDD2
600-Pin Signal Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
60
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 3. Pin Assignments for 792-Pin PBGA and 600-Pin LBGA by Pin Number Order (continued)
Pin
AW1
AW2
AW3
AW4
AW5
AW6
AW7
AW8
AW9
AW10
AW11
AW12
AW13
AW14
AW15
AW16
AW17
AW18
AW19
AW20
AW21
AW22
AW23
AW24
AW25
AW26
AW27
AW28
AW29
AW30
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AW39
792-Pin Signal Name
VDDD2
VDDD2
VDDD2
GNDD
GNDD
GNDD
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
RXDATAC11
GNDD
GNDD
RXDATAC1
RXERRC
VDDD2
VDDD2
VDDD2
TXPRTYD
TXDATAD11
GNDD
GNDD
RXDATAD13
RXDATAD8
RXDATAD4
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
GNDD
GNDD
GNDD
VDDD2
VDDD2
VDDD2
600-Pin Signal Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
61
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name
Pin
L37
AG36
AG37
A4
A5
A9
A15
A16
A24
A25
A26
A27
A34
A35
A36
B4
B5
B34
B35
B36
C4
C5
C31
C32
C33
C34
C35
C36
D1
D2
D3
D4
D5
D31
D32
D33
D34
D35
D36
792-Pin Signal Name
CLKDIV
ECLREFHI
ECLREFLO
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
Pin
L37
AG36
AG37
A4
A5
A9
A15
A16
A24
A25
A26
A27
A34
A35
A36
B4
B5
B34
B35
B36
C4
C5
C31
C32
C33
C34
C35
C36
D1
D2
D3
D4
D5
D31
D32
D33
D34
D35
D36
600-Pin Signal Name
—
—
—
GNDD
VDDD2
MPU_DATA1
MPU_ADDR12
GNDD
NC
NC
NC
GNDD
VDDD
VDDD
—
GNDD
NC
VDDD
VDDD
—
GNDD
PLLREF
NC
GNDD
VDDD
GNDD
GNDD
—
GNDD
GNDD
GNDD
VDDD2
PLLFB
NC
VDDD2
GNDD
GNDD
GNDD
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
62
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
D37
D38
D39
E1
E2
E3
E4
E5
E32
E35
E36
E37
E38
E39
F1
F2
F3
F4
F11
F12
F19
F20
F21
F28
F29
F36
F37
F38
F39
G3
G4
G36
G37
H3
H4
H35
H37
J3
J34
792-Pin Signal Name
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
Pin
D37
D38
D39
E1
E2
E3
E4
E5
E32
E35
E36
E37
E38
E39
F1
F2
F3
F4
F11
F12
F19
F20
F21
F28
F29
F36
F37
F38
F39
G3
G4
G36
G37
H3
H4
H35
H37
J3
J34
600-Pin Signal Name
—
—
—
VDDD2
IDDQMODE
PLL_VDDD2
PLL_GNDD
VDDD2
NC
VDDD2
—
—
—
—
VDDD2
TCLK
GNDD
TMS
—
—
—
—
—
—
—
—
—
—
—
TRSTN
NC
—
—
GNDD
CLKDIV
GNDD
—
TXD15N
TXDATAA15
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
63
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
J36
J37
J38
L6
L34
M6
M34
R1
R39
T1
T39
W6
W34
W35
Y6
Y34
AA6
AA34
AD1
AD39
AE1
AE39
AH6
AH34
AJ6
AJ34
AK37
AL37
AM3
AM36
AM37
AN3
AN4
AN36
AN37
AP1
AP2
AP3
AP4
792-Pin Signal Name
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
Pin
J36
J37
J38
L6
L34
M6
M34
R1
R39
T1
T39
W6
W34
W35
Y6
Y34
AA6
AA34
AD1
AD39
AE1
AE39
AH6
AH34
AJ6
AJ34
AK37
AL37
AM3
AM36
AM37
AN3
AN4
AN36
AN37
AP1
AP2
AP3
AP4
600-Pin Signal Name
—
—
—
—
TXDATAA6
—
TXDATAA1
VDDD
—
GNDD
—
—
TXADDRB0
RXSZA
—
TXADDRB1
—
TXPPAB
RXD5N
—
RXD3N
—
—
RXDATAB4
—
RXDATAB0
—
—
GNDD
—
—
VDDD
GNDD
—
—
VDDD
VDDD
GNDD
GNDD
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
64
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AP11
AP12
AP19
AP20
AP21
AP28
AP29
AP36
AP37
AP38
AP39
AR1
AR2
AR3
AR4
AR5
AR35
AR36
AR37
AR38
AR39
AT1
AT2
AT3
AT4
AT5
AT6
AT7
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
AU4
AU5
AU6
792-Pin Signal Name
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
Pin
AP11
AP12
AP19
AP20
AP21
AP28
AP29
AP36
AP37
AP38
AP39
AR1
AR2
AR3
AR4
AR5
AR35
AR36
AR37
AR38
AR39
AT1
AT2
AT3
AT4
AT5
AT6
AT7
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
AU4
AU5
AU6
600-Pin Signal Name
RXDATAD7
RXDATAD12
TXCLKD
RXADDRC0
RXPPAC
TXDATAC11
TXDATAC15
—
—
—
—
VDDD
VDDD
GNDD
GNDD
VDDD2
VDDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
65
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AU7
AU8
AU31
AU32
AU33
AU34
AU35
AU36
AV4
AV5
AV6
AV34
AV35
AV36
AW4
AW5
AW6
AW15
AW16
AW24
AW25
AW34
AW35
AW36
AH36
AH37
AG34
AG35
C10
D10
E29
H36
B15
C15
D15
E15
E23
F23
A23
792-Pin Signal Name
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GPIO0
GPIO1
GPIO2
GPIO3
GNDD
VDDD2
ICTN
IDDQMODE
NC
NC
NC
NC
MPU_ADDR0
MPU_ADDR1
MPU_ADDR2
Pin
AU7
AU8
AU31
AU32
AU33
AU34
AU35
AU36
AV4
AV5
AV6
AV34
AV35
AV36
AW4
AW5
AW6
AW15
AW16
AW24
AW25
AW34
AW35
AW36
AH36
AH37
AG34
AG35
C10
D10
E29
H36
B15
C15
D15
E15
E23
F23
A23
600-Pin Signal Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXDATAB8
RXDATAB9
MPU_DATA4
MPU_DATA3
NC
—
MPU_ADDR11
MPU_ADDR10
NC
MPU_ADDR9
NC
—
GNDD
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
66
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
B22
C22
D22
E22
F22
A22
B21
D21
E21
B20
C20
D20
E20
D27
E27
F26
E26
D26
C26
B26
E25
D25
C25
B25
B24
D24
E24
C24
B23
C23
D23
B27
D28
E28
C28
F27
C27
C21
D12
792-Pin Signal Name
MPU_ADDR3
MPU_ADDR4
MPU_ADDR5
MPU_ADDR6
MPU_ADDR7
MPU_ADDR8
MPU_ADDR9
MPU_ADDR10
MPU_ADDR11
MPU_ADDR12
MPU_ADDR13
MPU_ADDR14
MPU_ADDR15
MPU_ADSN
MPU_CSN
MPU_DATA0
MPU_DATA1
MPU_DATA2
MPU_DATA3
MPU_DATA4
MPU_DATA5
MPU_DATA6
MPU_DATA7
MPU_DATA8
MPU_DATA9
MPU_DATA10
MPU_DATA11
MPU_DATA12
MPU_DATA13
MPU_DATA14
MPU_DATA15
MPU_DSN
MPU_DTN
MPU_INTN
MPU_MPCLK
MPU_MPMODE
MPU_RWN
NC
NC
Pin
B22
C22
D22
E22
F22
A22
B21
D21
E21
B20
C20
D20
E20
D27
E27
F26
E26
D26
C26
B26
E25
D25
C25
B25
B24
D24
E24
C24
B23
C23
D23
B27
D28
E28
C28
F27
C27
C21
D12
600-Pin Signal Name
NC
NC
NC
NC
—
NC
NC
NC
NC
NC
NC
NC
VDDD2
VDDD2
NC
—
NC
NC
NC
NC
VDDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
—
NC
NC
MPU_DATA12
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
67
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
E30
E31
F30
J35
K37
D30
G35
C30
H34
F32
F31
D29
F13
B11
C11
E13
D13
C12
B12
B13
C13
A13
E14
F14
H5
H6
J6
D7
B7
C7
F8
D8
E8
C8
E9
F9
F10
A8
B8
792-Pin Signal Name
NC
NC
NC
NC
NC
PLL_GND
PLL_GNDD
PLL_VDDD2
PLL_VDDD2
PLLFB
PLLREF
PMRST
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Pin
E30
E31
F30
J35
K37
D30
G35
C30
H34
F32
F31
D29
F13
B11
C11
E13
D13
C12
B12
B13
C13
A13
E14
F14
H5
H6
J6
D7
B7
C7
F8
D8
E8
C8
E9
F9
F10
A8
B8
600-Pin Signal Name
NC
VDDD2
—
TXDATAA14
—
NC
GNDD
NC
TXENBA
RXSPAB
RXSPAA
NC
—
MPU_DATA9
MPU_DATA8
MPU_ADDR0
MPU_ADDR1
MPU_DATA13
MPU_DATA14
MPU_ADDR3
MPU_ADDR2
GNDD
MPU_ADDR4
—
GNDD
—
—
PMRST
MPU_INTN
RSTN
—
MPU_MPMODE
MPU_DTN
MPU_MPCLK
MPU_ADSN
—
—
GNDD
MPU_CSN
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
68
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
E10
C9
D9
B9
D11
E11
E12
A10
B10
C29
AA4
AA2
AA1
AM6
AN5
AP18
AV19
AR19
AT29
AR29
AA5
AM5
AR18
AU29
W38
Y38
AF35
AF34
AF39
AF38
AF37
AF36
AE38
AE37
AE36
AE35
AD38
AD37
AD36
792-Pin Signal Name
NC
NC
NC
NC
NC
NC
NC
NC
NC
RSTN
RXADDRA0
RXADDRA1
RXADDRA2
RXADDRB0
RXADDRB1
RXADDRC0
RXADDRC1
RXADDRC2
RXADDRD0
RXADDRD1
RXCLKA
RXCLKB
RXCLKC
RXCLKD
RXCLKN_RXDAN
RXCLKP_RXDAP
RXD0N
RXD0P
RXD1N
RXD1P
RXD2N
RXD2P
RXD3N
RXD3P
RXD4N
RXD4P
RXD5N
RXD5P
RXD6N
Pin
E10
C9
D9
B9
D11
E11
E12
A10
B10
C29
AA4
AA2
AA1
AM6
AN5
AP18
AV19
AR19
AT29
AR29
AA5
AM5
AR18
AU29
W38
Y38
AF35
AF34
AF39
AF38
AF37
AF36
AE38
AE37
AE36
AE35
AD38
AD37
AD36
600-Pin Signal Name
MPU_DATA2
MPU_DSN
MPU_RWN
MPU_DATA0
MPU_DATA7
VDDD
MPU_DATA11
MPU_DATA6
MPU_DATA5
NC
RXD12P_RXDCP
RXD11P_RXCLKCP
RXD11N_RXCLKCN
RXTOHDC
RXTOHFC
TXPPAD
—
VDDD
—
GNDD
GNDD
RXTOHDB
VDDD
—
—
—
RXDATAB14
RXDATAB13
—
—
—
—
—
—
—
TXDATAB2
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
69
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AD35
AC37
AC36
AC35
AC34
AB35
AB34
AC39
AC38
AB39
AB38
AB37
AB36
Y35
AA35
Y37
Y36
AA37
AA36
W4
W5
V2
V3
U1
V4
U2
V5
U3
V6
U4
T2
U5
T3
U6
T4
AK4
AK3
AJ5
AJ4
792-Pin Signal Name
RXD6P
RXD7N
RXD7P
RXD8N
RXD8P
RXD9N_RXCLKDN
RXD9P_RXCLKDP
RXD10N_RXDDN
RXD10P_RXDDP
RXD11N_RXCLKCN
RXD11P_RXCLKCP
RXD12N_RXDCN
RXD12P_RXDCP
RXD13N_RXCLKBN
RXD13P_RXCLKBP
RXD14N_RXCLKAN
RXD14P_RXCLKAP
RXD15N_RXDBN
RXD15P_RXDBP
RXDATAA0
RXDATAA1
RXDATAA2
RXDATAA3
RXDATAA4
RXDATAA5
RXDATAA6
RXDATAA7
RXDATAA8
RXDATAA9
RXDATAA10
RXDATAA11
RXDATAA12
RXDATAA13
RXDATAA14
RXDATAA15
RXDATAB0
RXDATAB1
RXDATAB2
RXDATAB3
Pin
AD35
AC37
AC36
AC35
AC34
AB35
AB34
AC39
AC38
AB39
AB38
AB37
AB36
Y35
AA35
Y37
Y36
AA37
AA36
W4
W5
V2
V3
U1
V4
U2
V5
U3
V6
U4
T2
U5
T3
U6
T4
AK4
AK3
AJ5
AJ4
600-Pin Signal Name
TXDATAB7
—
—
GNDD
TXDATAB11
TXPRTYB
TXDATAB15
—
—
—
—
—
—
GNDD
TXERRB
—
—
—
—
RXD15N_RXDBN
RXD15P_RXDBP
VDDD
GNDD
TXFSYNCN
RXCLKN_RXDAN
TXD0N_TXDDN
RXCLKP_RXDAP
TXFSYNCP
—
TXCLKP
TXD0P_TXDDP
TXCLKN
TXD1N_TXDCN
—
TXD1P_TXDCP
RXTOHFA
RXREF
TXSPAC
TXSPAD
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
70
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AJ3
AJ2
AH5
AH4
AH3
AH2
AG5
AG6
AG4
AG3
AG2
AG1
AU17
AW17
AV17
AR16
AT16
AU16
AV16
AU15
AR15
AT15
AV15
AW14
AV14
AT14
AP14
AR14
AT27
AP26
AU27
AR26
AW28
AV27
AT26
AU26
AW27
AR25
AV26
792-Pin Signal Name
RXDATAB4
RXDATAB5
RXDATAB6
RXDATAB7
RXDATAB8
RXDATAB9
RXDATAB10
RXDATAB11
RXDATAB12
RXDATAB13
RXDATAB14
RXDATAB15
RXDATAC0
RXDATAC1
RXDATAC2
RXDATAC3
RXDATAC4
RXDATAC5
RXDATAC6
RXDATAC7
RXDATAC8
RXDATAC9
RXDATAC10
RXDATAC11
RXDATAC12
RXDATAC13
RXDATAC14
RXDATAC15
RXDATAD0
RXDATAD1
RXDATAD2
RXDATAD3
RXDATAD4
RXDATAD5
RXDATAD6
RXDATAD7
RXDATAD8
RXDATAD9
RXDATAD10
Pin
AJ3
AJ2
AH5
AH4
AH3
AH2
AG5
AG6
AG4
AG3
AG2
AG1
AU17
AW17
AV17
AR16
AT16
AU16
AV16
AU15
AR15
AT15
AV15
AW14
AV14
AT14
AP14
AR14
AT27
AP26
AU27
AR26
AW28
AV27
AT26
AU26
AW27
AR25
AV26
600-Pin Signal Name
TXTOHD
TXTOHCLK
TXTOHF
GPIO0
GPIO1
GPIO2
GPIO3
—
ECLREFHI
ECLREFLO
RXD0P
RXD0N
—
—
—
GNDD
—
—
—
—
TXDATAD11
—
—
—
—
—
TXDATAD5
TXDATAD6
—
TXDATAC2
—
TXDATAC1
—
—
—
—
—
RXDATAC13
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
71
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AT25
AU25
AW26
AR24
AV25
Y4
AL4
AV18
AP27
W2
AK6
AP17
AU28
Y2
AL6
AW18
AV29
Y3
AL5
AU18
AT28
V1
AK5
AT17
AV28
AK34
W3
AL3
AR17
AR27
K6
J5
J4
K5
AA3
AM4
AT18
AR28
AL35
792-Pin Signal Name
RXDATAD11
RXDATAD12
RXDATAD13
RXDATAD14
RXDATAD15
RXENBA
RXENBB
RXENBC
RXENBD
RXEOPA
RXEOPB
RXEOPC
RXEOPD
RXERRA
RXERRB
RXERRC
RXERRD
RXPPAA
RXPPAB
RXPPAC
RXPPAD
RXPRTYA
RXPRTYB
RXPRTYC
RXPRTYD
RXREF
RXSOPA
RXSOPB
RXSOPC
RXSOPD
RXSPAA
RXSPAB
RXSPAC
RXSPAD
RXSZA
RXSZB
RXSZC
RXSZD
RXTOHCLKA
Pin
AT25
AU25
AW26
AR24
AV25
Y4
AL4
AV18
AP27
W2
AK6
AP17
AU28
Y2
AL6
AW18
AV29
Y3
AL5
AU18
AT28
V1
AK5
AT17
AV28
AK34
W3
AL3
AR17
AR27
K6
J5
J4
K5
AA3
AM4
AT18
AR28
AL35
600-Pin Signal Name
—
—
—
RXDATAC8
—
GNDD
RXTOHCLKB
—
TXDATAC7
RXD14N_RXCLKAN
—
TXDATAD15
—
RXD13N_RXCLKBN
RXTOHCLKC
—
—
RXD13P_RXCLKBP
VDDD2
—
—
VDDD
RXTOHCLKA
—
—
RXENBB
RXD14P_RXCLKAP
RXTOHFB
TXENBD
TXDATAC6
—
TXCLKQN
TXD15P
VDDD
RXD12N_RXDCN
VDDD2
—
GNDD
VDDD2
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
72
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AM34
AR31
AR30
AL34
AP32
AT31
AU30
AL36
AM35
AR32
AP30
C18
D18
A18
B18
D19
E19
B19
C19
C14
D14
A14
B14
D16
E16
B16
C16
E17
F17
C17
D17
A17
B17
F18
E18
K35
K36
L36
K34
792-Pin Signal Name
RXTOHCLKB
RXTOHCLKC
RXTOHCLKD
RXTOHDA
RXTOHDB
RXTOHDC
RXTOHDD
RXTOHFA
RXTOHFB
RXTOHFC
RXTOHFD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TCLK
TDI
TDO
TMS
Pin
AM34
AR31
AR30
AL34
AP32
AT31
AU30
AL36
AM35
AR32
AP30
C18
D18
A18
B18
D19
E19
B19
C19
C14
D14
A14
B14
D16
E16
B16
C16
E17
F17
C17
D17
A17
B17
F18
E18
K35
K36
L36
K34
600-Pin Signal Name
GNDD
VDDD2
VDDD2
RXCLKB
GNDD
—
—
—
GNDD
GNDD
TXENBC
NC
NC
VDDD
NC
NC
NC
NC
NC
MPU_ADDR6
MPU_ADDR5
MPU_ADDR8
MPU_ADDR7
MPU_ADDR13
VDDD2
MPU_ADDR15
MPU_ADDR14
NC
—
NC
NC
VDDD
NC
—
NC
TXDATAA9
—
—
TXDATAA10
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
73
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
L35
L5
K3
Y5
AB1
AB6
AR7
AP8
AU19
AT30
AP31
L4
AB5
AR8
AT19
V39
V38
M36
M35
V37
V36
V35
V34
U39
U38
U37
U36
U35
U34
T38
T37
T36
T35
R38
R37
P39
P38
R36
R35
792-Pin Signal Name
TRSTN
TXADDRA0
TXADDRA1
TXADDRA2
TXADDRB0
TXADDRB1
TXADDRC0
TXADDRC1
TXADDRC2
TXADDRD0
TXADDRD1
TXCLKA
TXCLKB
TXCLKC
TXCLKD
TXCLKN
TXCLKP
TXCLKQN
TXCLKQP
TXD0N_TXDDN
TXD0P_TXDDP
TXD1N_TXDCN
TXD1P_TXDCP
TXD2N_TXDBN
TXD2P_TXDBP
TXD3N_TXDAN
TXD3P_TXDAP
TXD4N
TXD4P
TXD5N
TXD5P
TXD6N
TXD6P
TXD7N
TXD7P
TXD8N
TXD8P
TXD9N
TXD9P
Pin
L35
L5
K3
Y5
AB1
AB6
AR7
AP8
AU19
AT30
AP31
L4
AB5
AR8
AT19
V39
V38
M36
M35
V37
V36
V35
V34
U39
U38
U37
U36
U35
U34
T38
T37
T36
T35
R38
R37
P39
P38
R36
R35
600-Pin Signal Name
TXDATAA5
VDDD
TXD13N
VDDD2
RXD9N_RXCLKDN
—
GNDD
RXERRD
—
—
TXCLKC
TXD11P
VDDD
GNDD
—
—
—
—
TXDATAA0
—
—
VDDD
RXADDRA2
—
—
—
—
VDDD
RXENBA
—
—
—
GNDD
—
—
—
—
—
RXDATAA2
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
74
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
P37
P36
P35
P34
N39
N38
N37
N36
N35
N34
M38
M37
R2
T5
P1
R3
R4
P2
R5
N1
P3
P4
N2
P5
N3
N4
P6
M2
AF6
AF5
AF4
AF3
AF2
AF1
AE5
AE4
AE3
AE2
AD2
792-Pin Signal Name
TXD10N
TXD10P
TXD11N
TXD11P
TXD12N
TXD12P
TXD13N
TXD13P
TXD14N
TXD14P
TXD15N
TXD15P
TXDATAA0
TXDATAA1
TXDATAA2
TXDATAA3
TXDATAA4
TXDATAA5
TXDATAA6
TXDATAA7
TXDATAA8
TXDATAA9
TXDATAA10
TXDATAA11
TXDATAA12
TXDATAA13
TXDATAA14
TXDATAA15
TXDATAB0
TXDATAB1
TXDATAB2
TXDATAB3
TXDATAB4
TXDATAB5
TXDATAB6
TXDATAB7
TXDATAB8
TXDATAB9
TXDATAB10
Pin
P37
P36
P35
P34
N39
N38
N37
N36
N35
N34
M38
M37
R2
T5
P1
R3
R4
P2
R5
N1
P3
P4
N2
P5
N3
N4
P6
M2
AF6
AF5
AF4
AF3
AF2
AF1
AE5
AE4
AE3
AE2
AD2
600-Pin Signal Name
—
—
RXDATAA7
RXDATAA8
—
—
—
—
GNDD
RXDATAA12
—
—
TXD2N_TXDBN
VDDD2
TXD4N
TXD2P_TXDBP
TXD3P_TXDAP
TXD4P
TXD3N_TXDAN
GNDD
TXD5N
VDDD
TXD6N
TXD5P
TXD6P
TXD7N
—
TXD8P
—
VDDD
RXD2P
RXD2N
RXD1P
RXD1N
VDDD
RXD4P
RXD4N
RXD3P
RXD5P
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
75
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AD3
AD5
AD4
AC2
AC3
AU14
AV13
AU13
AR13
AP13
AT13
AV12
AU12
AT12
AR12
AV11
AU11
AT11
AR11
AU10
AT10
AT24
AP23
AU24
AR23
AV24
AT23
AU23
AP22
AV23
AR22
AT22
AW23
AU22
AV22
AR21
AT21
N6
AC1
792-Pin Signal Name
TXDATAB11
TXDATAB12
TXDATAB13
TXDATAB14
TXDATAB15
TXDATAC0
TXDATAC1
TXDATAC2
TXDATAC3
TXDATAC4
TXDATAC5
TXDATAC6
TXDATAC7
TXDATAC8
TXDATAC9
TXDATAC10
TXDATAC11
TXDATAC12
TXDATAC13
TXDATAC14
TXDATAC15
TXDATAD0
TXDATAD1
TXDATAD2
TXDATAD3
TXDATAD4
TXDATAD5
TXDATAD6
TXDATAD7
TXDATAD8
TXDATAD9
TXDATAD10
TXDATAD11
TXDATAD12
TXDATAD13
TXDATAD14
TXDATAD15
TXENBA
TXENBB
Pin
AD3
AD5
AD4
AC2
AC3
AU14
AV13
AU13
AR13
AP13
AT13
AV12
AU12
AT12
AR12
AV11
AU11
AT11
AR11
AU10
AT10
AT24
AP23
AU24
AR23
AV24
AT23
AU23
AP22
AV23
AR22
AT22
AW23
AU22
AV22
AR21
AT21
N6
AC1
600-Pin Signal Name
RXD6N
VDDD
RXD6P
RXD7N
RXD7P
—
—
—
GNDD
TXDATAD1
—
—
—
—
RXDATAD13
—
—
—
RXDATAD8
—
—
—
RXDATAC4
—
GNDD
—
—
—
RXDATAC0
—
RXPRTYC
—
—
—
—
RXERRC
—
—
GNDD
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
76
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AT9
AV20
L2
AC6
AU9
AV21
L3
AB3
AP9
AR20
W36
W37
M4
AB2
AR9
AT20
N5
AC4
AR10
AW22
M3
AC5
AP10
AU21
K4
AK35
AK36
AJ35
M5
AB4
AT8
AU20
AJ37
AJ36
AH35
E6
E7
E33
E34
792-Pin Signal Name
TXENBC
TXENBD
TXEOPA
TXEOPB
TXEOPC
TXEOPD
TXERRA
TXERRB
TXERRC
TXERRD
TXFSYNCN
TXFSYNCP
TXPPAA
TXPPAB
TXPPAC
TXPPAD
TXPRTYA
TXPRTYB
TXPRTYC
TXPRTYD
TXSOPA
TXSOPB
TXSOPC
TXSOPD
TXSPAA
TXSPAB
TXSPAC
TXSPAD
TXSZA
TXSZB
TXSZC
TXSZD
TXTOHCLK
TXTOHD
TXTOHF
VDDD
VDDD
VDDD
VDDD
Pin
AT9
AV20
L2
AC6
AU9
AV21
L3
AB3
AP9
AR20
W36
W37
M4
AB2
AR9
AT20
N5
AC4
AR10
AW22
M3
AC5
AP10
AU21
K4
AK35
AK36
AJ35
M5
AB4
AT8
AU20
AJ37
AJ36
AH35
E6
E7
E33
E34
600-Pin Signal Name
—
—
TXD10P
—
—
—
TXD11N
RXD10N_RXDDN
RXSOPD
GNDD
—
—
TXD9P
RXD9P_RXCLKDP
RXPRTYD
—
TXD7P
RXD8N
RXDATAD4
—
TXD9N
RXD8P
RXDATAD3
—
TXD13P
VDDD2
—
GNDD
VDDD
RXD10P_RXDDP
—
—
—
—
GNDD
NC
ICTN
NC
NC
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
77
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
F5
F6
F7
F15
F16
F24
F25
F33
F34
F35
G5
G6
G34
R6
R34
T6
T34
AD6
AD34
AE6
AE34
AN6
AN34
AN35
AP5
AP6
AP7
AP15
AP16
AP24
AP25
AP33
AP34
AP35
AR6
AR33
AR34
A1
A2
792-Pin Signal Name
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD2
VDDD2
Pin
F5
F6
F7
F15
F16
F24
F25
F33
F34
F35
G5
G6
G34
R6
R34
T6
T34
AD6
AD34
AE6
AE34
AN6
AN34
AN35
AP5
AP6
AP7
AP15
AP16
AP24
AP25
AP33
AP34
AP35
AR6
AR33
AR34
A1
A2
600-Pin Signal Name
NC
—
—
—
—
—
—
RXSPAC
RXSPAD
VDDD2
TDI
—
TXCLKA
—
RXDATAA3
—
RXPRTYA
—
TXDATAB6
—
TXDATAB1
GNDD
GNDD
GNDD
TXADDRD1
RXTOHFD
RXADDRD1
TXDATAD10
TXDATAD14
RXDATAC9
RXDATAC14
GNDD
VDDD
VDDD
VDDD2
GNDD
VDDD
VDDD
VDDD
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
78
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
A3
A6
A7
A11
A12
A19
A20
A21
A28
A29
A30
A31
A32
A33
A37
A38
A39
B1
B2
B3
B6
B28
B29
B30
B31
B32
B33
B37
B38
B39
C1
C2
C3
C6
C37
C38
C39
D6
G1
792-Pin Signal Name
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
Pin
A3
A6
A7
A11
A12
A19
A20
A21
A28
A29
A30
A31
A32
A33
A37
A38
A39
B1
B2
B3
B6
B28
B29
B30
B31
B32
B33
B37
B38
B39
C1
C2
C3
C6
C37
C38
C39
D6
G1
600-Pin Signal Name
GNDD
VDDD2
GNDD
MPU_DATA10
MPU_DATA15
NC
GNDD
NC
GNDD
GNDD
VDDD2
VDDD2
GNDD
GNDD
—
—
—
VDDD
VDDD
GNDD
PLL_VDDD2
NC
NC
NC
NC
GNDD
GNDD
—
—
—
GNDD
GNDD
VDDD
PLL_GND
—
—
—
NC
GNDD
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
79
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
G2
G38
G39
H1
H2
H38
H39
J1
J2
J39
K1
K2
K38
K39
L1
L38
L39
M1
M39
W1
W39
Y1
Y39
AA38
AA39
AG38
AG39
AH1
AH38
AH39
AJ1
AJ38
AJ39
AK1
AK2
AK38
AK39
AL1
AL2
792-Pin Signal Name
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
Pin
G2
G38
G39
H1
H2
H38
H39
J1
J2
J39
K1
K2
K38
K39
L1
L38
L39
M1
M39
W1
W39
Y1
Y39
AA38
AA39
AG38
AG39
AH1
AH38
AH39
AJ1
AJ38
AJ39
AK1
AK2
AK38
AK39
AL1
AL2
600-Pin Signal Name
TDO
—
—
GNDD
TXCLKQP
—
—
TXD14N
TXD14P
—
TXD12N
TXD12P
—
—
TXD10N
—
—
TXD8N
—
VDDD
—
GNDD
—
—
—
—
—
GNDD
—
—
GNDD
—
—
VDDD2
TXSPAB
—
—
VDDD2
RXTOHDA
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
80
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AL38
AL39
AM1
AM2
AM38
AM39
AN1
AN2
AN38
AN39
AU1
AU2
AU3
AU37
AU38
AU39
AV1
AV2
AV3
AV7
AV8
AV9
AV10
AV30
AV31
AV32
AV33
AV37
AV38
AV39
AW1
AW2
AW3
AW7
AW8
AW9
AW10
AW11
AW12
792-Pin Signal Name
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
Pin
AL38
AL39
AM1
AM2
AM38
AM39
AN1
AN2
AN38
AN39
AU1
AU2
AU3
AU37
AU38
AU39
AV1
AV2
AV3
AV7
AV8
AV9
AV10
AV30
AV31
AV32
AV33
AV37
AV38
AV39
AW1
AW2
AW3
AW7
AW8
AW9
AW10
AW11
AW12
600-Pin Signal Name
—
—
GNDD
GNDD
—
—
GNDD
GNDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
81
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AW13
AW19
AW20
AW21
AW29
AW30
AW31
AW32
AW33
AW37
AW38
AW39
G31
G32
G33
H31
H32
H33
J31
J32
J33
K31
K32
K33
L31
L32
L33
M31
M32
M33
N31
N32
N33
P31
P32
P33
R31
R32
R33
792-Pin Signal Name
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pin
AW13
AW19
AW20
AW21
AW29
AW30
AW31
AW32
AW33
AW37
AW38
AW39
G31
G32
G33
H31
H32
H33
J31
J32
J33
K31
K32
K33
L31
L32
L33
M31
M32
M33
N31
N32
N33
P31
P32
P33
R31
R32
R33
600-Pin Signal Name
—
—
—
—
—
—
—
—
—
—
—
—
TXSPAA
TXADDRA0
TXADDRA1
TXSZA
TXERRA
TXPPAA
TXEOPA
TXSOPA
TXPRTYA
TXDATAA13
TXDATAA12
TXDATAA11
VDDD
TXDATAA8
TXDATAA7
TXDATAA4
TXDATAA3
TXDATAA2
RXDATAA15
RXDATAA14
RXDATAA13
RXDATAA11
RXDATAA10
RXDATAA9
RXDATAA6
RXDATAA5
RXDATAA4
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
82
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
T31
T32
T33
U31
U32
U33
V31
V32
V33
W31
W32
W33
Y31
Y32
Y33
AA31
AA32
AA33
AB31
AB32
AB33
AC31
AC32
AC33
AD31
AD32
AD33
AE31
AE32
AE33
AF31
AF32
AF33
AG31
AG32
AG33
AH31
AH32
AH33
792-Pin Signal Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pin
T31
T32
T33
U31
U32
U33
V31
V32
V33
W31
W32
W33
Y31
Y32
Y33
AA31
AA32
AA33
AB31
AB32
AB33
AC31
AC32
AC33
AD31
AD32
AD33
AE31
AE32
AE33
AF31
AF32
AF33
AG31
AG32
AG33
AH31
AH32
AH33
600-Pin Signal Name
VDDD2
RXDATAA1
RXDATAA0
RXSOPA
RXEOPA
TXADDRA2
GNDD
RXERRA
RXPPAA
RXADDRA0
RXADDRA1
RXCLKA
VDDD2
TXSZB
TXCLKB
TXEOPB
TXSOPB
TXENBB
TXDATAB13
TXDATAB12
TXDATAB14
TXDATAB8
TXDATAB9
TXDATAB10
TXDATAB3
TXDATAB4
TXDATAB5
VDDD
RXDATAB15
TXDATAB0
RXDATAB10
RXDATAB11
RXDATAB12
RXDATAB5
RXDATAB6
RXDATAB7
RXDATAB1
RXDATAB2
RXDATAB3
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
83
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AJ31
AJ32
AJ33
AK31
AK32
AK33
AL7
AL8
AL9
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AM7
AM8
AM9
AM10
AM11
AM12
792-Pin Signal Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pin
AJ31
AJ32
AJ33
AK31
AK32
AK33
AL7
AL8
AL9
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AM7
AM8
AM9
AM10
AM11
AM12
600-Pin Signal Name
RXEOPB
RXSOPB
RXPRTYB
RXSZB
RXERRB
RXPPAB
RXTOHCLKD
RXADDRD0
RXPPAD
RXDATAD0
VDDD
RXDATAD9
RXDATAD14
TXDATAD3
TXDATAD8
VDDD2
TXSOPD
VDDD
RXADDRC1
VDDD2
RXSOPC
RXDATAC3
RXDATAC7
RXDATAC12
VDDD
TXDATAC5
TXDATAC10
TXDATAC14
TXEOPC
TXSZC
VDDD2
RXADDRB1
RXADDRB0
TXADDRD0
RXCLKD
RXENBD
RXDATAD1
RXDATAD5
RXDATAD10
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
84
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
792-Pin Signal Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pin
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
600-Pin Signal Name
RXDATAD15
TXDATAD2
TXDATAD7
TXDATAD12
TXPRTYD
TXERRD
TXADDRC2
RXSZC
RXEOPC
RXDATAC2
RXDATAC6
RXDATAC11
TXDATAC0
TXDATAC4
TXDATAC9
TXDATAC13
TXSOPC
TXERRC
TXADDRC0
VDDD2
GNDD
RXTOHDD
RXSZD
RXEOPD
RXDATAD2
RXDATAD6
RXDATAD11
TXDATAD0
TXDATAD4
TXDATAD9
TXDATAD13
TXEOPD
TXSZD
RXADDRC2
RXCLKC
RXENBC
RXDATAC1
RXDATAC5
RXDATAC10
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
Agere Systems Inc.
85
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
792-Pin PBGA Pin Assignments (continued)
Table 4. Pin Assignments for 792-Pin PBGA by Signal Name (continued)
Pin
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
792-Pin Signal Name
—
—
—
—
—
—
—
—
—
Pin
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
600-Pin Signal Name
RXDATAC15
TXDATAC3
TXDATAC8
TXDATAC12
TXPRTYC
TXPPAC
TXADDRC1
GNDD
VDDD
Note: NC refers to no connect. Do not connect pins so designated. — indicates the pin does not exist for the specified package.
86
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
600-Pin LBGA Pin Assignments
Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
VDDD
B1
VDDD
C1
GNDD
D1
GNDD
A2
VDDD
B2
VDDD
C2
GNDD
D2
GNDD
A3
GNDD
B3
GNDD
C3
VDDD
D3
GNDD
A4
GNDD
B4
GNDD
C4
GNDD
D4
VDDD2
A5
VDDD2
B5
NC
C5
PLLREF
D5
PLLFB
A6
VDDD2
B6
PLL_VDDD2
C6
PLL_GND
D6
NC
A7
GNDD
B7
MPU_INTN
C7
RSTN
D7
PMRST
A8
GNDD
B8
MPU_CSN
C8
MPU_MPCLK
D8
MPU_MPMODE
A9
MPU_DATA1
B9
MPU_DATA0
C9
MPU_DSN
D9
MPU_RWN
A10
MPU_DATA6
B10
MPU_DATA5
C10
MPU_DATA4
D10
MPU_DATA3
A11
MPU_DATA10
B11
MPU_DATA9
C11
MPU_DATA8
D11
MPU_DATA7
A12
MPU_DATA15
B12
MPU_DATA14
C12
MPU_DATA13
D12
MPU_DATA12
A13
GNDD
B13
MPU_ADDR3
C13
MPU_ADDR2
D13
MPU_ADDR1
A14
MPU_ADDR8
B14
MPU_ADDR7
C14
MPU_ADDR6
D14
MPU_ADDR5
A15
MPU_ADDR12
B15
MPU_ADDR11
C15
MPU_ADDR10
D15
NC
A16
GNDD
B16
MPU_ADDR15
C16
MPU_ADDR14
D16
MPU_ADDR13
A17
VDDD
B17
NC
C17
NC
D17
NC
A18
VDDD
B18
NC
C18
NC
D18
NC
A19
NC
B19
NC
C19
NC
D19
NC
A20
GNDD
B20
NC
C20
NC
D20
NC
A21
NC
B21
NC
C21
NC
D21
NC
A22
NC
B22
NC
C22
NC
D22
NC
A23
GNDD
B23
NC
C23
NC
D23
NC
A24
NC
B24
NC
C24
NC
D24
NC
A25
NC
B25
NC
C25
NC
D25
NC
A26
NC
B26
NC
C26
NC
D26
NC
A27
GNDD
B27
NC
C27
NC
D27
VDDD2
A28
GNDD
B28
NC
C28
NC
D28
NC
A29
GNDD
B29
NC
C29
NC
D29
NC
A30
VDDD2
B30
NC
C30
NC
D30
NC
A31
VDDD2
B31
NC
C31
NC
D31
NC
A32
GNDD
B32
GNDD
C32
GNDD
D32
VDDD2
A33
GNDD
B33
GNDD
C33
VDDD
D33
GNDD
A34
VDDD
B34
VDDD
C34
GNDD
D34
GNDD
A35
VDDD
B35
VDDD
C35
GNDD
D35
GNDD
Note: NC refers to no connect. Do not connect pins so designated.
Agere Systems Inc.
87
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
600-Pin LBGA Pin Assignments (continued)
Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)
Pin
Pin
Signal Name
Pin
Signal Name
Pin
E1
VDDD2
Signal Name
F1
VDDD2
J31
TXEOPA
N1
GNDD
Signal Name
E2
IDDQMODE
F2
TCLK
J32
TXSOPA
N2
TXD6N
E3
PLL_VDDD2
F3
GNDD
J33
TXPRTYA
N3
TXD6P
E4
PLL_GNDD
F4
TMS
J34
TXDATAA15
N4
TXD7N
E5
VDDD2
F5
NC
J35
TXDATAA14
N5
TXD7P
E6
NC
F31
RXSPAA
K1
TXD12N
N31
RXDATAA15
E7
ICTN
F32
RXSPAB
K2
TXD12P
N32
RXDATAA14
E8
MPU_DTN
F33
RXSPAC
K3
TXD13N
N33
RXDATAA13
E9
MPU_ADSN
F34
RXSPAD
K4
TXD13P
N34
RXDATAA12
E10
MPU_DATA2
F35
VDDD2
K5
VDDD
N35
GNDD
E11
VDDD
G1
GNDD
K31
TXDATAA13
P1
TXD4N
E12
MPU_DATA11
G2
TDO
K32
TXDATAA12
P2
TXD4P
E13
MPU_ADDR0
G3
TRSTN
K33
TXDATAA11
P3
TXD5N
E14
MPU_ADDR4
G4
NC
K34
TXDATAA10
P4
VDDD
E15
MPU_ADDR9
G5
TDI
K35
TXDATAA9
P5
TXD5P
E16
VDDD2
G31
TXSPAA
L1
TXD10N
P31
RXDATAA11
E17
NC
G32
TXADDRA0
L2
TXD10P
P32
RXDATAA10
E18
NC
G33
TXADDRA1
L3
TXD11N
P33
RXDATAA9
E19
NC
G34
TXCLKA
L4
TXD11P
P34
RXDATAA8
E20
VDDD2
G35
GNDD
L5
VDDD
P35
RXDATAA7
E21
NC
H1
GNDD
L31
VDDD
R1
VDDD
E22
NC
H2
TXCLKQP
L32
TXDATAA8
R2
TXD2N_TXDBN
E23
NC
H3
GNDD
L33
TXDATAA7
R3
TXD2P_TXDBP
E24
NC
H4
CLKDIV
L34
TXDATAA6
R4
TXD3P_TXDAP
E25
VDDD
H5
GNDD
L35
TXDATAA5
R5
TXD3N_TXDAN
E26
NC
H31
TXSZA
M1
TXD8N
R31
RXDATAA6
E27
NC
H32
TXERRA
M2
TXD8P
R32
RXDATAA5
E28
NC
H33
TXPPAA
M3
TXD9N
R33
RXDATAA4
E29
NC
H34
TXENBA
M4
TXD9P
R34
RXDATAA3
E30
NC
H35
GNDD
M5
VDDD
R35
RXDATAA2
E31
VDDD2
J1
TXD14N
M31
TXDATAA4
T1
GNDD
E32
NC
J2
TXD14P
M32
TXDATAA3
T2
TXD0P_TXDDP
E33
NC
J3
TXD15N
M33
TXDATAA2
T3
TXD1N_TXDCN
E34
NC
J4
TXD15P
M34
TXDATAA1
T4
TXD1P_TXDCP
E35
VDDD2
J5
TXCLKQN
M35
TXDATAA0
T5
VDDD2
Note: NC refers to no connect. Do not connect pins so designated.
88
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
600-Pin LBGA Pin Assignments (continued)
Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)
Pin
T31
T32
T33
T34
T35
U1
U2
U3
U4
U5
U31
U32
U33
U34
U35
V1
V2
V3
V4
V5
V31
V32
V33
V34
V35
W1
W2
W3
W4
W5
W31
W32
W33
W34
W35
Signal Name
VDDD2
RXDATAA1
RXDATAA0
RXPRTYA
GNDD
TXFSYNCN
TXD0N_TXDDN
TXFSYNCP
TXCLKP
TXCLKN
RXSOPA
RXEOPA
TXADDRA2
RXENBA
VDDD
VDDD
VDDD
GNDD
RXCLKN_
RXDAN
RXCLKP_
RXDAP
GNDD
RXERRA
RXPPAA
RXADDRA2
VDDD
VDDD
RXD14N_
RXCLKAN
RXD14P_
RXCLKAP
RXD15N_
RXDBN
RXD15P_
RXDBP
RXADDRA0
RXADDRA1
RXCLKA
TXADDRB0
RXSZA
Pin
Y1
Y2
Y3
Y4
Y5
Y31
Y32
Y33
Y34
Y35
AA1
AA2
AA3
AA4
AA5
AA31
AA32
AA33
AA34
Signal Name
GNDD
RXD13N_RXCLKBN
RXD13P_RXCLKBP
GNDD
VDDD2
VDDD2
TXSZB
TXCLKB
TXADDRB1
GNDD
RXD11N_RXCLKCN
RXD11P_RXCLKCP
RXD12N_RXDCN
RXD12P_RXDCP
GNDD
TXEOPB
TXSOPB
TXENBB
TXPPAB
Pin
AC31
AC32
AC33
AC34
AC35
AD1
AD2
AD3
AD4
AD5
AD31
AD32
AD33
AD34
AD35
AE1
AE2
AE3
AE4
Signal Name
TXDATAB8
TXDATAB9
TXDATAB10
TXDATAB11
GNDD
RXD5N
RXD5P
RXD6N
RXD6P
VDDD
TXDATAB3
TXDATAB4
TXDATAB5
TXDATAB6
TXDATAB7
RXD3N
RXD3P
RXD4N
RXD4P
Pin
AG1
AG2
AG3
AG4
AG5
AG31
AG32
AG33
AG34
AG35
AH1
AH2
AH3
AH4
AH5
AH31
AH32
AH33
AH34
Signal Name
RXD0N
RXD0P
ECLREFLO
ECLREFHI
GPIO3
RXDATAB5
RXDATAB6
RXDATAB7
RXDATAB8
RXDATAB9
GNDD
GPIO2
GPIO1
GPIO0
TXTOHF
RXDATAB1
RXDATAB2
RXDATAB3
RXDATAB4
AA35 TXERRB
AE5
VDDD
AH35 GNDD
AB1
AB2
AB3
AB4
AB5
AB31
AB32
AE31
AE32
AE33
AE34
AE35
AF1
AF2
VDDD
RXDATAB15
TXDATAB0
TXDATAB1
TXDATAB2
RXD1N
RXD1P
AJ1
AJ2
AJ3
AJ4
AJ5
AJ31
AJ32
RXD9N_RXCLKDN
RXD9P_RXCLKDP
RXD10N_RXDDN
RXD10P_RXDDP
VDDD
TXDATAB13
TXDATAB12
GNDD
TXTOHCLK
TXTOHD
TXSPAD
TXSPAC
RXEOPB
RXSOPB
AB33 TXDATAB14
AF3
RXD2N
AJ33 RXPRTYB
AB34 TXDATAB15
AF4
RXD2P
AJ34 RXDATAB0
AB35 TXPRTYB
AF5
VDDD
AJ35 GNDD
AC1
AC2
AC3
AC4
AC5
AF31
AF32
AF33
AF34
AF35
RXDATAB10
RXDATAB11
RXDATAB12
RXDATAB13
RXDATAB14
AK1
AK2
AK3
AK4
AK5
GNDD
RXD7N
RXD7P
RXD8N
RXD8P
VDDD2
TXSPAB
RXREF
RXTOHFA
RXTOHCLKA
Note: NC refers to no connect. Do not connect pins so designated.
Agere Systems Inc.
89
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
600-Pin LBGA Pin Assignments (continued)
Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)
Pin
AK31
AK32
AK33
AK34
AK35
AL1
AL2
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
Signal Name
RXSZB
RXERRB
RXPPAB
RXENBB
VDDD2
VDDD2
RXTOHDA
RXTOHFB
RXTOHCLKB
VDDD2
RXTOHCLKC
RXTOHCLKD
RXADDRD0
RXPPAD
RXDATAD0
VDDD
RXDATAD9
RXDATAD14
TXDATAD3
TXDATAD8
VDDD2
TXSOPD
VDDD
RXADDRC1
VDDD2
RXSOPC
RXDATAC3
RXDATAC7
RXDATAC12
VDDD
TXDATAC5
TXDATAC10
TXDATAC14
TXEOPC
TXSZC
Pin
AL31
AL32
AL33
AL34
AL35
AM1
AM2
AM3
AM4
AM5
AM6
AM7
AM8
AM9
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
Signal Name
VDDD2
RXADDRB1
RXADDRB0
RXCLKB
VDDD2
GNDD
GNDD
GNDD
VDDD2
RXTOHDB
RXTOHDC
TXADDRD0
RXCLKD
RXENBD
RXDATAD1
RXDATAD5
RXDATAD10
RXDATAD15
TXDATAD2
TXDATAD7
TXDATAD12
TXPRTYD
TXERRD
TXADDRC2
RXSZC
RXEOPC
RXDATAC2
RXDATAC6
RXDATAC11
TXDATAC0
TXDATAC4
TXDATAC9
TXDATAC13
TXSOPC
TXERRC
Pin
AM31
AM32
AM33
AM34
AM35
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
Signal Name
TXADDRC0
VDDD2
GNDD
GNDD
GNDD
GNDD
GNDD
VDDD
GNDD
RXTOHFC
GNDD
RXTOHDD
RXSZD
RXEOPD
RXDATAD2
RXDATAD6
RXDATAD11
TXDATAD0
TXDATAD4
TXDATAD9
TXDATAD13
TXEOPD
TXSZD
RXADDRC2
RXCLKC
RXENBC
RXDATAC1
RXDATAC5
RXDATAC10
RXDATAC15
TXDATAC3
TXDATAC8
TXDATAC12
TXPRTYC
TXPPAC
Pin
AN31
AN32
AN33
AN34
AN35
AP1
AP2
AP3
AP4
AP5
AP6
AP7
AP8
AP9
AP10
AP11
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
Signal Name
TXADDRC1
GNDD
VDDD
GNDD
GNDD
VDDD
VDDD
GNDD
GNDD
TXADDRD1
RXTOHFD
RXADDRD1
RXERRD
RXSOPD
RXDATAD3
RXDATAD7
RXDATAD12
TXDATAD1
TXDATAD5
TXDATAD10
TXDATAD14
TXDATAD15
TXPPAD
TXCLKD
RXADDRC0
RXPPAC
RXDATAC0
RXDATAC4
RXDATAC9
RXDATAC14
TXDATAC2
TXDATAC7
TXDATAC11
TXDATAC15
TXENBC
Note: NC refers to no connect. Do not connect pins so designated.
90
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
600-Pin LBGA Pin Assignments (continued)
Table 5. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)
Pin
AP31
AP32
AP33
AP34
AP35
AR1
AR2
AR3
AR4
AR5
AR6
AR7
AR8
AR9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR25
AR26
AR27
AR28
AR29
AR30
Signal Name
TXCLKC
GNDD
GNDD
VDDD
VDDD
VDDD
VDDD
GNDD
GNDD
VDDD2
VDDD2
GNDD
GNDD
RXPRTYD
RXDATAD4
RXDATAD8
RXDATAD13
GNDD
TXDATAD6
TXDATAD11
GNDD
TXENBD
VDDD
VDDD
GNDD
RXERRC
RXPRTYC
GNDD
RXDATAC8
RXDATAC13
TXDATAC1
TXDATAC6
GNDD
GNDD
VDDD2
Pin
AR31
AR32
AR33
AR34
AR35
Signal Name
VDDD2
GNDD
GNDD
VDDD
VDDD
Note: NC refers to no connect. Do not connect pins so designated.
Agere Systems Inc.
91
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
600-Pin LBGA Pin Assignments (continued)
Table 6. Pin Assignments for 600-Pin LBGA by Signal Name
Signal Name
CLKDIV
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
H4
GNDD
H3
GNDD
AP33
MPU_ADDR9
E15
ECLREFHI
AG4
GNDD
H5
GNDD
AR3
MPU_ADDR10
C15
ECLREFLO
AG3
GNDD
H35
GNDD
AR4
MPU_ADDR11
B15
GNDD
A3
GNDD
N1
GNDD
AR7
MPU_ADDR12
A15
GNDD
A4
GNDD
N35
GNDD
AR8
MPU_ADDR13
D16
GNDD
A7
GNDD
T1
GNDD
AR13
MPU_ADDR14
C16
GNDD
A8
GNDD
T35
GNDD
AR16
MPU_ADDR15
B16
GNDD
A13
GNDD
V3
GNDD
AR20
MPU_ADSN
E9
GNDD
A16
GNDD
V31
GNDD
AR23
MPU_CSN
B8
GNDD
A20
GNDD
Y1
GNDD
AR28
MPU_DATA0
B9
GNDD
A23
GNDD
Y4
GNDD
AR29
MPU_DATA1
A9
GNDD
A28
GNDD
Y35
GNDD
AR32
MPU_DATA2
E10
GNDD
A29
GNDD
AA5
GNDD
AR33
MPU_DATA3
D10
GNDD
A32
GNDD
AC1
GPIO0
AH4
MPU_DATA4
C10
GNDD
A33
GNDD
AC35
GPIO1
AH3
MPU_DATA5
B10
GNDD
B3
GNDD
AH1
GPIO2
AH2
MPU_DATA6
A10
GNDD
B4
GNDD
AH35
GPIO3
AG5
MPU_DATA7
D11
GNDD
B32
GNDD
AJ1
GNDD
A27
MPU_DATA8
C11
GNDD
B33
GNDD
AJ35
NC
E26
MPU_DATA9
B11
GNDD
C1
GNDD
AM1
VDDD2
D27
MPU_DATA10
A11
GNDD
C2
GNDD
AM2
ICTN
E7
MPU_DATA11
E12
GNDD
C4
GNDD
AM3
IDDQMODE
E2
MPU_DATA12
D12
GNDD
C32
GNDD
AM33
NC
D21
MPU_DATA13
C12
GNDD
C34
GNDD
AM34
NC
A22
MPU_DATA14
B12
GNDD
C35
GNDD
AM35
NC
B22
MPU_DATA15
A12
GNDD
D1
GNDD
AN1
NC
C22
MPU_DSN
C9
GNDD
D2
GNDD
AN2
MPU_ADDR0
E13
MPU_DTN
E8
GNDD
D3
GNDD
AN4
MPU_ADDR1
D13
MPU_INTN
B7
GNDD
D33
GNDD
AN6
MPU_ADDR2
C13
MPU_MPCLK
C8
GNDD
D34
GNDD
AN32
MPU_ADDR3
B13
MPU_MPMODE
D8
GNDD
D35
GNDD
AN34
MPU_ADDR4
E14
MPU_RWN
D9
GNDD
F3
GNDD
AN35
MPU_ADDR5
D14
NC
D6
GNDD
G1
GNDD
AP3
MPU_ADDR6
C14
NC
E6
GNDD
G35
GNDD
AP4
MPU_ADDR7
B14
NC
F5
GNDD
H1
GNDD
AP32
MPU_ADDR8
A14
PLL_GND
C6
Note: NC refers to no connect. Do not connect pins so designated.
92
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
600-Pin LBGA Pin Assignments (continued)
Table 6. Pin Assignments for 600-Pin LBGA by Signal Name (continued)
Signal Name
PLL_GNDD
Pin
E4
Signal Name
NC
Pin
C29
Signal Name
RXD4N
Pin
AE3
Signal Name
RXDATAA11
Pin
P31
PLL_VDDD2
B6
NC
B28
RXD4P
AE4
RXDATAA12
N34
PLL_VDDD2
E3
NC
C28
RXD5N
AD1
RXDATAA13
N33
PLLFB
D5
NC
B27
RXD5P
AD2
RXDATAA14
N32
PLLREF
C5
NC
C27
RXD6N
AD3
RXDATAA15
N31
PMRST
D7
NC
B26
RXD6P
AD4
RXDATAB0
AJ34
NC
C25
NC
C26
RXD7N
AC2
RXDATAB1
AH31
NC
D25
NC
G4
RXD7P
AC3
RXDATAB2
AH32
NC
A25
NC
D15
RXD8N
AC4
RXDATAB3
AH33
NC
B25
NC
B5
RXD8P
AC5
RXDATAB4
AH34
NC
B24
RSTN
C7
RXD9N_RXCLKDN
AB1
RXDATAB5
AG31
NC
C24
RXADDRA0
W31
RXD9P_RXCLKDP
AB2
RXDATAB6
AG32
NC
D23
RXADDRA1
W32
RXD10N_RXDDN
AB3
RXDATAB7
AG33
NC
E23
RXADDRA2
V34
RXD10P_RXDDP
AB4
RXDATAB8
AG34
NC
E34
RXADDRB0
AL33
RXD11N_RXCLKCN
AA1
RXDATAB9
AG35
NC
D31
RXADDRB1
AL32
RXD11P_RXCLKCP
AA2
RXDATAB10
AF31
NC
E30
RXADDRC0
AP20
RXD12N_RXDCN
AA3
RXDATAB11
AF32
NC
B30
RXADDRC1
AL19
RXD12P_RXDCP
AA4
RXDATAB12
AF33
NC
E28
RXADDRC2
AN19
RXD13N_RXCLKBN
Y2
RXDATAB13
AF34
NC
D28
RXADDRD0
AL8
RXD13P_RXCLKBP
Y3
RXDATAB14
AF35
NC
E27
RXADDRD1
AP7
RXD14N_RXCLKAN
W2
RXDATAB15
AE32
NC
D26
RXCLKA
W33
RXD14P_RXCLKAP
W3
RXDATAC0
AP22
NC
A26
RXCLKB
AL34
RXD15N_RXDBN
W4
RXDATAC1
AN22
NC
E24
RXCLKC
AN20
RXD15P_RXDBP
W5
RXDATAC2
AM22
NC
D24
RXCLKD
AM8
RXDATAA0
T33
RXDATAC3
AL22
NC
A24
RXCLKN
_RXDAN
V4
RXDATAA1
T32
RXDATAC4
AP23
NC
E32
RXCLKP
_RXDAP
V5
RXDATAA2
R35
RXDATAC5
AN23
NC
E33
RXD0N
AG1
RXDATAA3
R34
RXDATAC6
AM23
NC
B31
RXD0P
AG2
RXDATAA4
R33
RXDATAC7
AL23
NC
C31
RXD1N
AF1
RXDATAA5
R32
RXDATAC8
AR24
NC
C30
RXD1P
AF2
RXDATAA6
R31
RXDATAC9
AP24
NC
D30
RXD2N
AF3
RXDATAA7
P35
RXDATAC10
AN24
NC
D29
RXD2P
AF4
RXDATAA8
P34
RXDATAC11
AM24
NC
E29
RXD3N
AE1
RXDATAA9
P33
RXDATAC12
AL24
NC
B29
RXD3P
AE2
RXDATAA10
P32
RXDATAC13
AR25
Note: NC refers to no connect. Do not connect pins so designated.
Agere Systems Inc.
93
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Information (continued)
600-Pin LBGA Pin Assignments (continued)
Table 6. Pin Assignments for 600-Pin LBGA by Signal Name (continued)
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
RXDATAC14
AP25
RXPRTYB
AJ33
NC
D17
TXCLKD
AP19
RXDATAC15
AN25
RXPRTYC
AR22
NC
B23
TXCLKN
U5
RXDATAD0
AL10
RXPRTYD
AR9
NC
C23
TXCLKP
U4
RXDATAD1
AM10
RXREF
AK3
NC
E22
TXCLKQN
J5
RXDATAD2
AN10
RXSOPA
U31
NC
D22
H2
RXDATAD3
AP10
RXSOPB
AJ32
NC
C21
TXCLKQP
TXD0N_TXDDN
U2
RXDATAD4
AR10
RXSOPC
AL21
NC
E21
TXD0P_TXDDP
T2
RXDATAD5
AM11
RXSOPD
AP9
NC
A21
TXD1N_TXDCN
T3
RXDATAD6
AN11
RXSPAA
F31
NC
B21
TXD1P_TXDCP
T4
RXDATAD7
AP11
RXSPAB
F32
NC
C20
TXD2N_TXDBN
R2
RXDATAD8
AR11
RXSPAC
F33
NC
D20
TXD2P_TXDBP
R3
RXDATAD9
AL12
RXSPAD
F34
NC
B19
TXD3N_TXDAN
R5
RXDATAD10
AM12
RXSZA
W35
NC
B20
TXD3P_TXDAP
R4
RXDATAD11
AN12
RXSZB
AK31
NC
E19
TXD4N
P1
RXDATAD12
AP12
RXSZC
AM20
NC
D19
TXD4P
P2
RXDATAD13
AR12
RXSZD
AN8
NC
A19
TXD5N
P3
RXDATAD14
AL13
RXTOHCLKA
AK5
NC
C19
TXD5P
P5
RXDATAD15
AM13
RXTOHCLKB
AL4
TCLK
F2
TXD6N
N2
U34
RXTOHCLKC
AL6
TDI
G5
TXD6P
N3
RXENBB
AK34
RXTOHCLKD
AL7
TDO
G2
TXD7N
N4
RXENBC
AN21
RXTOHDA
AL2
TMS
F4
TXD7P
N5
RXENBD
AM9
RXTOHDB
AM5
TRSTN
G3
TXD8N
M1
RXEOPA
U32
RXTOHDC
AM6
TXADDRA0
G32
TXD8P
M2
RXEOPB
AJ31
RXTOHDD
AN7
TXADDRA1
G33
TXD9N
M3
RXEOPC
AM21
RXTOHFA
AK4
TXADDRA2
U33
TXD9P
M4
RXEOPD
AN9
RXTOHFB
AL3
TXADDRB0
W34
TXD10N
L1
RXERRA
V32
RXTOHFC
AN5
TXADDRB1
Y34
TXD10P
L2
RXERRB
AK32
RXTOHFD
AP6
TXADDRC0
AM31
TXD11N
L3
RXERRC
AR21
NC
D18
TXADDRC1
AN31
TXD11P
L4
RXERRD
AP8
NC
B18
TXADDRC2
AM19
TXD12N
K1
RXPPAA
V33
NC
C18
TXADDRD0
AM7
TXD12P
K2
RXPPAB
AK33
NC
E18
TXADDRD1
AP5
TXD13N
K3
RXPPAC
AP21
NC
C17
TXCLKA
G34
TXD13P
K4
RXPPAD
AL9
NC
B17
TXCLKB
Y33
TXD14N
J1
RXPRTYA
T34
NC
E17
TXCLKC
AP31
TXD14P
J2
RXENBA
Note: NC refers to no connect. Do not connect pins so designated.
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Information (continued)
600-Pin LBGA Pin Assignments (continued)
Table 6. Pin Assignments for 600-Pin LBGA by Signal Name (continued)
Signal Name
TXD15N
TXD15P
TXDATAA0
TXDATAA1
TXDATAA2
TXDATAA3
TXDATAA4
TXDATAA5
TXDATAA6
TXDATAA7
TXDATAA8
TXDATAA9
TXDATAA10
TXDATAA11
TXDATAA12
TXDATAA13
TXDATAA14
TXDATAA15
TXDATAB0
TXDATAB1
TXDATAB2
TXDATAB3
TXDATAB4
TXDATAB5
TXDATAB6
TXDATAB7
TXDATAB8
TXDATAB9
TXDATAB10
TXDATAB11
TXDATAB12
TXDATAB13
TXDATAB14
TXDATAB15
TXDATAC0
Pin
J3
J4
M35
M34
M33
M32
M31
L35
L34
L33
L32
K35
K34
K33
K32
K31
J35
J34
AE33
AE34
AE35
AD31
AD32
AD33
AD34
AD35
AC31
AC32
AC33
AC34
AB32
AB31
AB33
AB34
AM25
Signal Name
TXDATAC1
TXDATAC2
TXDATAC3
TXDATAC4
TXDATAC5
TXDATAC6
TXDATAC7
TXDATAC8
TXDATAC9
TXDATAC10
TXDATAC11
TXDATAC12
TXDATAC13
TXDATAC14
TXDATAC15
TXDATAD0
TXDATAD1
TXDATAD2
TXDATAD3
TXDATAD4
TXDATAD5
TXDATAD6
TXDATAD7
TXDATAD8
TXDATAD9
TXDATAD10
TXDATAD11
TXDATAD12
TXDATAD13
TXDATAD14
TXDATAD15
TXENBA
TXENBB
TXENBC
TXENBD
Pin
AR26
AP26
AN26
AM26
AL26
AR27
AP27
AN27
AM27
AL27
AP28
AN28
AM28
AL28
AP29
AN13
AP13
AM14
AL14
AN14
AP14
AR14
AM15
AL15
AN15
AP15
AR15
AM16
AN16
AP16
AP17
H34
AA33
AP30
AR17
Signal Name
TXEOPA
TXEOPB
TXEOPC
TXEOPD
TXERRA
TXERRB
TXERRC
TXERRD
TXFSYNCN
TXFSYNCP
TXPPAA
TXPPAB
TXPPAC
TXPPAD
TXPRTYA
TXPRTYB
TXPRTYC
TXPRTYD
TXSOPA
TXSOPB
TXSOPC
TXSOPD
TXSPAA
TXSPAB
TXSPAC
TXSPAD
TXSZA
TXSZB
TXSZC
TXSZD
TXTOHCLK
TXTOHD
TXTOHF
VDDD
VDDD
Pin
J31
AA31
AL29
AN17
H32
AA35
AM30
AM18
U1
U3
H33
AA34
AN30
AP18
J33
AB35
AN29
AM17
J32
AA32
AM29
AL17
G31
AK2
AJ5
AJ4
H31
Y32
AL30
AN18
AJ2
AJ3
AH5
A1
A2
Signal Name
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
Pin
A17
A18
A34
A35
B1
B2
B34
B35
C3
C33
E11
E25
K5
L5
L31
M5
P4
R1
U35
V1
V2
V35
W1
AB5
AD5
AE5
AE31
AF5
AL11
AL18
AL25
AN3
AN33
AP1
AP2
Note: NC refers to no connect. Do not connect pins so designated.
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Data Sheet
August 18, 2004
Pin Information (continued)
600-Pin LBGA Pin Assignments (continued)
Table 6. Pin Assignments for 600-Pin LBGA by Signal Name (continued)
Signal Name
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
Pin
AP34
AP35
AR1
AR2
AR18
AR19
AR34
AR35
A5
A6
A30
A31
D4
D32
E1
E5
E16
E20
E31
E35
F1
F35
T5
T31
Y5
Y31
AK1
AK35
AL1
AL5
AL16
AL20
AL31
AL35
AM4
Signal Name
VDDD2
VDDD2
VDDD2
VDDD2
VDDD2
Pin
AM32
AR5
AR6
AR30
AR31
Note: NC refers to no connect. Do not connect pins so designated.
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions
Note: CMOS inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can
drive standard TTL inputs. All LVPECL buffers are differential. LVPECL inputs with an _ in the name indicate
multiple functionality. The name preceding the _ is the function in STS-48/STM-16 mode. The name after the
_ is the function in STS-3/STM-1 or STS-12/STM-4 mode. LVPECL is compliant with low-voltage (3.3 V)
pseudo-emitter-coupled logic interface levels. Load and termination specifications for the LVPECL I/O are
given in LVPECL I/O Termination and Load Specifications on page 178.
Table 7. Pin Descriptions—Line Interface Signals
Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally
disabled whenever the core registers are properly provisioned. The unused inputs can be considered to be NC
(no-connect).
600
V5
792
Y38
V4
W38
AG2
AG1
AF2
AF1
AF4
AF3
AE2
AE1
AE4
AE3
AD2
AD1
AD4
AD3
AC3
AC2
AC5
AC4
AB2
AF34
AF35
AF38
AF39
AF36
AF37
AE37
AE38
AE35
AE36
AD37
AD38
AD35
AD36
AC36
AC37
AC34
AC35
AB34
AB1
AB35
AB4
AC38
AB3
AC39
Symbol
RXCLKP_
RXDAP
RXCLKN_
RXDAN
RXD0P
RXD0N
RXD1P
RXD1N
RXD2P
RXD2N
RXD3P
RXD3N
RXD4P
RXD4N
RXD5P
RXD5N
RXD6P
RXD6N
RXD7P
RXD7N
RXD8P
RXD8N
RXD9P_
RXCLKDP
RXD9N_
RXCLKDN
RXD10P_
RXDDP
RXD10N_
RXDDN
Type
I/O*
Name/Description
LVPECL
I Receive Line Clock (STS-48/STM-16)/Receive Data Input
Channel A. In STS-48/STM-16 mode, the pins function as receive
line clock. This 155 MHz clock comes from an external clock and
data recovery circuit. This clock is used to clock in the RXD[15:0]
data inputs. This buffer is internally disabled when not in STS-48/
STM-16 mode.
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
receive data input channel A.
LVPECL
I Receive Data Inputs (STS-48/STM-16). In STS-48/STM-16 mode,
the pins function as receive line data inputs [8:0]. The remaining
line data inputs [15:9] (described below and on the next page) are
LVPECL
multiplexed for use in the STS-3/STM-1 or STS-12/STM-4 modes.
All 32 differential data input pins (RXD[15:0]P/N) are used when in
STS-48/STM-16 mode.
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
I
LVPECL
I
Receive Data Input [9]/Receive Line Clock Channel D†. In STS48/STM-16 mode, the pins function as receive data input [9].
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
receive line clock channel D.
This 155/622 MHz clock is used to clock in the RXDD data inputs.
Receive Data Input [10]/Receive Data Input Channel D. In STS48/STM-16 mode, the pins function as receive data input [10].
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
receive data input channel D.
* IU indicates a 100 kΩ internal pull-up. ID indicates a 50 kΩ internal pull-down.
† This buffer is internally disabled when the input is not active.
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Descriptions (continued)
Note: CMOS inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can
drive standard TTL inputs. All 2 V LVPECL buffers are differential. LVPECL inputs with a _ in the name indicate multiple functionality. The name preceding the _ is the function in STS-48/STM-16 mode. The name
after the _ is the function in STS-3/STM-1 or STS-12/STM-4 mode. LVPECL is compliant with low-voltage
(3.3 V) pseudo-emitter-coupled logic interface levels. Load and termination specifications for the LVPECL
I/O are given in LVPECL I/O Termination and Load Specifications on page 178.
Table 7. Pin Descriptions—Line Interface Signals (continued)
600
792
Symbol
Type
I/O*
AA2
AB38
RXD11P_
RXCLKCP
LVPECL
I
AA1
AB39
RXD11N_
RXCLKCN
Name/Description
Receive Data Input [11]/Receive Line Clock Channel C†. In
STS-48/STM-16 mode, the pins function as receive data input
[11].
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
receive line clock channel C.
This 155/622 MHz clock is used to clock in the RXDC data inputs.
AA4
AB36
RXD12P_
RXDCP
AA3
AB37
RXD12N_
RXDCN
Y3
AA35
RXD13P_
RXCLKBP
Y2
Y35
RXD13N_
RXCLKBN
LVPECL
I
Receive Data Input [12]/Receive Data Input Channel C. In
STS-48/STM-16 mode, the pins function as receive data input
[12].
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
receive data input channel C.
LVPECL
I
Receive Data Input [13]/Receive Line Clock Channel B†. In
STS-48/STM-16 mode, the pins function as receive data input
[13].
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
receive line clock channel B.
This 155/622 MHz clock is used to clock in the RXDB data inputs.
W3
Y36
RXD14P_
RXCLKAP
W2
Y37
RXD14N_
RXCLKAN
LVPECL
I
Receive Data Input [14]/Receive Line Clock Channel A†. In
STS-48/STM-16 mode, the pins function as receive data input
[14].
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
receive line clock channel A.
This 155/622 MHz clock is used to clock in the RXDA data inputs.
W5
AA36
RXD15P_
RXDBP
W4
AA37
RXD15N_
RXDBN
H4
L37
CLKDIV
LVPECL
I
Receive Data Input [15]/Receive Data Input Channel B. In
STS-48/STM-16 mode, the pins function as receive data input
[15].
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
receive data input channel B.
3.3 V
(5 V tolerant)
IU
Clock Division. This pin controls a divider in the line transmit
block to create a 77.76 MHz clock from either the 155.52 MHz
STS-3/STM-1 or STS-48/STM-16 transmit line clock, or the
622.08 MHz STS-12/STM-4 transmit line clock.
CLKDIV = 1 for STS-12/STM-4 (divide by 8).
CLKDIV = 0 for STS-3/STM-1 and STS-48 /STM-16 (divide by 2).
* IU indicates a 100 kΩ internal pull-up. ID indicates a 50 kΩ internal pull-down.
† This buffer is internally disabled when the input is not active.
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Note: CMOS inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can
drive standard TTL inputs. All 2 V LVPECL buffers are differential. LVPECL inputs with a _ in the name indicate multiple functionality. The name preceding the _ is the function in STS-48/STM-16 mode. The name
after the _ is the function in STS-3/STM-1 or STS-12/STM-4 mode. LVPECL is compliant with low-voltage
(3.3 V) pseudo-emitter-coupled logic interface levels. Load and termination specifications for the LVPECL
I/O are given in LVPECL I/O Termination and Load Specifications on page 178.
Table 7. Pin Descriptions—Line Interface Signals (continued)
600
792
Symbol
Type
AG3
AG37
ECLREFLO
—
AG4
AG36
ECLREFHI
—
U4
V38
TXCLKP
LVPECL
U5
V39
TXCLKN
I/O*
Name/Description
— Reference Voltage for LVPECL I/O Buffers. ECLREFLO and
— ECLREFHI provide the reference for the output level of the
LVPECL output buffers. The standard value for ECL termination
voltage is VDD – 2 V and the standard termination resistance is
50 Ω. All ECL output buffers on the chip must have the same
termination voltage and termination resistance as ECLREFLO
and ECLREFHI. ECLREFLO and ECLREFHI must have
separate termination. Thevenin termination of 50 Ω into VDDD –
2 V (this may be obtained from a passive voltage divider of a
130 Ω resistor connected from VDDD to one end of an 82 Ω
resistor, the other end of which is connected to GNDD) is
recommended for all ECL output buffers and ECLREFLO and
ECLREFHI.
I
Transmit Line Clock. When in STS-48/STM-16 or quad STS-3/
STM-1 mode, this clock is a 155.52 MHz input and clocks out
TXD[15:0].
When in STS-12/STM-4 mode, it is a 622.08 MHz input and
clocks out TXD[A—D].
U3
U1
W37
W36
TXFSYNCP
TXFSYNCN
LVPECL
ID
U
I
Transmit Line 8 kHz Frame Sync. This input is the external
8 kHz transmit line frame sync. Driving this input is optional. If
undriven from an external source, these pins must be no
connects. When this input is used, it must be (1) synchronized to
TXCLKP/N, and (2) at least one TXCLKP/N cycle wide, up to a
maximum of 1 frame period minus two TXCLKP/N cycles wide.
* IU indicates a 100 kΩ internal pull-up. ID indicates a 50 kΩ internal pull-down.
† This buffer is internally disabled when the input is not active.
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Descriptions (continued)
Note: CMOS inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can
drive standard TTL inputs. All 2 V LVPECL buffers are differential. LVPECL inputs with a _ in the name indicate multiple functionality. The name preceding the _ is the function in STS-48/STM-16 mode. The name
after the _ is the function in STS-3/STM-1 or STS-12/STM-4 mode. LVPECL is compliant with low-voltage
(3.3 V) pseudo-emitter-coupled logic interface levels. Load and termination specifications for the LVPECL
I/O are given in LVPECL I/O Termination and Load Specifications on page 178.
Table 7. Pin Descriptions—Line Interface Signals (continued)
600
792
Symbol
Type
I/O*
Name/Description
T2
V36
TXD0P_
TXDDP
LVPECL
O
U2
V37
TXD0N_
TXDDN
Transmit Data Output [0]/Transmit Data Output Channel D.
In STS-48/STM-16 mode, the pins function as transmit data output [0].
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
transmit data output channel D.
All 32 pins are used when in STS-48/STM-16 mode.
T4
V34
TXD1P_
TXDCP
T3
V35
TXD1N_
TXDCN
LVPECL
O
Transmit Data Output [1]/Transmit Data Output Channel C.
In STS-48/STM-16 mode, the pins function as transmit data output [1].
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
transmit data output channel C.
All 32 pins are used when in STS-48/STM-16 mode.
R3
U38
TXD2P_
TXDBP
R2
U39
TXD2N_
TXDBN
LVPECL
O
Transmit Data Output [2]/Transmit Data Output Channel B.
In STS-48/STM-16 mode, the pins function as transmit data output [2].
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
transmit data output channel B.
All 32 pins are used when in STS-48/STM-16 mode.
R4
U36
TXD3P_
TXDAP
R5
U37
TXD3N_
TXDAN
LVPECL
O
Transmit Data Output [3]/Transmit Data Output Channel A.
In STS-48/STM-16 mode, the pins function as transmit data output [3].
In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
transmit data output channel A.
All 32 pins are used when in STS-48/STM-16 mode.
IU
ID
*
indicates a 100 kΩ internal pull-up. indicates a 50 kΩ internal pull-down.
† This buffer is internally disabled when the input is not active.
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Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Note: CMOS inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic outputs can
drive standard TTL inputs. All 2 V LVPECL buffers are differential. LVPECL inputs with a _ in the name indicate multiple functionality. The name preceding the _ is the function in STS-48/STM-16 mode. The name
after the _ is the function in STS-3/STM-1 or STS-12/STM-4 mode. LVPECL is compliant with low-voltage
(3.3 V) pseudo-emitter-coupled logic interface levels. Load and termination specifications for the LVPECL
I/O are given in LVPECL I/O Termination and Load Specifications on page 178.
Table 7. Pin Descriptions—Line Interface Signals (continued)
600
792
Symbol
Type
I/O*
H2
M35
TXCLKQP
LVPECL
O
J5
M36
TXCLKQN
Name/Description
Transmit Line Clock. This 155.52 MHz clock is used in the
OC-48 mode for forward-directional timing with the 155 Mbits/s
16-bit parallel-to-2.5 Gbits/s serial MUX to clock out the data.
In OC-48 forward clock mode, TXD[15:0]P/N transitions at the
rising edge of TXCLKQP.
For an OC-48 contraclocking interface with the 155 Mbits/s
parallel-to-2.5 Gbits/s serial MUX, this clock is not used. In the
contraclocking mode, the SONET PLL must be active (see MPU
register MPU_LI_MODER, address 0x0021, bit 5.
P2
U34
TXD4P
P1
U35
TXD4N
P5
T37
TXD5P
P3
T38
TXD5N
N3
T35
TXD6P
N2
T36
TXD6N
N5
R37
TXD7P
N4
R38
TXD7N
M2
P38
TXD8P
M1
P39
TXD8N
M4
R35
TXD9P
M3
R36
TXD9N
L2
P36
TXD10P
L1
P37
TXD10N
L4
P34
TXD11P
L3
P35
TXD11N
K2
N38
TXD12P
K1
N39
TXD12N
K4
N36
TXD13P
K3
N37
TXD13N
J2
N34
TXD14P
J1
N35
TXD14N
J4
M37
TXD15P
J3
M38
TXD15N
LVPECL
O
Transmit Data Outputs (STS-48/STM-16). All 32 differential data
input pins (TXD[15:0]P/N) are used when in STS-48 mode.
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
U
* I indicates a 100 kΩ internal pull-up. ID indicates a 50 kΩ internal pull-down.
† This buffer is internally disabled when the input is not active.
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 8. Pin Descriptions—TOH Interface Signals
600
792
Symbol
Type
I/O*
Name/Description
AK3
AK34
RXREF
3.3 V
O
Receive Line Frame. This output provides the receive 8 kHz
frame reference for external timing needs. RXREF is derived from
one of the received line clocks (user-selectable). It is a 50% duty
cycle clock when MARS2G5 P-Pro is in frame. This signal may be
used to implement line timing on a SONET ring. When not
provisioned, this signal must not be used. RXREF is valid only
when the SONET framer is in frame. Upon LOC, RXREF is not
present. Upon LOF, RXREF is present but is free-running.
Because jitter may be present on this signal when the device
goes into and out of an LOF state, it should not be used as a
reference for TXFSYNCP/N.
AL7
AL6
AL4
AK5
AR30
AR31
AM34
AL35
RXTOHCLKD
RXTOHCLKC
RXTOHCLKB
RXTOHCLKA
3.3 V
O
Receive TOH Interface Clock. This clock is nominally a
5.184 MHz (STS-3/STM-1), 20.736 MHz (STS-12/STM-4), or a
20.736 MHz (STS-48/STM-16) clock which provides timing for
circuitry that receives and externally processes the receive
transport overhead bytes. These clocks are frequency shifted as
shown in Figure 32, STS-12/STM-4 and STS-48/STM-16
Receive TOAC Interface Timing on page 206 and Figure 33,
STS-3/STM-1 Receive TOAC Interface Timing on page 207.
AN7
AM6
AM5
AL2
AU30
AT31
AP32
AL34
RXTOHDD
RXTOHDC
RXTOHDB
RXTOHDA
3.3 V
O
Receive TOH Interface Data. This 5.184 Mbits/s or
20.736 Mbits/s signal contains all the receive transport overhead
bytes (A1, A2, J0/Z0, B1, E1, F1, D1—D3, H1—H3, K1, K2,
D4—D12, S1/Z1, M0, and E2) for all 3/12/48 STS-1s. This signal
can be used by external circuitry to process the TOH bytes.
RXTOHD is updated on the falling edge of RXTOHCLK.
AP6
AN5
AL3
AK4
AP30
AR32
AM35
AL36
RXTOHFD
RXTOHFC
RXTOHFB
RXTOHFA
3.3 V
O
Receive TOH Interface Frame. This 8 kHz framing signal is used
to locate the individual receive transport overhead bits in the
RXTOHD bit stream. RXTOHF[D—A] is only high while bit 1
(MSB) of the first framing byte (A1 during parity time in first byte)
is present on the RXTOHD output. RXTOHF[D—A] is updated on
the falling edge of RXTOHCLK.
* IU indicates a 100 kΩ internal pull-up. ID indicates a 50 kΩ internal pull-down.
Note: [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first byte).
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Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 8. Pin Descriptions—TOH Interface Signals (continued)
600
792
Symbol
Type
I/O*
Name/Description
AJ2
AJ37
TXTOHCLK
3.3 V
O
Transmit TOH Interface Clock. This clock is nominally a
5.184 MHz (STS-3/STM-1), 20.736 MHz (STS-12/STM-4), or a
20.736 MHz (STS-48/STM-16) clock which provides timing for
circuitry that externally generates and transmits the transmit
transport overhead bytes for inclusion in the transmit data stream.
This clock is frequency shifted as shown in Figure 31, STS-3/
STM1, STS-12/STM-4, and STS-48/STM-16 Transmit TOAC
Interface Timing on page 206.
AJ3
AJ36
TXTOHD
3.3 V
(5 V tolerant)
IU
Transmit TOH Interface Data. This 5.184 Mbits/s or
20.736 Mbits/s signal contains all the transmit transport overhead
bytes (A1, A2, J0/Z0, E1, F1, D1—D3, D4—D12, S1/Z1, M0, and
E2) for all 3/12/48 STS-1s. This signal is generated by external
circuitry for custom TOH byte definitions. TXTOHD is sampled on
the rising edge of TXTOHCK. The data format is different from
MARS2G5 P-ProLT.
AH5
AH35
TXTOHF
3.3 V
O
Transmit TOH Interface Frame. This 8 kHz framing signal is
used to align the individual transmit transport overhead bits in the
TXTOHD bit stream. TXTOHF is only high while bit 1 (MSB) of the
first framing byte (A1 during parity time in first byte) is expected
on the TXTOHD input. TXTOHF is updated on the falling edge of
TXTOHCK. This pin function is different from MARS2G5 P-ProLT.
* IU indicates a 100 kΩ internal pull-up. ID indicates a 50 kΩ internal pull-down.
Note: [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first byte).
Agere Systems Inc.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
792
Symbol
Type
I/O*
U33
G33
G32
Y34
W34
AM19
AN31
AM31
AP5
AM7
Y5
K3
L5
AB6
AB1
AU19
AP8
AR7
AP31
AT30
TXADDRA2
TXADDRA1
TXADDRA0
TXADDRB1
TXADDRB0
TXADDRC2
TXADDRC1
TXADDRC0
TXADDRD1
TXADDRD0
3.3 V
(5 V
tolerant)
IU
J34
J35
K31
K32
K33
K34
K35
L32
L33
L34
L35
M31
M32
M33
M34
M35
M2
P6
N4
N3
P5
N2
P4
P3
N1
R5
P2
R4
R3
P1
T5
R2
TXDATAA15
TXDATAA14
TXDATAA13
TXDATAA12
TXDATAA11
TXDATAA10
TXDATAA9
TXDATAA8
TXDATAA7
TXDATAA6
TXDATAA5
TXDATAA4
TXDATAA3
TXDATAA2
TXDATAA1
TXDATAA0
3.3 V
(5 V tolerant)
Name/Description
Transmit Address. The TXADDR is driven by the UTOPIA
master to poll and select the appropriate PHY channel of
MARS2G5 P-Pro to transmit data.
Note: The PHY address (0x00 to 0x1E) for each of the four
channels in MARS2G5 P-Pro is configured via software
provisioning. TXADDRA[2:0] concatenated with
TXDATAA[7:6] forms a 5-bit address bus.
TXADDRB[1:0] concatenated with TXDATAB[7:5] forms
a 5-bit address bus. TXADDRC[2:0] concatenated with
TXDATAC[7:6] forms a 5-bit address bus.
TXADDRD[1:0] concatenated with TXDATAD[7:5] forms
a 5-bit address bus.
IU
Transmit Data Channel A. Used to transport data into the
UTOPIA PHY Tx block. TXDATAA is only valid when TXENBA
is asserted, and is sampled on the rising edge of TXCLKA.
Note: TXDATAA is used in various UTOPIA modes. In 8-bit
mode, only bits 15 to 8 are valid.
In 32-bit mode, TXDATAA[15:0] forms the most significant
16 bits of the combined data bus (bits 31 to 16), and
TXDATAB[15:0] forms the least significant 16 bits of the combined data bus (bits 15 to 0).
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
104
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
792
Symbol
Type
I/O*
Name/Description
U
Transmit Data Channel B. Used to transport data into the
UTOPIA PHY Tx block. TXDATAB is only valid when TXENBB
is asserted (TXENBA for 32-bit mode), and is sampled on the
rising edge of TXCLKB (TXCLKA for 32-bit mode).
AB34
AB33
AB31
AB32
AC34
AC33
AC32
AC31
AD35
AD34
AD33
AD32
AD31
AE35
AE34
AE33
AC3
AC2
AD4
AD5
AD3
AD2
AE2
AE3
AE4
AE5
AF1
AF2
AF3
AF4
AF5
AF6
TXDATAB15
TXDATAB14
TXDATAB13
TXDATAB12
TXDATAB11
TXDATAB10
TXDATAB9
TXDATAB8
TXDATAB7
TXDATAB6
TXDATAB5
TXDATAB4
TXDATAB3
TXDATAB2
TXDATAB1
TXDATAB0
3.3 V
(5 V tolerant)
AP29
AL28
AM28
AN28
AP28
AL27
AM27
AN27
AP27
AR27
AL26
AM26
AN26
AP26
AR26
AM25
AT10
AU10
AR11
AT11
AU11
AV11
AR12
AT12
AU12
AV12
AT13
AP13
AR13
AU13
AV13
AU14
TXDATAC15
TXDATAC14
TXDATAC13
TXDATAC12
TXDATAC11
TXDATAC10
TXDATAC9
TXDATAC8
TXDATAC7
TXDATAC6
TXDATAC5
TXDATAC4
TXDATAC3
TXDATAC2
TXDATAC1
TXDATAC0
3.3 V
(5 V tolerant)
I
Note: TXDATAB is used in various UTOPIA modes. In 8-bit
mode, only bits 15 to 8 are valid.
In 32-bit mode, TXDATAB[15:0] forms the least significant
16 bits of the combined data bus (bits 15 to 0), and
TXDATAA[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16).
IU
Transmit Data Channel C. Used to transport data into the
UTOPIA PHY Tx block. TXDATAC is only valid when TXENBC
is asserted, and is sampled on the rising edge of TXCLKC.
Note: TXDATAC is used in various UTOPIA modes. In 8-bit
mode, only bits 15 to 8 are valid.
In 32-bit mode, TXDATAC[15:0] forms the most significant
16 bits of the combined data bus (bits 31 to 16), and
TXDATAD[15:0] forms the least significant 16 bits of the combined data bus (bits 15 to 0).
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
Agere Systems Inc.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
792
AP17 AT21
AP16 AR21
AN16 AV22
AM16 AU22
AR15 AW23
AP15 AT22
AN15 AR22
AL15 AV23
AM15 AP22
AR14 AU23
AP14 AT23
AN14 AV24
AL14 AR23
AM14 AU24
AP13 AP23
AN13 AT24
AM17 AW22
AN29 AR10
AB35 AC4
N5
J33
Symbol
Type
3.3 V
TXDATAD15
TXDATAD14 (5 V tolerant)
TXDATAD13
TXDATAD12
TXDATAD11
TXDATAD10
TXDATAD9
TXDATAD8
TXDATAD7
TXDATAD6
TXDATAD5
TXDATAD4
TXDATAD3
TXDATAD2
TXDATAD1
TXDATAD0
TXPRTYD
TXPRTYC
TXPRTYB
TXPRTYA
3.3 V
(5 V tolerant)
I/O*
Name/Description
U
Transmit Data Channel D. Used to transport data into the UTOPIA PHY Tx block. TXDATAD is only valid when TXENBD is
asserted, and is sampled on the rising edge of TXCLKD
(TXCLKA for 32-bit mode).
I
Note: TXDATAD is used in various UTOPIA modes. In 8-bit
mode, only bits 15 to 8 are valid.
In 32-bit mode, TXDATAD[15:0] forms the least significant
16 bits of the combined data bus (bits 15 to 0), and
TXDATAC[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16).
IU
Transmit Parity. This signal indicates the parity on the
TXDATA[D—A][15:0] bus. A parity error raises an alarm but does
not cause the cell/packet to be dropped. Odd or even parity may
be provisioned through a software register. TXPRTY[D—A] is
considered valid only when TXENB[D—A] is asserted, and is
sampled on the rising edge of TXCLK[D—A].
In 32-bit mode, the TXPRTYA and TXPRTYC parity pin of port A
and port C, respectively, indicates the parity for the entire 32-bit
data input.
AL17
AM29
AA32
J32
AU21
AP10
AC5
M3
TXSOPD
TXSOPC
TXSOPB
TXSOPA
3.3 V
(5 V tolerant)
IU
Transmit Start of Packet/Cell. In ATM mode, the TXSOP[D—A]
signal marks the start of a cell on the TXDATA[D—A][15:0] bus.
When TXSOP[D—A] is active, the first word of the cell is present
on the TXDATA[D—A][15:0] bus. An alarm will be raised if
TXSOP[D—A] goes high before the previous cell was completely
sent.
In packet modes, the TXSOP[D—A] signal marks the start of a
packet on the TXDATA[D—A][15:0] bus. When TXSOP[D—A] is
active, the first word of the packet is present on the TXDATA[D—
A][15:0] bus.
TXSOP[D—A] is considered valid only when TXENB[D—A] is
asserted, and is sampled on the rising edge of TXCLK[D—A].
In 32-bit mode, only the TXSOPA and TXSOPC pin of port A and
port C, respectively, is used to indicate a start of packet/cell for
the 32-bit data input.
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
106
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
792
Symbol
Type
I/O*
Name/Description
AP18
AN30
AA34
H33
AT20
AR9
AB2
M4
TXPPAD
TXPPAC
TXPPAB
TXPPAA
3.3 V
O
Transmit Cell/Polled Packet Available. This signal indicates
when the transmit FIFO is below a provisionable level. If the FIFO
is empty or more than the provisioned space is available in the
FIFO, TXPPA[D—A] is set active. In ATM mode, asserting
TXPPA[D—A] means that FIFO has room for one entire ATM cell.
TXPPA[D—A] should go low four cycles before the end of cell if the
selected channel does not have space available for one entire cell.
In packet modes, asserting TXPPA[D—A] means that the FIFO
has room for several words. If TXPPA[D—A] is inactive, it indicates
that the FIFO is full or that less than the provisioned amount of
space available. TXPPA[D—A] is updated on the rising edge of
TXCLK[D—A].
In 32-bit mode, only the TXPPA and TXPPC pin of port A and port
C, respectively, is used to indicate the packet/cell available status.
AP19
AP31
Y33
G34
AT19
AR8
AB5
L4
TXCLKD
TXCLKC
TXCLKB
TXCLKA
3.3 V
(5 V tolerant)
IU
Transmit Clock. This clock is used to write cells or packets into
the transmit FIFO. TXCLK[D—A] can operate at speeds from dc to
104 MHz.
This clock is required to access channels, i.e., to access channel 2
of slice C, this clock must be provided to slice C (see Table 750).
In 32-bit mode, both TXCLKA and TXCLKB are used and required
to clock data into port A. Both TXCLKC and TXCLKD are used and
required to clock data into port C.
AR17
AP30
AA33
H34
AV20
AT9
AC1
N6
TXENBD
TXENBC
TXENBB
TXENBA
3.3 V
(5 V tolerant)
IU
Transmit Data Enable (Active-Low). This signal is used to transfer data on the TXDATA[D—A][15:0] bus into the transmit FIFOs. If
TXENB[D—A] is high, no operation is performed. If TXENB[D—A]
is low, a write occurs.
TXENB[D—A] is sampled on the rising edge of TXCLK[D—A].
TXENB[D—A] has the same meaning as data valid.
In 32-bit mode, only the TXENBA and TXENBC input pin of port A
and port C, respectively, is used to enable the transfer of data.
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
Agere Systems Inc.
107
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
AN18
AL30
Y32
H31
792
AU20
AT8
AB4
M5
Symbol
TXSZD
TXSZC
TXSZB
TXSZA
Type
I/O*
Name/Description
3.3 V
(5 V tolerant)
U
Transmit Size. This signal defines the valid bytes transmitted and
their packing within (1) TXDATA[D—A][15:0] for 16-bit modes,
and (2) TXDATAA[15:0] and TXDATAB[15:0] for the 32-bit mode.
The meaning of these bits may be inverted through the
appropriate UT control register TXSZ/RXSZ mode.
I
In 8-bit modes, TXSZ[D—A] are unused.
For 16-bit mode,
TXSZ[D—A] = 0 defines the MSByte of TXDATA[D—A][15:0], i.e.,
TXDATA[D—A][15:8], to be the last byte of the packet transmitted
when using the default configuration.
TXSZ[D—A] = 1 defines the LSByte of TXDATA[D—A][15:0], i.e.,
TXDATA[D—A][7:0], to be the last byte of the packet transmitted
when using the default configuration.
For 32-bit mode, TXSZA and TXSZB are combined to define
four states of the transmitted data stream on ports A and B. Ports
C and D are controlled by TXSZC and TXSZD. The following
states are assigned by TXSZA and TXSZB (or TXSZC and
TXSZD) when TXEOPA (or TXEOPC) is asserted when using the
default configuration.
TXDATAA
TXDATAA[15:8] TXDATAA[7:0]
TXSZA TXSZB DATA[31:24]
DATA[23:16]
0
0
1
1
0
1
0
1
Valid
Valid
Valid
Valid
Not Valid
Valid
Valid
Valid
TXDATAB
TXDATAB[15:8] TXDATAB[7:0]
DATA[15:8]
DATA[7:0]
Not Valid
Not Valid
Valid
Valid
Not Valid
Not Valid
Not Valid
Valid
There is no byte swapping and the data bytes are packed into the
upper transmitted bytes first.
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
108
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
AN17
AL29
AA31
J31
792
AV21
AU9
AC6
L2
Symbol
TXEOPD
TXEOPC
TXEOPB
TXEOPA
Type
I/O*
Name/Description
3.3 V
(5 V tolerant)
U
Transmit End of Packet. This signal indicates that the last word
of a packet is on the TXDATA[D—A][15:0] bus. TXEOP[D—A] is
valid only when TXENB[D—A] is asserted, and is sampled on the
rising edge of TXCLK[D—A].
I
In 32-bit mode, only the TXEOPA and TXEOPC input pin of port A
and port C, respectively, is used to indicate the end of the
incoming packet.
AM18
AM30
AA35
H32
AR20
AP9
AB3
L3
TXERRD
TXERRC
TXERRB
TXERRA
3.3 V
(5 V tolerant)
IU
Transmit Error. TXERR[D—A] is only used in packet modes, and
indicates that the current packet is to be aborted and discarded, if
possible. TXERR[D—A] is only valid when TXEOP[D—A] and
TXENB[D—A] are asserted, and is sampled on the rising edge of
TXCLK[D—A].
In 32-bit mode, only the TXERRA and TXERRC input pin of port A
and port C, respectively, is used to indicate an error on the
incoming packet.
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
Agere Systems Inc.
109
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
792
Symbol
Type
I/O*
Name/Description
U
Receive Address. Receive address is driven in MPHY mode to
poll and select the appropriate MPHY channel.
V34
W32
W31
AL32
AL33
AN19
AL19
AP20
AP7
AL8
AA1
AA2
AA4
AN5
AM6
AR19
AV19
AP18
AR29
AT29
RXADDRA2
RXADDRA1
RXADDRA0
RXADDRB1
RXADDRB0
RXADDRC2
RXADDRC1
RXADDRC0
RXADDRD1
RXADDRD0
3.3 V
(5 V
tolerant)
I
N31
N32
N33
N34
P31
P32
P33
P34
P35
R31
R32
R33
R34
R35
T32
T33
T4
U6
T3
U5
T2
U4
V6
U3
V5
U2
V4
U1
V3
V2
W5
W4
RXDATAA15
RXDATAA14
RXDATAA13
RXDATAA12
RXDATAA11
RXDATAA10
RXDATAA9
RXDATAA8
RXDATAA7
RXDATAA6
RXDATAA5
RXDATAA4
RXDATAA3
RXDATAA2
RXDATAA1
RXDATAA0
3.3 V
O
AE32
AF35
AF34
AF33
AF32
AF31
AG35
AG34
AG33
AG32
AG31
AH34
AH33
AH32
AH31
AJ34
AG1
AG2
AG3
AG4
AG6
AG5
AH2
AH3
AH4
AH5
AJ2
AJ3
AJ4
AJ5
AK3
AK4
RXDATAB15
RXDATAB14
RXDATAB13
RXDATAB12
RXDATAB11
RXDATAB10
RXDATAB9
RXDATAB8
RXDATAB7
RXDATAB6
RXDATAB5
RXDATAB4
RXDATAB3
RXDATAB2
RXDATAB1
RXDATAB0
3.3 V
Note: The address for each channel is configured by the
microprocessor. RXADDRA[2:0] concatenated with
TXDATAA[1:0] forms a 5-bit address bus. RXADDRB[1:0]
concatenated with TXDATAB[2:0] forms a 5-bit address
bus. RXADDRC[2:0] concatenated with TXDATAC[1:0]
forms a 5-bit address bus. RXADDRD[1:0] concatenated
with TXDATAD[2:0] forms a 5-bit address bus.
Receive Data Channel A. Used to transport data out of the
UTOPIA PHY Rx block. RXDATAA[15:0] is only valid when
RXENBA is asserted, and is updated on the rising edge of
RXCLKA.
Note: RXDATAA[15:0] is used in various UTOPIA modes. In 8-bit
mode, only bits 15 to 8 are valid.
In 32-bit mode, RXDATAA[15:0] forms the most significant
16 bits of the combined data bus (bits 31 to 16), and
RXDATAB[15:0] forms the least significant 16 bits of the
combined data bus (bits 15 to 0).
O
Receive Data Channel B. Used to transport data out of the
UTOPIA PHY Rx block. RXDATAB[15:0] is only valid when
RXENBB is asserted, and is updated on the rising edge of
RXCLKB.
Note: RXDATAB[15:0] is used in various UTOPIA modes. In 8-bit
mode, only bits 15 to 8 are valid.
In 32-bit mode, RXDATAB[15:0] forms the least significant
16 bits of the combined data bus (bits 15 to 0), and
RXDATAA[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16).
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
792
Type
I/O*
AN25 AR14 RXDATAC15
AP25 AP14 RXDATAC14
AR25 AT14 RXDATAC13
AL24 AV14 RXDATAC12
AM24 AW14 RXDATAC11
AN24 AV15 RXDATAC10
AP24 AT15 RXDATAC9
AR24 AR15 RXDATAC8
AL23 AU15 RXDATAC7
AM23 AV16 RXDATAC6
AN23 AU16 RXDATAC5
AP23 AT16 RXDATAC4
AL22 AR16 RXDATAC3
AM22 AV17 RXDATAC2
AN22 AW17 RXDATAC1
AP22 AU17 RXDATAC0
3.3 V
O
AM13 AV25 RXDATAD15
AL13 AR24 RXDATAD14
AR12 AW26 RXDATAD13
AP12 AU25 RXDATAD12
AN12 AT25 RXDATAD11
AM12 AV26 RXDATAD10
AL12 AR25 RXDATAD9
AR11 AW27 RXDATAD8
AP11 AU26 RXDATAD7
AN11 AT26 RXDATAD6
AM11 AV27 RXDATAD5
AR10 AW28 RXDATAD4
AP10 AR26 RXDATAD3
AN10 AU27 RXDATAD2
AM10 AP26 RXDATAD1
AL10 AT27 RXDATAD0
3.3 V
AR9
AR22
AJ33
T34
3.3 V
AV28
AT17
AK5
V1
Symbol
RXPRTYD
RXPRTYC
RXPRTYB
RXPRTYA
Name/Description
Receive Data Channel C. Used to transport data out of the
UTOPIA PHY Rx block. RXDATAC[15:0] is only valid when
RXENBC is asserted, and is updated on the rising edge of
RXCLKC.
Note: RXDATAC[15:0] is used in various UTOPIA modes. In 8-bit
mode, only bits 15 to 8 are valid.
In 32-bit mode, RXDATAC[15:0] forms the most significant
16 bits of the combined data bus (bits 31 to 16), and
RXDATAD[15:0] forms the least significant 16 bits of the combined data bus (bits 15 to 0).
O
Receive Data Channel D. Used to transport data out of the
UTOPIA PHY Rx block. RXDATAD[15:0] is only valid when
RXENBD is asserted, and is updated on the rising edge of
RXCLKD.
Note: RXDATAD[15:0] is used in various UTOPIA modes. In 8-bit
mode, only bits 15 to 8 are valid.
In 32-bit mode, RXDATAD[15:0] forms the least significant
16 bits of the combined data bus (bits 15 to 0), and
RXDATAC[15:0] forms the most significant 16 bits of the combined data bus (bits 31 to 16).
O
Receive Parity. This signal indicates the parity on the
RXDATA[D—A][15:0] bus, when it is used. Odd or even parity is
provisioned through bit 3 of register 0x7012 (Table 773).
RXPRTY[D—A] is considered valid only when RXENB[D—A] is
asserted, and is updated on the rising edge of RXCLK[D—A].
In 32-bit mode, the RXPRTYA and RXPRTYC parity pin of port A
and port C, respectively, indicates the parity for the entire 32-bit
data output.
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
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Data Sheet
August 18, 2004
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
792
Symbol
Type
I/O*
Name/Description
AP9
AL21
AJ32
U31
AR27
AR17
AL3
W3
RXSOPD
RXSOPC
RXSOPB
RXSOPA
3.3 V
O
Receive Start of Packet/Cell. In ATM mode, RXSOP[D—A] signal
marks the start of a cell on the RXDATA[D—A][15:0] bus. When
RXSOP[D—A] is high, the first word of the cell structure is present
on the RXDATA[D—A][15:0] bus.
In packet modes, the RXSOP[D—A] signal marks the start of a
packet on the RXDATA[D—A][15:0] bus. When RXSOP[D—A] is
high, the first word of the packet is present on the RXDATA[D—
A][15:0] bus. RXSOP[D—A] is considered valid only when
RXENB[D—A] is asserted, and is updated on the rising edge of
RXCLK[D—A].
In 32-bit mode, only the RXSOPA and RXSOPC pin of port A and
port C, respectively, is used to indicate a start of packet/cell for the
32-bit data output.
AL9
AP21
AK33
V33
AT28
AU18
AL5
Y3
RXPPAD
RXPPAC
RXPPAB
RXPPAA
3.3 V
O
Receive Cell/Polled Packet Available. This signal indicates when
the receive FIFO is below a provisionable level. If the FIFO is empty
or less than the provisioned number of bytes are available in the
FIFO, RXPPA[D—A] is set low. If RXPPA[D—A] is high, it indicates
that the FIFO is full or that more than the provisioned number of
bytes are available.
In ATM mode, asserting RXPPA[D—A] means that FIFO has one
entire ATM cell to send. On the other hand, in packet modes,
RXPPA[D—A] just tells that FIFO has data to send, and it operates
on a word-by-word basis. RXPPA[D—A] is updated on the rising
edge of RXCLK[D—A].
In 32-bit mode, only the RXPPAA and RXPPAC pin of port A and
port C, respectively, is used to indicate the packet/cell available status.
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
792
AM8
AN20
AL34
W33
AU29
AR18
AM5
AA5
Symbol
Type
I/O*
Name/Description
I/O Receive Clock. This clock is used to read cells or packets from the
3.3 V
RXCLKD
receive FIFO. RXCLK[D—A] can operate at speeds from dc to
RXCLKC (5 V toler104 MHz.
ant)
RXCLKB
RXCLKA
This clock is required to access channels, i.e., to access channel 2
of slice C, this clock must be provided to slice C (see Table 750).
In 32-bit mode, both RXCLKA and RXCLKB are used and required
to clock data out of port A. Both RXCLKC and RXCLKD are used
and required to clock data out of port C.
AM9
AN21
AK34
U34
AP27
AV18
AL4
Y4
RXENBD
3.3 V
RXENBC (5 V tolerRXENBB
ant)
RXENBA
IU
Receive Data Enable (Active-Low). This signal is used to indicate
to the UTOPIA PHY Rx block that it is selected. If RXENB[D—A] is
high, no operation is performed. For an unused interface,
RXENB[D—A] must be tied high or left unconnected. If RXENB[D—
A] is low, the UTOPIA PHY Rx block sends the next word.
In 32-bit mode, only the RXENBA and RXENBC input pin of port A
and port C, respectively, is used to enable the transfer of data.
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
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Data Sheet
August 18, 2004
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
792
Symbol
Type
I/O*
Name/Description
AN8
AM20
AK31
W35
AR28
AT18
AM4
AA3
RXSZD
RXSZC
RXSZB
RXSZA
3.3 V
O
Receive Size. This signal defines the valid bytes received and
their packing within (1) RXDATA[D—A][15:0] for 16-bit mode, and
(2) RXDATAA[15:0] and RXDATAB[15:0] for the 32-bit mode. The
meaning of these bits may be inverted through TXSZ/RXSZ mode.
In 8-bit modes, RXSZ[D—A] are unused.
For 16-bit mode,
RXSZ[D—A] = 0 defines the MSByte of RXDATA[D—A][15:0], i.e.,
RXDATA[D—A][15:8], to be the last byte of the packet received
when using the default configuration.
RXSZ[D—A] = 1 defines the LSByte of RXDATA[D—A][15:0], i.e.,
RXDATA[D—A][7:0], to be the last byte of the packet received
when using the default configuration.
For 32-bit mode, RXSZA and RXSZB are combined to define
four states of the transmitted data stream on ports A and B. Ports
C and D are controlled by RXSZC and RXSZD. The following
states are assigned by RXSZA and RXSZB (or RXSZC and
RXSZD) when RXEOPA (or RXEOPC) is asserted when using the
default configuration.
RXDATAA
RXDATAA[15:8] RXDATAA[7:0]
RXSZA RXSZB DATA[31:24]
DATA[23:16]
0
0
1
1
0
1
0
1
Valid
Valid
Valid
Valid
RXDATAB
RXDATAB[15:8] RXDATAB[7:0]
DATA[15:8]
DATA[7:0]
Not Valid
Valid
Valid
Valid
Not Valid
Not Valid
Valid
Valid
Not Valid
Not Valid
Not Valid
Valid
There is no byte swapping and the data bytes are packed into the
upper transmitted bytes first.
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
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Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
792
Symbol
Type
I/O*
Name/Description
AN9
AM21
AJ31
U32
AU28
AP17
AK6
W2
RXEOPD
RXEOPC
RXEOPB
RXEOPA
3.3 V
O
Receive End of Packet. This signal indicates that the last word of
a packet is on the RXDATA[D—A][15:0] bus. RXEOP[D—A] is
valid only when RXENB[D—A] is asserted, and is updated on the
rising edge of RXCLK[D—A].
In 32-bit mode, only the RXEOPA and RXEOPC output pin of port
A and port C, respectively, is used to indicate the end of the
outgoing packet.
AP8
AR21
AK32
V32
AV29
AW18
AL6
Y2
RXERRD
RXERRC
RXERRB
RXERRA
3.3 V
O
Receive Error. RXERR[D—A] is only used in POS mode, and
indicates that the current packet is to be aborted and discarded, if
possible. RXERR[D—A] is only valid when RXEOP[D—A] and
RXENB[D—A] are asserted, and is updated on the rising edge of
RXCLK[D—A].
In 32-bit mode, only the RXERRA and RXERRC output pin of port
A and port C, respectively, is used to indicate an error on the
outgoing packet.
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB). [D—A] refers to four physical interfaces (when bundled, D = last byte, A = first
byte).
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Data Sheet
August 18, 2004
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 9. Pin Descriptions—Enhanced UTOPIA Interface Signals (continued)
Note: For 32-bit mode operation, both 16-bit interfaces forming the 32-bit interface must be configured; see 32-Bit
Mode Configuration (Necessary Configuration for Proper Operation) on page 718.
600
792
Symbol
Type
I/O*
F31
K6
RXSPAA
3.3 V
O
Receive Selected Cell/Packet Available, Interface A.
Name/Description
F32
J5
RXSPAB
O
Receive Selected Cell/Packet Available, Interface B.
F33
J4
RXSPAC
O
Receive Selected Cell/Packet Available, Interface C.
F34
K5
RXSPAD
O
Receive Selected Cell/Packet Available, Interface D.
G31
K4
TXSPAA
O
Transmit Selected Cell/Packet Available, Interface A.
AK2
AK35
TXSPAB
O
Transmit Selected Cell/Packet Available, Interface B.
AJ5
AK36
TXSPAC
O
Transmit Selected Cell/Packet Available, Interface C.
AJ4
AJ35
TXSPAD
O
Transmit Selected Cell/Packet Available, Interface D.
* IU indicates a 100 kΩ internal pull-up. This makes external pull-up resistors on unused inputs unnecessary.
Note: These active-high signals indicate the FIFO status of the selected channel on the given interface. On the MARS2G5 P-Pro, two different
types of packet available signals are provided, known as polled packet available (PPA) and selected packet available (SPA). PPA is similar to the normal CLAV (cell available) signal in UTOPIA standard documentation, and operates similarly to the PA signals in the
MARS2G5 P-ProLT (TDAT042G5) device. PPA is feedback to the UTOPIA master about whether it can start a transfer at some time in
the near future on a given interface. SPA is similar to PPA, except that it is feedback to the master about the current transfer, and tells it
whether that transfer needs to pause. For the Tx direction, it would need to pause transmission of a long packet when the UTOPIA interface FIFO becomes full. For the Rx direction, it would need to pause transmission of a long packet if the UTOPIA FIFO becomes empty
(or nearly so). So while the function of these two signals is similar, the semantics are quite different. PPA tells a master whether it can
start a transfer on a given interface. SPA tells a master whether it has to end it. The distinction between PPA and SPA is only needed in
cases where the length of the transfer is not known a priori. For ATM cells, the length is fixed (53 bytes), so when a transfer is started, it
is known whether there is enough data to complete the transfer, and the SPA signal is not required. On the other hand, for packets of
arbitrary length, there is no guarantee, and the SPA signal can be used to differentiate between the end of a packet and the FIFO temporarily running dry/full. Although the SPA signals need not be used when transferring ATM cells, the SPA can indicate to the master when
back-to-back transfers are possible, which maximizes the bandwidth efficiency of the interface.
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 10. Pin Descriptions—Microprocessor Interface Signals
600
C7
792
Symbol
C29
RSTN
Type
I/O*
Name/Description
3.3 V
(5 V tolerant)
IU
Reset (Synchronous) (Active-Low). The RSTN signal highto-low transition (given that RSTN is high for at least four
TXCLKP/TXCLKN clock cycles for the edge detector to work
properly) resets the digital auto-trim logic of the OC-48 contraclocking 1x PLL (resets the PLL).
After the high-to-low transition of RSTN, the PLL will then
reset (the auto-trimming function will be done and then normal
locking will be completed, a process which may take up to
100 ms) at the end of which time the PLL will be locked. It is
suggested that RSTN remain low during this time. The PLL
outputs may change over a wide range of frequencies during
the 100 ms. See Figure 9 on page 122.
3.3 V
(5 V tolerant)
IU
E7
E29
ICTN
D7
D29
PMRST
D8
F27
MPU_
MPMODE
3.3 V
(5 V tolerant)
IU
MPU Mode Select. This signal is set high for a synchronous
microprocessor, or low for an asynchronous microprocessor.
C8
C28
MPU_
MPCLK
3.3 V
(5 V tolerant)
IU
MPU Clock. This clock can operate at up to 66 MHz when in
synchronous mode.
B8
E27
MPU_CSN
3.3 V
(5 V tolerant)
IU
Chip Select (Active-Low). This signal must be low during
register access.
B7
E28
MPU_INTN
3.3 V
O
Interrupt (Active-Low). This signal goes low when the device
generates an unmasked interrupt. This signal is open drain.
A12
B12
C12
D12
E12
A11
B11
C11
D11
A10
B10
C10
D10
E10
A9
B9
D23
C23
B23
C24
E24
D24
B24
B25
C25
D25
E25
B26
C26
D26
E26
F26
3-State Control (Active-Low). ICTN has an internal 100 kΩ
pull-up. Assertion of this input causes all 3.3 V IO pins to enter
a 3-state mode.
3.3 V
IU/ 1 Second PM Clock. PM clock can be generated on-chip.
(5 V tolerant) O This signal will have a 50% duty cycle. When the PMRST is
under software control (PM mode), it can be activated longer
or shorter than once per second. The performance-monitoring
registers are updated on the rising edge of this signal.
MPU_DATA15
3.3 V
IU/ Data Bus. This bus is a bidirectional data bus for writing and
MPU_DATA14 (5 V tolerant) O reading software registers.
MPU_DATA13
MPU_DATA12
MPU_DATA11
MPU_DATA10
MPU_DATA9
MPU_DATA8
MPU_DATA7
MPU_DATA6
MPU_DATA5
MPU_DATA4
MPU_DATA3
MPU_DATA2
MPU_DATA1
MPU_DATA0
* IU indicates a 100 kΩ internal pull-up.
Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).
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Data Sheet
August 18, 2004
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 10. Pin Descriptions—Microprocessor Interface Signals (continued)
600
792
Symbol
Type
B16
C16
D16
A15
B15
C15
E15
A14
B14
C14
D14
E14
B13
C13
D13
E13
E20
D20
C20
B20
E21
D21
B21
A22
F22
E22
D22
C22
B22
A23
F23
E23
E9
D27
MPU_ADSN
D9
C27
C9
E8
I/O*
Name/Description
IU
Address Bus. This bus is used to address registers.
3.3 V
(5 V tolerant)
IU
Address Strobe (Active-Low). This signal indicates the
address is valid for MPU access.
MPU_RWN
3.3 V
(5 V tolerant)
IU
Read/Write. This signal is low to indicate a write operation and
is high to indicate a read operation.
B27
MPU_DSN
3.3 V
(5 V tolerant)
IU
Data Strobe (Active-Low). This signal used in the asynchronous mode (MPU_MPMODE = 0) indicates that the data is
valid for MPU writes.
D28
MPU_DTN
3.3 V
O
Data Transfer Acknowledge (Active-Low). This signal
acknowledges the data transfer cycle.
MPU_ADDR15
3.3 V
MPU_ADDR14 (5 V tolerMPU_ADDR13
ant)
MPU_ADDR12
MPU_ADDR11
MPU_ADDR10
MPU_ADDR9
MPU_ADDR8
MPU_ADDR7
MPU_ADDR6
MPU_ADDR5
MPU_ADDR4
MPU_ADDR3
MPU_ADDR2
MPU_ADDR1
MPU_ADDR0
* IU indicates a 100 kΩ internal pull-up.
Table 11. Pin Descriptions—General-Purpose I/O Signals: Interface Signals
600
AG5
AH2
AH3
AH4
792
AG35
AG34
AH37
AH36
Symbol
GPIO3
GPIO2
GPIO1
GPIO0
Type
I/O*
Name/Description
3.3 V
(5 V tolerant)
IU/
General-Purpose I/O. These programmable I/O pins may be used
to monitor or control external circuitry.
O
* IU indicates a 100 kΩ internal pull-up.
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Note: All 3.3 V logic is rated as 5 V TTL tolerant. Logic inputs can be driven from standard TTL levels, and logic
outputs can drive standard TTL inputs.
Table 12. Pin Descriptions—JTAG Interface Signals
600
792
Symbol
Type
I/O*
U
Name/Description
F2
K35
TCLK
3.3 V
(5 V tolerant)
I
JTAG Test Clock. This 10 MHz maximum signal provides timing
for test operations.
F4
K34
TMS
3.3 V
(5 V tolerant)
IU
JTAG Test Mode Select. Controls test operations. TMS is sampled on the rising edge of TCK. TMS has an internal 100 kΩ pullup resister.
G5
K36
TDI
3.3 V
(5 V tolerant)
IU
JTAG Test Data In. Serial 10 Mbits/s maximum test data input signal. TDI is sampled on the rising edge of TCK. TDI has an internal
100 kΩ pull-up resister.
G2
L36
TDO
3.3 V
O
JTAG Test Data Out. This serial 10 Mbits/s maximum data output
signal is updated on the falling edge of TCK. The TDO output is
3-stated except when scanning out test data.
G3
L35
TRSTN
3.3 V
(5 V tolerant)
I
JTAG Test Reset (Active-Low). This signal provides an asynchronous reset for the test access port (TAP). TRSTN has an internal
200 kΩ pull-up resistor.
* IU indicates a 100 kΩ internal pull-up.
Note: JTAG interface signals are used for test operations that are carried out using the IEEE P1149.1 test access port (TAP).
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Data Sheet
August 18, 2004
Pin Descriptions (continued)
Table 13. Pin Descriptions—Power Signals
600
792
B6
C30
Symbol Type* I/O
Name/Description
PLL_
VDDD2
P
— OC-48 Contraclocking 1x PLL
1.6 V Digital Power Supply.
E6, E7, E33, E34,F5, F6,
A1, A2, A17, A18, A34,
F7, F15, F16, F24, F25,
A35, B1, B2, B34, B35,
F33, F34, F35, G5, G6,
C3, C33, E11, E25, K5, L5,
G34, R6, R34, T6, T34,
L31, M5, P4, R1, U35, V1,
AD6, AD34, AE6, AE34,
V2, V35, W1, AB5, AD5,
AN6, AN34, AN35, AP5,
AE5, AE31, AF5, AL11,
AP6, AP7, AP15, AP16,
AL18, AL25, AN3, AN33,
AP1, AP2, AP34, AP35, AP24, AP25, AP33, AP34,
AP35, AR6, AR33, AR34
AR1, AR2, AR18, AR19,
AR34, AR35
VDDD
P
— 3.3 V Digital Power Supply.
A5, A6, A30, A31, D4,
D27, D32, E1, E5, E16,
E20, E31, E35, F1, F35,
T5, T31, Y5, Y31, AK1,
AK35, AL1, AL5, AL16,
AL20, AL31, AL35, AM4,
AM32, AR5, AR6, AR30,
AR31
A1, A2, A3, A6, A7, A11,
A12, A19, A20, A21, A28,
A29, A30, A31, A32, A33,
A37, A38, A39, B1, B2, B3,
B6, B28, B29, B30, B31,
B32, B33, B37, B38, B39,
C1, C2, C3, C6, C37, C38,
C39, D6, D10, G1, G2,
G38, G39, H1, H2, H38,
H39, J1, J2, J39, K1, K2,
K38, K39, L1, L38, L39,
M1, M39, W1, W39, Y1,
Y39, AA38, AA39, AG38,
AG39, AH1, AH38, AH39,
AJ1, AJ38, AJ39, AK1,
AK2, AK38, AK39, AL1,
AL2, AL38, AL39, AM1,
AM2, AM38, AM39, AN1,
AN2, AN38, AN39, AU1,
AU2, AU3, AU37, AU38,
AU39, AV1, AV2, AV3,
AV7, AV8, AV9, AV10,
AV30, AV31, AV32, AV33,
AV37, AV38, AV39, AW1,
AW2,AW3, AW7, AW8,
AW9, AW10, AW11,AW12,
AW13, AW19, AW20,
AW21, AW29, AW30,
AW31, AW32, AW33,
AW37, AW38, AW39
VDDD2
P
— 1.6 V Digital Power Supply.
E3
H34
PLL_
VDDD2
P
— OC-48 Contraclocking 1x PLL
1.6 V Digital Power Supply.
C6
D30
PLL_
GND
P
— OC-48 Contraclocking 1x PLL
Ground.
* P = power.
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pin Descriptions (continued)
Table 13. Pin Descriptions—Power Signals (continued)
600
792
Symbol Type* I/O
Name/Description
A3, A4, A7, A8, A13, A16,
A20, A23, A27, A28, A29,
A32, A33, B3, B4, B32,
B33, C1, C2, C4, C32,
C34, C35, D1, D2, D3,
D33, D34, D35, F3, G1,
G35, H1, H3, H5, H35, N1,
N35, T1, T35, V3, V31, Y1,
Y4, Y35, AA5, AC1, AC35,
AH1, AH35, AJ1, AJ35,
AM1, AM2, AM3, AM33,
AM34, AM35, AN1, AN2,
AN4, AN6, AN32, AN34,
AN35, AP3, AP4, AP32,
AP33, AR3, AR4, AR7,
AR8, AR13, AR16, AR20,
AR23, AR28, AR29, AR32,
AR33
A4, A5, A9, A15, A16, A24,
A25, A26, A27, A34, A35,
A36, B4, B5, B34, B35,
B36, C4, C5, C10, C31,
C32, C33, C34, C35, C36,
D1, D2, D3, D4, D5, D31,
D32, D33, D34, D35, D36,
D37, D38, D39, E1, E2,
E3, E4, E5, E32, E35, E36,
E37, E38, E39, F1, F2, F3,
F4, F11, F12, F19, F20,
F21, F28, F29, F36, F37,
F38, F39, G3, G4, G36,
G37, H3, H4, H35, H37,
J3, J34, J36, J37, J38, L6,
L34, M6, M34, R1, R39,
T1, T39, W6, W34, W35,
Y6, Y34, AA6, AA34, AD1,
AD39, AE1, AE39, AH6,
AH34, AJ6, AJ34, AK37,
AL37, AM3, AM36, AM37,
AN3, AN4, AN36, AN37,
AP1, AP2, AP3, AP4,
AP11, AP12, AP19, AP20,
AP21, AP28, AP29, AP36,
AP37, AP38, AP39, AR1,
AR2, AR3, AR4, AR5,
AR35, AR36, AR37, AR38,
AR39, AT1, AT2, AT3, AT4,
AT5, AT6, AT7, AT32,
AT33, AT34, AT35, AT36,
AT37, AT38, AT39, AU4,
AU5, AU6, AU7, AU8,
AU31, AU32, AU33, AU34,
AU35, AU36, AV4, AV5,
AV6, AV34, AV35, AV36,
AW4, AW5, AW6, AW15,
AW16, AW24, AW25,
AW34, AW35, AW36
GNDD
P
— Digital Ground.
E4
G35
PLL_
GNDD
P
— OC-48 Contraclocking 1x PLL
Digital Ground.
* P = power.
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Data Sheet
August 18, 2004
Pin Descriptions (continued)
Table 14. PLL Test Outputs
600
792
Symbol
Type
I/O
Name/Description
C5
F31
PLLREF
—
O
Test output for PLL (normally no connect).
D5
F32
PLLFB
—
O
Test output for PLL (normally no connect).
Table 15. Pin Descriptions—No-Connect Pins
600
792
Symbol
Type
I/O
Name/Description
B5, D6, D15,
E6, F5, G4
C21, E30, E31, F30,
J35, K37
NC
—
— No Connection. Has internal 100 kΩ pullup resistor. Do not connect to these pins.
B26, B27, B28, B29,
A8, A10, B7, B8,
B31, B24, B25, B22, B10, B11, B13, B15,
A22, A25, C22, C24, C7, C9, C11, C12,
C25, C26, C27, C28, C13, C15, D8, D9,
C29, C30, C31, D21, D11, D13, D15, E8,
D23, D25, D29, D30, E9, E11, E14, E15,
E23, E29, E32, E33
F9, F14, H6, J6
NC
—
— No Connection. Do not connect to these
pins.
A24, A26, B30, D24,
D26, D28, D31, E24,
E27, E28, E30, E34
A13, B9, B12, C8,
D7, E10, E12, E13
F8, F10, F13, H5
NC
—
— No Connection. Do not connect to these
pins.
A19, A21, B17, B18,
B19, B20, B21, B23,
C17, C18, C19, C20,
C21, C23, D17, D18,
D19, D20, D22, E17,
E18, E19, E21, E22,
E26
A14, A17, A18, B14,
B16, B17, B18, B19,
C14, C16, C17, C18,
C19, D12, D14, D16,
D17, D18, D19, E16,
E17, E18, E19, F17,
F18
NC
—
— No Connection. Do not connect to these
pins.
Table 16. Leakage Test Pin
600
792
Symbol
Type
I/O
E2
H36
IDDQMODE
—
I
A
B
Name/Description
Leakage Test Pin. This must be connected to digital
ground via a 1 kΩ resistor.
C
2668(F)
Note: A = 4 TXCLKP/TXCLKN clock cycles, B = 100 ms, and C = PLL in normal-locking mode.
Figure 9. PLL Outputs Lock-In Process
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface
Device Address Space Assignments
This device is equipped with a generic 16-bit microprocessor interface that allows operation with most commercially available microprocessors. A 16-bit address space allows the selection of the registers in each block of the
chip, shown in the following table. The addresses are 16-bit word addresses, not byte addresses. When writing
reserved bits, a value of 0 should be used, unless otherwise specified.
Note: Specified device reset default values are valid only when line interface RXCLK[A—D][P/N] and TXCLK[P/N]
clocks; UTOPIA interface TXCLK[A—D] and RXCLK[A—D] clocks are present, the microprocessor clock
(MPU_MPCLK) does not need to be present.
Table 17. Device Address Space Assignment
Base Address and Page
Block
Block Name
0x0000 (page 164)
Microprocessor Interface.
MPU
0x0800 (page 208)
Transport Overhead Processor.
TOHP
0x1000 (page 258)
Pointer Processor.
PP
0x2000
Reserved.
—
0x3000
Reserved.
—
0x4000 (page 357)
Path Terminator.
PT
0x5000 (page 518)
DS3/E3 Mapper.
DS3
0x5800 (page 613)
Receive Sequencer.
RXS
0x6000 (page 677)
Data Engine.
DE
0x7000 (page 748)
UTOPIA Interface.
UT
Reserved.
—
0x7400
0x8000 (page 415)
0x8968—0xFFFF
Receive Terminator.
Reserved.
RXT
—
Reset Default Value of Registers/Bits
The reset default value is defined as:
1.
2.
3.
4.
The value after RSTN (pin C7, Table 10) is pulled high.
OC-48 optics transponder is attached to the device line interface with valid STS-48 data being transferred.
Valid TXCLKP/N clock.
All UTOPIA clocks supplied.
A reset default value of X represents an undefined value of either a 0 or 1. Generally, status register contents after
a reset are dependent on architecture and system design; therefore, may vary from one design to the next.
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Microprocessor Interface Modes
Input MPU_MPMODE (pin D8) is used to configure the microprocessor interface into one of two possible modes
(synchronous or asynchronous). In synchronous mode, the microprocessor interface can operate at speeds from
1 MHz up to 66 MHz. In asynchronous mode, the internal 78 MHz system clock is used to operate this interface.
This interface is functionally identical to the interface in the MARS2G5 P-ProLT (TDAT042G5) device with one
enhancement made to the synchronous interface mode. In order to enhance reliability, the internal 78 MHz system
clock is used to transfer data between the internal device blocks and the MPU interface. The data transferred is
then resynchronized to the external MPU clock at the microprocessor interface. The net effect will be a slight
uncertainty in the length of an access cycle. Thus, the location of the MPU_DTN (pin E8) signal may not be deterministic. A compatibility mode with MARS2G5 P-ProLT has been preserved, which utilizes the MPU_MPCLK (pin
C8) for internal data transfer, but this mode is not recommended.
Table 18. MPU Modes
MPU_
MPMODE
Mode
Microprocessor Interface Signals
0
Async
MPU_CSN, MPU_INTN, MPU_DATA[15:0], MPU_ADDR[15:0], MPU_ADSN, MPU_RWN,
MPU_DSN, MPU_DTN
1
Sync
MPU_MPCLK, MPU_CSN, MPU_INTN, MPU_DATA[15:0], MPU_ADDR[15:0],
MPU_ADSN, MPU_RWN, MPU_DSN, MPU_DTN
The host interface is designed to connect directly to a commonly used asynchronous or synchronous host buses.
The interface to this block includes a separate clock, MPU_MPCLK, which is used in the synchronous interface
mode. The interface is only a slave on the host bus. There is no posting of writes in the host interface all registers
are directly accessible. Following are the timing diagrams for reads and writes in both synchronous and asynchronous modes.
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Microprocessor Interface Timing
Synchronous Mode
The synchronous microprocessor interface mode is selected when MPU_MPMODE (pin D8) = 1. Interface timing
for the synchronous mode write cycle is given in Figure 10 and in Table 19 (pages 125—126), and for the read
cycle in Figure 11 and in Table 20 (pages 127—128).
T0
T1
T2
Tn – 2
Tn – 1
Tn
MPU_MPCLK
(66 MHz MAX)
t1
t2
MPU_ADDR[15:0]
t3
MPU_CSN
t4
t5
MPU_ADSN
t2
t1
MPU_RWN
t2
t1
MPU_DATA[15:0]
(INPUT)
t6
t7
HIGH
IMPEDANCE
MPU_DTN
5-8718(F)r.5
Figure 10. Microprocessor Interface Synchronous Write Cycle (MPU_MPMODE (Pin D8) = 1)
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Microprocessor Interface Timing (continued)
Table 19. Microprocessor Interface Synchronous Write Cycle Specifications
(See Figure 10 on page 125 for the timing diagram.)
Symbol
126
Parameter
Setup
(ns)
Hold
(ns)
Delay
(ns)
(Min)
(Min)
(Max)
t1
MPU_ADDR, MPU_RWN, MPU_DATA (write) Valid to MPU_MPCLK
3
—
—
t2
MPU_MPCLK to ADDR, MPU_RWN, MPU_DATA (write) Invalid
—
5
—
t3
MPU_CSN Valid to MPU_MPCLK
3.5
—
—
t4
MPU_ADSN Valid to MPU_MPCLK
5.5
—
—
t5
MPU_MPCLK to MPU_ADSN Invalid
—
5
—
t6
MPU_MPCLK to MPU_DTN Valid
—
—
8
t7
MPU_MPCLK to MPU_DTN Invalid
—
1
—
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Microprocessor Interface Timing (continued)
T0
T1
T2
Tn – 3
Tn – 2
Tn – 1
Tn
MPU_MPCLK
(66 MHz MAX)
t8
t9
MPU_ADDR[15:0]
t10
MPU_CSN
t11
t12
MPU_ADSN
MPU_RWN
MPU_DTN
HIGH
IMPEDANCE
t13
t15
t14
t16
MPU_DATA[15:0]
(OUTPUT)
5-8719(F)r.4
Figure 11. Microprocessor Interface Synchronous Read Cycle (MPU_MPMODE (Pin D8) = 1)
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Microprocessor Interface Timing (continued)
Table 20. Microprocessor Interface Synchronous Read Cycle Specifications
(See Figure 11 on page 127 for the timing diagram.)
Symbol
128
Parameter
Setup
(ns)
Hold
(ns)
Delay
(ns)
(Min)
(Min)
(Max)
t8
MPU_ADDR Valid to MPU_MPCLK
3
—
—
t9
MPU_MPCLK to MPU_ADDR Invalid
—
5
—
t10
MPU_CSN Valid to MPU_MPCLK
3.5
—
—
t11
MPU_ADSN Valid to MPU_MPCLK
5.5
—
—
t12
MPU_MPCLK to MPU_ADSN Invalid
—
5
—
t13
MPU_MPCLK to MPU_DTN Valid
—
—
8
t14
MPU_MPCLK to MPU_DTN Invalid
—
1
—
t15
MPU_MPCLK to MPU_DATA Valid
—
—
24
t16
MPU_MPCLK to MPU_DATA 3-state
—
1
—
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Microprocessor Interface Timing (continued)
Asynchronous Mode
The asynchronous microprocessor interface mode is selected when MPU_MPMODE (pin D8) = 0. Interface timing
for the asynchronous mode write cycle is given in Figure 12 and in Table 21 on page 130, and for the read cycle in
Figure 13 and in Table 22 (see pages 131—132).
MPU_ADDR[15:0]
t17
t18
MPU_CSN
t19
t20
MPU_ADSN
t21
t22
t23
t24
MPU_DSN
MPU_RWN
t26
t25
MPU_DATA[15:0]
(INPUT)
t29
t27
t28
t30
MPU_DTN
5-8720(F)r.1
Figure 12. Microprocessor Interface Asynchronous Write Cycle Description (MPU_MPMODE (Pin D8) = 0)
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Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Microprocessor Interface Timing (continued)
Table 21. Microprocessor Interface Asynchronous Write Cycle Specifications
(See Figure 12 on page 129 for the timing diagram.)
Symbol
Parameter
Min Interval Max Interval
(ns)
(ns)
t17
MPU_CSN Fall to MPU_DSN Fall
0
—
t18
MPU_ADDR Invalid to MPU_CSN Rise
0
—
t19
MPU_ADDR Valid to MPU_ADSN Fall
0
—
t20
MPU_ADSN Rise to MPU_ADDR Invalid
5
—
t21
MPU_ADDR Valid to MPU_DSN Fall
0
—
t22
MPU_DSN Rise to MPU_ADDR Invalid
0
—
t23
MPU_RWN Fall to MPU_DSN Fall
0
—
t24
MPU_DSN Rise to MPU_RWN Rise
0
—
t25
MPU_DATA Valid to MPU_DSN Fall
0
—
t26
MPU_DSN Rise to MPU_DATA Invalid
0
—
t27
MPU_CSN Fall to MPU_DTN High
0
—
t28
MPU_DSN Fall to MPU_DTN Fall
0
—*
t29
MPU_ADSN Rise to MPU_DTN Rise
0
37.5
t30
MPU_CSN Rise to MPU_DTN 3-state
0
—
* Use the following formula to obtain the maximum value of t28, which is dependent on the UTOPIA clock
frequency (TXCLK[D—A], RXCLK[D—A]), which can vary from dc to 104 MHz.
t28 maximum = 145 ns + 4(1/UTOPIA clock frequency).
For example, at a UTOPIA clock frequency of 52 MHz the maximum value of t28 is:
t28 (@ 52 MHz) = 145 ns + 4(1/52,000,000) = 232 ns
and t28 (@ 104 MHz) = 193 ns.
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Microprocessor Interface Timing (continued)
MPU_ADDR
t32
t31
MPU_CSN
t34
t33
MPU_ADSN
t36
t35
MPU_DSN
MPU_RWN
t37
t40
t38
t39
MPU_DTN
t41
t42
MPU_DATA
5-8721(F)r.1
Figure 13. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0)
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Microprocessor Interface Timing (continued)
Table 22. Microprocessor Interface Asynchronous Read Cycle Specifications
(See Figure 13 on page 131 for the timing diagram.)
Symbol
Parameter
Min Interval Max Interval
(ns)
(ns)
t31
MPU_CSN Fall to MPU_DSN Fall
0
—
t32
MPU_ADDR Invalid to MPU_CSN Rise
0
—
t33
MPU_ADDR Valid to MPU_ADSN Fall
0
—
t34
MPU_ADSN Rise to MPU_ADDR Invalid
0
—
t35
MPU_ADDR Valid to MPU_DSN Fall
0
—
t36
MPU_DSN Rise to MPU_ADDR Invalid
0
—
t37
MPU_CSN Fall to MPU_DTN High
0
—
t38
MPU_DSN Fall to MPU_DTN Fall
0
—*
t39
MPU_ADSN Rise to MPU_DTN Rise
—
37.5
t40
MPU_CSN Rise to MPU_DTN 3-state
0
—
t41
MPU_DTN Valid to MPU_DATA Valid
—
12
t42
MPU_ADSN Rise to MPU_DATA 3-state
0
—
* Use the following formula to obtain the maximum value of t38, which is dependent on the UTOPIA clock
frequency (TXCLK[D—A], RXCLK[D—A]), which can vary from dc to 104 MHz.
t38 maximum = 145 ns + 4(1/UTOPIA clock frequency).
For example, at a UTOPIA clock frequency of 52 MHz the maximum value of t38 is:
t38 (@ 52 MHz) = 145 ns + 4(1/52,000,000) = 232 ns
and t38 (@ 104 MHz) = 193 ns.
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Necessary Register Provisioning Sequence and Clocks
When configuring the device internal clock rates, core registers must be written (programmed) prior to provisioning
any other registers because writing to certain core registers resets the remainder of the device. Specific clocks
must be present to read/write registers prior to provisioning the device.
One of the following clocks must be present prior to provisioning to enable register access:
■
TXCLKP (pin U4) and TXCLKN (pin U5).
■
MPU clock (microprocessor interface synchronous mode only).
Provisioning must be implemented in the following sequence:
■
Core register 0x0021 (MPU_LI_MODER (Table 41)).
■
Remainder of the core registers must then be provisioned (order does not matter).
It is recommended that the remainder of the device be provisioned in the following order (allowing the path terminator (PT) synchronous payload envelop (SPE) FIFO to operate properly, i.e., FIFO overflow on setup is prevented):
■
TOHP, PP, CDA maps within the DE, remainder of the DE, DS3 mapper, SPE mapper/pointer interpreter (PT),
RXS block (order does not matter).
■
UT block to turn on the data source to the master and slave.
If after provisioning the device as described above there is a lockup in the SPE transmit FIFO, software reset the
SPE FIFO by writing a 1 to the appropriate channel through the PT_TX_SOFTRST (Table 266) register and then
writing a 0 to release the reset.
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Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers
Several registers in MARS2G5 P-Pro require that certain clocks be present in order to be read or written by the
microprocessor.
Internal clocks SYSCLK, PAY_RXCLK, PAY_SYSCLK, RX_CLK1, RX_CLK2, RX_CLK3, and RX_CLK4 are used
as domain names only. How to ensure the activation of each clock domain is described below the reference to that
domain.
All RXT registers are in the PAY_RXCLK domain.
>
MPU_PAY_RXCLKPDN_SYSCLKPDN reg 0x001b bit 4 must be 0 and
>
if MPU_LI_MODE reg 0x0021 bit 6 is 0 (not POF)
>
or MPU_LPBKCTRL reg 0x0012 bit 13 is 1 (SONET terminal loopback)
>
A clock must be present on TXCLKP and TXCLKN
>
else if MPU_LI_MODE reg 0x0021 bit 4 is 1 (OC48)
>
A clock is present on RXCLKP_RXDAP and RXCLKN_RXDAN
>
else
>
MPU_LI_MODE reg 0x0021 bit 11 is 1
>
A clock is present on RXD14P_RXCLKAP and RXD14N_RXCLKAN
Other PT registers are in the PAY_SYSCLK domain.
■
MPU_PAY_TXCLKPDN_SYSCLKPDN reg 0x001b bit 5 must be 0.
■
A clock must be present on TXCLKP and TXCLKN.
Some DS3 registers are in the PAY_RXCLK domain.
■
PAY_RXCLK is as specified for RXT.
■
0x5081 and 0x5094 registers require PAY_RXCLK to complete the MPU bus cycle. Otherwise, the MPU must
drop MPU_CSN (Chip Select) before proceeding.
134
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
The following UTOPIA registers require clocks as specified. (PAY_SYSCLK and PAY_RXCLK are as specified for
PT and RXT. TxClkA, TxClkB, TxClkC, TxClkD, RxClkA, RxClkB, RxClkC, and RxClkD are pins.)
■
0x7011 TxClkA
■
0x7015 TxClkB
■
0x7019 TxClkC
■
0x701D TxClkD
■
0x7030 TxClkA
■
0x7038 TxClkA
■
0x7040 TxClkA
■
0x7048 TxClkA
■
0x7050 TxClkB
■
0x7058 TxClkB
■
0x7060 TxClkB
■
0x7068 TxClkB
■
0x7070 TxClkC
■
0x7078 TxClkC
■
0x7080 TxClkC
■
0x7088 TxClkC
■
0x7090 TxClkD
■
0x7098 TxClkD
■
0x70A0 TxClkD
■
0x70A8 TxClkD
If these UTOPIA registers do not have the required clocks, the MPU bus cycle will not complete. In this case, the
MPU must drop MPU_CSN (chip select) before proceeding.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
PP registers fall in five domains:
1. For PP registers in the SYSCLK domain.
MPU_SON_PP_SYSCLKPDN reg 0x001b bit 2 must be 0.
■
■
A clock must be present on TXCLKP and TXCLKN.
2. For PP registers in RX_CLK1 domain (A).
>
if MPU_LPBKCTRL reg 0x0012 bit 13 is 1 (SONET terminal loopback)
>
>
A clock must be present on TXCLKP and TXCLKN
else if MPU_LI_MODE reg 0x0021 bit4 is 1 (OC48)
>
>
A clock is present on RXCLKP_RXDAP and RXCLKN_RXDAN
else
>
MPU_LI_MODE reg 0x0021 bit 11 is 1
>
A clock is present on RXD14P_RXCLKAP and RXD14N_RXCLKAN
3. For PP registers in RX_CLK2 domain (B).
>
if MPU_LPBKCTRL reg 0x0012 bit 13 is 1 (SONET terminal loopback)
>
>
A clock must be present on TXCLKP and TXCLKN
else if MPU_LI_MODE reg 0x0021 bit 4 is 1 (OC48)
>
>
A clock is present on RXCLKP_RXDAP and RXCLKN_RXDAN
else
>
MPU_LI_MODE reg 0x0021 bit 10 is 1
>
A clock is present on RXD13P_RXCLKBP and RXD13N_RXCLKBN
136
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
4. For PP registers in RX_CLK3 domain (C).
>
if MPU_LPBKCTRL reg 0x0012 bit 13 is 1 (SONET terminal loopback)
>
>
A clock must be present on TXCLKP and TXCLKN
else if MPU_LI_MODE reg 0x0021 bit 4 is 1 (OC48)
>
>
A clock is present on RXCLKP_RXDAP and RXCLKN_RXDAN
else
>
MPU_LI_MODE reg 0x0021 bit 9 is 1
>
A clock is present on RXD11P_RXCLKCP and RXD11N_RXCLKCN
5. For PP registers in RX_CLK3 domain (D)
>
if MPU_LPBKCTRL reg 0x0012 bit 13 is 1 (SONET terminal loopback)
>
>
A clock must be present on TXCLKP and TXCLKN
else if MPU_LI_MODE reg 0x0021 bit 4 is 1 (OC48)
>
>
A clock is present on RXCLKP_RXDAP and RXCLKN_RXDAN
else
>
MPU_LI_MODE reg 0x0021 bit 8 is 1
>
A clock is present on RXD9P_RXCLKDP and RXD9N_RXCLKDN
Agere Systems Inc.
137
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
If PP registers in an unclocked domain are written, they will not be written but the MPU bus cycle will complete. If
PP registers in an unclocked domain are read, garbage will be read and the MPU bus cycle will complete.
The following PP registers are in the SYSCLK domain:
■
0x1300: 32 // PATH_TRACE_BUF_1f
■
0x1301: 31 // PATH_TRACE_BUF_1e
■
0x1302: 30 // PATH_TRACE_BUF_1d
■
0x1303: 29 // PATH_TRACE_BUF_1c
■
0x1304: 28 // PATH_TRACE_BUF_1b
■
0x1305: 27 // PATH_TRACE_BUF_1a
■
0x1306: 26 // PATH_TRACE_BUF_19
■
0x1307: 25 // PATH_TRACE_BUF_18
■
0x1308: 24 // PATH_TRACE_BUF_17
■
0x1309: 23 // PATH_TRACE_BUF_16
■
0x130A: 22 // PATH_TRACE_BUF_15
■
0x130B: 21 // PATH_TRACE_BUF_14
■
0x130C: 20 // PATH_TRACE_BUF_13
■
0x130D: 19 // PATH_TRACE_BUF_12
■
0x130E: 18 // PATH_TRACE_BUF_11
■
0x130F: 17 // PATH_TRACE_BUF_10
■
0x1310: 16 // PATH_TRACE_BUF_f
■
0x1311: 15 // PATH_TRACE_BUF_e
■
0x1312: 14 // PATH_TRACE_BUF_d
■
0x1313: 13 // PATH_TRACE_BUF_c
■
0x1314: 12 // PATH_TRACE_BUF_b
■
0x1315: 11 // PATH_TRACE_BUF_a
■
0x1316: 10 // PATH_TRACE_BUF_9
■
0x1317: 9 // PATH_TRACE_BUF_8
■
0x1318: 8 // PATH_TRACE_BUF_7
■
0x1319: 7 // PATH_TRACE_BUF_6
■
0x131A: 6 // PATH_TRACE_BUF_5
■
0x131B: 5 // PATH_TRACE_BUF_4
■
0x131C: 4 // PATH_TRACE_BUF_3
■
0x131D: 3 // PATH_TRACE_BUF_2
■
0x131E: 2 // PATH_TRACE_BUF_1
■
0x131F: 1 // PATH_TRACE_BUF_0
■
0x1333: 0 // J1_BUFFER_ACCESS_BEGIN
138
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
>
Dpathtrace_regsel[32:0] = 33'h0;
■
0x1000: 102 // PP_ID
■
0x1001: 101 // CORW_SETTING
■
0x1010: 100 // GLOBAL_ALARM
■
0x1210: 99 // GLOBAL_ALARM_IMR
■
0x100F: 98 // GLOBAL_ALARM2
■
0x120F: 97 // GLOBAL_ALARM2_IMR
■
0x1021: 96 // MAIN_ELASTIC_STORE_OVERRUN
■
0x1211: 95 // MAIN_ELASTIC_STORE_OVERRUN_IMR
■
0x1031: 94 // MAIN_SF_P
■
0x1221: 93 // MAIN_SF_P_IMR
■
0x1041: 92 // MAIN_RDI_P
■
0x1231: 91 // MAIN_RDI_P_IMR
■
0x1111: 90 // MAIN_RDI_DELTA_P
■
0x1291: 89 // MAIN_RDI_DELTA_P_IMR
■
0x1051: 88 // MAIN_PLM_P
■
0x1241: 87 // MAIN_PLM_P_IMR
■
0x1121: 86 // MAIN_PLM_DELTA_P
■
0x12A1: 85 // MAIN_PLM_DELTA_P_IMR
■
0x1061: 84 // MAIN_UNEQ_P
■
0x1251: 83 // MAIN_UNEQ_P_IMR
■
0x1131: 82 // MAIN_UNEQ_DELTA_P
■
0x12B1: 81 // MAIN_UNEQ_DELTA_P_IMR
■
0x1071: 80 // MAIN_AIS_P
■
0x1261: 79 // MAIN_AIS_P_IMR
■
0x1141: 78 // MAIN_AIS_DELTA_P
■
0x12C1: 77 // MAIN_AIS_DELTA_P_IMR
■
0x1081: 76 // MAIN_LOP_P
■
0x1271: 75 // MAIN_LOP_P_IMR
■
0x1151: 74 // MAIN_LOP_DELTA_P
■
0x12D1: 73 // MAIN_LOP_DELTA_P_IMR
■
0x1181: 72 // MAIN_SS_NEW_VALIDATED
■
0x12F9: 71 // MAIN_SS_NEW_VALIDATED_IMR
■
0x1187: 70 // MAIN_SS_MISMATCH
Agere Systems Inc.
139
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x12E2: 69 // MAIN_SS_MISMATCH_IMR
■
0x117F: 68 // F2_NEW_VALIDATED
■
0x12F7: 67 // F2_NEW_VALIDATED_IMR
■
0x117D: 66 // H4_NEW_VALIDATED
■
0x12F5: 65 // H4_NEW_VALIDATED_IMR
■
0x117B: 64 // Z3_NEW_VALIDATED
■
0x12F3: 63 // Z3_NEW_VALIDATED_IMR
■
0x1179: 62 // Z4_NEW_VALIDATED
■
0x12F1: 61 // Z4_NEW_VALIDATED_IMR
■
0x1177: 60 // Z5_NEW_VALIDATED
■
0x12EF: 59 // Z5_NEW_VALIDATED_IMR
■
0x1101: 58 // MAIN_PDI_P
■
0x1281: 57 // MAIN_PDI_P_IMR
■
0x1171: 56 // MAIN_PDI_DELTA_P
■
0x12E9: 55 // MAIN_PDI_DELTA_P_IMR
■
0x1091: 54 // CONC_MISMATCH
■
0x1277: 53 // CONC_MISMATCH_MASK
■
0x10A1: 52 // CONC_UNSUPPORT
■
0x1279: 51 // CONC_UNSUPPORT_MASK
■
0x1400: 50 // SET_SF_WINDOW_SIZE_SEL[0:7]
■
0x1401: 49 // CLEAR_SF_WINDOW_SIZE_SEL[0:7]
■
0x1410—0x1417 // TH_DETECT_[0:7]
■
0x1418—0x141F // TH_CLEAR_[0:7]
■
0x1420: 32 // SF_WINDOW_SIZE0
■
0x1430: 31 // SF_WINDOW_SIZE1
■
0x1440: 30 // SF_WINDOW_SIZE2
■
0x1450: 29 // SF_WINDOW_SIZE3
■
0x1590: 28 // INC_DEC_SEL_1
■
0x1591: 27 // INC_DEC_SEL_2
■
0x1592: 26 // INC_DEC_SEL_3
■
0x1593: 25 // INC_DEC_SEL_4
■
0x162C: 24 // ES_INC_MIN, // ES_DEC_MAX
■
0x162D: 23 // ES_OVR_MIN, // ES_OVR_MAX
■
0x1330: 22 // J1_CHANNEL_SEL
140
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x1331: 21 // J1_BUFFER_MESSAGE_TYPE
■
0x1332: 20 // J1_BUFFER_ACCESS_TYPE
■
0x1338: 19 // J1_MESSAGE_MODE_STREAM_SEL
■
0x1339: 18 // J1_MESSAGE_TYPE_STREAM_SEL
■
0x133C: 17 // J1_ACCUM_CHANNEL_SEL_1
■
0x133D: 16 // J1_ACCUM_CHANNEL_SEL_2
■
0x133E: 15 // J1_ACCUM_CHANNEL_SEL_3
■
0x133F: 14 // J1_ACCUM_CHANNEL_SEL_4
■
0x1160: 13 // J1_ACCESS_COMPLETE
■
0x12E0: 12 // J1_ACCESS_COMPLETE_IMR
■
0x1C1: 11 // J1_NEW_VALIDATED
■
0x127B: 10 // J1_NEW_VALIDATED_IMR
■
0x10D1: 9 // J1_MISMATCH
■
0x127D: 8 // J1_MISMATCH_IMR
■
0x1780: 7 // GLOBAL_PM
■
0x1781: 6 // ONE_BIT_RDI_P_PM_STREAM
■
0x1791: 5 // ERDI_PAYLOAD_P_PM_STREAM
■
0x17A1: 4 // ERDI_CONNECT_P_PM_STREAM
■
0x17B1: 3 // ERDI_SERVER_P_PM_STREAM
■
0x17C1: 2 // UNEQ_P_PM_STREAM
■
0x17D1: 1 // AIS_P_PM_STREAM
■
0x17E1: 0 // LOP_P_PM_STREAM
>
Dsys_regsel[102:0] = 103'h0;
Agere Systems Inc.
141
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
The following PP registers are in RX_CLK1 domain:
■
0x1022: 148 // ELASTIC_STORE_OVERRUN_1
■
0x1212: 147 // ELASTIC_STORE_OVERRUN_MASK_1
■
0x1032: 146 // SF_P_1
■
0x1222: 145 // SF_P_MASK_1
■
0x1042: 144 // RDI_P_1
■
0x1232: 143 // RDI_P_MASK_1
■
0x1112: 142 // RDI_DELTA_P_1
■
0x1292: 141 // RDI_DELTA_P_MASK_1
■
0x1382: 140 // RDI_PERSIST_P_1
■
0x13C2: 139 // RDI_DELTA_STATE_P_1
■
0x1052: 138 // PLM_P_1
■
0x1242: 137 // PLM_P_MASK_1
■
0x1122: 136 // PLM_DELTA_P_1
■
0x12A2: 135 // PLM_DELTA_P_MASK_1
■
0x138A: 134 // PLM_PERSIST_P_1
■
0x13CA: 133 // PLM_DELTA_STATE_P_1
■
0x1062: 132 // UNEQ_P_1
■
0x1252: 131 // UNEQ_P_MASK_1
■
0x1132: 130 // UNEQ_DELTA_P_1
■
0x12B2: 129 // UNEQ_DELTA_P_MASK_1
■
0x1392: 128 // UNEQ_PERSIST_P_1
■
0x13D2: 127 // UNEQ_DELTA_STATE_P_1
■
0x1072: 126 // AIS_P_1
■
0x1262: 125 // AIS_P_MASK_1
■
0x1142: 124 // AIS_DELTA_P_1
■
0x12C2: 123 // AIS_DELTA_P_MASK_1
■
0x139A: 122 // AIS_PERSIST_P_1
■
0x13DA: 121 // AIS_DELTA_STATE_P_1 PDI_DELTA_STATE_P_1
■
0x1082: 120 // LOP_P_1
■
0x1272: 119 // LOP_P_MASK_1
■
0x1152: 118 // LOP_DELTA_P_1
■
0x12D2: 117 // LOP_DELTA_P_MASK_1
■
0x13A2: 116 // LOP_PERSIST_P_1
142
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x13E2: 115 // LOP_DELTA_STATE_P_1
■
0x1102: 114 // PDI_P_1
■
0x1282: 113 // PDI_P_MASK_1 SS_MISMATCH_MASK_1
■
0x1172: 112 // PDI_DELTA_P_1
■
0x12EA: 111 // PDI_DELTA_P_MASK_1
■
0x13AA: 110 // PDI_PERSIST_P_1
■
0x1182: 109 // SS_NEW_VLD_1
■
0x12FA: 108 // SS_NEW_VLD_MASK_1
■
0x1188: 107 // SS_MISMATCH_1
■
0x1502: 106 // EXP_CONC_1
■
0x1507: 105 // CONC_EN_1
■
0x1512: 104 // REC_CONC_1
■
0x1542: 103 // PATH_AIS_INS_1
■
0x1547: 102 // UNEQ_AIS_INS_1
■
0x154C: 101 // PLM_AIS_INS_1
■
0x1551: 100 // TIM_AIS_INS_1
■
0x1582: 99 // SS_INSERT_CONTROL_1
■
0x1587: 98 // E1_F1_INSERT_CONTROL_1
■
0x158C: 97 // E2_INSERT_CONTROL_1
■
0x15A2: 96 // PDI_VALIDATE_ENABLE_1
■
0x1594: 95 // TIM_P_INSERT_CONTROL_1
■
0x1341: 94 // REC_F2_1 REC_H4_1
■
0x1342: 93 // REC_Z3_1 REC_Z4_1
■
0x1343: 92 // REC_Z5_1
■
0x1344: 91 // F2_VLDP_1 H4Z3Z4_VLDP_1 Z5_VLDP_1 CH_SEL_1
■
0x1351: 90 // REC_SS_1_TSLOT[1:6]
■
0x1352: 89 // REC_SS_1_TSLOT[7:12]
■
0x1600—0x1605 // EXP_C2_STS_[1:12]
■
0x1618: 82 // COUNT_BB_ERRORS_SEL_1
■
0x1580: 81 // SONET_SDH_RULES_1
■
0x1620: 80 // SS_BITS_SETTING_[1:6]
■
0x1621: 79 // SS_BITS_SETTING_[7:12]
■
0x1650—0x1655 //E1_F1_INSERT_BYTE_[1:12]
■
0x1668: 72 // E2_INSERT_BYTE_1
Agere Systems Inc.
143
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x1682: 71 // SD_INSERT_1
■
0x1690: 70 // SF_THRESH_SEL_STS_1
■
0x1691: 69 // SF_THRESH_SEL_STS_2
■
0x1692: 68 // SF_THRESH_SEL_STS_3
■
0x1693: 67 // SF_THRESH_SEL_STS_4
■
0x1694: 66 // SF_THRESH_SEL_STS_5
■
0x1695: 65 // SF_THRESH_SEL_STS_6
■
0x1696: 64 // SF_THRESH_SEL_STS_7
■
0x1697: 63 // SF_THRESH_SEL_STS_8
■
0x1698: 62 // SF_THRESH_SEL_STS_9
■
0x1699: 61 // SF_THRESH_SEL_STS_10
■
0x169A: 60 // SF_THRESH_SEL_STS_11
■
0x169B: 59 // SF_THRESH_SEL_STS_12
■
0x1702: 58 // LAST_INT_INC_1
■
0x1712: 57 // LAST_INT_DEC_1
■
0x1742: 56 // LAST_GEN_INC_1
■
0x1752: 55 // LAST_GEN_DEC_1
■
0x1782: 54 // ONE_BIT_RDI_PM_1
■
0x1792: 53 // ERDI_PAYLOAD_PM_1
■
0x17A2: 52 // ERDI_CONNECT_PM_1
■
0x17B2: 51 // ERDI_SERVER_PM_1
■
0x17C2: 50 // UNEQ_P_PM_1
■
0x17D2: 49 // AIS_P_PM_1
■
0x17E2: 48 // LOP_P_PM_1
■
0x1800: 47 // CV_COUNT_STS_1_PM
■
0x1801: 46 // CV_COUNT_STS_2_PM
■
0x1802: 45 // CV_COUNT_STS_3_PM
■
0x1803: 44 // CV_COUNT_STS_4_PM
■
0x1804: 43 // CV_COUNT_STS_5_PM
■
0x1805: 42 // CV_COUNT_STS_6_PM
■
0x1806: 41 // CV_COUNT_STS_7_PM
■
0x1807: 40 // CV_COUNT_STS_8_PM
■
0x1808: 39 // CV_COUNT_STS_9_PM
■
0x1809: 38 // CV_COUNT_STS_10_PM
144
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x180A: 37 // CV_COUNT_STS_11_PM
■
0x180B: 36 // CV_COUNT_STS_12_PM
■
0x1880: 35 // REI_COUNT_STS_1_PM
■
0x1881: 34 // REI_COUNT_STS_2_PM
■
0x1882: 33 // REI_COUNT_STS_3_PM
■
0x1883: 32 // REI_COUNT_STS_4_PM
■
0x1884: 31 // REI_COUNT_STS_5_PM
■
0x1885: 30 // REI_COUNT_STS_6_PM
■
0x1886: 29 // REI_COUNT_STS_7_PM
■
0x1887: 28 // REI_COUNT_STS_8_PM
■
0x1888: 27 // REI_COUNT_STS_9_PM
■
0x1889: 26 // REI_COUNT_STS_10_PM
■
0x188A: 25 // REI_COUNT_STS_11_PM
■
0x188B: 24 // REI_COUNT_STS_12_PM
■
0x1900—0x190B // RECEIVED_RDI_STS_[1:12]
■
0x1930: 11 // REC_C2_STS_1, // REC_C2_STS_2
■
0x1931: 10 // REC_C2_STS_3, // REC_C2_STS_4
■
0x1932: 9 // REC_C2_STS_5, // REC_C2_STS_6
■
0x1933: 8 // REC_C2_STS_7, // REC_C2_STS_8
■
0x1934: 7 // REC_C2_STS_9, // REC_C2_STS_10
■
0x1935: 6 // REC_C2_STS_11, // REC_C2_STS_12
■
0x1960: 5 // REC_PDI_STS_1, // REC_PDI_STS_2
■
0x1961: 4 // REC_PDI_STS_3, // REC_PDI_STS_4
■
0x1962: 3 // REC_PDI_STS_5, // REC_PDI_STS_6
■
0x1963: 2 // REC_PDI_STS_7, // REC_PDI_STS_8
■
0x1964: 1 // REC_PDI_STS_9, // REC_PDI_STS_10
■
0x1965: 0 // REC_PDI_STS_11, // REC_PDI_STS_12
Agere Systems Inc.
145
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
The following PP registers are in RX_CLK2 domain:
■
0x1023: 149 // ELASTIC_STORE_OVERRUN_2
■
0x1213: 148 // ELASTIC_STORE_OVERRUN_MASK_2
■
0x1033: 147 // SF_P_2
■
0x1223: 146 // SF_P_MASK_2
■
0x1043: 145 // RDI_P_2
■
0x1233: 144 // RDI_P_MASK_2
■
0x1113: 143 // RDI_DELTA_P_2
■
0x1293: 142 // RDI_DELTA_P_MASK_2
■
0x1383: 141 // RDI_PERSIST_P_2
■
0x13C3: 140 // RDI_DELTA_STATE_P_2
■
0x1053: 139 // PLM_P_2
■
0x1243: 138 // PLM_P_MASK_2
■
0x1123: 137 // PLM_DELTA_P_2
■
0x12A3: 136 // PLM_DELTA_P_MASK_2
■
0x138B: 135 // PLM_PERSIST_P_2
■
0x13CB: 134 // PLM_DELTA_STATE_P_2
■
0x1063: 133 // UNEQ_P_2
■
0x1253: 132 // UNEQ_P_MASK_2
■
0x1133: 131 // UNEQ_DELTA_P_2
■
0x12B3: 130 // UNEQ_DELTA_P_MASK_2
■
0x1393: 129 // UNEQ_PERSIST_P_2
■
0x13D3: 128 // UNEQ_DELTA_STATE_P_2
■
0x1073: 127 // AIS_P_2
■
0x1263: 126 // AIS_P_MASK_2
■
0x1143: 125 // AIS_DELTA_P_2
■
0x12C3: 124 // AIS_DELTA_P_MASK_2
■
0x139B: 123 // AIS_PERSIST_P_2
■
0x13DB: 122 // AIS_DELTA_STATE_P_2, // PDI_DELTA_STATE_P_2
■
0x1083: 121 // LOP_P_2
■
0x1273: 120 // LOP_P_MASK_2
■
0x1153: 119 // LOP_DELTA_P_2
■
0x12D3: 118 // LOP_DELTA_P_MASK_2
■
0x13A3: 117 // LOP_PERSIST_P_2
146
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x13E3: 116 // LOP_DELTA_STATE_P_2
■
0x1103: 115 // PDI_P_2
■
0x1283: 114 // PDI_P_MASK_2
■
0x1173: 113 // PDI_DELTA_P_2
■
0x12EB: 112 // PDI_DELTA_P_MASK_2
■
0x13AB: 111 // PDI_PERSIST_P_2
■
0x1183: 110 // SS_NEW_VLD_2
■
0x12FB: 109 // SS_NEW_VLD_MASK_2
■
0x1189: 108 // SS_MISMATCH_2
■
0x12E4: 107 // SS_MISMATCH_MASK_2
■
0x1503: 106 // EXP_CONC_2
■
0x1508: 105 // CONC_EN_2
■
0x1513: 104 // REC_CONC_2
■
0x1543: 103 // PATH_AIS_INS_2
■
0x1548: 102 // UNEQ_AIS_INS_2
■
0x154D: 101 // PLM_AIS_INS_2
■
0x1552: 100 // TIM_AIS_INS_2
■
0x1583: 99 // SS_INSERT_CONTROL_2
■
0x1588: 98 // E1_F1_INSERT_CONTROL_2
■
0x158D: 97 // E2_INSERT_CONTROL_2
■
0x15A3: 96 // PDI_VALIDATE_ENABLE_2
■
0x1345: 95 // REC_F2_2, // REC_H4_2
■
0x1346: 94 // REC_Z3_2, // REC_Z4_2
■
0x1347: 93 // REC_Z5_2
■
0x1348: 92 // F2_VLDP_2 H4Z3Z4_VLDP_2 Z5_VLDP_2 CH_SEL_2
■
0x1353: 91 // REC_SS_2_TSLOT[1:6]
■
0x1354: 90 // REC_SS_2_TSLOT[7:12]
■
0x1606—0x160B // EXP_C2_STS_[13:24]
■
0x1619: 83 // COUNT_BB_ERRORS_SEL_2
■
0x1580: 82 // SONET_SDH_RULES_2
■
0x1622: 81 //SS_BITS_SETTING_[13:18]
■
0x1623: 80 //SS_BITS_SETTING_[19:24]
■
0x1656—0x165B // E1_F1_INSERT_BYTE_[13:24]
■
0x1669: 73 // E2_INSERT_BYTE_2
Agere Systems Inc.
147
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x1595: 72 // TIM_P_INSERT_CONTROL_2
■
0x1683: 71 // SD_INSERT_2
■
0x169C: 70 // SF_THRESH_SEL_STS_13
■
0x169D: 69 // SF_THRESH_SEL_STS_14
■
0x169E: 68 // SF_THRESH_SEL_STS_15
■
0x169F: 67 // SF_THRESH_SEL_STS_16
■
0x16A0: 66 // SF_THRESH_SEL_STS_17
■
0x16A1: 65 // SF_THRESH_SEL_STS_18
■
0x16A2: 64 // SF_THRESH_SEL_STS_19
■
0x16A3: 63 // SF_THRESH_SEL_STS_20
■
0x16A4: 62 // SF_THRESH_SEL_STS_21
■
0x16A5: 61 // SF_THRESH_SEL_STS_22
■
0x16A6: 60 // SF_THRESH_SEL_STS_23
■
0x16A7: 59 // SF_THRESH_SEL_STS_24
■
0x1703: 58 // LAST_INT_INC_2
■
0x1713: 57 // LAST_INT_DEC_2
■
0x1743: 56 // LAST_GEN_INC_2
■
0x1753: 55 // LAST_GEN_DEC_2
■
0x1783: 54 // ONE_BIT_RDI_PM_2
■
0x1793: 53 // ERDI_PAYLOAD_PM_2
■
0x17A3: 52 // ERDI_CONNECT_PM_2
■
0x17B3: 51 // ERDI_SERVER_PM_2
■
0x17C3: 50 // UNEQ_P_PM_2
■
0x17D3: 49 // AIS_P_PM_2
■
0x17E3: 48 // LOP_P_PM_2
■
0x180C: 47 // CV_COUNT_STS_13_PM
■
0x180D: 46 // CV_COUNT_STS_14_PM
■
0x180E: 45 // CV_COUNT_STS_15_PM
■
0x180F: 44 // CV_COUNT_STS_16_PM
■
0x1810: 43 // CV_COUNT_STS_17_PM
■
0x1811: 42 // CV_COUNT_STS_18_PM
■
0x1812: 41 // CV_COUNT_STS_19_PM
■
0x1813: 40 // CV_COUNT_STS_20_PM
■
0x1814: 39 // CV_COUNT_STS_21_PM
148
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x1815: 38 // CV_COUNT_STS_22_PM
■
0x1816: 37 // CV_COUNT_STS_23_PM
■
0x1817: 36 // CV_COUNT_STS_24_PM
■
0x188C: 35 // REI_COUNT_STS_13_PM
■
0x188D: 34 // REI_COUNT_STS_14_PM
■
0x188E: 33 // REI_COUNT_STS_15_PM
■
0x188F: 32 // REI_COUNT_STS_16_PM
■
0x1890: 31 // REI_COUNT_STS_17_PM
■
0x1891: 30 // REI_COUNT_STS_18_PM
■
0x1892: 29 // REI_COUNT_STS_19_PM
■
0x1893: 28 // REI_COUNT_STS_20_PM
■
0x1894: 27 // REI_COUNT_STS_21_PM
■
0x1895: 26 // REI_COUNT_STS_22_PM
■
0x1896: 25 // REI_COUNT_STS_23_PM
■
0x1897: 24 // REI_COUNT_STS_24_PM
■
0x190C—0x1917 // RECEIVED_RDI_STS_[13:24]
■
0x1936: 11 // REC_C2_STS_13, // REC_C2_STS_14
■
0x1937: 10 // REC_C2_STS_15, // REC_C2_STS_16
■
0x1938: 9 // REC_C2_STS_17, // REC_C2_STS_18
■
0x1939: 8 // REC_C2_STS_19, // REC_C2_STS_20
■
0x193A: 7 // REC_C2_STS_21, // REC_C2_STS_22
■
0x193B: 6 // REC_C2_STS_23, // REC_C2_STS_24
■
0x1966: 5 // REC_PDI_STS_13, // REC_PDI_STS_14
■
0x1967: 4 // REC_PDI_STS_15, // REC_PDI_STS_16
■
0x1968: 3 // REC_PDI_STS_17, // REC_PDI_STS_18
■
0x1969: 2 // REC_PDI_STS_19, // REC_PDI_STS_20
■
0x196A: 1 // REC_PDI_STS_21, // REC_PDI_STS_22
■
0x196B: 0 // REC_PDI_STS_23, // REC_PDI_STS_24
Agere Systems Inc.
149
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
The following PP registers are in RX_CLK3 domain:
■
0x1024: 151 // ELASTIC_STORE_OVERRUN_3
■
0x1214: 150 // ELASTIC_STORE_OVERRUN_MASK_3
■
0x1034: 149 // SF_P_3
■
0x1224: 148 // SF_P_MASK_3
■
0x1044: 147 // RDI_P_3
■
0x1234: 146 // RDI_P_MASK_3
■
0x1114: 145 // RDI_DELTA_P_3
■
0x1294: 144 // RDI_DELTA_P_MASK_3
■
0x1384: 143 // RDI_PERSIST_P_3
■
0x13C4: 142 // RDI_DELTA_STATE_P_3
■
0x1054: 141 // PLM_P_3
■
0x1244: 140 // PLM_P_MASK_3
■
0x1124: 139 // PLM_DELTA_P_3
■
0x12A4: 138 // PLM_DELTA_P_MASK_3
■
0x138C: 137 // PLM_PERSIST_P_3
■
0x13CC: 136 // PLM_DELTA_STATE_P_3
■
0x1064: 135 // UNEQ_P_3
■
0x1254: 134 // UNEQ_P_MASK_3
■
0x1134: 133 // UNEQ_DELTA_P_3
■
0x12b4: 132 // UNEQ_DELTA_P_MASK_3
■
0x1394: 131 // UNEQ_PERSIST_P_3
■
0x13D4: 130 // UNEQ_DELTA_STATE_P_3
■
0x1074: 129 // AIS_P_3
■
0x1264: 128 // AIS_P_MASK_3
■
0x1144: 127 // AIS_DELTA_P_3
■
0x12C4: 126 // AIS_DELTA_P_MASK_3
■
0x139C: 125 // AIS_PERSIST_P_3
■
0x13DC: 124 // AIS_DELTA_STATE_P_3, // PDI_DELTA_STATE_P_3
■
0x1084: 123 // LOP_P_3
■
0x1274: 122 // LOP_P_MASK_3
■
0x1154: 121 // LOP_DELTA_P_3
■
0x12D4: 120 // LOP_DELTA_P_MASK_3
■
0x13A4: 119 // LOP_PERSIST_P_3
150
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x13E4: 118 // LOP_DELTA_STATE_P_3
■
0x1104: 117 // PDI_P_3
■
0x1284: 116 // PDI_P_MASK_3
■
0x1174: 115 // PDI_DELTA_P_3
■
0x12EC: 114 // PDI_DELTA_P_MASK_3
■
0x13AC: 113 // PDI_PERSIST_P_3
■
0x1184: 112 // SS_NEW_VLD_3
■
0x12FC: 111 // SS_NEW_VLD_MASK_3
■
0x118A: 110 // SS_MISMATCH_3
■
0x12E5: 109 // SS_MISMATCH_MASK_3
■
0x1504: 108 // EXP_CONC_3
■
0x1509: 107 // CONC_EN_3
■
0x1514: 106 // REC_CONC_3
■
0x1544: 105 // PATH_AIS_INS_3
■
0x1549: 104 // UNEQ_AIS_INS_3
■
0x154E: 103 // PLM_AIS_INS_3
■
0x1553: 102 // TIM_AIS_INS_3
■
0x1584: 101 // SS_INSERT_CONTROL_3
■
0x1589: 100 // E1_F1_INSERT_CONTROL_3
■
0x158E: 99 // E2_INSERT_CONTROL_3
■
0x15A4: 98 // PDI_VALIDATE_ENABLE_3
■
0x1349: 97 // REC_F2_3, // REC_H4_3
■
0x134A: 96 // REC_Z3_3, // REC_Z4_3
■
0x134B: 95 // REC_Z5_3
■
0x134C: 94 // F2_VLDP_3 H4Z3Z4_VLDP_3 Z5_VLDP_3 CH_SEL_3
■
0x1355: 93 // REC_SS_3_TSLOT[1:6]
■
0x1356: 92 // REC_SS_3_TSLOT[7:12]
■
0x160C—0x1611 // EXP_C2_STS_[25:36]
■
0x161A: 85 // COUNT_BB_ERRORS_SEL_3
■
0x1580: 84 // SONET_SDH_RULES_3
■
0x1624: 83 // SS_BITS_SETTING_[25:30]
■
0x1625: 82 // SS_BITS_SETTING_[31:36]
■
0x1629: 81 // SS_BITS_MONITOR_MODE
■
0x162A: 80 // SS_BITS_VALIDATE_PERIOD
Agere Systems Inc.
151
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x165C—0x1661 // E1_F1_INSERT_BYTE_[25:36]
■
0x166A: 73 // E2_INSERT_BYTE_3
■
0x1596: 72 // TIM_P_INSERT_CONTROL_3
■
0x1684: 71 // SD_INSERT_3
■
0x16A8: 70 // SF_THRESH_SEL_STS_25
■
0x16A9: 69 // SF_THRESH_SEL_STS_26
■
0x16AA: 68 // SF_THRESH_SEL_STS_27
■
0x16AB: 67 // SF_THRESH_SEL_STS_28
■
0x16AC: 66 // SF_THRESH_SEL_STS_29
■
0x16AD: 65 // SF_THRESH_SEL_STS_30
■
0x16AE: 64 // SF_THRESH_SEL_STS_31
■
0x16AF: 63 // SF_THRESH_SEL_STS_32
■
0x16B0: 62 // SF_THRESH_SEL_STS_33
■
0x16B1: 61 // SF_THRESH_SEL_STS_34
■
0x16B2: 60 // SF_THRESH_SEL_STS_35
■
0x16B3: 59 // SF_THRESH_SEL_STS_36
■
0x1704: 58 // LAST_INT_INC_3
■
0x1714: 57 // LAST_INT_DEC_3
■
0x1744: 56 // LAST_GEN_INC_3
■
0x1754: 55 // LAST_GEN_DEC_3
■
0x1784: 54 // ONE_BIT_RDI_PM_3
■
0x1794: 53 // ERDI_PAYLOAD_PM_3
■
0x17A4: 52 // ERDI_CONNECT_PM_3
■
0x17B4: 51 // ERDI_SERVER_PM_3
■
0x17C4: 50 // UNEQ_P_PM_3
■
0x17D4: 49 // AIS_P_PM_3
■
0x17E4: 48 // LOP_P_PM_3
■
0x1818: 47 // CV_COUNT_STS_25_PM
■
0x1819: 46 // CV_COUNT_STS_26_PM
■
0x181A: 45 // CV_COUNT_STS_27_PM
■
0x181B: 44 // CV_COUNT_STS_28_PM
■
0x181C: 43 // CV_COUNT_STS_29_PM
■
0x181D: 42 // CV_COUNT_STS_30_PM
■
0x181E: 41 // CV_COUNT_STS_31_PM
152
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x181F: 40 // CV_COUNT_STS_32_PM
■
0x1820: 39 // CV_COUNT_STS_33_PM
■
0x1821: 38 // CV_COUNT_STS_34_PM
■
0x1822: 37 // CV_COUNT_STS_35_PM
■
0x1823: 36 // CV_COUNT_STS_36_PM
■
0x1898: 35 // REI_COUNT_STS_25_PM
■
0x1899: 34 // REI_COUNT_STS_26_PM
■
0x189A: 33 // REI_COUNT_STS_27_PM
■
0x189B: 32 // REI_COUNT_STS_28_PM
■
0x189C: 31 // REI_COUNT_STS_29_PM
■
0x189D: 30 // REI_COUNT_STS_30_PM
■
0x189E: 29 // REI_COUNT_STS_31_PM
■
0x189F: 28 // REI_COUNT_STS_32_PM
■
0x18A0: 27 // REI_COUNT_STS_33_PM
■
0x18A1: 26 // REI_COUNT_STS_34_PM
■
0x18A2: 25 // REI_COUNT_STS_35_PM
■
0x18A3: 24 // REI_COUNT_STS_36_PM
■
0x1918—0x1923 // RECEIVED_RDI_STS_[25:36]
■
0x193C: 11 // REC_C2_STS_25, // REC_C2_STS_26
■
0x193D: 10 // REC_C2_STS_27, // REC_C2_STS_28
■
0x193E: 9 // REC_C2_STS_29, // REC_C2_STS_30
■
0x193F: 8 // REC_C2_STS_31, // REC_C2_STS_32
■
0x1940: 7 // REC_C2_STS_33, // REC_C2_STS_34
■
0x1941: 6 // REC_C2_STS_35, // REC_C2_STS_36
■
0x196C: 5 // REC_PDI_STS_25, // REC_PDI_STS_26
■
0x196D: 4 // REC_PDI_STS_27, // REC_PDI_STS_28
■
0x196E: 3 // REC_PDI_STS_29, // REC_PDI_STS_30
■
0x196F: 2 // REC_PDI_STS_31, // REC_PDI_STS_32
■
0x1970: 1 // REC_PDI_STS_33, // REC_PDI_STS_34
■
0x1971: 0 // REC_PDI_STS_35, // REC_PDI_STS_36
Agere Systems Inc.
153
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
The following PP registers are in RX_CLK4 domain:
■
0x1025: 149 // ELASTIC_STORE_OVERRUN_4
■
0x1215: 148 // ELASTIC_STORE_OVERRUN_MASK_4
■
0x1035: 147 // SF_P_4
■
0x1225: 146 // SF_P_MASK_4
■
0x1045: 145 // RDI_P_4
■
0x1235: 144 // RDI_P_MASK_4
■
0x1115: 143 // RDI_DELTA_P_4
■
0x1295: 142 // RDI_DELTA_P_MASK_4
■
0x1385: 141 // RDI_PERSIST_P_4
■
0x13C5: 140 // RDI_DELTA_STATE_P_4
■
0x1055: 139 // PLM_P_4
■
0x1245: 138 // PLM_P_MASK_4
■
0x1125: 137 // PLM_DELTA_P_4
■
0x12A5: 136 // PLM_DELTA_P_MASK_4
■
0x138D: 135 // PLM_PERSIST_P_4
■
0x13CD: 134 // PLM_DELTA_STATE_P_4
■
0x1065: 133 // UNEQ_P_4
■
0x1255: 132 // UNEQ_P_MASK_4
■
0x1135: 131 // UNEQ_DELTA_P_4
■
0x12B5: 130 // UNEQ_DELTA_P_MASK_4
■
0x1395: 129 // UNEQ_PERSIST_P_4
■
0x13D5: 128 // UNEQ_DELTA_STATE_P_4
■
0x1075: 127 // AIS_P_4
■
0x1265: 126 // AIS_P_MASK_4
■
0x1145: 125 // AIS_DELTA_P_4
■
0x12C5: 124 // AIS_DELTA_P_MASK_4
■
0x139D: 123 // AIS_PERSIST_P_4
■
0x13DD: 122 // AIS_DELTA_STATE_P_4, PDI_DELTA_STATE_P_4
■
0x1085: 121 // LOP_P_4
■
0x1275: 120 // LOP_P_MASK_4
■
0x1155: 119 // LOP_DELTA_P_4
■
0x12D5: 118 // LOP_DELTA_P_MASK_4
■
0x13A5: 117 // LOP_PERSIST_P_4
154
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x13E5: 116 // LOP_DELTA_STATE_P_4
■
0x1105: 115 // PDI_P_4
■
0x1285: 114 // PDI_P_MASK_4
■
0x1175: 113 // PDI_DELTA_P_4
■
0x12ED: 112 // PDI_DELTA_P_MASK_4
■
0x13AD: 111 // PDI_PERSIST_P_4
■
0x1185: 110 // SS_NEW_VLD_4
■
0x12FD: 109 // SS_NEW_VLD_MASK_4
■
0x118B: 108 // SS_MISMATCH_4
■
0x12E6: 107 // SS_MISMATCH_MASK_4
■
0x1505: 106 // EXP_CONC_4
■
0x150A: 105 // CONC_EN_4
■
0x1515: 104 // REC_CONC_4
■
0x1545: 103 // PATH_AIS_INS_4
■
0x154A: 102 // UNEQ_AIS_INS_4
■
0x154F: 101 // PLM_AIS_INS_4
■
0x1554: 100 // TIM_AIS_INS_4
■
0x1585: 99 // SS_INSERT_CONTROL_4
■
0x158A: 98 // E1_F1_INSERT_CONTROL_4
■
0x158F: 97 // E2_INSERT_CONTROL_4
■
0x134D: 96 // REC_F2_4, // REC_H4_4
■
0x134E: 95 // REC_Z3_4, // REC_Z4_4
■
0x134F: 94 // REC_Z5_4
■
0x1350: 93 // F2_VLDP_4 H4Z3Z4_VLDP_4 Z5_VLDP_4 CH_SEL_4
■
0x1357: 92 // REC_SS_4_TSLOT[1:6]
■
0x1358: 91 // REC_SS_4_TSLOT[7:12]
■
0x1612—0x1617 // EXP_C2_STS_[37:48]
■
0x15A5: 84 // PDI_VALIDATE_ENABLE_4
■
0x161B: 83 // COUNT_BB_ERRORS_SEL_4
■
0x1580: 82 // SONET_SDH_RULES_4
■
0x1626: 81 // SS_BITS_SETTING_[37:42]
■
0x1627: 80 // SS_BITS_SETTING_[43:48]
■
0x1662—0x1667 // E1_F1_INSERT_BYTE_[37:48]
■
0x166B: 73 // E2_INSERT_BYTE_4
Agere Systems Inc.
155
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x1597: 72 // TIM_P_INSERT_CONTROL_4
■
0x1685: 71 // SD_INSERT_4
■
0x16B4: 70 // SF_THRESH_SEL_STS_37
■
0x16B5: 69 // SF_THRESH_SEL_STS_38
■
0x16B6: 68 // SF_THRESH_SEL_STS_39
■
0x16B7: 67 // SF_THRESH_SEL_STS_40
■
0x16B8: 66 // SF_THRESH_SEL_STS_41
■
0x16B9: 65 // SF_THRESH_SEL_STS_42
■
0x16BA: 64 // SF_THRESH_SEL_STS_43
■
0x16BB: 63 // SF_THRESH_SEL_STS_44
■
0x16BC: 62 // SF_THRESH_SEL_STS_45
■
0x16BD: 61 // SF_THRESH_SEL_STS_46
■
0x16BE: 60 // SF_THRESH_SEL_STS_47
■
0x16BF: 59 // SF_THRESH_SEL_STS_48
■
0x1705: 58 // LAST_INT_INC_4
■
0x1715: 57 // LAST_INT_DEC_4
■
0x1745: 56 // LAST_GEN_INC_4
■
0x1755: 55 // LAST_GEN_DEC_4
■
0x1785: 54 // ONE_BIT_RDI_PM_4
■
0x1795: 53 // ERDI_PAYLOAD_PM_4
■
0x17A5: 52 // ERDI_CONNECT_PM_4
■
0x17B5: 51 // ERDI_SERVER_PM_4
■
0x17C5: 50 // UNEQ_P_PM_4
■
0x17D5: 49 // AIS_P_PM_4
■
0x17E5: 48 // LOP_P_PM_4
■
0x1824: 47 // CV_COUNT_STS_37_PM
■
0x1825: 46 // CV_COUNT_STS_38_PM
■
0x1826: 45 // CV_COUNT_STS_39_PM
■
0x1827: 44 // CV_COUNT_STS_40_PM
■
0x1828: 43 // CV_COUNT_STS_41_PM
■
0x1829: 42 // CV_COUNT_STS_42_PM
■
0x182A: 41 // CV_COUNT_STS_43_PM
■
0x182B: 40 // CV_COUNT_STS_44_PM
■
0x182C: 39 // CV_COUNT_STS_45_PM
156
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Clocks Required for MPU Read or Write of MARS2G5 P-Pro Registers (continued)
■
0x182D: 38 // CV_COUNT_STS_46_PM
■
0x182E: 37 // CV_COUNT_STS_47_PM
■
0x182F: 36 // CV_COUNT_STS_48_PM
■
0x18A4: 35 // REI_COUNT_STS_37_PM
■
0x18A5: 34 // REI_COUNT_STS_38_PM
■
0x18A6: 33 // REI_COUNT_STS_39_PM
■
0x18A7: 32 // REI_COUNT_STS_40_PM
■
0x18A8: 31 // REI_COUNT_STS_41_PM
■
0x18A9: 30 // REI_COUNT_STS_42_PM
■
0x18AA: 29 // REI_COUNT_STS_43_PM
■
0x18AB: 28 // REI_COUNT_STS_44_PM
■
0x18AC: 27 // REI_COUNT_STS_45_PM
■
0x18AD: 26 // REI_COUNT_STS_46_PM
■
0x18AE: 25 // REI_COUNT_STS_47_PM
■
0x18AF: 24 // REI_COUNT_STS_48_PM
■
0x1924—0x192F // RECEIVED_RDI_STS_[37:48]
■
0x1942: 11 // REC_C2_STS_37, // REC_C2_STS_38
■
0x1943: 10 // REC_C2_STS_39, // REC_C2_STS_40
■
0x1944: 9 // REC_C2_STS_41, // REC_C2_STS_42
■
0x1945: 8 // REC_C2_STS_43, // REC_C2_STS_44
■
0x1946: 7 // REC_C2_STS_45, // REC_C2_STS_46
■
0x1947: 6 // REC_C2_STS_47, // REC_C2_STS_48
■
0x1972: 5 // REC_PDI_STS_37, // REC_PDI_STS_38
■
0x1973: 4 // REC_PDI_STS_39, // REC_PDI_STS_40
■
0x1974: 3 // REC_PDI_STS_41, // REC_PDI_STS_42
■
0x1975: 2 // REC_PDI_STS_43, // REC_PDI_STS_44
■
0x1976: 1 // REC_PDI_STS_45, // REC_PDI_STS_46
■
0x1977: 0 // REC_PDI_STS_47, // REC_PDI_STS_48
Agere Systems Inc.
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Performance Monitor (PM) Reset
A PM reset signal is sent to all blocks for performing monitoring (collecting statistics). A PM reset signal can come
from external pins, internal 1 second timer, or be controlled by software, depending on the PM mode,
MPU_PMMODE[1:0] bits (Table 31).
Table 23. PM Reset Signal Provisioning
MPU_
PMMODE[1:0]
(Table 31)
Description
00
PM Reset Signal Comes from External Pin (1 Hz, 50% Duty Cycle Signal).
01
PM Reset Signal Comes from Internal 1 Second Counter (1 Hz, 50% Duty Cycle Signal).
Writing a logic 1 to the PM reset signal bit MPU_PM_TRIGGER_SWRS (Table 29) in this mode
will reset the counter so that a 0→1 transition occurs on the PM reset signal within 10 clock
cycles of the 77.76 MHz clock.
11
PM Reset Signal Is Software Controlled. Writing a logic 1 to the PM reset signal bit
MPU_PM_TRIGGER_SWRS will cause a 0→1 transition on the internal PM reset signal. This
pulse will be high for 100 cycles of the 77.76 MHz clock and low for 100 cycles of the 77.76 MHz
clock. Writing the PM reset signal bit to a logic 1 during this 200 clock cycle interval will have no
effect (2.57 µs). The PM reset signal rising edge must occur within 10 clock cycles of writing the
PM reset signal bit.
The external PMRST pin is a bidirectional signal controlled by the MPU_PMRST_OE bit (Table 31). This bit
defaults to 0, making the pin an input.
158
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Performance Monitor (PM) Reset (continued)
EXTERNAL
(MPU_PMMODE[1:0] = 00)
PMRSTI
MPU_SWRSR REGISTER
MPU_PM_TRIGGER_SWRS BIT
SOFTWARE CONTROLLED
(MPU_PMMODE[1:0] = 11)
MPU_PM_TRIGGER_SWRS
MPU_MPCLK
IPMRST(TO BLOCKS)
PMRST
PIN
PMRSTO
DELAY
CLK78M
1/2 SECOND
COUNTER
FREE RUNNING
(MPU_PMMODE[1:0] = 01)
MPU_PROVISION0 REGISTER
MPU_PMMODE[1:0] BITS
MPU_PMMODE[1:0]
MPU_MPCLK
MPU_PROVISION0 REGISTER
MPU_PMRST_OE BIT
MPU_MPCLK
MPU_PMRST_OE
MPU BLOCK
5-8157(F)r.1
Figure 14. PM Reset Signal Generation
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
General-Purpose Input/Output Interface
The programmable I/O general-purpose input/output (GPIO) consists of four device pins that can be used for internal block state observation. There functionality is controlled by MPU_GPIO_MODE[3:0] bits (Table 34).
MPU_GPIO_MODE[3:0] = 0000 normal mode
MPU_GPIO_MODE[3:0] = others undefined
Mode 0 (normal mode):
In normal mode, GPIO pins can be programmed individually to be either input or output through
MPU_GPIO_DIR_CTL[3:0] bits (Table 34). Figure 15 shows pictorially the GPIO functionality. These pins are useful for board designers who need the ability to monitor or control signals on their boards. If the pin is an input, the
value on the pin can be read from MPU_GPIO_I_CND[3:0] bits (Table 26). It can also be programmed to generate
a level-sensitive interrupt or a positive-edge detect interrupt contributing to the external interrupt pin. If the pin is an
output, the value provisioned in MPU_GPIO_O_CTL[3:0] bits (Table 30) will appear on the device pin immediately.
160
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
General-Purpose Input/Output Interface (continued)
Programmable I/O Bus
0x0000
VERSION
0x0001
NAME =
0x0002
TADMVC2G52
3
IRQ
2
1
0
GPIO INPUT
3
2
1
0
GPIO OUT
3
2
1
0
0x0003
0x0004
+
0x0005
0x000F
GPIO OUTPUTS
0x0010
LINE PROVISION
0x0012
LOOPBACK
0x0013
GPIO MODE
0x001F
SCRATCH
STM/DCC MODE 2
ACTIVE H/L
3
2
1
0
LEVEL/EDGE
3
2
1
0
POSITIVE
EDGE DET
DIRECTION
3
2
1
0
INPUT 0
GPIO MODE
MPU_GPIOCFG
STM_DCC_RX_CLK
ONE SHOTS
STM_DCC_RX_DATA
IRQ MASKS
0x000E
STM_DCC_TX_CLK
0x000C
INPUTS
INTERRUPTS
GPIO INPUTS
STM_DCC_TX_DATA
0x0008
0x000A
0
GPIO3 PIN
GPIO2 PIN
INPUT 1
OUTPUT ENABLE CONTROLS:
NORMAL MODE 0 EN = MPU_GPIO_MODE[3:0]
STM/DCC MODE 2 EN = 0111
INPUT 2
MODE 1
GPIO1 PIN
GPIO0 PIN
5-8158(F).a
Figure 15. General Input/Output (GPIO)
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Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
Interrupts
The interrupt functionality is shown in Figure 16.
NAME =
0x0002
TADMVC2G52
IRQ[1] (PT)
IRQ[0] (TOHP)
VERSION
0x0001
IRQ[3] (UT)
IRQ[2] (DE)
0x0000
0x0003
0x0004
0x0005
0x0008
INTERRUPTS
0x000A
GPIO INPUTS
0x000C
IRQ MASKS
0x000E
ONE SHOTS
0x000F
GPIO OUTPUTS
0x0010
LINE PROVISION
0x0012
LOOPBACK
0x0013
GPIO MODE
0x0014
GPIO SELECT[1:0]
0x0015
GPIO SELECT[3:2]
0x001F
SCRATCH
SYNC_ERR
(GPIO)
PMIRQ
DE
IRQ
OH
3 2 1 0 UT
PM PT
IRQ MASKS
3 2 1 0
INT
5-7409(F).a
Figure 16. Interrupt Functionality
162
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
Loopback Operation
TERMINAL B
DE
PP
LINE
TOHP
CONT
SOURCE
LAYER 2
FACILITY
(OPTICS)
UT
NEAR
END
TERMINAL
OPTICS
CONT
OPTICS
LINE
TOHP
PP
DE
FACILITY
UT
LAYER 2
SINK
Figure 17 illustrates the different types of loopback provided in the device.
TERMINAL A
5-7411(F)r.2TDAT16
Figure 17. Loopback Operation
In the following description, only the data path from A to B is discussed, but the same terms apply to the reverse
direction.
Near-End Loopback (NELB)
The packet/cell payload is looped back to the data source (layer 2 device) as soon as it crosses the layer 1 to layer
2 mapping (UTOPIA block).
Terminal Loopback
The SDH signal is looped back to the terminal at the end of the piece of equipment (before it is transmitted onto the
facility).
Facility Loopback
The optical signal is looped back to the facility as soon as it enters the terminal.
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Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
MPU Register Descriptions
Table 24. MPU_VERR[0—5], Version Control Registers (RO)
Address
Bit
Name
0x0000
15:0
MPU_VER0
164
Function
Reset
Default
Indicates version number for version 2.0.
0x0207
Indicates version number for version 2.2.
0x0227
Indicates version number for version 2.3.
0x0237
0x0001
15:0
MPU_VER1
Indicates version number.
ASCII T A.
0x5441
0x0002
15:0
MPU_VER2
Indicates version number.
ASCII D M.
0x444D
0x0003
15:0
MPU_VER3
Indicates version number.
ASCII 0 4.
0x3034
0x0004
15:0
MPU_VER4
Indicates version number.
ASCII 2 G.
0x3247
0x0005
15:0
MPU_VER5
Indicates version number.
ASCII 5 CR.
0x350D
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
MPU Register Descriptions (continued)
Table 25. MPU_ISR, Interrupt Status Register (RO or COR/W)
Address
Bit
Name
Function
Reset
Default
0x0008
15
MPU_SYNC_ERR_IS
Sync Error Interrupt (RO). This is a read-only bit. This
bit is set when the TXFSYNCP/N pins (U3, U1) are not
driven by a 2 kHz or greater frame sync signal. When
the TXFSYNCP/N pins are not used, simply ignore this
interrupt by setting the corresponding mask bit
MPU_SYNC_ERR_IM (Table 27) so that the interrupt
does not contribute to the MPU_INTN pin (B7). This bit
can be cleared by setting bit MPU_SYNC_ERR_ICLR
(Table 28).
X
14:13
—
12
MPU_PP_IS
11:8
MPU_GPI_IS[3:0]
General-Purpose Inputs Interrupt (RO or COR/W).
Signal indicating the associated input is active. When
the GPIO are outputs, this signal will be forced low.
These interrupts are COR/COW when the interrupt is
programmed to the positive edge mode; otherwise, this
is a read-only (RO) location.
7
MPU_UT48_IS
UTOPIA Composite Interrupt (RO). Active-high signal
indicating an unmasked delta or event is active in the
UTOPIA block.
6
MPU_DE48_IS
Data Engine Composite Interrupt (RO). Active-high
signal indicating an unmasked delta or event is active
in the data engine block.
5
MPU_PMRST_IS
4
—
3
MPU_DS3_IS
DS3 Composite Interrupt (RO). When set, indicates
that an interrupt from the DS3 block is active.
2
MPU_RXT_IS
RXT Composite Interrupt (RO). When set, indicates
that an interrupt from the RXT block is active.
1
MPU_PT48_IS
Path Terminator Composite Interrupt (RO). Activehigh signal indicating an unmasked delta or event is
active in the path terminator block.
0
MPU_TOHP48_IS
Transport Overhead Processor Composite Interrupt (RO). Active-high signal indicating an unmasked
delta or event is active in the transport overhead processor block.
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Reserved.
PP Composite Interrupt (RO). When set, indicates
that an interrupt from the PP block is active.
Performance-Monitor Reset Interrupt (COR/W).
Active-high signal indicating a 1 second event has
occurred.
Reserved.
165
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Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
MPU Register Descriptions (continued)
Table 26. MPU_CNDR, Condition Register (RO)
Address
Bit
Name
0x000A
15:4
—
3:0
MPU_GPIO_I_CND[3:0]
Function
Reset
Default
Reserved.
—
General-Purpose Input Value. These values are
direction connections between the GPIO[3:0] input pins
and the register map. The value at the GPIO pins is
latched when this register is read.
N/A
Table 27. MPU_IMR, Interrupt Mask Register (R/W)
Address
Bit
Name
Function
Reset
Default
0x000C
15
MPU_SYNC_ERR_IM
Sync Error Interrupt Mask. When set (active-high), the
associated interrupt bit will be inhibited from contributing to the interrupt pin (MPU_INTN).
1
14:13
—
Reserved.
11
12
MPU_PP_IM
Pointer Processor Composite Interrupt Mask. When
set (active-high), the associated composite interrupt bit
will be inhibited from contributing to the interrupt pin
(MPU_INTN).
1
11:8
MPU_GPI_IM[3:0]
General-Purpose Inputs Composite Interrupt Mask.
When set (active-high), the associated composite interrupt bit will be inhibited from contributing to the interrupt
pin (MPU_INTN).
1111
7
MPU_UT48_IM
UTOPIA Composite Interrupt Mask. When set (activehigh), the associated composite interrupt bit will be
inhibited from contributing to the interrupt pin
(MPU_INTN).
1
6
MPU_DE48_IM
Data Engine Composite Interrupt Mask. When set
(active-high), the associated composite interrupt bit will
be inhibited from contributing to the interrupt pin
(MPU_INTN).
1
5
MPU_PMRST_IM
Performance-Monitor Composite Reset Mask. When
set (active-high), the associated composite interrupt bit
will be inhibited from contributing to the interrupt pin
(MPU_INTN).
1
166
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
MPU Register Descriptions (continued)
Table 27. MPU_IMR, Interrupt Mask Register (R/W) (continued)
Address
Bit
Name
0x000C
4
—
3
Function
Reset
Default
Reserved.
—
MPU_DS3_IM
DS3 Composite Interrupt Mask. When set (activehigh), the associated composite interrupt bit will be
inhibited from contributing to the interrupt pin
MPU_INTN (pin B7).
1
2
MPU_RXT_IM
Receive Terminator Composite Interrupt Mask. When
set (active-high), the associated composite interrupt bit
will be inhibited from contributing to the interrupt pin
MPU_INTN.
1
1
MPU_PT48_IM
Path Terminator Composite Interrupt Mask. When set
(active-high), the associated composite interrupt bit will
be inhibited from contributing to the interrupt pin
MPU_INTN.
1
0
MPU_TOHP48_IM
Transport Overhead Processor Composite Interrupt
Mask. When set (active-high), the associated composite
interrupt bit will be inhibited from contributing to the interrupt pin MPU_INTN.
1
Table 28. MPU_ICLRR, Interrupt Clear Register (R/W)
Address
Bit
0x000D
15
14:0
Name
Function
MPU_SYNC_ERR_ICLR Sync Error Interrupt Clear. When this bit is set, interrupt status bit MPU_SYNC_ERR_IS (Table 25) will be
cleared.
—
Reserved.
Reset
Default
0
0
Table 29. MPU_SWRSR, Software Reset Register (R/W)
Address
Bit
Name
0x000E
15:8
—
7
Reserved.
MPU_PM_TRIGGER_SWRS Performance-Monitor Reset Trigger. This bit is
used in software controlled mode to generate a PM
reset signal pulse. It is also used in free-running
mode to synchronize the PM reset signal pulse. To
generate the trigger, write 1, then write 0 to this bit.
6:1
—
0
MPU_RST_SWRS
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Function
Reset
Default
0
0
Reserved.
0
Software Reset. Writing 1 to this bit will reset the
device. This bit will clear itself.
0
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
MPU Register Descriptions (continued)
Table 30. MPU_GPIO_CTLR, GPIO Output Value (R/W)
Address
Bit
Name
Function
0x000F
15:4
—
3:0
MPU_GPIO_O_CTL[3:0]
Reset
Default
Reserved.
0
General-Purpose Output Values. The value written
into these registers will appear on the associated
output.
0000
Table 31. MPU_PROVISION0, Provisioning Register 0 (R/W)
Address
Bit
Name
Function
Reset
Default
0x0010
15
MPU_PMRST_OE
PMRST Output Enable. Controls the 3-state buffer
that drives the external PMRST (pin D7). If 0, the
buffer is disabled, and PMRST is input. If 1, PMRST is
output.
0
14:10
—
9:8
MPU_PMMODE[1:0]
7
—
6
MPU_COR_COW_CTL
5
Reserved.
00100
Performance-Monitoring Mode. 00 or 10 = PM reset
signal comes from external pin; 01 = PM reset signal
comes from internal 1 second counter; 11 = PM reset
signal is software controlled.
00
Reserved.
0
Clear-on-Read/Clear-on-Write Control for MPU
Registers. 1 = COR, 0 = COW.
0
—
Reserved.
1
4
—
OC-48/OC-3 Mode for Internal System Clock Divisor. 1 = OC-48, 0 = OC-12 and OC-3.
1
3:0
—
Reserved.
0
Table 32. MPU_PROVISION1, Provisioning Register 1 (R/W)
Address
Bit
Name
0x0011
15
MPU_EQA
14:12
—
11
MPU_EQB
10:8
—
7
MPU_EQC
6:4
—
3
MPU_EQD
2:0
—
168
Function
Reset
Default
Equip Channel A. 1 = enable; 0 = disable. Turn off clock in
receive direction, no effect in transmit direction.
0
Reserved.
0
Equip Channel B. 1 = enable; 0 = disable. Turn off clock in
receive direction, no effect in transmit direction.
0
Reserved.
0
Equip Channel C. 1 = enable; 0 = disable. Turn off clock in
receive direction, no effect in transmit direction.
0
Reserved.
0
Equip Channel D. 1 = enable; 0 = disable. Turn off clock in
receive direction, no effect in transmit direction.
0
Reserved.
0
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
MPU Register Descriptions (continued)
Table 33. MPU_LPBKCTLR, Loopback Control Register (R/W)
Address
Bit
Name
0x0012
15:14
MPU_LPBKD[3:2]
13:12
MPU_LPBKA[1:0]
11:10
MPU_LPBKC[3:2]
9:8
MPU_LPBKB[1:0]
Function
Loopback Control. SONET facility and terminal loopback
are only available in STS-3/STM-1 and STS-12/STM-4
modes.
For MPU_LPBK[A—D][1:0]:
Reset
Default
00
00
00
00
7:6
MPU_LPBKB[3:2]
5:4
MPU_LPBKC[1:0]
3:2
MPU_LPBKA[3:2]
00 = No loopbacks.
01 = SONET facility loopback.
10 = SONET terminal loopback.
11 = Reserved.
1:0
MPU_LPBKD[1:0]
For MPU_LPBK[D—A][3:2]:
00
00
00
00
00 = No loopbacks.
01 = Reserved.
10 = UTOPIA near-end loopback.
11 = Reserved.
Table 34. MPU_GPIOCFG, GPIO Configuration Register (R/W)
Address
Bit
Name
0x0013
15:12
MPU_GPIO_MODE[3:0]
Function
GPIO Mode.
Reset
Default
0000
0000 = Normal mode. Enables all four GPIO signals.
0001 = Reserved.
Else = Undefined.
11:8
MPU_GPIO_POL[3:0]
7:4
MPU_GPIO_ITYPE[3:0]
3:0
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GPIO Interrupt Active State. 0 = report received
value unchanged. (Level = input pin value, positive
edge = 1 when signal rises); 1 = invert received value
(level = invert input pin value, positive edge = 0 when
detected).
0000
GPIO Interrupt Type. 0 = positive edge; 1 = level.
0000
MPU_GPIO_DIR_CTL[3:0] GPIO Direction Control. 0 = input; 1 = output.
0000
169
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
MPU Register Descriptions (continued)
Table 35. MPU_GPIO_OER[1—2], GPIO Output Enable (R/W)
Address
Bit
Name
0x0014
15:9
—
8
7:1
0
0x0015
15:9
8
7:1
0
170
Function
Reset
Default
Reserved.
0x0000
MPU_GPIO1_OE GPIO1 Output Enable. Write 1 to enable output. Write 0 to
3-state the output.
—
Reserved.
MPU_GPIO0_OE GPIO0 Output Enable. Write 1 to enable output. Write 0 to
3-state the output.
—
Reserved.
0x0000
MPU_GPIO3_OE GPIO3 Output Enable. Write 1 to enable output. Write 0 to
3-state the output.
—
Reserved.
MPU_GPIO2_OE GPIO2 Output Enable. Write 1 to enable output. Write 0 to
3-state the output.
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
MPU Register Descriptions (continued)
Table 36. MPU_PDN1, Powerdown Register 1 (R/W)
Note: A read or write should not be performed to blocks that are powered down, since it may not be completed.
The MPU_DTN signal may not be generated for blocks that are powered down.
Address
Bit
Name
0x001B
15:14
—
13
MPU_LI_PDN
12:9
—
Power Down the Line Interface Block. 1 = powerdown.
Reserved.
8
—
Must Be Set to 1.
0
7:6
—
Reserved.
5
MPU_PAY_TXCLKPDN
0
0
4
3
2
1:0
Function
Reserved.
Power Down PAY Transmit Clock. 1 = powerdown.
MPU_PAY_RXCLKPDN
Power Down PAY Receive Clock. 1 = powerdown.
MPU_SON_TOH_SYCLKPDN Power Down the TOH System Clock. 1 = powerdown.
MPU_SON_PP_SYCLKPDN Power Down the PP System Clock. 1 = powerdown.
—
Must Be Set to 11.
Reset
Default
0
0
0
0
0
0
00
Table 37. MPU_PDN2, Powerdown Register 2 (R/W)
Address
Bit
Name
Function
Reset
Default
0x001D
15:12
—
Reserved.
0000
11:0
—
Must Be Set to 0xFFF.
0x000
Table 38. MPU_PDN3, Powerdown Register 3 (R/W)
Address
Bit
Name
Function
Reset
Default
0x001E
15:12
—
Reserved.
0000
11:0
—
Must Be Set to 0xFFF.
0x000
Table 39. MPU_SCRATCHR, Scratch Register (R/W)
Address
Bit
0x001F
15:0
Name
Function
MPU_SCRATCH[15:0] Read/Write Register with No Other Internal Connections.
Reset
Default
0x0
Table 40. MPU_TDAT16_MODER, MARS2G5 P-Pro Mode Selection Register (R/W)
Address
Bit
Name
0x0020
15:1
0
—
—
Agere Systems Inc.
Function
Reserved.
Must Be Set to 1.
Reset
Default
0
0
171
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
MPU Register Descriptions (continued)
Table 41. MPU_LI_MODER, Register (R/W)*
Address
Bit
Name
0x0021
15:12
—
Function
Reset
Default
Reserved.
0
11
MPU_LI_MODE[11:0] Channel A OC-12 and OC-3 Enable†. 1 = enable, 0 = disable.
0
10
Channel B OC-12 and OC-3 Enable†. 1 = enable, 0 = disable.
0
9
Channel C OC-12 and OC-3 Enable†. 1 = enable, 0 = disable.
0
8
Channel D OC-12 and OC-3 Enable†. 1 = enable, 0 = disable.
0
7
Additional Delay in PLL Feedback Path When Set to 1.
0
6
POF/SONET Select. 1 = packet over fiber (POF), 0 = SONET.
0
Note: For proper operation of POF mode, register 0x400F bit 5
(Table 263) and register 0x5801 (Table 680) need to be
configured correctly.
5
PLL On/Off Select. Controls the transmit line clock PLL used
for STS-48/STM-16 contraclocking mode. 1 = PLL off (inactive), 0 = PLL on (active).
1
4
OC-48/OC-3 Mode for Internal System Clock Divisor.
1 = OC-48, 0 = OC-12 and OC-3.
1
3
Channel A OC-12/OC-3 Select. 1 = OC-12, 0 = OC-3.
0
2
Channel B OC-12/OC-3 Select. 1 = OC-12, 0 = OC-3.
0
1
Channel C OC-12/OC-3 Select. 1 = OC-12, 0 = OC-3.
0
0
Channel D OC-12/OC-3 Select. 1 = OC-12, 0 = OC-3.
0
* For normal OC-12 operation write 0x0F0F, normal OC-3 operation write 0x0F00, and normal OC-48 operation write 0x0010.
† For OC-48 mode, channels A, B, C, and D are always enabled (on). There is no way to disable them in OC-48 mode.
Table 42. MPU_HSI_TST_CTL, High-Speed Interface Control
Address
Bit
Name
Function
Reset
Default
0x0030
15
—
Reserved.
0
14
—
Must Be Set to 1.
0
13:11
—
Reserved.
000
10:8
—
Reserved.
110
7:0
—
Reserved.
0x00
Table 43. MPU_HSI_LPBKR, High-Speed Interface Loopback Register
Address
Bit
Name
0x0032
15:12
—
Reserved.
11:0
—
Must Be Set to 0xFFF.
172
Function
Reset
Default
0x0
0x000
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Microprocessor (MPU) Interface (continued)
MPU Register Map
Table 44. MPU Register Map
Note: Shading denotes reserved bits.
Addr
Symbol
Type
0x0000
MPU_VER0
RO
VERSION = 0x01
0x0001
MPU_VER1
RO
0x54 = T
0x41 = A
0x0002
MPU_VER2
RO
0x44 = D
0x4C = M
0x0003
MPU_VER3
RO
0x30 = 0
0x34 = 4
0x0004
MPU_VER4
RO
0x32 = 2
0x47 = G
0x0005
MPU_VER5
RO
0x35 = 5
0x0D = CR
0x0006
—
—
0x0007
—
—
0x0008
MPU_ISR
RO or
COR/W
Bit 15
Bit 14
Bit 13
MPU_
SYNC_
ERR_IS
0x0009
—
—
0x000A
MPU_CNDR
R/W
0x000B
—
—
0x000C
MPU_IMR
R/W
MPU_
SYNC_
ERR_IM
0x000D
MPU_ICLRR
R/W
MPU_
SYNC_ER
R_ICLR
0x000E
MPU_SWRSR
R/W
Bit 12
Bit 11
MPU_
PP_IS
Bit 10
Bit 9
Bit 8
MPU_GP_IS[3:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
MPU_
DS3_IS
MPU_
RXT_IS
MPU_
PT48_IS
MPU_
TOHP48_
IS
MPU_
UT48_IS
MPU_
DE48_IS
MPU_
PMRST_
IS
MPU_GPIO_I_CND[3:0]
MPU_
PP_IM
MPU_
GP_IM3
MPU_
GP_IM2
MPU_
GP_IM1
MPU_
GP_IM0
MPU_
UT48_IM
MPU_
DE48_IM
MPU_
PMRST_
IM
MPU_
DS3_IM
MPU_
RXT_IM
MPU_
PT48_IM
MPU_PM_
TRIGGER
_SWRS
0x000F
MPU_GPIO_CTLR
R/W
0x0010
MPU_PROVISION0
R/W
MPU_
PMRST_
IOCTL
MPU_EQA
MPU_
TOHP48_
IM
MPU_
RST_
SWRS
MPU_GPIO_O_CTL[3:0]
MPU_PMMODE[1:0]
—
0x0011
MPU_PROVISION1
R/W
0x0012
MPU_LPBKCTLR
R/W
0x0013
MPU_GPIOCFG
R/W
0x0014
MPU_GPIO_OER1
R/W
MPU_GPI
O1_OE
MPU_GPI
O0_OE
0x0015
MPU_GPIO_OER2
R/W
MPU_GPI
O3_OE
MPU_GPI
O2_OE
0x0016
—
0x001A
—
—
Agere Systems Inc.
MPU_EQB
MPU_
COR_CO
W_CTL
MPU_LPBKD[3:2]
MPU_LPBKA[1:0]
MPU_GPIO_MODE[3:0]
MPU_EQC
MPU_LPBKC[3:2]
MPU_LPBKB[1:0]
MPU_GPIO_POL[3:0]
MPU_EQD
MPU_LPBKB[3:2]
MPU_LPBKC[1:0]
MPU_GPIO_ITYPE[3:0]
MPU_LPBKA[3:2]
MPU_LPBKD[1:0]
MPU_GPIO_DIR_CTL[3:0]
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Microprocessor (MPU) Interface (continued)
MPU Register Map (continued)
Table 44. MPU Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Type
0x001B
MPU_PDN1
R/W
0x001C—
0x001E
—
—
0x001F
MPU_SCRATCHR
R/W
0x0020
—
—
0x0021
MPU_LI_MODER
R/W
0x0022—
0x07FF
—
—
174
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
MPU_LI_P
DN
Bit 6
Bit 5
MPU_PAY
_TXCLKP
DN
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MPU_PAY MPU_SON MPU_SON
_RXCLKP _TOH_SY _PP_SYC
DN
CLKPDN
LKPDN
MPU_SCRATCH[15:0]
MPU_LI_MODE[11:0]
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Functional Description
The block diagram for the MARS2G5 P-Pro indicating the signal pins per block is shown in Figure 18.
TXCLKQP/N,
TXCLKP/N,
AND TXF
TXTOH
6
2
ECL
REF
RXD
4 x 24
UTOPIA
INTERFACE
32
32
RXC
2
RXLINE
TXD
350 SIGNAL PINS
TXLINE
6
OHP
PP
DE
TX
UTOPIA
4 x 24
RX
UTOPIA
UT
CTRL
12
RXREF
RXTOH
43
6
4
JTAG ALM/GPIO
MPU
INTERFACE
5-7396(F)r.2TDAT162
Figure 18. MARS2G5 P-Pro Block Diagram Indicating the Signal Pins per Block
Agere Systems Inc.
175
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Line Interface
This block provides the interface between the SONET/SDH line and the transport overhead (TOH) processing
block. The line interface must provide transmit/receive functions for quad OC-3, quad OC-12, and single OC-48
applications. All external inputs and outputs for the MARS2G5 P-Pro line I/O block are referenced to the positive
edge of the clock.
The following is a list of the receive line interface functions:
■
The quad OC-3 application consists of four differential PECL 155.52 Mbits/s data inputs and four 155.52 MHz differential clocks from an optical transceiver.
■
The quad OC-12 application consists of four differential PECL 622.08 Mbits/s data inputs and four 622.08 MHz
differential clocks from an optical transceiver.
■
The OC-48 application consists of 16 differential PECL data inputs at 155.52 Mbits/s with a single differential
PECL 155.52 MHz clock.
The transmit interface performs the following functions:
■
The quad OC-3 application consists of four differential PECL 155.52 Mbits/s data outputs to an optical transceiver. A SONET compliant 155 MHz differential PECL clock input is required in this mode.
■
The quad OC-12 application consists of four each: a differential PECL 622.08 Mbits/s data to an optical transceiver. A SONET compliant 622 MHz differential PECL clock input is required in this mode.
■
The OC-48 application consists of 16 differential PECL data outputs at 155.52 Mbits/s with a differential PECL
155.52 MHz clock.
■
The 8k frame sync is a clock cycle wide pulse latched in at the system rate (622.08 MHz or 155.52 MHz). This
signal will set the transmit frame location. If this signal is kept low, the transmit frame will free-run at the 8 kHz
rate.
The line interface also supports loopback functions:
■
In the quad OC-3 and quad OC-12 applications, the line interface supports both terminal and facility loopback on
a per-port basis.
176
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Line Interface (continued)
This device is designed to work with commonly available multiplexer and demultiplexer chipsets for STS-3, STS12, and STS-48 line interface rates. The line interface will operate in one of three possible modes.
Table 45. Line Interface Modes
MPU_LI_MODE[4:0]
0x0021 (Table 41)
Interfaces
Line Interface Signals
10000
OC-48
RXCLK[P/N], RXD[15:0], TXCLK[P/N], TXD[15:0]
01111
OC-12
RXCLKD[P/N], RXDD[P/N], TXCLK[P/N], TXDD[P/N]
RXCLKC[P/N], RXDC[P/N], TXCLK[P/N], TXDC[P/N]
RXCLKB[P/N], RXDB[P/N], TXCLK[P/N], TXDB[P/N]
RXCLKA[P/N], RXDA[P/N], TXCLK[P/N], TXDA[P/N]
00000
OC-3
RXCLKD[P/N], RXDD[P/N], TXCLK[P/N], TXDD[P/N]
RXCLKC[P/N], RXDC[P/N], TXCLK[P/N], TXDC[P/N]
RXCLKB[P/N], RXDB[P/N], TXCLK[P/N], TXDB[P/N]
RXCLKA[P/N], RXDA[P/N], TXCLK[P/N], TXDA[P/N]
TXCLKP
TXCLKN
TXD[15:0]
VALID
RXCLK[A:D]P
RXCLK[A:D]N
RXD[15:0]
VALID
5-7418(F)r.2
Figure 19. Line Interface
Agere Systems Inc.
177
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Line Interface (continued)
LVPECL I/O Termination and Load Specifications
The LVPECL buffers are compatible with the temperature independent ECL 100K levels, but the output levels that
are guaranteed are relaxed 30 mV from the actual 100K levels allowing for noise and variations in the power supply and process.
All LVPECL output buffers require a terminating resistor. These terminating resistors, which must also be connected to both LVPECLREFHI and LVPECLREFLO, go to a common terminating voltage. All of the terminating
resistors used with a chip must be identical precision (1%) resistors. The value of these terminating resistors is
usually chosen to match the characteristic impedance of the board. To save on power, a terminating voltage equal
to VDDD – 2 V is available in most ECL systems. The minimum value of the terminating resistor that can be used on
these buffers is 50 Ω. This is also the standard termination used in most ECL systems. Larger values of resistance
will save power, but will also slow down the high-to-low transition of the output, since it is RC limited.
If no VDDD – 2 V supply is available, a larger value resistor may be connected directly to GND. It should be chosen
such that the current through it does not exceed the current through a 50 Ω resistor to VDDD – 2 V (21 mA in the
high state). This large resistor will most likely be a poor match to the board impedance. The match can be
improved by the use of a Thevenin equivalent resistor pair. Such a Thevenin equivalent resistor will burn much
more system power (but not on-chip power) than would a single resistor, but it does allow for impedance matching
in the absence of a VDDD – 2 V supply. Termination resistor options are shown in Table 46 and Figure 20.
Experienced ECL designers sometimes use the (bipolar) ECL output buffers in a tied-OR configuration. Unfortunately, this cannot be done with these LVPECL buffers.
178
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Line Interface (continued)
LVPECL I/O Termination and Load Specifications (continued)
Table 46. Nominal dc Power for Suggested Terminations
Note: The value is the average of the high and low states in LVPECL output buffer and external terminating resistors, for a single-ended output. The values double for double-ended outputs.
Terminating Resistor and Voltage
Output Transistor (On-Chip)
Power (mW)
Terminating Resistor (Off-Chip)
Power (mW)
15
13
15
52
50 Ω (RP) to VDDD – 2 V*
130 Ω (R1) to VDDD and 82 Ω (R2) to GND
†
* Standard ECL termination (parallel).
† Thevenin equivalent of 50 Ω to VDDD – 2 V.
VDDD
VDDD
VDDD – 2 V
LVPECL OUTPUT
RP
RP
LVPECL INPUT
LVPECL OUTPUT
DIFFERENTIAL CONFIGURATION
WITH PARALLEL TERMINATION
R1
R1
R2
R2
LVPECL INPUT
DIFFERENTIAL CONFIGURATION
WITH THEVENIN TERMINATION
VDDD – 2 V
VDDD
VDDD
VDDD – 1.3 V
LVPECL OUTPUT
RP
LVPECL INPUT
X
LVPECL OUTPUT
R1
R2
R2
R1
LVPECL INPUT
X
SINGLE-ENDED CONFIGURATION
WITH PARALLEL TERMINATION
SINGLE-ENDED CONFIGURATION
WITH THEVENIN TERMINATION
1264(F)a
Figure 20. LVPECL Load Connections
Agere Systems Inc.
179
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Line Interface (continued)
Line Interface I/O Timing
Note: VDD = VDDA = VDDD (3.300 volts nominal) in this section.
Figure 21, Figure 22, Table 47, and Table 48 give the timing specifications for the STS-3/STM-1,
STS-12/STM-4, and STS-48/STM-16 interfaces.
tRCCP
tRCR
tRCF
RXCLKP/RXCLK[D—A]P
VIH (MIN)
50%
VIL (MAX)
RXCLKN/RXCLK[D—A]N
RXD[15:0]P/RXD[D—A]P
tRCPL
tRCPH
tRSU
tRH
RXD[15:0]N/RXD[D—A]N
5-9252 (F).ar.2
Figure 21. Receive Line-Side Timing Waveform
180
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Line Interface (continued)
Line Interface I/O Timing (continued)
tTCCP
tTCR
tTCF
TXCLKP
VIH (MIN)
50%
VIL (MAX)
TXCLKN
tTCPL
tTCPH
tPDCC
TXD[15:0]P/TXD[D—A]P*
50%
TXD[15:0]N/TXD[D—A]N*
5-9253(F).dr.1
* Loading of TXD[15:4][P/N] is 12 pF. Loading of TXD[3:0][P/N]/TXD[D:A][P/N] is 8 pF with the PLL on, and 12 pF with the PLL off.
Figure 22. Transmit Line-Side Timing Waveform—OC-48 Contraclocking
TXCLKP
VIH (MIN)
50%
VIL (MAX)
TXCLKN
tPDFC1
TXCLKQP
50%
TXCLKQN
tPDFC2
TXD[15:0]P/TXD[D—A]P*
50%
TXD[15:0]N/TXD[D—A]N*
tPDFC3
5-9253(F).fr.2
* Loading of TXD[15:4][P/N] is 12 pF. Loading of TXD[3:0][P/N]/TXD[D:A][P/N] is 8 pF with the PLL on, and 12 pF with the PLL off.
Figure 23. Transmit Line-Side Timing Waveform—OC-48 Forward Clocking
TXCLKP
VIH (MIN)
50%
VIL (MAX)
TXCLKN
tTFSSU
tTFSH
TXFSYNCN
TXFSYNCP
tTFSPW
5-9253(F).er.4
Figure 24. Transmit Line-Side Timing Waveform—Frame Sync
Agere Systems Inc.
181
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Line Interface (continued)
Line Interface I/O Timing (continued)
For the following tables,
VIL (max) = (VDD – 1.475) V, nominal of 1.825 V;
VIH (min) = (VDD – 1.165) V, nominal of 2.135 V;
VOH (min) = (VDD – 1.025) V, nominal of 2.275 V;
VOL (max) = (VDD – 1.620) V, nominal of 1.680 V.
Table 47. Receive Line-Side Timing Specifications
Symbol
tRCCP
tRCR
tRCF
tRCPL
tRCPH
tRSU
tRH
182
Parameter
Min
Typ
Max
Units
—
—
6.4300
1.60751
—
—
ns
ns
Receive Clock/Data Rise Time:
OC-3 Mode
OC-12 Mode
OC-48 Mode
200
200
200
—
—
—
2200
600
1500
ps
ps
ps
Receive Clock/Data Fall Time:
OC-3 Mode
OC-12 Mode
OC-48 Mode
200
200
200
—
—
—
2200
600
1500
ps
ps
ps
Receive Clock Pulse Low (for P input):
STS-3/STM-1 and STS-48/STM-16
STS-12/STM-4
2.800
700
3.2150
803.75
3.630
907
ns
ps
Receive Clock Pulse High (for P input):
STS-3/STM-1 and STS-48/STM-16
STS-12/STM-4
2.800
700
3.2150
803.75
3.630
907
ns
ps
Receive Data Setup Time:
RXD[D—A][P/N]
OC-3 Mode
OC-12 Mode
RXD[15:0][P/N]
OC-48 Mode
600
400
—
—
—
—
ps
ps
500
—
—
ps
Receive Data Hold Time:
RXD[D—A][P/N]
OC-3 Mode
OC-12 Mode
RXD[15:0][P/N]
OC-48 Mode
600
400
—
—
—
—
ps
ps
1
—
—
ns
Receive Clock-Cycle Period:
STS-3/STM-1 and STS-48/STM-16
STS-12/STM-4
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Line Interface (continued)
Line Interface I/O Timing (continued)
Table 48. Transmit Line-Side Timing Specifications
Note: The recommended termination for LVPECL outputs is 50 Ω to a termination voltage equal to VDD – 2 V.
Symbol
tTCCP
tTCR
tTCF
tTCPL
tTCPH
tPDCC
tPDFC1
tPDFC2
tPDFC3
tTFSSU
tTFSH
tTFSPW
Parameter
Transmit Clock-Cycle Period:
STS-3/STM-1 and STS-48/STM-16
STS-12/STM-4
Transmit Clock (TXCLK[P/N])/Transmit Frame Sync
(TXFSYNC[P/N]) Rise Time:
OC-3 Mode
OC-12 Mode
OC-48 Mode
Transmit Clock (TXCLK[P/N])/Frame Sync
(TXFSYNC[P/N]) Fall Time:
OC-3 Mode
OC-12 Mode
OC-48 Mode
Transmit Clock Pulse Low (for P input):
STS-3/STM-1 and STS-48/STM-16
STS-12/STM-4
Transmit Clock Pulse High (for P input):
STS-3/STM-1 and STS-48/STM-16
STS-12/STM-4
Propagation Delay—Contraclocking*:
(TXCLK[P/N] to TXD[15:0][P/N], with PLL)
Propagation Delay—Forward Clocking:
(TXCLK[P/N] to TXCLKQ[P/N])†
Propagation Delay—Forward Clocking:
(TXCLKQ[P/N] to TXD[15:0][P/N], no PLL)*
Propagation Delay—Forward Clocking:
(TXCLK[P/N] to TXD[15:0][P/N], no PLL)
TXFSYNC[P/N] Setup Time:
OC-3 Mode
OC-12 Mode
OC-48 Mode (no PLL)
OC-48 Mode (with PLL)
TXFSYNC[P/N] Hold Time:
OC-3 Mode
OC-12 Mode
OC-48 Mode (no PLL)
OC-48 Mode (with PLL)
Transmit TXFSYNC[P/N] Width‡:
STS-3/STM-1 and STS-48/STM-16
STS-12/STM-4
Min
Typ
Max
Unit
—
—
6.4300
1.60751
—
—
ns
ns
200
200
200
—
—
—
2200
600
1500
ps
ps
ps
200
200
200
—
—
—
2200
600
1500
ps
ps
ps
2.800
700
3.2150
803.75
3.630
907
ns
ps
2.800
700
3.2150
803.75
3.630
907
ns
ps
1
—
3
ns
1.5
—
4.5
ns
0
—
1.5
ns
2
—
5
ns
600
400
0
2
—
—
—
—
—
—
—
—
ps
ps
ns
ns
600
400
2
0
—
—
—
—
—
—
—
—
ps
ps
ns
ns
6.430
1.608
—
—
19,438
77,758
clock cycles
clock cycles
* TXFSYNC[P/N] must be synchronized to TXCLK[P/N]; it must be at least one TXCLK[P/N] clock-cycle wide, but less than one frame
period minus two TXCLK[P/N] clock-cycles wide.
† TXCLKQ[P/N] is used in STS-48/STM-16 mode only.
‡ The PLL can be invoked in STS-48/STM-16 mode only.
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Transport Overhead Processor (TOHP-48) Block
Introduction
This section describes the functions of the transport overhead processing block (TOHP-48) in the MARS2G5 PPro. This block supports regenerator section overhead (RSOH) or line section overhead and multiplex section
overhead (MSOH) processing for quad STS-3/STM-1, quad STS-12/STM-4 signals, or a single STS-48/STM-16
signal. Control inputs and outputs for each functional block are specified, along with the appropriate control register
bit definitions.
TOHP-48 Functional Block Diagram
Figure 25 shows a high-level view of the interconnect between the TOHP-48 processor block and other blocks
(pointer interpreter, SPE mapper block, serial-to-parallel and parallel-to-serial conversion blocks, and the microprocessor interface).
RECEIVE
TOAC
CHANNELS
TOH PROCESSOR
RX_DATAI[31:0]
SERIAL-TO-PARALLEL
CONVERSION
RECEIVE DIRECTION
(FROM SONET/SDH LINE)
RX_DATAO[31:0]
POINTER
PROCESSOR
RX_SYNCO
TX_DATAI[31:0]
TX_DATAO[31:0]
PARALLEL-TO-SERIAL
CONVERSION
TRANSMIT DIRECTION
(TO SONET/SDH LINE)
CONTROL AND STATUS
MICROPROCESSOR
PATH TERMINATOR
TX_SYNCI
TRANSMIT
TOAC
CHANNELS
5-8127(F)r.1TDAT16
Figure 25. High-Level Block Interconnect
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Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Functional Block Diagram (continued)
The TOHP-48 functional blocks are shown in Figure 26.
FROM SONET/SDH LINE (RECEIVE DIRECTION)
RDATAI
[31:0]
DESCRAMBLER
FRAME
ALIGN
INSERT
AIS-L
B1
J0
INPUT
LOC
MONITOR
OOF
LOF
MONITOR
LOS
DETECTOR
F1
J0
MONITOR
F1
MONITOR
K1
K2
B2
B2
BIP N
CHECK
B1
BIP-8
CHECK
K2
K1/K2
APS
MONITOR
M1
AIS-L
RDI-L
DETECT
RDATAO
[7:0]
RSYNCO
S1
M1
REI-L
DETECT
SYNC
STATUS
MONITOR
M1
REI
COUNTER
TOAC
DROP
BER
ALGORITHM
TO SONET/SDH LINE (TRANSMIT DIRECTION)
TSYNCO
TDATAO[7:0]
INSERT J0
Z0-X,
A1/A2
TDATAI[31:0]
SCRAMBLER
INSERT
SECTION/RSOH
B1
TRANSPOSE
F1
B1
GENERATE
F1
INSERT LINE/MSOH
INSERT
AIS
MSOH
DIVIDER
B2
B2
GENERATE
J0, E1, F1, D1—D3 INSERT
TSYNCI
K1
K2
K2[2:0]
M1
K1/K2
APS
RDI-L
INSERT
M1
REI-L
S1
SYNC
STATUS
TOAC INSERT
D4—D12, S1, AND E2
(Z1 AND Z2 ONLY OC-12/OC-48)
5-8129(F)r.1
Figure 26. TOHP-48 Block Diagram (One Channel)
Figure 26 describes a detailed view of one of four TOH channel processing blocks in both the receive and transmit
direction. A detailed description of each block is provided in the following sections.
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Transport Overhead Processor (TOHP-48) Block (continued)
Enhancements
This section includes the enhancements added to the TOHP block for the MARS2G5 P-Pro device. The enhancements are K1K2 validation and pass through mode for APSMON and K2MON processing, transposer (OC-48) and
divider (OC-3), the TOAC must run at 20.736 MHz clock for all modes, and Rx output to the pointer processor block
changes on the falling edge of the clock.
APSMON and K2MON Processing (Including K1K2 Validation and Pass Through)
Note: The three least significant bits of the K2 byte take on different meaning depending on the linear APS mode or
ring status mode. Therefore, the integration is different.
The K1 byte will be stored in TOHP_K1DMON[7:0] (Table 85), while the K2 byte will be stored in
TOHP_K2DMON[7:0] (Table 85). The updating of these registers depends on mode bit TOHP_K1K2_2OR1
(Table 67), as follows:
■
When TOHP_K1K2_2OR1 = 0, the K1 and K2 byte registers will be updated after TOHP_CNTDK1K2[3:0]
(Table 66) consecutive frames of identical K1[7:0] and K2[7:3], i.e., the 13-bit pattern must be identical for
TOHP_CNTDK1K2[3:0] frames prior to updating the K1 and K2 registers. In this mode, the TOHP_K2DMON[2:0]
register will be updated after TOHP_CNTDK2[3:0] (Table 66) consecutive frames of identical K2[2:0].
■
When TOHP_K1K2_2OR1 = 1, the K1 and K2 byte registers will be updated after TOHP_CNTDK1K2[3:0] consecutive frames of identical K1[7:0] and K2[7:0], i.e., the 16-bit pattern must be identical for
TOHP_CNTDK1K2[3:0] frames prior to updating the registers.
Whenever the contents of the TOHP_K1DMON[7:0] and TOHP_K2DMON[7:3] (for TOHP_K1K2_2OR1 = 0) or
TOHP_K2DMON[7:0] (for TOHP_K1K2_2OR1 = 1) register changes, a delta bit TOHP_K1K2DMOND (Table 62)
will be set (TOHP_K1K2DMONM (Table 64)). This event bit is valid in both monitoring modes.
The block will monitor the APS bytes (K1[7:0], K2[7:3]) or K2[7:0] (when TOHP_K1K2_2OR1 = 1) in the receive
direction and report to the control interface (TOHP_RAPSBABLEE (Table 62), TOHP_RAPSBABLEM (Table 64))
when the K1 bytes are inconsistent. Inconsistent APS bytes are defined as TOHP_CNTDK1K2FRAME[3:0]
(Table 66) (default = 0xC) successive frames, starting with the last frame containing previously consistent code,
where no TOHP_CNTDK1K2[3:0] (default = 0x3) consecutive frames contain identical APS bytes.
Whenever the contents of TOHP_K2DMON[2:0] changes, a delta bit TOHP_K2DMOND (Table 62) will be set
(TOHP_K2DMONM (Table 64)). This event bit is only valid when TOHP_K1K2_2OR1 is a logic 0.
Whenever the register bit TOHP_RVALIDK_CTL (Table 67) is a logic 1, the received K1K2 bytes will be compared
with their reverse bytes for validation. Using the TOHP_CNTDK1K2[3:0] for the K1 byte and TOHP_CNTDK2[3:0]
for the K2 byte, the received K1K2 will be written to the output TOHP_K1DMON[7:0] and TOHP_K2DMON[7:0].
Otherwise, TOHP_K1DMON[7:0] and TOHP_K2DMON[7:0] will be updated every frame with new received K1[7:0]
and K2[7:0] bytes. (TOHP_K1K2_2OR1 has a higher priority.)
All continuous N-times detection counters will be reset to 0, if there are any received B1 errors and the register bit
TOHP_CNTDB1SEL (Table 67) is set to 1.
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Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Receive Direction
All monitoring functions supported by TOHP-48 in the receive direction are summarized here:
■
Input clock and loss-of-signal monitoring
■
Frame alignment and short frame
■
B1 BIP-8 check
■
J0/Z0 monitor
■
Descrambler
■
F1 monitor
■
B2 BIP-8xN check
■
APSMON and K2MON processing (including K1K2 validation and pass through)
■
AIS-L and RDI-L detect
■
MS-REI detect
■
Sync status monitor
■
Signal degrade BER algorithm
■
Signal fail BER algorithm
■
Transport overhead access channel (TOAC) drop
■
Insertion of AIS-L (MS-AIS)
Whenever the continuous N times detect (CNTD) signals are defined, they require not only that the monitored signal be consistent for N consecutive frames, but also that the frame bytes be error free for all N frames before the
status can be updated. If there are any errors in the framing pattern, then the consecutive N times detection
counters will reset to 0. N can range from 1 to 15. Programming a CNTD block with any value less than 1 will set
the CNTD to 1 time detect. The receive direction can be programmed into bypass mode bit TOHP_ROH_BYPASS
(Table 67), in which all 32-bit input data will be retimed and passed through without any processing. The four output sync signals are forced low in this mode.
Loss of Input Clock (LOC) and Loss of Signal (LOS) Monitoring
The TOHP-48 block detects and reports loss of input clock (LOC), as determined by stuck high or stuck low for
time T. The detection time T is greater than 6.58 µs. The state of monitoring is controlled by bits (TOHP_LOC[A—
D] (Table 63), TOHP_LOCD[A—D] (Table 62), and TOHP_LOCM[A—D] (Table 64)).
The TOHP-48 block detects and reports loss of signal (LOS) on the input data signal before descrambling, as
determined by stuck high or stuck low for time T. The detection time T is user programmable through
TOHP_LOSDETCNT[A—D][12:0] (Table 67), in steps of 8 (OC-3, OC-12) or 32 bits (OC-48) at a time with a range
of (51.44 ns to 421.4 µs) for OC-3 or (12.86 ns to 105.35 µs) for OC-12/OC-48, respectively. A value of zero disables the stuck high/low monitoring feature of LOS detection. An LOS is not reported unless a clock is present.
To recover from the LOS state, two consecutive frames must be received with the correct framing pattern spaced
125 µs apart and, during the intervening time (one frame), no all-zeros/ones pattern indicates an LOS defect.
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Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Receive Direction (continued)
Frame Alignment
Specification
The framer goes in frame if it finds two consecutive frames with the desired framing bytes and goes out of frame if
it finds five consecutive frames with at least one framing bit error in each frame.
The following framing bytes indicate frame integrity and are observed every 125 µs.
Table 49. Framing Bytes Observed for Framing Integrity
Interface
Sequence
OC-3
F6, 28
OC-12
F6, F6, 28, 28
OC-48 (32-bit)
F6, F6, 28, 28
OOF is declared after the fifth errored A1A1A2A2 pattern, and reported to the control system (TOHP_OOF
(Table 63), TOHP_OOFD (Table 62), and TOHP_OOFM (Table 64)).
After 24 continuous frames (3 ms) of OOF, the block will declare a loss of frame defect and report this state
(TOHP_LOF (Table 63), TOHP_LOFD (Table 62), and TOHP_LOFM (Table 64)).
Once set, the block will clear the LOF state after 24 consecutive frames (3 ms) of no OOF events with correct framing patterns spaced 125 µs apart.
B1 BIP-8 Check
A BIP-8 even parity is computed over the incoming scrambled data, and compared to the B1 byte received in the
next frame.
The total number of B1 BIP-8 bit errors (raw count), or block errors (as determined by bit TOHP_B1BITBLKCNT
(Table 67), is counted. Upon the performance-monitor latch control signal, the value of the counter is presented to
the control interface in a 16-bit counter, TOHP_B1ECNT[15:0] (Table 81). In case of overflow, the counter remains
at its maximum value until it is cleared. Host microprocessor is expected to clear the counter at least once a second.
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Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Receive Direction (continued)
J0/Z0 Monitor
J0 (section trace) monitoring has four different monitoring modes controlled by TOHP_J0MONMODE[1:0]
(Table 67):
■
J0MONMODE[1:0] = 00: The J0 byte of every frame is captured for 64 consecutive frames for a total of 64 bytes
(RJ0DMON[1—64][7:0] (Table 86)). The incoming J0 byte is compared with the next expected-value (the
expected value is obtained by cycling through the previous stored 64 received bytes in round-robin fashion) and
sets an event bit (J0MISE, J0MISM), if different.
■
J0MONMODE[1:0] = 01: This is the SONET framing mode. A J0 byte pattern of 0x0D followed by 0x0A character indicates that the next byte is the first byte of the path trace message. The J0 byte message is continuously
written into RJ0DMON[1—64][7:0] with the first byte residing at the first address. If any received byte does not
match the previously received byte for its location, then an event bit (J0MISE, J0MISM) is set.
■
J0MONMODE[1:0] = 10: This is the SDH framing mode. The first J0 byte with the MSB set to one indicates that
the next byte is the second byte of the message. The rest of operation is the same as in SONET framing mode.
■
J0MONMODE[1:0] = 11: A new J0 byte (RJ0DMON[1][7:0]) will be detected after CNTDJ0Z0[3:0] consecutive
consistent occurrences of a new pattern in the J0 overhead byte. Any changes to this byte is reported by
(J0MISE, J0MISM). This event bit acts as a delta bit in this mode indicating a change in state for the
RJ0DMON[1][7:0] byte.
Note: In OC-48 mode, the device will monitor the first three (2, 3, and 4) Z0 bytes using the CNTD mode of the J0
monitors.
Descrambler
A frame synchronous descrambler of length 127 and generating polynomial x7 + x6 +1 will descramble the entire
STS/STM signals except for the first row of overhead. The framing bytes (A1, A2), the section trace bytes (J0), and
the growth bytes (Z0) are not descrambled. The scrambler will be set to 1111111 on the first byte following the last
section OH byte in the first row (i.e., after byte J0 for STS-1, after the second Z0 for STS-3, etc.). The descrambler
operates in a byte wide mode for OC-3/OC-12 and a 32-bit-word wide mode for OC-48.
The frame descrambler can be disabled through TOHP_DSCRINH (Table 67).
F1 Monitor
The fault location byte TOHP_F1DMON0[7:0] (Table 85) is monitored by the F1 monitor. A new fault location state
is detected after TOHP_CNTDF1[3:0] (Table 66) consecutive consistent occurrences of a new pattern in the F1
overhead byte. A history of the previous valid F1 byte, TOHP_F1DMON1[7:0], is also maintained. Any changes to
this byte will be reported by bits TOHP_F1DMOND (Table 62) and TOHP_F1DMONM (Table 64).
B2 BIP-8xN Check
A BIP-8N even parity is computed over the incoming frame (except for rows 1, 2, and 3 of the section OH), and
compared to the N B2 bytes received in the next frame, (N = 3, 12, or 48). The total number of B2 BIP-8N bit errors
(raw count), or block errors as determined by TOHP_B2BITBLKCNT (Table 67) is counted. Upon a PM latch control signal PM_LATCH, the internal running counter is placed into a holding register TOHP_B2ECNTR (Table 82)
and then cleared. In case of overflow, the internal counter will stay at its maximum value until cleared.
The checker must output a per-frame error count (B2ECntPerF[7:0]), which is needed in the transmit direction to
form M1 byte. The count is truncated at 255 for OC-48.
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Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Receive Direction (continued)
APSMON and K2MON Processing (Including K1K2 Validation and Pass Through)
Note: The three least significant bits of the K2 byte take on different meaning depending on the linear APS mode or
ring status mode. Therefore, the integration is different.
The K1 byte will be stored in TOHP_K1DMON[7:0] (Table 85), while the K2 byte will be stored in
TOHP_K2DMON[7:0] (Table 85). The updating of these registers depends on mode bit TOHP_K1K2_2OR1
(Table 67), as follows:
■
When TOHP_K1K2_2OR1 = 0, the K1 and K2 byte registers will be updated after TOHP_CNTDK1K2[3:0]
(Table 66) consecutive frames of identical K1[7:0] and K2[7:3], i.e., the 13-bit pattern must be identical for
TOHP_CNTDK1K2[3:0] frames prior to updating the K1 and K2 registers. In this mode, the TOHP_K2DMON[2:0]
register will be updated after TOHP_CNTDK2[3:0] (Table 66) consecutive frames of identical K2[2:0].
■
When TOHP_K1K2_2OR1 = 1, the K1 and K2 byte registers will be updated after TOHP_CNTDK1K2[3:0] consecutive frames of identical K1[7:0] and K2[7:0], i.e., the 16-bit pattern must be identical for
TOHP_CNTDK1K2[3:0] frames prior to updating the registers.
Whenever the contents of the TOHP_K1DMON[7:0] and TOHP_K2DMON[7:3] (for TOHP_K1K2_2OR1 = 0) or
TOHP_K2DMON[7:0] (for TOHP_K1K2_2OR1 = 1) register changes, a delta bit TOHP_K1K2DMOND (Table 62)
will be set (TOHP_K1K2DMONM (Table 64)). This event bit is valid in both monitoring modes.
The block will monitor the APS bytes (K1[7:0], K2[7:3]) or K2[7:0] (when TOHP_K1K2_2OR1 = 1) in the receive
direction and report to the control interface (TOHP_RAPSBABLEE (Table 62), TOHP_RAPSBABLEM (Table 64))
when the K1 bytes are inconsistent. Inconsistent APS bytes are defined as TOHP_CNTDK1K2FRAME[3:0]
(Table 66) (default = 0xC) successive frames, starting with the last frame containing previously consistent code,
where no TOHP_CNTDK1K2[3:0] (default = 0x3) consecutive frames contain identical APS bytes.
Whenever the contents of TOHP_K2DMON[2:0] changes, a delta bit TOHP_K2DMOND (Table 62) will be set
(TOHP_K2DMONM (Table 64)). This event bit is only valid when TOHP_K1K2_2OR1 is a logic 0.
Whenever the register bit TOHP_RVALIDK_CTL (Table 67) is a logic 1, the received K1K2 bytes will be compared
with their reverse bytes for validation. Using the TOHP_CNTDK1K2[3:0] for the K1 byte and TOHP_CNTDK2[3:0]
for the K2 byte, the received K1K2 will be written to the output TOHP_K1DMON[7:0] and TOHP_K2DMON[7:0].
Otherwise, TOHP_K1DMON[7:0] and TOHP_K2DMON[7:0] will be updated every frame with new received K1[7:0]
and K2[7:0] bytes. (TOHP_K1K2_2OR1 has a higher priority.)
All continuous N-times detection counters will be reset to 0, if there are any received B1 errors and the register bit
TOHP_CNTDB1SEL (Table 67) is set to 1.
AIS-L and RDI-L Detect
The block will monitor for line AIS (AIS-L/MS-AIS) in the K2[2:0] bits. Line AIS will be detected and LAISMON will
be set to 1 after TOHP_CNTDK2[3:0] consecutive occurrences of K2[2:0] = 111. Once set, AIS-L will be cleared
after TOHP_CNTDK2[3:0] consecutive frames of K2[2:0] = 111. Any change to TOHP_LAISMON (Table 63) will be
reported (TOHP_LAISMOND (Table 62), TOHP_LAISMONM (Table 64)). This function is only valid when
TOHP_K1K2_2OR1 is a logic 0.
The block will also monitor for a remote defect indication (RDI-L/MS-RDI) condition in the K2[2:0] bits. A line RDI
condition will be detected, and TOHP_LRDIMON (Table 63) will be set to 1 after TOHP_CNTDK2[3:0] consecutive
occurrences of K2[2:0] = 110. Once set, RDI-L will be cleared after TOHP_CNTDK2[3:0] consecutive frames of
K2[2:0] = 110. Any change to TOHP_LRDIMON will be reported (TOHP_LRDIMOND (Table 62),
TOHP_LRDIMONM (Table 64)). This function is only valid when TOHP_K1K2_2OR1 is a logic 0.
All continuous N times detection counters will be reset to 0 if there are any received B1 errors and the register bit
TOHP_CNTDB1SEL (Table 67) is set to 1.
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Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Receive Direction (continued)
Multiplex Section Remote Error Indication (MS-REI) Detect
One byte (M1) is allocated for use as a MS-REI. For STS/STM signals, this byte conveys the count (in the range of
[0, 255]) of interleaved bit blocks that have been detected by the BIP-8xN (B2). For rates of STS-48/STM-16, this
value will be truncated to 255.
The block will allow access to the MS-REI errored bit count TOHP_M1ECNT[20:0] (Table 83), which is the accumulated error count from the M1 byte. This counter will hold at its maximum value and update when PMRST
(pin D7) transitions from a logic 0 to a logic 1.
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Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Receive Direction (continued)
Sync Status Monitor
The S1 byte is allocated for synchronization status. S1 bits 3 to 0 are used to convey a 4-bit code of which only six
patterns are defined with the remaining codes reserved for quality levels defined by individual administrations.
The S1 byte can be monitored in two modes: (1) as an entire 8-bit word or (2) as two 4-bit nibbles as programmed
by TOHP_S1MON8OR4CTL (Table 67) control bit.
■
TOHP_S1DMON8OR4CTL = 0 the associated state, delta, and mask registers are TOHP_S1DMON[7:0]
(Table 85), TOHP_S1DMON8D (Table 62), TOHP_S1DMON8M (Table 64), respectively.
■
TOHP_S1DMON8OR4CTL = 1 the associated state, delta, and mask registers are TOHP_S1DMON[7:4],
TOHP_S1DMON8D, TOHP_S1DMON8M (most significant nibble (MSN)), and TOHP_S1DMON[3:0],
TOHP_S1DMON4D (Table 62), TOHP_S1DMON4M (Table 64) (least significant nibble (LSN)), respectively.
A new value will be detected after TOHP_CNTDS1[3:0] (Table 66) consecutive occurrences of a consistent new
value in the incoming S1 byte. This value is used in both monitoring modes. An event bit TOHP_S1BABLEE
(Table 62) will be set (TOHP_S1BABLEM (Table 64)) if TOHP_CNTDS1BABLE[3:0] (Table 66) consecutive frames
pass without a validated message occurring. In 8-bit mode, the entire value is monitored for an inconsistent value;
while in 4-bit mode, only the LSN is monitored for an inconsistent value.
Signal Degrade BER Algorithm
A signal degrade state and change of state indication will be provided to the control interface (SD, SDD, and SDM).
This bit error rate algorithm can operate on either B1 or B2 errors (TOHP_SDB1B2SEL (Table 67)). Signal degrade
is declared when TOHP_SDLSET[6:0] (Table 71) or more bit errors in TOHP_SDNSSET[17:0] (Table 71) frames
occur TOHP_SDMSET[7:0] (Table 71) times out of TOHP_SDBSET[15:0] (Table 72) blocks (one block is equal to
one measurement period of TOHP_SDNSSET[17:0] frames), and it is removed when less than
TOHP_SDLCLEAR[3:0] (Table 73) bit errors in TOHP_SDNSCLEAR[17:0] (Table 71) frames occur
TOHP_SDMCLEAR[6:0] (Table 73) times out of TOHP_SDBCLEAR[15:0] (Table 74) blocks.
A TOHP_SDSET (Table 65) and TOHP_SDCLEAR (Table 65) one shot signal must be provided to force the BER
algorithm into the failed state or normal state, respectively.
The set parameters are used when SD = 0, and the clear parameters are used when SD = 1.
The above algorithm can detect bit error rates from 1 x 10–3 to 1 x 10–9.
Signal Fail BER Algorithm
A signal fail state and change of state indication will be provided to the control interface (SF, SFD, and SFM). This
bit error rate algorithm can operate on either B1 or B2 errors (TOHP_SFB1B2SEL(Table 67)). Signal fail is
declared when TOHP_SFLSET[7 (version 2.2 and version 2.3) 6 (version 2.0):0] (Table 75) or more bit errors in
TOHP_SFNSSET[17:0] (Table 75) frames occur TOHP_SFMSET[5 (version 2.2 and version 2.3) 6 (version 2.0):0]
(Table 75) times out of TOHP_SFBSET[15:0] (Table 76) blocks (one block is equal to one measurement period of
TOHP_SFNSSET[17:0] frames), and it is removed when less than TOHP_SFLCLEAR[3:0] (Table 77) bit errors in
TOHP_SFNSCLEAR[17:0] (Table 77) frames occur TOHP_SFMCLEAR[6:0] (Table 77) times out of
TOHP_SFBCLEAR[15:0] (Table 78) blocks.
A SFSET and SFCLEAR one shot signal must be provided to force the BER algorithm into the failed state or normal state, respectively.
The set parameters are used when SF = 0, and the clear parameters are used when SF = 1.
The above algorithm can detect bit error rates from 1 x 10–3 to 1 x 10–9.
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Receive Direction (continued)
TOAC Drop
The receive TOAC interface provides four TOAC output signals. Depending on the operation mode, the data rate
of TOAC channels is listed as follows:
■
Quad STS-3/STM-1. Four (1) TOAC channels, each at 5.184 Mbits/s.
■
Quad STS-12/STM-4. Four (1) TOAC channels, each at 20.736 Mbits/s.
■
Single STS-48/STM-16. Four (4) TOAC channels, each at 20.736 Mbits/s.
To form a higher-level signal STS-N (N = 3M; M = 1, 4, 16), M STS-3s are interleaved one byte at a time. The first
byte of the STS-N is the first A1 framing byte from STS-3 number 1 followed sequentially by the first A1 byte from
STS-3 number 2 through M. [The lowest bit rate signal for SDH is STM-1, which is equivalent to a SONET OC-3
signal. To form a higher-level STM-M (M = 1, 2, or 16), M administrative unit groups (AUG) are interleaved one
byte at a time. An AUG consists of either 1 AU-4 (STS-3c) or 3 AU-3s (STS-1).]
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Receive Direction (continued)
The following figure shows the time-slot byte interleaving sequence per STS-1.
STS-1
1
STS-1
2
3:1
STS-3/STM-1
3
2
1
STS-1
3
STS-1
4
STS-1
5
3:1
TIME
STS-3/STM-1
6
5
4
STS-1
6
STS-1
4:1
7
STS-1
8
3:1
STM-4
10 7 4 1 10 7 4 1 10 7 4 1
STS-3/STM-1
9
8
7
STS-12
STS-1
12 9 6 3 11 8 5 2 10 7 4 1
9
STS-1
10
STS-1
11
3:1
STS-3/STM-1
12
11
10
INTERLEAVING ORDER
STS-1
12
THE INTERLEAVING ORDER FOR A STS-48/STM-16 IS AS FOLLOWS:
STS-48
48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 47 44 41 38 35 32 29 26 23 20 17 14 11 8 5 2 46 43 40 37 34 31 28 25 22 19 16 13 10 7 4 1
STM-16
46 43 40 37 34 31 28 25 22 19 16 13 10 7 4 1 46 43 40 37 34 31 28 25 22 19 16 13 10 7 4 1 46 43 40 37 34 31 28 25 22 19 16 13 10 7 4 1
Figure 27. Time-Slot Assignments
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Receive Direction (continued)
The time-slot assignment for each TOAC channel is summarized in the following table.
Table 50. TOAC Channel Output Versus Time-Slot Assignment
Output Rate
TOAC Channel Outputs vs. Output Time Slot
A
B
321
C
321
D
STS-3/STM-1
321
321
STS-12/STM-4
12 9 6 3 11 8 5 2 10 12 9 6 3 11 8 5 2 10 12 9 6 3 11 8 5 2 10 12 9 6 3 11 8 5 2 10
741
741
741
741
STS-48/STM-16
39 27 15 3 38 26 14 42 30 18 6 41 29 17 45 33 21 9 44 32 20 48 36 24 12 47 35
2 37 25 13 1
5 40 28 16 4
8 43 31 19 7
23 11 46 34 22 10
The transport overhead access channel consists of the following signals:
■
Four 5.184/20.736 MHz clock signals, RXTOHCLK[A—D] pins AK5, AL4, AL6, and AL7, respectively.
■
Four 5.184/20.736 Mbits/s data signals, RXTOHD[A—D] pins AL2, AM5, AM6, and AN7, respectively.
■
Four 8 kHz synchronization signals, RXTOHF[A—D] pins AK4, AL3, AN5, and AP6, respectively.
An inhibit signal is provided through the control interface to force the clock, sync, and selected data signal to zero
(TOHP_RTOACCINH (Table 68), TOHP_RTOACSINH (Table 68), and TOHP_RTOACDINH (Table 68)).
The data signal is partitioned into frames of 81 bytes for STS-3 mode and 324 bytes for STS-12 or STS-48 modes.
The frame repetition rate is 8 kHz. Each byte consists of 8 bits that are transmitted/received most significant bit
first. The MSB of the first byte of each frame contains an odd/even parity bit over the 648 bits of the previous
frame. The remaining 7 bits of this byte are not specified.
■
Bytes shown in Table 51 summarize the access capabilities of the receive TOAC. Bytes indicated in bold type
are not specified in the standard, but are labeled here for clarity.
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Data Sheet
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Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Receive Direction (continued)
Table 51. Transport Overhead Bytes Received Via RxTOAC Interface*
Note: Numbers after - indicates byte number.
OH Parity A1-[2—12]
A2-1
A2-[2—12]
J0
Z0-[2—12]
B1-1
B1-[2—12]
E1-1
E1-[2—12]
F1-1
F1-[2—12]
D1-1
D1-[2—12]
D2-1
D2-[2—12]
D3-1
D3-[2—12]
H1-1
H1-[2—12]
H2-1
H2-[2—12]
H3-1
H3-[2—12]
B2-1
B2-[2—12]
K1-1
K1-[2—12]
K2-1
K2-[2—12]
D4-1
D4-[2—12]
D5-1
D5-[2—12]
D6-1
D6-[2—12]
D7-1
D7-[2—12]
D8-1
D8-[2—12]
D9-1
D9-[2—12]
D10-1
D10-[2—12] D11-1
D11-[2—12] D12-1
D12-[2—12]
S1
Z1-[2—12]
Z2-2
M1 (Z2-3)
Z2-[4—12]
E2-[2—12]
Z2-1
E2-1
* Each TOAC output will have the corresponding byte value assigned to the time slot being accessed. This example is for an STS-12 signal for
TOAC output.
Even or odd parity can be inserted into the first bit of the MSB byte of the TOAC outgoing frame, using register bits
(TOHP_RTOAC_OEPINS[A—D] (Table 68)).
Insertion of AIS-L (MS-AIS)
The TOH-48 block will automatically generate AIS-L (MS-AIS) when TOHP_LOS, TOHP_OOF, or TOHP_LOF
state bits (Table 63) are active and the appropriate inhibit signals are inactive or software insert TOHP_LAISINS
(Table 67) is active.
■
Failure signal is comprised of LINE_AIS_GENERATE and FRM_ERR value for continuous N-times detect
(CNTD) detectors, but only LINE_AIS_GENERATE for error counters.
The TOHP-48 block will start/stop generating AIS-L within 125 µs of the detection/absence of a failure condition.
AIS-L (MS-AIS) is generated as a valid section overhead and an all 1s pattern in the remainder of the signal.
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
Transmit Direction (to SONET/SDH line)
This block accepts a frame with payload data (SPE), path overhead (POH), and pointer information (H1—H3)
bytes inserted. All other overhead bytes are inserted by this block; therefore, the incoming frame may put a fixed
stuff value into these time slots. The only other control signal needed by the block along with the data is a frame
sync signal active high one clock cycle aligned the A1-1 byte time. A bypass mode is also supported in the transmit
direction. When TOHP_TOH_BYPASS (Table 69) is set high, all 32 bits input data will be passed through to output
unprocessed and the output sync signal is invalid.
This section is broken down into the following functional parts:
■
Transpose (OC-48) and divider (OC-3)
■
TOAC insert
■
Sync status byte (S1) insert
■
REI-L insert: M1
■
K1 and K2 insert (including validation and pass through)
■
AIS-L insert
■
B2 calculation and insert
■
F1 byte insert
■
B1 generate and error insert
■
Scrambler
■
J0/Z0 insert control
■
A2 error insert
All insert control functions that are inhibited will insert all 0s for SONET and all 1s for SDH into the outgoing byte.
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Data Sheet
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Transport Overhead Processor (TOHP-48) Block (continued)
Transmit Direction (to SONET/SDH line) (continued)
TOAC Insert
One transport overhead access channel (TOAC) is provided on-chip to provision the TOH portion of the outgoing
frame. The TOAC consists of the following signals:
■
A 5.184/20.736 MHz clock signal, sourced by the block (TTOACCLKO).
■
One 20.736 Mbits/s data signal received by the block in the transmit direction (TTOACDATAI).
■
An 8 kHz synchronization signal (TTOACSYNCO), sourced by this block. The sync signal is normally low; during
the first clock period of each frame coincident with the most significant bit of the first byte, the sync signal will go
high.
An inhibit signal is provided to place the clock and sync signal in a logic 0 state (TOHP_TTOACINH (Table 69)).
TOAC Channel Input Versus Time-Slot Assignments
Table 52. TOAC Channel Input Versus Time-Slot Assignments
Output Rate
TOAC Channel
Inputs vs. Input
Time Slot
STS-3/STM-1
1
STS-12/STM-4
741
STS-48/STM-16
34 31 28 25 22 19
16 13 10 7 4 1
The data signal is partitioned into frames of 324 bytes (except for OC-3). The frame repetition rate is 8 kHz. Each
byte consists of 8 bits that are received most significant bit first. The MSB of the first byte of each frame contains an
odd/even parity bit over the 648(OC-3)/2592(OC-12/OC-48) bits of the previous frame. The remaining 7 bits of this
byte are not specified. In mixed/quad STS-3/STS-12 mode, the TOAC input has byte multiplexed data from each
output signal (see Table 53, Table 54, and Table 55).
Table 53. TTOAC OC-3 Signal Definition*
OC-3 Mode Signal Format (Letters Indicate Port Designations)
OH Pty
K1-A†
X
K2-A†
J0-A†
J0-B†
J0-C†
J0-D†
X
†
F1-B
F1-C
†
†
X
E1-A
E1-B
E1-C
E1-D
F1-A†
D1-A
D1-B
D1-C
D1-D
D2-A
D2-B
D2-C
D2-D
D3-A
†
K1-C†
K2-C†
K1-D†
K2-D†
F1-D
D3-B
D3-C
D3-D
K1-B
K2-B†
D4-A/
K1-A†
D4-B/
K2-A†
D4-C/
K1-B†
D4-D/
K2-B†
D5-A/
K1-C†
D5-B/
K2-C†
D5-C/
K1-D†
D5-D/
K2-D†
D6-A
D6-B
D6-C
D6-D
D7-A
D7-B
D7-C
D7-D
D8-A
D8-B
D8-C
D8-D
D9-A
D9-B
D9-C
D9-D
D10-A
D10-B
D10-C
D10-D
D11-A
D11-B
D11-C
D11-D
D12-A
D12-B
D12-C
D12-D
†
†
†
†
E2-A
E2-B
E2-C
E2-D
X
S1-A
S1-B
S1-C
S1-D
* X = reserved bytes (4 bytes).
† Inserted via TOAC or TOHP registers.
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
Transmit Direction (to SONET/SDH line) (continued)
Table 54. TTOAC OC-12 Signal Definition
OC-12 Mode Signal Format (Letters Indicate Port Designations)
A B C D
A
B
C
D
A
B
C
D
A B C D A
B
C
D
A
B
C
D
A B C D
A
B
C
D
A
B
C
D
OH
Pty
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
J0
J0
J0
J0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
E1
E1
E1
E1
E1-2
E1-2
E1-2
E1-2
E1-3
E1-3
E1-3
E1-3
F1
F1
F1
F1
F1-2
F1-2
F1-2
F1-2
F1-3
F1-3
F1-3
F1-3
D1
D1
D1
D1
D1-2
D1-2
D1-2
D1-2
D1-3
D1-3
D1-3
D1-3
D2
D2
D2
D2
D2-2
D2-2
D2-2
D2-2
D2-3
D2-3
D2-3
D2-3
D3
D3
D3
D3
D3-2
D3-2
D3-2
D3-2
D3-3
D3-3
D3-3
D3-3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
K1
K1
K1
K1
K2
K2
K2
K2
X
X
X
X
K2
K2
K2
K2
K1
K1
K1
K1
X
X
X
X
D4
D4
D4
D4
D4-2
D4-2
D4-2
D4-2
D4-3
D4-3
D4-3
D4-3
D5
D5
D5
D5
D5-2
D5-2
D5-2
D5-2
D5-3
D5-3
D5-3
D5-3
D6
D6
D6
D6
D6-2
D6-2
D6-2
D6-2
D6-3
D6-3
D6-3
D6-3
D7
D7
D7
D7
D7-2
D7-2
D7-2
D7-2
D7-3
D7-3
D7-3
D7-3
D8
D8
D8
D8
D6-2
D6-2
D6-2
D6-2
D6-3
D6-3
D6-3
D6-3
D9
D9
D9
D9
D9-3
D9-3
D9-3
D9-3
D9-3
D9-3
D9-3
D9-3
D10 D10 D10 D10 D10-2 D10-2 D10-2 D10-2 D10-3 D10-3 D10-3 D10-3 D11 D11 D11 D11 D11-2 D11-2 D11-2 D11-2 D11-3 D11-3 D11-3 D11-3 D12 D12 D12 D12 D12-2 D12-2 D12-2 D12-2 D12-3 D12-3 D12-3 D12-3
S1
S1
S1
S1
Z1 -2
Z1 -2
Z1 -2
Z1 -2
Z1-3
Z1-3
Z1-3
Z1-3
Z2
Z2
Z2
Z2
Z2-2
Z2-2
Z2-2
Z2-2
Z2-4
Z2-4
Z2-4
Z2-4
E2
E2
E2
E2
E2-2
E2-2
E2-2
E2-2
E2-3
E2-3
E2-3
E2-3
Note: X = reserved bytes (99 bytes).
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Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
Transmit Direction (to SONET/SDH line) (continued)
Table 55. TTOAC OC-48 Signal Definition
OC-48 Mode Signal Format (Letters Indicate Port Designations)
OH
Pty
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
E1
E1-2 to 12
F1
F1-2 to 12
D2
D2-2 to 12
D3
D3-2 to 12
D1
D1-2 to 12
X
X
X
X
X
X
X
X
X
X
X
J0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
K1
K2
X
X
X
X
X
X
X
X
X
X
K2
K1 X
X
X
X
X X
X
X
X
X
D4
D4-2 to 12
D5
D5-2 to 12
D6
D6-2 to 12
D7
D7-2 to 12
D8
D8 -2 to 12
D9
D9-2 to 12
D10
D10-2 to 12
D11
D11-2 to 12
D12
D12-2 to 12
S1
Z1-2 to 12
E2
E2-2 to 12
Z2 Z2-2 X
Z2-4 to 12
Note: X = reserved bytes (115 bytes).
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
Transmit Direction (to SONET/SDH line) (continued)
In STS-48 mode, each TOAC input has access to those columns of overhead bytes as defined in Table 52.
■
An event indication is provided to indicate parity errors on the TOAC input channel. Odd (logic 0)/even (logic 1)
parity is checked (TOHP_TTOAC_OEPMON (Table 69), TOHP_TTOAC_PERRM (Table 64),
TOHP_TTOAC_PERRE (Table 62)).
Table 56 summarizes the insertion options for the specified overhead bytes for the transmit TOAC. A predefined
stuff value (all 0s for SONET and all 1s for SDH) or the corresponding TOAC value is inserted as shown in
Table 56.
Table 56. TTOAC Control Bits
Overhead Bytes
OC-3
OC-12
OC-48
Control Bits
(Table 69)
J0
TOHP_TTOAC_J0[A—D]
E1
TOHP_TTOAC_E1[A—D]
F1
TOHP_TTOAC_F1[A—D]
D1—D3
TOHP_TTOAC_D1TO3[A—D]
K1, K2[7:3]
TOHP_TTOAC_K1K2[A—D]
K2[2:0]*
TOHP_TK2SINS[A—D][1:0]
D4—D12
TOHP_TTOAC_D4TO12[A—D]
S1
TOHP_TTOAC_S1[A—D]
E2
TOHP_TTOAC_E2[A—D]
D1-[2-3]
to
D3, D3-[2-3]
D1-2, . . ., N to
D3-2, . . ., N
TOHP_TTOAC_INS
Values
0 (Default
Value)
1
SONET/SDH
(00000000/
11111111)
TTOAC
Data
SONET/SDH
(00000000/
11111111)
TTOAC
Data
D4-[2-3]
D4-2, . . ., N to
D12-2, . . ., N
to
D12, D12-[2-3]
E1-[2-3]
E1-2, . . ., E1-N
F1-[2-3]
F1-2, . . ., F1-N
E2-[2-3]
E2-2, . . ., E2-N
Z1-2, Z1-3
Z1-2, . . ., Z1-N
Z2-[2-3]
Z2-1, Z2-2
Z2-4, . . ., Z2-N
* When TOHP_TK2SINS[A—D][1:0] = 11 TOAC data is inserted into the outgoing k2[2:0] value; otherwise, the source of this value can come
from hardware, software, or raw K value.
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Data Sheet
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Transport Overhead Processor (TOHP-48) Block (continued)
Transmit Direction (to SONET/SDH line) (continued)
Sync Status Byte Insert
Via microprocessor control of TOHP_TS1INS (active-high) (Table 69) and TOHP_TS1DINS[7:0] (Table 84), data
information may be inserted into the outgoing S1 byte [9, 1, 1]. Direct microprocessor insert has higher priority than
the TOAC insert control bit (TOHP_TTOAC_S1(Table 69)).
REI-L (MS-REI): M1
One byte is allocated for use as an MS-REI. For STS-N/STM-M levels, this byte conveys the count (in the range of
[0, 255]) of interleaved bit blocks that have been detected in error by the BIP-24xM (B2) detector on the received
signal (B2ECntPerF[7:0]). For STS-48/STM-16 signals, this value is held at 255 if the received signal has more
than 255 BIP errors.
This function can be inhibited (TOHP_TM1_REIL_INH (Table 69)) and the default value inserted (STUFFBYTE[7:0]) via microprocessor control. A continuous error in the M1 byte can be inserted under user control
(TOHP_TM1_ERR_INS (Table 69)). A value of 0x03 is inserted when the TOHP_TM1_ERR_INS signal is active.
REI-L (MS-REI) is inserted into M1 byte as defined in the following figure.
23 (MSB)
0 (LSB)
Z2-1
Z2-2
M1
7 (MSB)
0 (LSB)
REI-L (MS-REI) [9, 2, 3]
5-8497(F)r.1
Figure 28. REI-L (MS-REI) Location
For STS-3/STM-1 signals, the M1 value is in the range of 0 to 24. For STS-12/STM-4 signals, the M1 value is in the
range of 0 to 96. For STS-48/STM-16 signals, the M1 value is in the range of 0 to 255 (truncated).
K1 and K2 Insert Control Parameters
Via microprocessor control (TOHP_TAPSINS = 1 (Table 70)) the K1 [5, 2, 1] and K2 [5, 3, 1] outgoing bytes are
written from TK1DINS[7:0] (Table 84) and TK2DINS[7:3] (Table 84), respectively. When TOHP_TAPSINS is logic 0,
K1[7:0] and K2[7:3] outgoing bytes are written from TX_RAWK[15:3]. Since TX_RAWK[15:0] is a multibyte register,
both values must be valid at the same time. When TOHP_TK2SINS[1] = 1 (Table 70), data from the
TOHP_TK2DINS[2:0] register is written into K2[2:0] (transmit K2 software insertion). For hardware insertion of RDIL (110) to be written to K2[2:0], set TOHP_TK2SINS[1:0] = 01. Otherwise, when TOHP_TK2SINS[1:0] = 00,
TX_RAWK[2:0] is written to K2[2:0].
When TOHP_TVALIDK_CTL (Table 70) is a logic 1, reversed K1 byte is written to K1 ([5, 2, 2] for OC-3/OC-12,
[5, 2, 5] for OC-48) and reversed K2 byte is written to K2 ([5, 3, 2] for OC-3/OC-12, [5, 3, 5] for OC-48). Otherwise,
K1 and K2 reverse bytes are written with default values (all 0s for SONET and all 1s for SDH).
APS babbling test control: Setting the TOHP_TAPSBABLEINS bit (Table 69), via microprocessor control, forces
the K1[7:0], K2[7:3) to an inconsistent state; no three consecutive values are the same continuously.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
Transmit Direction (to SONET/SDH line) (continued)
Line RDI is inserted into the data signal when one or more of the following occurs and the corresponding inhibit bit
is not set:
Input loss of clock (LOC)
Loss-of-signal (LOS)
Out-of-frame (OOF)
Loss-of-frame (LOF)
Line AIS (LAISMON)
Signal fail (BER algorithm) (SF)
When a failure condition exists that will cause RDI-L to be generated, the generation of RDI-L will last for at least
20 frames before clearing; even if the original failure cause has cleared in less than 20 frames. This function can
be inhibited by setting TOHP_TIMER_LRDIINH (Table 69) to a logic 1.
AIS Line/MS-AIS Generation
Line AIS/MS-AIS is specified as all 1s in the entire STS/STM signal before scrambling, excluding the section overhead (RSOH).
Line AIS can be generated via microprocessor control on a per STS-1 basis (TOHP_TAISLINS[48:1] (Table 70)).
For a concatenated or STM type signal, the user must determine which time slots should be provisioned to generate a valid AIS signal.
B2 BIP 8XN Calculation and Insert
The B2 bytes are allocated for a line overhead (multiplex section) error monitoring function. This function will be a
bit interleaved parity N X 8 code (BIP-N X 8) using even parity. The BIP-N X 8 is computed over all bits of the previous STS-N/STM-M frame except the first three rows of SOH (RSOH) and is placed in bytes B2 of the current
frame before scrambling. N = 3M and M = 1, 4, and 16.
Via microprocessor control all B2 bytes can be inverted (TOHP_TB2ERRINS (Table 69)).
F1 Byte Insert
Via microprocessor control of TOHP_TF1INS (Table 69) and TOHP_TF1DINS[7:0] (Table 84), data information
may be inserted into the outgoing F1 byte[2, 3, 1]. Direct microprocessor insert has higher priority than the TOAC
insert control bit (TOHP_TTOAC_F1 (Table 69)).
When TOHP_TF1INS is a logic 1, insert the value in register TOHP_TF1DINS[7:0]; otherwise, insert the associated TOAC value when TOHP_TTOAC_F1 is a logic 1 or insert the default value of all zeros for SONET and all
ones for SDH when TOHP_TTOAC_F1 is logic 0.
B1 Generate and Error Insert
The section bit interleaved parity code (BIP-8) byte—this is a parity code (even parity), used to check for transmission errors over a section. Its value is calculated over all bits in the previous frame after scrambling, and then
placed in the B1 byte of time slot 1 before scrambling.
Via microprocessor control the B1 byte can be inverted (TOHP_TB1ERRINS (Table 69)).
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Data Sheet
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Transport Overhead Processor (TOHP-48) Block (continued)
Transmit Direction (to SONET/SDH line) (continued)
Scrambler
The outgoing frame will be scrambled with the frame synchronous scrambler of length 127 and generating polynomial x7 + x6 + 1. The entire STS/STM signal will be scrambled except for the first row of overhead. The scrambler
will be set to 1111111 on the first byte following the last overhead byte in the first row.
For test purposes, the scrambler will be disabled when TOHP_SCRINH (Table 69) is a logic 1.
J0/Z0 Insert Control
A 16-byte sequence stored in registers TOHP_TJ0DINS[1—16][7:0] (Table 87) will be inserted into the outgoing J0
byte if TOHP_TJ0INS (Table 69) is set to logic 1; otherwise, the associated TOAC value is inserted when
TOHP_TTOAC_J0 (Table 69) is a logic 1 or the default value is inserted when TOHP_TTOAC_J0 is logic 0.
A programmable value is inserted into each Z0 byte. The values are stored in registers TOHP_TZ0DINS[A—D][3—
2][7:0] (Table 88) for OC-3 mode and TOHP_TZ0DINS[A—D][12—2][7:0] for OC-12 mode. In OC-48 mode, there
are 47 Z0 bytes that are stored in {TOHP_TZ0DINS[D][12—2], TOHP_TJ0INS[D][1], TOHP_TZ0DINS[C][12—2],
TOHP_TJ0INS[C][1], TOHP_TZ0DINS[B][12—2], TOHP_TJ0INS[B][1], and TOHP_TZ0DINS[A][12—2]}.
A2 Error Insert
From 1 to 32 continuous outgoing (TOHP_TA1A2ERRINS[4:0] (Table 69), TOHP_TA1A2ERREN (Table 65))
frames can have inverted A2-1 (0x28 to 0xD7) pattern. The value in the TOHP_TA1A2ERRINS[4:0] register specifies the number of frames to insert errors into, while the TOHP_TA1A2ERREN one-shot register starts the error
insertion process.
Receive/Transmit TOHP-48 Interface
All receive transport overhead bytes are output on the RTOH interface for external processing needs. All transmit
transport overhead bytes can optionally be inserted from the TTOH interface for external needs.
Table 57. Rx/Tx TOHP-48 Interface Rates
Rate Selection R/T
(TOHP_RX_MODE[1:0]/
TOHP_TX_MODE[1:0] 0x0800 (Table 60))
Mode
Rx/Tx TOHP-48 Interface Rate
1X
OC-48
20,736,000* baud
01
OC-12
20,736,000 bits/s
00
OC-3
5,184,000 bits/s
* This OC-48 interface is a four-line interface resulting in an effective interface rate of 82,944,000 bits/s.
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
Receive/Transmit TOHP-48 Interface (continued)
RXTOHCLK[A—D]
RXTOHF[A—D]
RXTOHD[A—D]
E2#34[0]
OH PARITY[7]
X[6]
OC-48 MODE
E2—3D[0]
OH PARITY[7]
X[6]
OC-12 MODE
E2—3[0]
OH PARITY[7]
X[6]
OC-3 MODE
5-7419(F)r.5U
Note: Numbers in brackets denote bits. X[number] indicates a reserved bit.
Figure 29. RTOH Interface
TXTOHCLK
TXTOHF
TXTOHD
E2#34[0]
OH PARITY[7]
X[6]
OC-48 MODE
E2—3D[0]
OH PARITY[7]
X[6]
OC-12 MODE
X[0]
OH PARITY[7]
X[6]
OC-3 MODE
5-7420(F)r.4U
Note: Numbers in brackets denote bits. X[number] indicates a reserved bit.
Figure 30. TTOH Interface
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Data Sheet
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Transport Overhead Processor (TOHP-48) Block (continued)
Transport Overhead Access Channel (TOAC) Interface Timing
Transport overhead access channel (TOAC) interface timing specifications are given for the transmit direction in
Figure 31 and in Table 58, and for the receive direction in Figure 32 and in Table 59.
33%
OUTPUT—TXTOHCLK
DUTY CYCLE CLOCK
5.184 MHz (STS-3/STM-1)
20.736 MHz (STS-12/STM-4)
(STS-48/STM-16)
67%
50%
0.75tCP*
50%
50%
50%
50%
50%
33%
67%
tCP
tTTSDU
tTTDH
INPUT—TXTOHD
tTTFSPD
OUTPUT—TXTOHF 8 kHz
0151(F)r.4
Note: Duty cycles shown are nominal.
* tCP = x/y where y is the clock frequency in MHz on the TXCLKP/N pins and x = 32 for OC-3 and OC-12. For OC-48, x = 8.
Figure 31. STS-3/STM1, STS-12/STM-4, and STS-48/STM-16 Transmit TOAC Interface Timing
Table 58. Transmit TOAC Interface Timing Specifications
Symbol
Test Conditions
Setup
(Min)
Hold
(Min)
tTTDSU
tTTDH
tTTFSPD
—
—
CL = 50 pF
10
—
—
—
10
—
33%
OUTPUT—RXTOHCLK[D—A]
DUTY CYCLE CLOCK
20.736 MHz (STS-12/STM-4)
(STS-48/STM-16)
67%
0.75tCP*
Propagation Delay
(Min)
(Max)
—
—
0
—
—
10
50%
50%
50%
Unit
ns
ns
ns
50%
50%
50%
33%
67%
tCP
tRTDPD
RXTOHD[D—A]
OUTPUTS
tRTFSPD
RXTOHF[D—A] 8 kHz
0152(F)r.2
Note: Duty cycles shown are nominal.
* tCP = x/y where y is the clock frequency in MHz on the TXCLKP/N pins and x = 32 for OC-3 and OC-12. For OC-48, x = 8.
Figure 32. STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
Transport Overhead Access Channel (TOAC) Interface Timing (continued)
33%
67%
50%
50%
50%
50%
50%
50%
33%
67%
OUTPUT—RXTOCLK[D—A]
DUTY CYCLE CLOCK
5.184 MHz (STS-3/STM-1)
tCP
0.75tCP*
tRTDPD
RXTOHD[D—A]
OUTPUTS
tRTFSPD
RXTOHF[D—A] 8 kHz
0153(F)r.4
Note: Duty cycles shown are nominal.
* tCP = x/y where y is the clock frequency in MHz on the TXCLKP/N pins and x = 32 for OC-3 and OC-12. For OC-48, x = 8.
Figure 33. STS-3/STM-1 Receive TOAC Interface Timing
Table 59. Receive TOAC Interface Timing Specifications
Symbol
tRTDPD
tRTFSPD
Test Conditions
CL = 50 pF
CL = 50 pF
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Propagation Delay
(Min)
(Max)
0
0
10
10
Unit
ns
ns
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Data Sheet
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Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions
To access (read and write) registers RXCLK[A—D][P/N] (see Pin Descriptions—Line Interface Signals, Table 7 on
page 97) must always be present for a given application.
Note:Parameters of more than 16 bits are made up of 32-bit register pairs (Table 75, Table 77). Each pair gets written at the same time.
Two consecutive writes are needed to complete a write to these registers. For example, when writing
address 0x0852, the data is held in a shadow register; when writing address 0x0853, the data gets written in
0x0853 and at the same time, the data in the shadow register is transferred to address 0x0852.
When reading, the registers are accessed without using the shadow register and are read one at a time.
Table 60. TOHP_MODE_VERR, Mode (R/W) and Block Version (RO)
Address
Bit
0x0800
15:13
Name
Function
Reset
Default
TOHP_RX_MODE[2:0] Receive Direction Mode. TOHP_RX_MODE[2], bit
15, has two functions: default value for the registers
and the number of errored frames required before
declaring and OOF condition in the framer.
011
[2] 1 = SDH, 0 = SONET
[1] 1= OC-48, 0 = OC-3/12
[0] 1 = OC-12, 0 = OC-3
12:10
TOHP_TX_MODE[2:0] Transmit Direction Mode. TOHP_TX_MODE[2], bit
12, has two functions: default value for the registers
and the number of errored frames required before
declaring and OOF condition in the framer.
011
[2] 1 = SDH, 0 = SONET
[1] 1 = OC-48, 0 = OC-3/12
[0] 1 = OC-12, 0 = OC-3
9:0
TOHP_VER[9:0]
Block Version Number. Block version register will
change each time the device is changed.
0000000
001
Table 61. TOHP_CH_INT, Channel Interrupt (R/W, RO)
Address
Bit
Name
0x0801
15
TOHP_CORWN
14:12
—
11:8
208
Function
Reset
Default
Clear on Read/(Not) Write. 1 = COR, 0 = COW.
Reserved.
0x0
TOHP_INTH[D—A] High Interrupt (RO). Active-high interrupt bits for channel D to A. Each bit is the ORing of all event and delta
signals of OOF, LOF, LOS, and LOC of that channel
(Table 62).
7:4
—
3:0
TOHP_INTL[D—A]
0
0x0
Reserved.
0x0
Low Interrupt (RO). Active-high interrupt bits for channel D to A. Each bit is the ORing of all event and delta of
all monitoring features, i.e., TOHP_K2DMON
(Table 85), of that channel.
0x0
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 62. TOHP_DLT_EVT[A—D][1—2], 0x0802—0x0809, Delta/Event Registers (COR/COW-RO)
Address
Bit
0x0802,
0x0804,
0x0806,
0x0808
15
TOHP_LRDIMOND Line/Multiplex RDI Delta. Delta bit indicates a change of state 1, 1, 1,
1
[A—D]
for the line/multiplex RDI state bits, TOHP_LRDIMON[A—D].
The delta bits clear when read. Their mask bits are
TOHP_LRDIMONM[A—D]. In STS-48 mode, only
TOHP_LRDIMOND[A] is valid.
14
TOHP_LAISMOND
[A—D]
13
TOHP_
RAPSBABLEE
[A—D]
Function
Reset
Default
1, 1, 1,
Line/Multiplex AIS Delta. Delta bit indicates a change of
1
states for the line/multiplex AIS state bits
TOHP_LAISMON[A—D]. The delta bits clear when read. Their
mask bits are TOHP_LAISMONM[A—D]. In STS-48 mode,
only TOHP_LAISMOND[A] is valid.
APS Babble Event Bit. Each bit is active-high to indicate the
inconsistence in K1 byte of that channel. Their mask bits are
TOHP_RAPSBABLEM[A—D]. In STS-48 mode, only
TOHP_RAPSBABLEE[A] is valid.
0, 0, 0,
0
12
TOHP_S1DMON4D Delta Register for S1DMON[3:0] When S1MON8or4CTL = 1. 0, 0, 0,
[A—D]
Each delta bit indicates a change of state for
0
TOHP_S1DMON[3:0] in its channel. The delta bit clears when
read. Their mask bits are TOHP_S1DMON4M[A—D]. In
STS-48 mode, only TOHP_S1DMON4D[A] is valid.
11
TOHP_S1DMON8D Delta Register for S1DMON[7:4] When S1MON8or4CTL = 1 0, 0, 0,
0
[A—D]
or S1DMON[7:0] When S1MON8or4CTL = 0. Each delta bit
indicates a change of state for TOHP_S1DMON[7:4]/
TOHP_S1DMON[7:0] in its channel. The delta bit clears when
read. Their mask bits are TOHP_S1DMON8M[A—D]. In
STS-48 mode, only S1DMON8D[A] is valid.
10
TOHP_K2DMOND
[A—D]
9
0x0802
Name
K2[2:0] Data Monitor Delta Bit. Each bit is active-high to indi- 0, 0, 0,
0
cate a change in TOHP_K2DMON[A—D] for that channel.
These bits will clear when read or write. Their mask bits are
TOHP_K2DMONM[A—D]. In STS-48 mode, only
TOHP_K2DMONE[A] is valid.
0, 0, 0,
TOHP_K1K2DMOND K1K2 Data Monitor Delta Bit. Each bit is active-high to indi0
[A—D]
cate a change in (K1[7:0] and K2[7:3]) or (K1[7:0] and K2[7:0])
for that channel depending on K1K2_2OR1. Their mask bits
are TOHP_K1K2DMONM[A—D]. In STS-48 mode, only
TOHP_K1K2DMONE[A] is valid.
8
TOHP_F1DMOND
[A—D]
7
TOHP_
TTOAC_PERRE
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F1 Data Monitor Delta Bit. Their mask bits are
TOHP_F1DMONM[A—D]. In STS-48 mode, only
TOHP_F1DMOND[A] is valid.
0, 0, 0,
0
Transmit TOAC Parity Error Event. Event register indicates a 1, 0, 0,
parity error was detected on the incoming TOAC.
0
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Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 62. TOHP_DLT_EVT[A—D][1—2], 0x0802—0x0809, Delta/Event Registers (COR/COW-RO) (continued)
Address
Bit
Name
Function
Reset
Default
0x0802,
0x0804,
0x0806,
0x0808
6
TOHP_
S1BABLEE[A—D]
Receive S1 Byte Babbling Event. This event register will be
set if TOHP_CNTDS1BABLE[A—D][3:0] consecutive frames
pass without a validated S1 byte.
0, 0, 0,
0
5
TOHP_SFD[A—D]
Signal Fail BER Algorithm Delta. Delta bit indicates a
change of state for the signal fail BER algorithm state bits
TOHP_SF[A—D]. The delta bits clear when read. Their mask
bits are TOHP_SFM[A—D]. In STS-48 mode, only
TOHP_SFD[A] is valid.
1, 1, 1,
1
4
TOHP_SDD[A—D] Signal Degrade BER Algorithm Delta. Delta bit indicates a
change of states for the signal degrade BER algorithm state
bits TOHP_SD[A—D]. The delta bits clear when read. Their
mask bits are TOHP_SDM[A—D]. In STS-48 mode, only
TOHP_SDD[A] is valid.
0x0802,
0x0804,
0x0806,
0x0808
0x0803,
0x0805,
0x0807,
0x0809
210
1, 1, 1,
1
3
TOHP_OOFD
[A—D]
Receive Out of Frame Delta. Delta bit indicates change of
state for the out-of-frame TOHP_OOF[A—D]. The delta bits
clear when read. Their mask bits are TOHP_OOFM[A—D]. In
STS-48 mode, only TOHP_OOFD[A] is valid.
1, 0, 0,
0
2
TOHP_LOFD
[A—D]
Receive Loss of Frame Delta. Delta bit indicates change of
state for the loss-of-frame TOHP_LOF[A—D]. The delta bits
clear when read. Their mask bits are TOHP_LOFM[A—D]. In
STS-48 mode, only TOHP_LOFD[A] is valid.
1, 0, 0,
0
1
TOHP_LOSD
[A—D]
Receive Loss of Signal Delta. Delta bit indicates change of
state for the loss-of-signal TOHP_LOS[A—D]. The delta bits
clear when read. Their mask bits are TOHP_LOSM[A—D]. In
STS-48 mode, only TOHP_LOSD[A] is valid.
1, 1, 1,
1
0
TOHP_LOCD
[A—D]
Receive Loss of Clock Delta. Delta bit indicates change of
states for the loss-of-clock TOHP_LOC[A—D]. The delta bits
clear when read. Their mask bits are TOHP_LOCM[A—D]. In
STS-48 mode, only TOHP_LOCD[A] is valid.
1, 1, 1,
1
15:2
—
1
TOHP_TTOAC_
K1K2ERRE[A—D]
0
TOHP_J0MISE
[A—D]
Reserved.
000
0000
0000
000
Transmit TOAC K1and K2 Error Event. Event bits indicate
when an error is detected between the true and complement
K1/K2 values. Their mask bits are
TOHP_TTOAC_K1K2ERRM[A—D]. In STS-48 mode, only
TOHP_TTOAC_K1K2ERRE[A] is valid.
0
J0 Mismatch Event Bits. Their mask bits are
TOHP_J0MISM[A—D]. In STS-48 mode, only
TOHP_J0MISE[A] is valid for J0 byte while
TOHP_J0MISE[D—B] are used for Z0 bytes as
TOHP_Z0DMOND[D—B][1].
1
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 63. TOHP_RX_TX_STATE[A—D], 0x080A—0x080D, Receive/Transmit State Registers (RO)
Address
Bit
Name
Function
Reset
Default
0x080A—
0x080D
15
TOHP_LRDIMON[A—D]
Line/Multiplex RDI State Bit. In STS-48 mode,
only TOHP_LRDIMON[A] is valid.
0
14
TOHP_LAISMON[A—D]
Line/Multiplex AIS State Bit. In STS-48 mode,
only TOHP_LAISMON[A] is valid.
0
13:7
—
Reserved.
0
6
TOHP_TLRDIINT[A—D]
Transmit Line RDI Insert State Bit. State bit for
inserting line RDI value into the K2[2:0] bits. In
STS-48 mode, only TOHP_TLRDIINT[A] is valid.
0
5
TOHP_SF[A—D]
Signal Fail State Bit. In STS-48 mode, only
TOHP_SF[A] is valid.
0
4
TOHP_SD[A—D]
Signal Degrade State Bit. In STS-48 mode,
only TOHP_SD[A] is valid.
0
3
TOHP_OOF[A—D]
Out-of-Frame. Active-high out-of-frame state
bit. In STS-48 mode, only TOHP_OOF[A] is
valid.
0
2
TOHP_LOF[A—D]
Loss-of-Frame. Active-high loss-of-frame state
bit. In STS-48 mode, only TOHP_LOF[A] is valid.
0
1
TOHP_LOS[A—D]
Loss-of-Signal. Active-high loss-of-signal state
bit. In STS-48 mode, only TOHP_LOS[A] is
valid.
0
0
TOHP_LOC[A—D]
Loss-of-Clock. Active-high loss-of-clock state
bit. In STS-48 mode, only TOHP_LOC[A] is
valid.
0
When a loss-of-clock is detected for a line interface, associated status registers for that line
interface may not be updated.
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Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 64. TOHP_MSK[A—D][1—2], 0x080E—0x0815, Mask Bit Registers (R/W)
Address
Bit
Name
0x080E,
0x0810,
0x0812,
0x0814
15
TOHP_LRDIMONM
[A—D]
Line/Multiplex RDI Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In
STS-48 mode, only TOHP_LRDIMONM[A] is valid.
1
14
TOHP_LAISMONM
[A—D]
Line/Multiplex AIS Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In
STS-48 mode, only TOHP_LAISMONM[A] is valid.
1
13
TOHP_RAPSBABLEM
[A—D]
APS Babble Mask Bit. A 1 masks the corresponding
occurrence of the alarm to the interrupt. In STS-48
mode, only TOHP_RAPSBABLEM[A] is valid.
1
12
TOHP_S1DMON4M
[A—D]
Mask Bit for S1DMON4D When S1MON8or4CTL = 1.
A 1 masks the corresponding occurrence of the alarm to
the interrupt. In STS-48 mode, only
TOHP_S1DMON4LSNM[A] is valid.
1
11
TOHP_S1DMON8M
[A—D]
Mask Bit for S1DMON8D. A 1 masks the corresponding
occurrence of the alarm to the interrupt. In STS-48
mode, only TOHP_S1DMON8M[A] is valid.
1
10
9
Function
Reset
Default
TOHP_K2DMONM[A—D] K2[2:0] Data Monitor Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In
STS-48 mode, only TOHP_K2DMONM[A] is valid.
TOHP_K1K2DMONM
[A—D]
K1K2 Data Monitor Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In
STS-48 mode, only TOHP_K1K2DMONM[A] is valid.
1
1
8
TOHP_F1DMONM[A—D] F1 Data Monitor Mask Bit. A 1 masks the corresponding occurrence of the alarm to the interrupt. In STS-48
mode, only TOHP_F1DMONM[A] is valid.
1
0x080E
7
TOHP_TTOAC_PERRM Transmit TOAC Parity Error Mask. A 1 masks the corresponding occurrence of the alarm to the interrupt. All
4 bits are valid in every mode.
1
0x080E,
0x0810,
0x0812,
0x0814
6
TOHP_S1BABLEM
[A—D]
S1 Babbling Mask Bit. A 1 masks the corresponding
occurrence of the alarm to the interrupt. In STS-48
mode, only TOHP_S1BABLEM[A] is valid.
1
5
TOHP_SFM[A—D]
Signal Fail Mask Bit. Active-high signal fail mask bit. In
STS-48 mode, only TOHP_SFM[A] is valid.
1
4
TOHP_SDM[A—D]
Signal Degrade Mask Bit. Active-high signal degrade
mask bit. In STS-48 mode, only TOHP_SDM[A] is valid.
1
3
TOHP_OOFM[A—D]
Out-of-Frame Mask Bit. Active-high out-of-frame mask
bit. In STS-48 mode, only TOHP_OOFM[A] is valid.
1
2
TOHP_LOFM[A—D]
Loss-of-Frame Mask Bit. Active-high loss-of-frame
mask bit. In STS-48 mode, only TOHP_LOFM[A] is valid.
1
1
TOHP_LOSM[A—D]
Loss-of-Signal Mask Bit. Active-high loss-of-signal
mask bit. In STS-48 mode, only TOHP_LOSM[A] is valid.
1
0
TOHP_LOCM[A—D]
Loss-of-Clock Mask Bit. Active-high loss-of-clock mask
bit. In STS-48 mode, only TOHP_LOCM[A] is valid.
1
212
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 64. TOHP_MSK[A—D][1—2], 0x080E—0x0815, Mask Bit Registers (R/W) (continued)
Address
Bit
Name
0x080F,
0x0811,
0x0813,
0x0815
15
TOHP_INTM[A—D]
14:2
—
1
TOHP_TTOAC_
K1K2ERRM[A—D]
0
TOHP_J0MISM[A—D]
Function
Interrupt Mask Bit. A 1 masks the alarm to the interrupt.
Reserved.
Reset
Default
1
00
0000
0000
000
Transmit TOAC K1 and K2 Error Mask Bits. Activehigh. Transmit TOAC K1 and K2 error mask bits. In
STS-48 mode, only TOHP_TTOAC_K1K2ERRM[A] is
valid.
1
J0 Mismatch Mask Bit. A 1 masks the alarm to the
TOHP_INTL[D—A] (Table 61) interrupt.
1
Table 65. TOHP_TRG[A—D], 0x0816—0x0819, Trigger Register 0 → 1 (R/W)
Address
Bit
Name
Function
Reset
Default
0x0816—
0x0819
15:12
TOHP_RST_SWRS
[A—D][3:0]
Software Reset. For channels A to D, to enable
software reset, write TOHP_RST_SWRS
[A—D][3:0] to 1100 (0xC) and then write it to 0 to
release the reset.
0x0
11:5
—
4
TOHP_TA1A2ERREN
[A—D]
Transmit A1/A2 Error Enable. Enable signal to
start the insertion of A2 errors in the outgoing
frame. The number of consecutive errors is controlled by TOHP_TA1A2ERRINS[4:0].
TOHP_TA1A2ERREN[A] is valid in STS-48
mode.
0
3
TOHP_SFCLEAR[A—D]
Signal Fail Clear. Allows the signal fail algorithm
to be forced into the normal state.
0
2
TOHP_SFSET[A—D]
Signal Fail Set. Allows the signal fail algorithm to
be forced into the failed state.
0
1
TOHP_SDCLEAR[A—D]
Signal Degrade Clear. Allows the signal degrade
algorithm to be forced into the normal state.
0
0
TOHP_SDSET[A—D]
Signal Degrade Set. Allows the signal degrade
algorithm to be forced into the degraded state.
0
Agere Systems Inc.
Reserved.
0000
000
213
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 66. TOHP_CNTD[A—D][1—2], 0x081A—0x0821, Continuous N-Times Detect (CNTD) Values (R/W)
Address
Bit
Name
Function
Reset
Default
0x081A,
0x081C,
0x081E,
0x0820
15:12
TOHP_CNTDK2
[A—D][3:0]
Continuous N-Times Detect for K2[2:0] Byte.
The valid range for this register is 0x3-0xF.
Invalid values will be mapped to a value of 0x3.
In STS-48 mode, CNTDK2[A] is valid.
0x3
11:8
TOHP_CNTDK1K2
[A—D][3:0]
Continuous N-Times Detect for APS (K1,
K2[7:3]) Byte. The valid range for this register is
0x3—0xF. Invalid values will be mapped to a
value of 0x3. In STS-48 mode, CNTDK1K2[A] is
valid.
0x3
7:4
0x081B,
0x081D,
0x081F,
0x0821
TOHP_CNTDF1[A—D][3:0] Continuous N-Times Detect for F1 Byte. The
valid range for this register is 0x3—0xF. Invalid
values will be mapped to a value of 0x3. In
STS-48 mode, CNTDF1[A] is valid.
0x3
3:0
TOHP_CNTDJ0Z0
[A—D][3:0]
Continuous N-Times Detect for J0Z0 Bytes.
The valid range for this register is 0x3—0xF.
Invalid values will be mapped to a value of 0x3.
In STS-48 mode, CNTDJ0Z0[A] is valid.
0x3
15:13
—
Reserved. Applies for version 2.2 and 2.3 only.
0x0
12
—
APS Babble. Applies for version 2.2 and 2.3
only.
0 = Use either K1 and K2[7:3] or K1 and K2[7:0]
1 = K1 only
15:12
—
11:8
7:4
3:0
214
Reserved. Applies for version 2.0 only.
0x0
TOHP_CNTDS1BABLE
[A—D][3:0]
Continuous N-Times Detect for S1 Byte Babbling. The valid range for this register is 0x3—
0xF. Invalid values will be mapped to a value of
0x3. In STS-48 mode,
TOHP_CNTDS1BABLE[A] is valid.
0x5
TOHP_CNTDS1
[A—D][3:0]
Continuous N-Times Detect for S1 Byte. The
valid range for this register is 0x3—0xF. Invalid
values will be mapped to a value of 0x3. In
STS-48 mode, TOHP_CNTDS1[A] is valid.
0x3
TOHP_CNTDK1K2FRAME Continuous N-Times Detect for APS Frame.
[A—D][3:0]
The valid range for this register is 0x3—0xF.
Invalid values will be mapped to a value of 0x3.
In STS-48 mode, TOHP_CNTDK1K2FRAME[A]
is valid.
0xC
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 67. TOHP_RCTL[A—D][1—2], 0x0822—0x0829, Receive Control [1—2] (R/W)
Address
Bit
Name
0x0822,
0x0824,
0x0826,
0x0828
15:14
TOHP_J0MONMODE
[A—D][1:0]
Function
J0 Monitoring Mode. There are four modes as
defined in the document. All four parameters
TOHP_J0MONMODE[A—D] need to be set in
STS-48 mode.
Reset
Default
00
00 = The TOHP-48 will latch the value of the J0
byte every frame for a total of 16 bytes. The
TOHP-48 will compare the incoming J0 byte
with the next expected value (the expected
value is obtained by cycling through the
previously stored 16 received bytes in
round-robin fashion) and set the event bit if
different.
01 = This is the SONET-framing mode. The
hardware looks for 0x0D followed by 0x0A
to indicate that the next byte is the first byte
of the path trace message. The J0 byte is
continuously written into TOHP_RJ0DMON
(Table 86) with the first byte residing at the
first address. If any received byte does not
match the previously received byte for its
location, then the event bit is set.
10 = This is the SDH-framing mode. The hardware looks for the byte with the MSB set to
1, which indicates that the next byte is the
second byte of the message. The rest of the
operation is the same as the SONET framing mode.
11 = A new J0 byte TOHP_RJ0DMON[1][7:0] will
be detected after TOHP_CNTDJ0Z0[3:0]
(Table 66) consecutive consistent occurrences of a new pattern in the J0 overhead
byte. Any changes to this byte are reported
to TOHP_J0MISE[A—D] (Table 62) and
TOHP_J0MISM[A—D] (Table 64). These
event bits will act as delta bits indicating a
change of state for the
TOHP_RJ0DMON[1][7:0].
13
TOHP_M1B7IGNORE
[A—D]
Bit 7 of M1 Byte Ignore. Bit 7 of M1 byte will be
ignored if TOHP_M1B7IGNORE is set to 1 for
that channel. Only TOHP_M1B7IGNORE[A] is
valid for STS-48.
0
12
TOHP_LAISINS[A—D]
Line AIS Software Insertion. Active-high for
AIS insertion. In STS-48 mode, only
TOHP_LAISINS[A] is valid.
0
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 67. TOHP_RCTL[A—D][1—2], 0x0822—0x0829, Receive Control [1—2] (R/W) (continued)
Address
Bit
0x0822,
0x0824,
0x0826,
0x0828
11
216
10
Name
Function
Reset
Default
TOHP_LOF_AISINH[A—D] Loss-of-Frame AIS Inhibit. When set to logic 1,
the AIS insertion will be inhibited in case of lossof-frame.
TOHP_OOF_AISINH
[A—D]
Out-of-Frame AIS Inhibit. When set to logic 1,
the AIS insertion will be inhibited in case of outof-frame.
0
0
9
TOHP_LOS_AISINH[A—D] Loss-of-Signal AIS Inhibit. When set to logic 1,
the AIS insertion will be inhibited in case of lossof-signal.
0
8
TOHP_SFB1B2SEL[A—D] Signal Fail B1/B2 Error Count Select. When
set to logic 0, the B1 errors will be used by the
signal fail error rate algorithm; otherwise, B2
errors are used.
0
7
TOHP_SDB1B2SEL[A—D] Signal Degrade B1/B2 Error Count Select.
When set to logic 0, the B1 errors will be used by
the signal degrade error rate algorithm; otherwise, B2 errors are used.
0
6
TOHP_CNTDB1SEL[A—D] Reset CNTD Counters on B1 Error. Active-high
control bit to reset continuous N-times detect
counters upon received B1 errors. Only
TOHP_CNTDB1SEL[A] is valid for STS-48.
0
5
TOHP_S1MON8OR4CTL
[A—D]
S1 Byte or Nibble. When set to logic 1, the S1
byte will be monitored as two nibbles. Otherwise,
it is treated as a byte. Only
TOHP_S1MON8OR4CTL[A] is valid for STS-48.
0
4
TOHP_K1K2_2OR1[A—D] K1 and K2 Treated as 2 Registers or 1. When
set to 1, the K1 and K2 bytes will be treated as
one 16-bit register. When K1 and K2 are treated
as one 16-bit register, AIS-L detection is disabled. Both AIS-L and RDI-L monitoring will not
be performed. When set to 0, the K1 and K2
bytes will be treated as 2 registers of size 13 bits
(K1[7:0], K2[7:3]) and 3 bits (K2[2:0]). Only
TOHP_K1K2_2OR1[A] is valid for STS-48.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 67. TOHP_RCTL[A—D][1—2], 0x0822—0x0829, Receive Control [1—2] (R/W) (continued)
Address
Bit
Name
Function
Reset
Default
0x0822,
0x0824,
0x0826,
0x0828
3
TOHP_B2BITBLKCNT
[A—D]
B2 Error Count in Bit or Block. When set to 0,
B2 check logic will count bit errors; otherwise, it
counts block errors. Only
TOHP_B2BITBLKCNT[A] is valid for STS-48.
0
2
TOHP_DSCRINH[A—D]
Descramble Inhibit Control. When a bit is set to
1, the descrambler for that is disabled. In STS-48
mode, all 4 bits need to be set to same value.
0
1
TOHP_B1BITBLKCNT
[A—D]
B1 Error Count in Bit or Block. When set to 0,
B1 check logic will count bit errors; otherwise, it
counts block errors. Only
TOHP_B1BITBLKCNT[A] is valid for STS-48.
0
0
TOHP_ROH_BYPASS
[A—D]
Receive Overhead Bypass. Control bit, when
set to 1, causes the received data to pass
through the block retimed. In STS-48 mode, all
4 bits need to be set to same value.
0
15
TOHP_M1BITBLKCNT
[A—D]
M1 Error Count in Bit or Block. When set to 0,
M1 check logic will count bit errors; otherwise, it
counts block errors. Only
TOHP_M1BITBLKCNT[C] is valid for STS-48.
0
14
—
Reserved.
0
13
TOHP_RVALIDK_CTL
[A—D]
Receive Validated K Bytes Control. When set
to 1, received K1[5, 2, 1] and K2 [5, 3, 1] bytes
are used to compare with received reversed
K1[5, 2, 2] and K2 [5, 3, 2] bytes, respectively.
0
12:0
TOHP_LOSDETCNT
[A—D][12:0]
Loss-of-Signal Detection Count. Set the number of consecutive all-zeros/ones pattern
detected to declare receive LOS state for each
channel. The time scale is in steps of 8 bits (for
STS-3 and STS-12) or 32 (STS-48) at a time.
Only TOHP_LOSDETCNT[A][12:0] is valid for
STS-48.
0x0000
0x0823,
0x0825,
0x0827,
0x0829
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
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Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 68. TOHP_RCTL[A—D][3], 0x082A—0x082D, Receive Control 3 (R/W)
Address
Bit
Name
Function
Reset
Default
0x082A
15:14
TOHP_RREFSEL[1:0]
Receive Reference Sync Select. Select reference output from channel A (00), B (01), C (10),
and D (11).
0
13
TOHP_RREF_EN
Receive Reference Sync Enable. Enables or
disables output from the RXREF pin AK3
(Table 8). When set to 1, the receive 8 kHz 50%
duty cycle sync output is high impedance.
0
12
TOHP_RREF_INH
Receive Reference Sync Inhibit. When set to
logic 0, the receive 8 kHz 50% duty cycle sync
output. When set to 1, the RXREF (pin AK3
Table 8) output is forced to 0 during LOS, OOF,
and LOF conditions.
0
11:4
—
Reserved.
000
00000
0x082B—
0x082D
15:4
—
Reserved.
0x000
0x082A—
0x082D
3
TOHP_RTOACSINH[A—D] Receive TOAC Sync Inhibit. When set to logic
1, the TOAC sync output, RXTOHF[A—D] is
forced to high impedance.
0
2
TOHP_RTOACCINH[A—D] Receive TOAC Clock Inhibit. When set to logic
1, the TOAC clock output is forced to high impedance.
0
1
TOHP_RTOACDINH[A—D] Receive TOAC Data Inhibit. When set to logic 1,
the TOAC data output is high impedance.
0
0
218
TOHP_RTOAC_OEPINS
[A—D]
Receive TOAC Odd or Even Parity Insert.
When set to logic 1, the output TOAC parity bit is
even; otherwise, the parity is odd.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 69. TOHP_TCTL[A—D][1—2], 0x082E—0x0835, Transmit Control [1—2] (R/W)
Address
Bit
Name
Function
Reset
Default
0x082E
15
TOHP_TTOACINH
Transmit TOAC Clock and Sync Inhibit. When
set to 1, the transmit TOAC clock and sync are high
impedance.
0
0x0830
15
TOHP_TTOAC_K1K2[A]
Transmit TOAC K1K2 Byte Control. Control bits,
when set to logic 0, the value in registers
TOHP_TK1DINS[7:0] and TOHP_TK2DINS[7:3]
will be inserted into the K1K2 byte in the transmit
frame. Setting these bits to logic 1 causes the
TTOAC value to be inserted into the K1K2 byte.
TOHP_TTOAC_K1K2[A] is valid for STS-48 mode
only.
0
0x0832
15
TOHP_TTOAC_
VALIDK_CTL
Transmit TOAC Validated K1K2 Byte Control.
Control bit, when set to 1, the reversed K1 K2 bytes
are compared to the received K1 K2 bytes (all 16
bits) before the insertion; otherwise, TTOAC
received K1K2 bytes are inserted.
0
0x0834
15
TOHP_TK2SWHWINS_INH Transmit K2 Byte Software and Hardware Control. Control bit, when set to 1, K2[2:0] =
TTOAC_K1K2[2:0] or TK2SINS[2:0]. When
TK2SWHW_INT clear to 0 and LRDIINT = 1, the
K2[2:0] is set to 110 (RDI-L).
0
0x082E,
0x0830,
0x0832,
0x0834
14
TOHP_TJ0INS[A—D]
Transmit J0 Insert Control. Control bit, when set
to a logic 1, inserts the value in
TOHP_TJ0DINS[A—D][64:1][7:0] into the outgoing J0 bytes; otherwise, the insert value depends
on TOHP_TTOAC_J0[A—D] registers. TJ0INS[A]
is valid in STS-48 mode.*
0
13
TOHP_TTOAC_J0[A—D]
Transmit TOAC J0 Byte Control. Control bits,
when set to logic 0, cause the default value
00000000 for SONET or 11111111 for SDH to be
inserted into the J0 byte in the transmit frame. Setting these bits to logic 1 causes the TTOAC value
to be inserted into the J0 byte.
TOHP_TTOAC_J0[A] is valid for STS-48 mode.*
0
12
TOHP_TTOAC_
K1K2[B—D]
Transmit TOAC K1K2 Byte Control. Control bits,
when set to logic 0, the value in registers
TOHP_TK1DINS[7:0] and TOHP_TK2DINS[7:3]
will be inserted into the K1K2 byte in the transmit
frame. Setting these bits to logic 1 causes the
TTOAC value to be inserted into the K1K2 byte.
TOHP_TTOAC_K1K2[A] is valid for STS-48 mode.
0
0x0830,
0x0832,
0x0834
0x082E
TOHP_TTOAC_OEPMON Transmit TOAC Odd or Even Parity Monitor.
When set to 1, even parity is checked for transmit
TOAC channels; otherwise, odd parity is checked.
0
* TOHP_TJ0INS = 1 always sets J0 to the TOHP_TJ0DINS values regardless of the value of TOHP_TTOAC_J0.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 69. TOHP_TCTL[A—D][1—2], 0x082E—0x0835, Transmit Control [1—2] (R/W) (continued)
Address
Bit
Name
Function
Reset
Default
0x082E,
0x0830,
0x0832,
0x0834
11
TOHP_TTOAC_INS[A—D] Transmit TOAC Byte Control. Control bits, when
set to logic 0, cause the default value 00000000 for
SONET or 11111111 for SDH to be inserted into all
overhead bytes without specific insert control bits in
the transmit frame. Setting these bits to logic 1
causes the TTOAC value to be inserted into all
overhead bytes without specific insert control bits.
TOHP_TTOAC_INS[A] is valid for STS-48 mode.
0
10
TOHP_TTOAC_E2[A—D]
Transmit TOAC E2 Byte Control. Control bits,
when set to logic 0, cause the default value to be
inserted into the E2 byte in the transmit frame. Setting these bits to logic 1 causes the TTOAC value
to be inserted into the E2 byte.
TOHP_TTOAC_E2[A] is valid for STS-48 mode.
0
9
TOHP_TTOAC_S1[A—D] Transmit TOAC S1 Byte Control. Control bits,
when set to logic 0, cause the default value to be
inserted into the S1 byte in the transmit frame. Setting these bits to logic 1 causes the TTOAC value
to be inserted into the S1 byte.
TOHP_TTOAC_S1[A] is valid for STS-48 mode.
0
8
TOHP_TTOAC_D4TO12
[A—D]
0
Transmit TOAC D4 to D12 Byte Control. Control
bits, when set to logic 0, cause the default value to
be inserted into the D4 to D12 bytes in the transmit
frame. Setting these bits to logic 1 causes the
TTOAC value to be inserted into the D4 to D12
bytes. TOHP_TTOAC_D4TO12[A] is valid for
STS-48 mode.
Note: When TOHP_TTOAC_K1K2 = 1 and
TOHP_TTOAC_VALIDK_CTL = 1,
TOHP_TTOAC_D4TO12[A—D] has
* TOHP_TJ0INS = 1 always sets J0 to the TOHP_TJ0DINS values regardless of the value of TOHP_TTOAC_J0.
220
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 69. TOHP_TCTL[A—D][1—2], 0x082E—0x0835, Transmit Control [1—2] (R/W) (continued)
Address
Bit
Name
Function
Reset
Default
0x082E,
0x0830,
0x0832,
0x0834
7
TOHP_TTOAC_D1TO3
[A—D]
Transmit TOAC D1 to D3 Byte Control. Control
bits, when set to logic 0, cause the default value
to be inserted into the D1 to D3 bytes in the
transmit frame. Setting these bits to logic 1
causes the TTOAC value to be inserted into the
D1 to D3 bytes. TOHP_TTOAC_D1TO3[A] is
valid for STS-48 mode.
0
6
TOHP_TTOAC_F1[A—D]
Transmit TOAC F1 Byte Control. Control bits,
when set to logic 0, cause the default value to be
inserted into the F1 byte in the transmit frame.
Setting these bits to logic 1 causes the TTOAC
value to be inserted into the F1 byte.
TOHP_TTOAC_F1[A] is valid for STS-48 mode.
0
5
TOHP_TTOAC_E1[A—D] Transmit TOAC E1 Byte Control. Control bits,
when set to logic 0, cause the default value to be
inserted into the E1 byte in the transmit frame.
Setting these bits to logic 1 causes the TTOAC
value to be inserted into the E1 byte.
TOHP_TTOAC_E1[A] is valid for STS-48 mode.
0
4
TOHP_TAPSBABLEINS
[A—D]
Transmit APS Babble Insert. Control bit, when
set to 1, causes an inconsistent APS byte
(K1[7:0], K2[7:3]) to be inserted into the outgoing
STS-M frame until this register is reset to 0.
0
3
TOHP_TM1_ERR_INS
[A—D]
Transmit M1 Error Insert. Once this register is
set to 1, an error will be inserted continuously
into the outgoing M1 byte until this register is
reset to 0. In STS-48 mode, only
TOHP_TM1_ERR_INS[C] is valid.
0
2
TOHP_TM1_REIL_INH
[A—D]
Transmit M1 REI-L Inhibit. Active high to inhibit
automatic insertion of REI-L (MS-REI). In
STS-48 mode, only TOHP_TM1_REIL_INH[C] is
valid.
0
1
TOHP_TF1INS[A—D]
Transmit F1 Insert Control. Control bit, when
set to a logic 1, inserts the value in
TOHP_TF1DINS[7:0] into the outgoing F1 byte in
the STS-M frame; otherwise, the insert value
depends on TTOAC_F1 register.
TOHP_TF1INS[A] is valid in STS-48 mode.
1
0
TOHP_TS1INS[A—D]
Transmit S1 Insert Control. Control bit, when
set to a logic 1, inserts the value in
TOHP_TS1DINS[7:0] into the outgoing S1 byte
in the STS-M frame; otherwise, the insert value
depends on TOHP_TTOAC_S1 bit.
TOHP_TS1INS[A] is valid in STS-48 mode.
1
* TOHP_TJ0INS = 1 always sets J0 to the TOHP_TJ0DINS values regardless of the value of TOHP_TTOAC_J0.
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Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 69. TOHP_TCTL[A—D][1—2], 0x082E—0x0835, Transmit Control [1—2] (R/W) (continued)
Address
Bit
Name
Function
Reset
Default
0x082F,
0x0831,
0x0833,
0x0835
15:11
TOHP_TA1A2ERRINS
[A—D][4:0]
Number of Consecutive Frames with A2
Error Insertion. These bits specify the number
of consecutive frames to be inserted with a
frame error of A2.
0x00
10
TOHP_TOH_BYPASS[A—D] Transmit Overhead Bypass. Control bit, when
set to 1, causes the frame from PT pass through
untouched. In STS-48 mode, all 4 bits need to
be set to same value.
0
9
TOHP_SCRINH[A—D]
Scramble Inhibit. When set to high, the scrambling is inhibited. In STS-48 mode, all 4 bits
need to be set to same value.
0
8
TOHP_TB1ERRINS[A—D]
Transmit B1 Error Insertion. When set to high,
the B1 output will be inverted. For STS-48, only
TOHP_TB1ERRINS[A] is valid.
0
7
TOHP_TB2ERRINS[A—D]
Transmit B2 Error Insertion. When set to high,
all B2 bytes in that channel will be inverted. All
4 bits are valid in STS-48 mode.
0
6
TOHP_TIMER_LRDIINH
[A—D]
Transmit 20-Frame Line RDI Inhibit. Control
bits, when set to high, inhibit the requirement of
minimum 20 frame RDI insertion.
0
5
TOHP_TSF_LRDIINH[A—D] Transmit Signal Fail Line RDI Inhibit. Activehigh.
0
4
TOHP_TLAISMON_LRDIINH Transmit Line-AIS-Monitored Line RDI
[A—D]
Inhibit. Active-high.
0
3
TOHP_TLOF_LRDIINH
[A—D]
Transmit Loss-of-Frame Line RDI Inhibit.
Active-high.
0
2
TOHP_TOOF_LRDIINH
[A—D]
Transmit Out-of-Frame Line RDI Inhibit.
Active-high.
0
1
TOHP_TLOS_LRDIINH
[A—D]
Transmit Loss-of-Signal Line RDI Inhibit.
Active-high.
0
0
TOHP_TLOC_LRDIINH
[A—D]
Transmit Loss-of-Clock Line RDI Inhibit. Control bits, when set to a logic 1, cause the associated failure not to contribute to the automatic
insertion of RDI-L; otherwise, the associated
alarm contributes to the generation of RDI-L.
0
* TOHP_TJ0INS = 1 always sets J0 to the TOHP_TJ0DINS values regardless of the value of TOHP_TTOAC_J0.
222
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 70. TOHP_TCTL[A—D][3], 0x0836—0x0839, Transmit Control 3 (R/W)
Address
Bit
Name
Function
Reset
Default
0x0836—
0x0839
15
TOHP_TAPSINS[A—D]
Transmit APS Software Insert. When set to
logic 1, the value in registers
TOHP_TK1DINS[7:0] and TOHP_TK2DINS[7:3],
or TTOAC value controlled by
TOHP_TTOAC_K1K2, will be inserted into
K1[7:0] and K2[7:3] in the transmit frame; otherwise, data from TX_RAWK[15:3] will be inserted.
1
14:13
TOHP_TK2SINS
[A—D][1:0]
Transmit K2 Software Insert.
0x0
11 = TTOAC_K1K2[2:0].
10 = TK2DINS[2:0].
01 = Hardware insert is enabled for RDI-L (110).
00 = The value in TX_RAWK[2:0] will be inserted
into K2[2:0] in the transmit frame.
12
TOHP_TVALIDK_CTL
[A—D]
Transmit Validated K Bytes Control. When set
to 1, reversed K1[5, 2, 1] and K2 [5, 3, 1] bytes
will be inserted into K1[5, 2, 2] and K2 [5, 3, 2]
bytes, respectively; otherwise, default value (all
1s for SDH and all 0s for SONET) will be inserted
at this location.
0
11:0
TOHP_TAISLINS
[A—D][11:0]
Force Line AIS in the Selected Output Time
Slot. Active-high. For OC-3, the index [0:2] corresponds to time slot 1-2-3; for OC-12, the
index[0:11] corresponds to time slot 1-4-7-10-2-58-11-3-6-9-12; and for OC-48, the index [A][0:11]
is for time slot 1-13-25-37-2-14-26-38-3-15-2739, [B][0:11] for 4-16-28-40-5-17-29-41-6-18-3042, [C][0:11] for 7-19-31-43-8-20-32-44-9-21-3345, and [D][0:11] for 10-22-34-46-11-23-35-4712-24-36-48.
0x000
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Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 71. TOHP_SD_SETR[A—D][1—2], 0x083A—0x0841, Signal Degrade BER Algorithm Set Control
Registers [1—2] (R/W)
Address
Bit
Name
Function
Reset
Default
0x083A,
0x083C,
0x083E,
0x0840
15:0
TOHP_SDNSSET
[A—D][17:2]
Signal Degrade Ns Set. Number of frames in a
monitoring block for signal degrade (SD) of slice
[A—D] is equal to
TOHP_SDNSSET[A—D][17:0], respectively.
0x00000
0x083B,
0x083D,
0x083F,
0x0841
1:0
TOHP_SDNSSET
[A—D][1:0]
0x083B,
0x083D,
0x083F,
0x0841
15:9
TOHP_SDMSET
[A—D][6:0]
Signal Degrade M Set. Threshold of the number of bad monitoring blocks in an observation
interval. If the number of bad blocks is above this
threshold, then signal degrade is set.
0x00
TOHP_SDLSET[A—D][6:0] Signal Degrade L Set. Error threshold for determining if a monitoring block is bad.
0x00
8:2
Table 72. TOHP_SD_SETR[A—D][3], 0x0842—0x0845, Signal Degrade BER Algorithm Set Control
Register [3] (R/W)
Address
Bit
Name
0x0842—
0x0845
15:0
TOHP_SDBSET
[A—D][15:0]
224
Function
Reset
Default
Signal Degrade B Set. Number of monitoring
blocks.
0x0000
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 73. TOHP_SD_CLEARR[A—D][1—2], 0x0846—0x084D, Signal Degrade BER Algorithm Clear
Control Registers [1—2] (R/W)
Address
Bit
Name
Function
Reset
Default
0x0846,
0x0848,
0x084A,
0x084C
15:0
TOHP_SDNSCLEAR
[A—D][17:2]
Signal Degrade Ns Clear. Number of frames in
a monitoring block for SD of slice[A—D] is equal
to TOHP_SDNSCLEAR[A—D][17:0], respectively.
0x00000
0x0847,
0x0849,
0x084B,
0x084D
1:0
TOHP_SDNSCLEAR
[A—D][1:0]
0x0847,
0x0849,
0x084B,
0x084D
15:9
TOHP_SDMCLEAR
[A—D][6:0]
Signal Degrade M Clear. Threshold of the number of bad monitoring blocks in an observation
interval. If the number of bad blocks is below this
threshold, then SD is cleared.
0x00
8:2
TOHP_SDLCLEAR
[A—D][6:0]
Signal Degrade L Clear. Error threshold for
determining if a monitoring block is bad.
0x0
Table 74. TOHP_SD_CLEARR[A—D][3], 0x084E—0x0851, Signal Degrade BER Algorithm Clear Control
Register [3] (R/W)
Address
Bit
Name
Function
Reset
Default
0x084E—
0x0851
15:0
TOHP_SDBCLEAR
[A—D][15:0]
Signal Degrade B Clear. Number of monitoring
blocks.
0x0000
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 75. TOHP_SF_SETR[A—D][1—2], 0x0852—0x0859, Signal Fail Set BER Algorithm Control
Registers [1—2] (R/W)*
Address
Bit
Name
Function
Reset
Default
0x0852,
0x0854,
0x0856,
0x0858
15:0
TOHP_SFNSSET
[A—D][17:2]
Signal Fail Ns Set. Number of frames in a monitoring block for signal fail (SF) of slice[A—D] is
equal to TOHP_SFNSSET[A—D][17:0], respectively.
0x00000
0x0853,
0x0855,
0x0857,
0x0859
1:0
TOHP_SFNSSET
[A—D][1:0]
0x0853,
0x0855,
0x0857,
0x0859
15:10
TOHP_SFMSET
[A—D][5:0] Applies for
version 2.2 and 2.3 only.
Signal Fail M Set. Threshold of the number of
bad monitoring blocks in an observation interval.
If the number of bad blocks is above this threshold, then signal fail is set.
0x00
9:2
15:9
8:2
TOHP_SFLSET[A—D][7:0] Signal Fail L Set. Error threshold for determinApplies for version 2.2 ing if a monitoring block is bad.
and 2.3 only.
TOHP_SFMSET
[A—D][6:0] Applies for
version 2.0 only.
Signal Fail M Set. Threshold of the number of
bad monitoring blocks in an observation interval.
If the number of bad blocks is above this threshold, then signal fail is set.
TOHP_SFLSET[A—D][6:0] Signal Fail L Set. Error threshold for determinApplies for version 2.0 ing if a monitoring block is bad.
only.
0x00
0x00
0x00
* See page 208 for the description of reading and writing parameters of more than 16 bits.
Table 76. TOHP_SF_SETR[A—D][3], 0x085A—0x085D, Signal Fail BER Algorithm Set Control
Register [3] (R/W)
Address
Bit
Name
Function
Reset
Default
0x085A—
0x085D
15:0
TOHP_SFBSET
[A—D][15:0]
Signal Fail B Set. Number of monitoring blocks.
0x0000
226
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 77. TOHP_SF_CLEARR[A—D][1—2], 0x085E—0x0865, Signal Fail BER Algorithm Clear
Control Registers [1—2] (R/W)*
Address
Bit
Name
Function
Reset
Default
0x085E,
0x0860,
0x0862,
0x0864
15:0
TOHP_SFNSCLEAR
[A—D][17:2]
Signal Fail Ns Clear. Number of frames in a
monitoring block for SD of slice[A—D] is equal to
TOHP_SFNSCLEAR[A—D][17:0], respectively.
0x00000
0x085F,
0x0861,
0x0863,
0x0865
1:0
TOHP_SFNSCLEAR
[A—D][1:0]
0x085F,
0x0861,
0x0863,
0x0865
15:9
TOHP_SFMCLEAR
[A—D][6:0]
Signal Fail M Clear. Threshold of the number of
bad monitoring blocks in an observation interval.
If the number of bad blocks is below this threshold, then SF is cleared.
0x00
8:2
TOHP_SFLCLEAR
[A—D][6:0]
Signal Fail L Clear. Error threshold for determining if a monitoring block is bad.
0x0
* See page 208 for the description of reading and writing parameters of more than 16 bits.
Table 78. TOHP_SF_CLEARR[A—D][3], 0x0866—0x0869, Signal Fail BER Algorithm Clear
Control Register [3] (R/W)
Address
Bit
Name
0x0866—
0x0869
15:0
TOHP_SFBCLEAR
[A—D][15:0]
Agere Systems Inc.
Function
Signal Fail B Clear. Number of monitoring
blocks.
Reset
Default
0x0000
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Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Figure 34 illustrates the parameters used in determining the bit error detection rate.
NUMBER OF MONITORING BLOCKS SFBSET[A—D] OR SDBSET[A—D] (IN THIS CASE, 3)
NUMBER OF FRAMES IN A MONITORING BLOCK SFNSSET[A—D] OR SDNSSET[A—D],
SFNSCLEAR[A—D] OR SDNSCLEAR[A—D]
(IN THIS CASE, 7)
FRAME
BOUNDARY
BLOCK
BOUNDARY
SFLSET[A—D] OR SDLSET[A—D]
SFLCLEAR[A—D] OR SDLCLEAR[A—D]
SFMSET[A—D] OR SDMSET[A—D]
SFMCLEAR[A—D] OR SDMCLEAR[A—D]
ACCUMULATED BIP ERROR COUNT:
B1 OR B2 FOR LINE
B3 FOR PATH
BLOCK GOOD/BAD COUNT
5-7934(F)
Figure 34. Signal Degrade and Failure Parameters for BER
MARS2G5 P-Pro provides a method to monitor the BER at the line and path layers. The following explains the
algorithm for this method to set and clear the BER. The algorithm for this method is the same for setting and clearing the BER; the only difference is the programmed values. MARS2G5 P-Pro includes two complete sets of identical counters, one used to determine signal fail (SF) and one used to determine signal degrade (SD). The only
difference between SF and SD is the provisioned values. The same algorithm is used for both the line and path layers of SONET.
The algorithm uses four sets of counters: labeled Ns (number of frames), L (number of errors), M (number of
errored blocks), and B (total number of blocks). Each of these counters has different values that are provisioned to
either set the BER high or clear the BER indication. The algorithm works by counting blocks, i.e., a preset number
of SONET/SDH frames (Ns). If the number of errors in the block exceeds the provisioned level (L), then the errored
block counter is incremented by 1; otherwise, the number of blocks in error stays at its current level. At this point,
the frame counter and the error counter are reset back to 0 and counting is started again. At the end of a preset
number of blocks (B), the count in the errored block counter is compared against a provisioned threshold (M). If the
total number of blocks in error equals or exceeds the provisioned threshold (M), then the BER alarm is raised. If the
total number of blocks in error is less than the provisioned amount (M), then the BER alarm is cleared. In other
words: given the error distribution as defined by the GR-253 standard, the probability of getting L BIP errors out of
8 * N BIP bits in M out of B blocks.
The values used by the counters are determined by the state of the algorithm. If the BER state is low, then the set
parameters are used. If the BER state is high, then the clear parameters are used.
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 79 and Table 80 show values of Ns, L, M, and B for STS-3/STM-1, STS-12/STM-4, and STS-48/STM-16 to
set and clear the BER indicator. SF registers are 0x852—0x0869 (Table 75—Table 78) and SD registers are
0x083A—0x0851 (Table 71—Table 74). All SF/SD set and clear values are hexadecimal.
Table 79. Ns, L, M, and B Values to Set the BER Indicator
Note: The Ns, L, M, and B values shown are the numbers to be provisioned in the MARS2G5 P-Pro. The actual
values of Ns, M, and B of the BER algorithm are 1 greater than the values shown, excluding L.
Mode
BER
SF/SD Set Values
Ns
STS-3/
STM-1
STS-12/
STM-4
STS-48/
STM-16
Actual
Number of
Frames
L
M
B
Probability of
Detecting L
Errors (%)
@BER
@BER/2
Probability of
Declaring
SF/SD (%)
@BER
@BER/2
IntegraMaximum
tion
Time
Number
of Frames
(s)
1.00E-03
0
7
3D
3D
62
99.96
85.13
97.68
0.00
0.008
64
1.00E-04
5
A
3
7
48
72.70
7.28
96.06
0.16
0.013
104
1.00E-05
2F
8
3
7
384
71.34
10.08
95.19
0.52
0.1
800
1.00E-06
1DF
8
3
7
3840
71.34
10.09
95.19
0.52
1
8000
1.00E-07
1274
8
4
9
47250
69.74
9.44
95.07
0.13
10
80000
1.00E-08
B5A3
8
3
9
465000
68.07
8.82
98.47
0.82
83
664000
1.00E-09
3F79F
5
5
F
4160000
56.90
11.25
96.52
0.60
667
5336000
1.00E-10
—
—
—
—
—
—
—
—
—
—
—
1.00E-03
0
20
3F
3F
64
100.00
88.43
100.00
0.04
0.008
64
1.00E-04
1
C
6
A
22
84.92
9.64
98.38
0.00
0.008
64
1.00E-05
C
9
3
8
117
67.93
7.17
96.48
0.25
0.025
200
1.00E-06
7F
9
3
8
1152
66.19
6.66
95.46
0.19
0.25
2000
1.00E-07
4FA
9
3
8
11475
65.75
6.53
95.16
0.18
2.5
20000
1.00E-08
31CD
9
3
8
114750
65.75
6.53
95.16
0.18
21
168000
1.00E-09
1F20B
9
3
8
1147500
65.75
6.53
95.16
0.18
167
1336000
1.00E-10
—
—
—
—
—
—
—
—
—
—
—
1.00E-03
0
4B
3F
3F
64
100.00
100.00
100.00
100.00
0.008
64
1.00E-04
0
F
3F
3F
64
99.95
58.97
96.89
0.00
0.008
64
1.00E-05
4
B
35
3F
320
90.60
16.25
96.47
0.00
0.008
64
1.00E-06
1F
8
8
E
480
77.55
13.09
96.69
0.00
0.0625
500
1.00E-07
139
8
8
E
4710
75.80
12.15
95.17
0.00
0.625
5000
1.00E-08
C1B
8
7
E
46500
74.58
11.54
98.09
0.01
5.2
41600
1.00E-09
765B
7
6
A
333300
82.92
19.71
97.29
0.18
42
336000
1.00E-10
—
—
—
—
—
—
—
—
—
—
—
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 80. Ns, L, M, and B Values to Clear the BER Indicator
Note: The Ns, L, M, and B values shown are the numbers to be provisioned in the MARS2G5 P-Pro. The actual
values of Ns, M, and B of the BER algorithm are 1 greater than the values shown, excluding L.
Mode
STS-3/
STM-1
STS-12/
STM-4
STS-48/
STM-16
230
BER
SF/SD Set Values
Actual
Probability of
Number Detecting L Errors
of Frames
(%)
@BER * 5
Probability of
Clearing
SF/SD (%)
@BER @BER * 5 @BER
IntegraMaximum
tion
Time
Number
of Frames
(s)
Ns
L
M
B
1.00E-03
—
—
—
—
—
—
—
—
—
—
—
1.00E-04
0
7
3
7
8
85.13
0.39
0.27
100.00
0.013
104
1.00E-05
5
3
3
7
48
93.01
11.33
0.01
99.21
0.1
800
1.00E-06
2F
3
3
7
384
84.42
6.84
0.34
99.88
1
8000
1.00E-07
1DF
3
3
7
3840
84.42
6.84
0.34
99.88
10
80000
1.00E-08
1274
3
4
9
47250
83.66
6.59
0.22
99.98
83
664000
1.00E-09
B5A3
3
3
9
465000
82.86
6.35
0.03
99.75
667
5336000
1.00E-10
3F79F
3
2
F
4160000
46.31
1.48
0.50
99.84
6670
53360000
1.00E-03
—
—
—
—
—
—
—
—
—
—
—
1.00E-04
0
8
6
6
7
100.00
51.54
0.00
99.03
0.008
64
1.00E-05
1
3
8
A
22
98.36
20.51
0.07
100.00
0.025
200
1.00E-06
C
3
3
8
117
87.99
8.23
0.02
99.59
0.25
2000
1.00E-07
7F
3
3
8
1152
87.34
7.94
0.02
99.64
2.5
20000
1.00E-08
4FA
3
3
8
11475
87.17
7.87
0.03
99.65
21
168000
1.00E-09
31CD
3
3
8
114750
87.17
7.87
0.03
99.65
167
1336000
1.00E-10
1F20B
3
3
8
1147500
87.17
7.87
0.03
99.65
1670
13360000
1.00E-03
—
—
—
—
—
—
—
—
—
—
—
1.00E-04
0
20
27
3F
64
100.00
45.99
0.00
99.42
0.008
64
1.00E-05
0
3
D
E
15
100.00
60.11
0.00
99.47
0.008
64
1.00E-06
4
4
D
3F
320
95.07
7.28
0.00
99.98
0.0625
500
1.00E-07
1F
3
6
13
640
87.34
7.94
0.00
99.94
0.625
5000
1.00E-08
139
3
6
13
6280
86.52
7.61
0.00
99.95
5.2
41600
1.00E-09
C1B
3
6
13
62000
85.95
7.38
0.00
99.96
42
336000
1.00E-10
765B
3
4
A
333300
84.89
7.00
0.03
99.95
420
3360000
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 81. TOHP_B1ECNTR[A—D], 0x086A—0x086D, B1 Error Count (RO)
Address
Bit
Name
0x086A—
0x086D
15:0
TOHP_B1ECNT
[A—D][15:0]
Function
B1 Error Count. The value of internal running
counter is transferred into this holding register
at the 0-to-1 transition of PMRST (pin D7)
(Table 10) signal.
Reset
Default
0x0000
Table 82. TOHP_B2ECNTR[A—D][1—2], 0x086E—0x0875, B2 Error Count (RO)
Address
Bit
Name
0x086E, 0x0870,
0x0872, 0x0874
0x086F, 0x0871,
0x0873, 0x0875
5:0
TOHP_B2ECNT
[A—D][21:16]
TOHP_B2ECNT
[A—D][15:0]
15:0
Function
B2 Error Count. The value of internal running
counter is transferred into this holding register
at the 0-to-1 transition of PMRST (pin D7)
(Table 10) signal.
Reset
Default
0x000000
Table 83. TOHP_M1ECNTR[A—D][1—2], 0x0876—0x087D, M1 Error Count (RO)
Note:Stream C of the M1 error count registers 0x087A[4:0] and 0x087B[15:0] must be used for OC-48 mode.
Address
Bit
Name
Function
Reset
Default
0x0876, 0x0878,
0x087A, 0x087C
0x0877, 0x0879,
0x087B, 0x087D
4:0
TOHP_M1ECNT
[A—D][20:16]
TOHP_M1ECNT
[A—D][15:0]
M1 Error Count. The value of internal running
counter is transferred into this holding register
at the 0-to-1 transition of PMRST (pin D7)
(Table 10) signal.
0x000000
Agere Systems Inc.
15:0
231
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 84. TOHP_TOH_INSR[A—D][1—2], 0x087E—0x0885, Transmit OH Insert Value (R/W)
Address
Bit
Name
0x087E, 0x0880,
0x0882, 0x0884
15:8
TOHP_TF1DINS
[A—D][7:0]
Transmit F1 Byte Value. Register value is
inserted into the transmit F1 byte.
0x00
7:0
TOHP_TS1DINS
[A—D][7:0]
Transmit S1 Byte Value. Register value is
inserted into the transmit S1 byte.
0x00
15:8
TOHP_TK2DINS
[A—D][7:0]
Transmit K2 Byte Value. Register value is
inserted into the transmit K2 byte.
0x00
7:0
TOHP_TK1DINS
[A—D][7:0]
Transmit K1 Byte Value. Register value is
inserted into the transmit K1 byte.
0x00
0x087F, 0x0881,
0x0883, 0x0885
Function
Reset
Default
Table 85. TOHP_RMONR[A—D][1—3], 0x0886—0x0891, Receive Monitor Value (RO)
Address
Bit
Name
0x0886, 0x0889,
0x088C, 0x088F
15:8
TOHP_F1DMON1
[A—D][7:0]
Receive F1 Previous Monitor Value.
0x00
7:0
TOHP_F1DMON0
[A—D][7:0]
Receive F1 Current Monitor Value.
0x00
15:8
TOHP_K2DMON
[A—D[7:0]
Receive K2 Monitor Value.
0x00
7:0
TOHP_K1DMON
[A—D][7:0]
Receive K1 Monitor Value.
0x00
7:0
TOHP_S1DMON
[A—D][7:0]
Receive S1 Monitor Value.
0x00
0x0887, 0x088A,
0x088D, 0x0890
0x0888, 0x088B,
0x088E, 0x0891
232
Function
Reset
Default
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 86. TOHP_RJ0DMONR[A—D][1—32], 0x0892—0x0911, Receive J0/Z0 Monitor Value Registers (RO)
Address
Bit
Name
0x0892—
0x08B1
15:8
TOHP_RJ0DMON
[A][2, 4, 6, . . ., 64][7:0]
7:0
TOHP_RJ0DMON
[A][1, 3, 5, . . ., 63][7:0]
0x08B2—
0x08D1
0x08D2—
0x08F1
0x08F2—
0x0911
15:8
TOHP_RJ0DMON
[B][2, 4, 6, . . ., 64][7:0]
7:0
TOHP_RJ0DMON
[B][1, 3, 5, . . ., 63][7:0]
15:8
TOHP_RJ0DMON
[C][2, 4, 6, . . ., 64][7:0]
7:0
TOHP_RJ0DMON
[C][1, 3, 5, . . ., 63][7:0]
15:8
TOHP_RJ0DMON
[D][2, 4, 6, . . ., 64][7:0]
7:0
TOHP_RJ0DMON
[D][1, 3, 5, . . ., 63][7:0]
Agere Systems Inc.
Function
Reset
Default
Receive J0 Monitor Value. These registers cap- 0x0000
ture a 64-byte sequence from the J0 byte of each
channel.
In STS-48 mode, TOHP_RJ0DMON[A]
[1—64][7:0] is valid for J0 bytes while
TOHP_RJ0DMON[B—D][1][7:0] are used for
TOHP_Z0DMON[B—D][1][7:0] (see TOHP-48
register map (Table 93)).
Receive J0 Monitor Value. See functional
description above.
0x0000
Receive J0 Monitor Value. See functional
description above.
0x0000
Receive J0 Monitor Value. See functional
description above.
0x0000
233
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 87. TOHP_TJ0DINSR[A—D][1—32], 0x0912—0x09A9, Transmit J0/Z0 Insert Value Registers (R/W)
Address
Bit
Name
0x0912—
0x0931
15:8
TOHP_TJ0DINS
[A][2, 4, 6, . . ., 64][7:0]
7:0
TOHP_TJ0DINS
[A][1, 3, 5, . . ., 63][7:0]
0x0932—
0x0951
0x0952—
0x0971
0x0972—
0x09A9
234
15:8
TOHP_TJ0DINS
[B][2, 4, 6, . . ., 64][7:0]
7:0
TOHP_TJ0DINS
[B][1, 3, 5, . . ., 63][7:0]
15:8
TOHP_TJ0DINS
[C][2, 4, 6, . . ., 64][7:0]
7:0
TOHP_TJ0DINS
[C][1, 3, 5, . . ., 63][7:0]
15:8
TOHP_TJ0DINS
[D][2, 4, 6, . . ., 64][7:0]
7:0
TOHP_TJ0DINS
[D][1, 3, 5, . . ., 63][7:0]
Function
Reset
Default
Transmit J0 Insert Value. These registers allow 0x0000
a 64-byte sequence to be inserted into the J0
byte of each channel.
In STS-48 mode, TOHP_TJ0DINS[A][1—64][7:0]
is valid for J0 bytes while TOHP_TJ0DINS[B—
D][1][7:0] are used for TOHP_TZ0DINS[B—D][1,
2, 3][7:0] (see TOHP-48 register map (Table 93)).
Transmit J0 Insert Value. See functional
description above.
0x0000
Transmit J0 Insert Value. See functional
description above.
0x0000
Transmit J0 Insert Value. See functional
description above.
0x0000
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 88. TOHP_TZ0DINSR[A—D][1—6], 0x09AA—0x09C1, Transmit Z0 Insert Value Registers (R/W)
Address
Bit
0x09AA
15:8
Name
Function
TOHP_TZ0DINS[A][2][7:0] Transmit Z0 Insert Value. Register values are
inserted into the transmit Z0 bytes.
Reset
Default
—
In STS-3 mode, TOHP_TZ0DINS[A—D][2—3] are
valid; in STS-12 mode, TOHP_TZ0DINS[A—D][2—
12][7:0] are valid; and in STS-48 mode, all 44
TOHP_TZ0DINS bytes plus TOHP_TJ0DINS[B—
D][1][7:0] (Table 87) are used for 47 Z0 byte values
(see Table 89 for Z0 byte ordering in these registers).
0x09AB—
0x09AF
0x09B0
0x09B1—
0x09B5
0x09B6
0x09B7—
0x09BB
0x09BC
0x09BD—
0x09C1
7:0
—
15:8
TOHP_TZ0DINS[A]
[4, 6, 8, 10, 12][7:0]
7:0
TOHP_TZ0DINS[A]
[3, 5, 7, 9, 11][7:0]
0x0
15:8
TOHP_TZ0DINS[B][2][7:0]
—
7:0
—
15:8
TOHP_TZ0DINS[B]
[4, 6, 8, 10, 12][7:0]
7:0
TOHP_TZ0DINS[B]
[3, 5, 7, 9, 11][7:0]
0x0
15:8
TOHP_TZ0DINS[C][2][7:0]
0x0
7:0
—
15:8
TOHP_TZ0DINS[C]
[4, 6, 8, 10, 12][7:0]
7:0
TOHP_TZ0DINS[C]
[3, 5, 7, 9, 11][7:0]
0x0
15:8
TOHP_TZ0DINS[D][2][7:0]
0x0
7:0
—
15:8
TOHP_TZ0DINS[D]
[4, 6, 8, 10, 12][7:0]
7:0
TOHP_TZ0DINS[D]
[3, 5, 7, 9, 11][7:0]
Agere Systems Inc.
Reserved.
Transmit Z0 Insert Value. See functional description
above.
—
0x0
Reserved.
0x0
Transmit Z0 Insert Value. See functional description
above.
0x0
Reserved.
Transmit Z0 Insert Value. See functional description
above.
Reserved.
Transmit Z0 Insert Value. See functional description
above.
—
0x0
—
0x0
0x0
235
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Descriptions (continued)
Table 89. Z0 Byte Ordering STS-48 Mode for Z0-1—Z0-47
Channel
Time Slots [1—12]
1
2
3
4
5
6
7
8
9
10
11
12
A
J0
Z0-12
Z0-24
Z0-36
Z0-1
Z0-13
Z0-25
Z0-37
Z0-2
Z0-14
Z0-26
Z0-38
B
Z0-3
Z0-15
Z0-27
Z0-39
Z0-4
Z0-16
Z0-28
Z0-40
Z0-5
Z0-17
Z0-29
Z0-41
C
Z0-6
Z0-18
Z0-30
Z0-42
Z0-7
Z0-19
Z0-31
Z0-43
Z0-8
Z0-20
Z0-32
Z0-44
D
Z0-9
Z0-21
Z0-33
Z0-45
Z0-10
Z0-22
Z0-34
Z0-46
Z0-11
Z0-23
Z0-35
Z0-47
Table 90. Z0 Byte Ordering STS-12 Mode for Z0-1—Z0-11
Channel
Time Slots [1—12]
1
2
3
4
5
6
7
8
9
10
11
12
A
J0
Z0-3
Z0-6
Z0-9
Z0-1
Z0-4
Z0-7
Z0-10
Z0-2
Z0-5
Z0-8
Z0-11
B
J0
Z0-3
Z0-6
Z0-9
Z0-1
Z0-4
Z0-7
Z0-10
Z0-2
Z0-5
Z0-8
Z0-11
C
J0
Z0-3
Z0-6
Z0-9
Z0-1
Z0-4
Z0-7
Z0-10
Z0-2
Z0-5
Z0-8
Z0-11
D
J0
Z0-3
Z0-6
Z0-9
Z0-1
Z0-4
Z0-7
Z0-10
Z0-2
Z0-5
Z0-8
Z0-11
Table 91. Z0 Byte Ordering STS-3 Mode for Z0-1—Z0-2
Channel
Time Slots [1—3]
1
2
3
A
J0
Z0-1
Z0-2
B
J0
Z0-1
Z0-2
C
J0
Z0-1
Z0-2
D
J0
Z0-1
Z0-2
Table 92. TOHP_SCRATCHR, 0x09C2, TOHP-48 Scratch Register (R/W)
Address
Bit
Name
Function
Reset
Default
0x09C2
15:0
TOHP_SCRATCH[15:0]
TOHP-48 Scratch Register. Allows the control
system to verify read and write operations to the
device without affecting device operation.
0x0000
236
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Map
Table 93. TOHP-48 Register Map
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TOHP_
INTL[D]
TOHP_
INTL[C]
TOHP_
INTL[B]
TOHP_
INTL[A]
TOHP_
OOFD[A]
TOHP_
LOFD[A]
TOHP_
LOSD[A]
TOHP_
LOCD[A]
TOHP-48 MODE—R/W and Block Version—RO
0x0800
TOHP_MODE
_VERR
TOHP_RX_MODE[2:0]
TOHP_TX_MODE[2:0]
TOHP_VER[9:0]
0x0801
TOHP_CH_
INT
0x0802
TOHP_DLT_
EVTA1
0x0803
TOHP_DLT_
EVTA2
0x0804
TOHP_DLT_
EVTB1
0x0805
TOHP_DLT_
EVTB2
0x0806
TOHP_DLT_
EVTC1
0x0807
TOHP_DLT_
EVTC2
0x0808
TOHP_DLT_
EVTD1
0x0809
TOHP_DLT_
EVTD2
0x080A
TOHP_RX_
TX_STATEA
TOHP_LRD TOHP_LAIS
IMON[A]
MON[A]
TOHP_TLR
DIINT[A]
TOHP_
SF[A]
TOHP_
SD[A]
TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC[
[A]
[A]
[A]
A]
0x080B
TOHP_RX_
TX_STATEB
TOHP_LRD TOHP_LAIS
IMON[B]
MON[B]
TOHP_TLR
DIINT[B]
TOHP_
SF[B]
TOHP_
SD[B]
TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC[
[B]
[B]
[B]
B]
0x080C
TOHP_RX_
TX_STATEC
TOHP_LRD TOHP_LAIS
IMON[C]
MON[C]
TOHP_TLR
DIINT[C]
TOHP_
SF[C]
TOHP_
SD[C]
TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC[
[C]
[C]
[C]
C]
0x080D
TOHP_RX_
TX_STATED
TOHP_LRD TOHP_LAIS
IMON[D]
MON[D]
TOHP_TLR
DIINT[D]
TOHP_
SF[D]
TOHP_
SD[D]
TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC[
[D]
[D]
[D]
D]
Channel Interrupts—RO
TOHP_
CORWN
TOHP_
INTH[D]
TOHP_
INTH[C]
TOHP_
INTH[B]
TOHP_
INTH[A]
TOHP-48 Delta and Event Parameters—COR/COW—RO
TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D TOHP_TTO TOHP_S1B
IMOND[A]
MOND[A]
SBABLEE MON4D[A] MON8D[A]
MOND[A]
2DMOND
MOND[A] AC_PERRE ABLEE[A]
[A]
[A]
[A]
TOHP_
SFD[A]
TOHP_
SDD[A]
TOHP_
TOHP_J0MI
TTOAC_K1
SE[A]
K2ERRE[A]
TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D
IMOND[B]
MOND[B]
SBABLEE MON4D[B] MON8D[B]
MOND[B]
2DMOND
MOND[B]
[B]
[B]
TOHP_S1B TOHP_SFD TOHP_SDD
ABLEE[B]
[B]
[B]
TOHP_
OOFD[B]
TOHP_
LOFD[B]
TOHP_
LOSD[B]
TOHP_
LOCD[B]
TOHP_
TOHP_J0MI
TTOAC_K1
SE[B]
K2ERRE[B]
TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D
IMOND[C]
MOND[C]
SBABLEE MON4D[C] MON8D[C]
MOND[C]
2DMOND
MOND[C]
[C]
[C]
TOHP_S1B TOHP_SFD TOHP_SDD
ABLEE[C]
[C]
[C]
TOHP_
OOFD[C]
TOHP_
LOFD[C]
TOHP_
LOSD[C]
TOHP_
LOCD[C]
TOHP_
TOHP_J0MI
TTOAC_K1
SE[C]
K2ERRE[C]
TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D
IMOND[D]
MOND[D]
SBABLEE MON4D[D] MON8D[D]
MOND[D]
2DMOND
MOND[D]
[D]
[D]
TOHP_S1B TOHP_SFD TOHP_SDD
ABLEE[D]
[D]
[D]
TOHP_
OOFD[D]
TOHP_
LOFD[D]
TOHP_
LOSD[D]
TOHP_
LOCD[D]
TOHP_
TTOAC_K1
K2ERRE[D]
TOHP_
J0MISE[D]
TOHP-48 Receive/Transmit State and Value Parameters—RO
Agere Systems Inc.
237
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Map (continued)
Table 93. TOHP-48 Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Interrupt Mask Parameters—R/W
0x080E
TOHP_
MSKA1
TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D TOHP_TTO TOHP_S1B TOHP_SFM
IMONM[A]
MONM[A]
SBABLEM MON4M[A] MON8M[A]
MONM
2DMONM
MONM[A]
ABLEM[A]
[A]
AC_PERR
[A]
[A]
[A]
M[A]
TOHP_SD
M[A]
TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC
M[A]
M[A]
M[A]
M[A]
0x080F
TOHP_
MSKA2
TOHP_INT
M[A]
0x0810
TOHP_
MSKB1
TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D
IMONM[B]
MONM[B]
SBABLEM MON4M[B] MON8M[B]
MONM[B]
2DMONM
MONM[B]
[B]
[B]
0x0811
TOHP_
MSKB2
TOHP_INT
M[B]
0x0812
TOHP_
MSKC1
TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D
IMONM[C]
MONM[C]
SBABLEM MON4M[C] MON8M[C] MONM[C]
2DMONM
MONM[C]
[C]
[C]
0x0813
TOHP_
MSKC2
TOHP_INT
M[C]
0x0814
TOHP_
MSKD1
TOHP_LRD TOHP_LAIS TOHP_RAP TOHP_S1D TOHP_S1D TOHP_K2D TOHP_K1K TOHP_F1D
IMONM[D]
MONM[D]
SBABLEM MON4M[D] MON8M[D] MONM[D]
2DMONM
MONM[D]
[D]
[D]
0x0815
TOHP_
MSKD2
TOHP_INT
M[D]
0x0816
TOHP_TRGA
TOHP_RSTN_SW[A][15:12]
TOHP_TA1 TOHP_SFC
LEAR[A]
A2ERREN
[A]
TOHP_
SFSET[A]
TOHP_SDC
LEAR[A]
TOHP_
SDSET[A]
0x0817
TOHP_TRGB
TOHP_RSTN_SW[B][15:12]
TOHP_TA1 TOHP_SFC
LEAR[B]
A2ERREN
[B]
TOHP_
SFSET[B]
TOHP_SDC
LEAR[B]
TOHP_
SDSET[B]
0x0818
TOHP_TRGC
TOHP_RSTN_SW[C][[15:12]
TOHP_TA1 TOHP_SFC
LEAR[C]
A2ERREN
[C]
TOHP_
SFSET[C]
TOHP_SDC
LEAR[C]
TOHP_
SDSET[C]
0x0819
TOHP_TRGD
TOHP_RSTN_SW[D][15:12]
TOHP_TA1 TOHP_SFC
LEAR[D]
A2ERREN
[D]
TOHP_
SFSET[D]
TOHP_SDC
LEAR[D]
TOHP_
SDSET[D]
TOHP_
TOHP_J0MI
TTOAC_K1
SM[A]
K2ERRM[A]
TOHP_S1B TOHP_SFM
ABLEM[B]
[B]
TOHP_SD
M[B]
TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC
M[B]
M[B]
M[B]
M[B]
TOHP_
TTOAC_K1
K2ERRM[B]
TOHP_S1B TOHP_SFM
ABLEM[C]
[C]
TOHP_SD
M[C]
J0MISM[B]
TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC
M[C]
M[C]
M[C]
M[C]
TOHP_
TOHP_J0MI
TTOAC_K1
SM[C]
K2ERRM[C]
TOHP_S1B TOHP_SFM
ABLEM[D]
[D]
TOHP_SD
M[D]
TOHP_OOF TOHP_LOF TOHP_LOS TOHP_LOC
M[D]
M[D]
M[D]
M[D]
TOHP_
TOHP_J0MI
TTOAC_K1
SM[D]
K2ERRM[D]
Triggers—R/W
238
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Map (continued)
Table 93. TOHP-48 Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Continuous N-Times Detect Values—R/W
0x081A
TOHP_
CNTDA1
0x081B
TOHP_
CNTDA2
0x081C
TOHP_
CNTDB1
0x081D
TOHP_
CNTDB2
0x081E
TOHP_
CNTDC1
0x081F
TOHP_
CNTDC2
0x0820
TOHP_
CNTDD1
0x0821
TOHP_
CNTDD2
0x0822
TOHP_
RCTLA1
0x0823
TOHP_
RCTLA2
0x0824
TOHP_
RCTLB1
0x0825
TOHP_
RCTLB2
0x0826
TOHP_
RCTLC1
0x0827
TOHP_
RCTLC2
0x0828
TOHP_
RCTLD1
0x0829
TOHP_
RCTLD2
0x082A
TOHP_
RCTLA3
0x082B
TOHP_
RCTLB3
TOHP_CNTDK2[A][3:0]
— (Version
2.2 and 2.3)
Reserved
(Version 2.0)
TOHP_CNTDK2[B][3:0]
— (Version
2.2 and 2.3)
Reserved
(Version 2.0)
TOHP_CNTDK2[C][3:0]
— (Version
2.2 and 2.3)
Reserved
(Version 2.0)
TOHP_CNTDK2[D][3:0]
— (Version
2.2 and 2.3)
Reserved
(Version 2.0)
TOHP_CNTDK1K2[A][3:0]
TOHP_CNTDF1[A][3:0]
TOHP_CNTDJ0Z0[A][3:0]
TOHP_CNTDS1BABLE[A][3:0]
TOHP_CNTDS1[A][3:0]
TOHP_CNTDK1K2FRAME[A][3:0]
TOHP_CNTDK1K2[B][3:0]
TOHP_CNTDF1[B][3:0]
TOHP_CNTDJ0Z0[B][3:0]
TOHP_CNTDS1BABLE[B][3:0]
TOHP_CNTDS1[B]3:0]
TOHP_CNTDK1K2FRAME[B][3:0]
TOHP_CNTDK1K2[C][3:0]
TOHP_CNTDF1[C][3:0]
TOHP_CNTDJ0Z0[C][3:0]
TOHP_CNTDS1BABLE[C][3:0]
TOHP_CNTDS1[C]3:0]
TOHP_CNTDK1K2FRAME[C][3:0]
TOHP_CNTDK1K2[D][3:0]
TOHP_CNTDF1[D][3:0]
TOHP_CNTDJ0Z0[D][3:0]
TOHP_CNTDS1BABLE[D][3:0]
TOHP_CNTDS1[D]3:0]
TOHP_CNTDK1K2FRAME[D][3:0]
Receive Control Parameters—R/W
TOHP_J0MONMODE
[A][1:0]
TOHP_M1B
ITBLKCNT
[A]
TOHP_J0MONMODE
[B][1:0]
TOHP_M1B
ITBLKCNT
[B]
TOHP_J0MONMODE
[C][1:0]
TOHP_M1B
ITBLKCNT
[C]
TOHP_J0MONMODE
[D][1:0]
TOHP_M1B
ITBLKCNT
[D]
Agere Systems Inc.
TOHP_RREFSEL[1:0]
TOHP_M1B TOHP_LAIS TOHP_LOF TOHP_OOF TOHP_LOS TOHP_SFB TOHP_SDB TOHP_CNT TOHP_S1M TOHP_K1K TOHP_B2BI TOHP_DSC TOHP_B1BI TOHP_ROH
INS[A]
_AISINH[A] _AISINH[A] _AISINH[A] 1B2SEL[A] 1B2SEL[A] DB1SEL[A] ON8OR4CT 2_2OR1[A] TBLKCNT
RINH[A]
TBLKCNT
_BYPASS
7IGNORE
L[A]
[A]
[A]
[A]
[A]
TOHP_RVA
LIDK_CTL
[A]
TOHP_LOSDETCNT[A][12:0]
TOHP_M1B TOHP_LAIS TOHP_LOF TOHP_OOF TOHP_LOS TOHP_SFB TOHP_SDB TOHP_CNT TOHP_S1M TOHP_K1K TOHP_B2BI TOHP_DSC TOHP_B1BI TOHP_ROH
INS[B]
_AISINH[B] _AISINH[B] _AISINH[B] 1B2SEL[B] 1B2SEL[B] DB1SEL[B] ON8OR4CT 2_2OR1[B] TBLKCNT
RINH[B]
TBLKCNT
_BYPASS
7IGNOR[B]
L[B]
[B]
[B]
[B]
TOHP_RVA
LIDK_CTL
[B]
TOHP_LOSDETCNT[B][12:0]
TOHP_M1B TOHP_LAIS TOHP_LOF TOHP_OOF TOHP_LOS TOHP_SFB TOHP_SDB TOHP_CNT TOHP_S1M TOHP_K1K TOHP_B2BI TOHP_DSC TOHP_B1BI TOHP_ROH
INS[C]
_AISINH[C] _AISINH[C] _AISINH[C] 1B2SEL[C] 1B2SEL[C] DB1SEL[C] ON8OR4CT 2_2OR1[C] TBLKCNT
RINH[C]
TBLKCNT
_BYPASS
7IGNORE
L[C]
[C]
[C]
[C]
[C]
TOHP_RVA
LIDK_CTL
[C]
TOHP_LOSDETCNT[C][12:0]
TOHP_M1B TOHP_LAIS TOHP_LOF TOHP_OOF TOHP_LOS TOHP_SFB TOHP_SDB TOHP_CNT TOHP_S1M TOHP_K1K TOHP_B2BI TOHP_DSC TOHP_B1BI TOHP_ROH
INS[D]
_AISINH[D] _AISINH[D] _AISINH[D] 1B2SEL[D] 1B2SEL[D] DB1SEL[D] ON8OR4CT 2_2OR1[D] TBLKCNT
RINH[D]
TBLKCNT
_BYPASS
7IGNORE
L[D]
[D]
[D]
[D]
[D]
TOHP_RVA
LIDK_CTL
[D]
TOHP_
RREF_EN
TOHP_LOSDETCNT[D][12:0]
TOHP_
RREF_INH
TOHP_RTO TOHP_RTO TOHP_RTO TOHP_RTO
ACSINH[A] ACCINH[A] ACDINH[A] AC_OEPIN
S[A]
TOHP_RTO TOHP_RTO TOHP_RTO TOHP_RTO
ACSINH[B] ACCINH[B] ACDINH[B] AC_OEPIN
S[B]
239
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Map (continued)
Table 93. TOHP-48 Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x082C
TOHP_
RCTLC3
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
TOHP_RTO TOHP_RTO TOHP_RTO TOHP_RTO
ACSINH[C] ACCINH[C] ACDINH[C] AC_OEPIN
S[C]
Bit 3
Bit 2
Bit 1
Bit 0
0x082D
TOHP_
RCTLD3
TOHP_RTO TOHP_RTO TOHP_RTO TOHP_RTO
ACSINH[D] ACCINH[D] ACDINH[D] AC_OEPIN
S[D]
0x082E
TOHP_
TCTLA1
0x082F
TOHP_
TCTLA2
0x0830
TOHP_
TCTLB1
0x0831
TOHP_
TCTLB2
0x0832
TOHP_
TCTLC1
0x0833
TOHP_
TCTLC2
0x0834
TOHP_
TCTLD1
0x0835
TOHP_
TCTLD2
0x0836
TOHP_
TCTLA3
TOHP_
TAPSINS[A]
TOHP_TK2SINS[A][1:0]
TOHP_TVA
LIDK_
CTL[A]
TOHP_TAISLINS[A][11:0]
0x0837
TOHP_
TCTLB3
TOHP_
TAPSINS[B]
TOHP_TK2SINS[B][1:0]
TOHP_TVA
LIDK_
CTL[B]
TOHP_TAISLINS[B][11:0]
0x0838
TOHP_
TCTLC3
TOHP_
TAPSINS
[C]
TOHP_TK2SINS[C][1:0]
TOHP_TVA
LIDK_
CTL[C]
TOHP_TAISLINS[C][11:0]
0x0839
TOHP_
TCTLD3
TOHP_
TAPSINS
[D]
TOHP_TK2SINS[D][1:0]
TOHP_TVA
LIDK_
CTL[D]
TOHP_TAISLINS[D][11:0]
Transmit Control Parameters—R/W
240
TOHP_TTO TOHP_TJ0I TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TAP TOHP_TM1 TOHP_TM1
ACINH
NS[A]
AC_J0[A]
AC_OEPM AC_INS[A]
AC_E2[A]
AC_S1[A] AC_D4TO1 AC_D1TO3 AC_F1[A]
AC_E1[A]
SBABLEIN _ERR_INS _REIL_INH
ON[A]
2[A]
[A]
S[A]
[A]
[A]
TOHP_TA1A2ERRINS[A][4:0]
TOHP_
TTOAC_
K1K2[A]
TOHP_TJ0I TOHP_TTO
NS[B]
AC_J0[B]
TOHP_
TTOAC_
K1K2[B]
TOHP_TA1A2ERRINS[B][4:0]
TOHP_
TOHP_TJ0I TOHP_TTO
TTOAC_VA
NS[C]
AC_J0[C]
LIDK_CTL
TOHP_
TTOAC_
K1K2[C]
TOHP_TA1A2ERRINS[C][4:0]
TOHP_
TOHP_TJ0I TOHP_TTO
TK2SWHWI
NS[D]
AC_J0[D]
NS_INH
TOHP_
TTOAC_
K1K2[D]
TOHP_TA1A2ERRINS[D][4:0]
TOHP_TOH TOHP_SCR TOHP_TB1
_BYPASS
INH[A]
ERRINS[A]
[A]
TOHP_TB2 TOHP_TIM TOHP_TSF TOHP_TLAI TOHP_TLO TOHP_TOO TOHP_TLO
ERRINS[A] ER_LRDIIN _LRDIINH SMON_LR F_LRDIINH F_LRDIINH S_LRDIINH
H[A]
[A]
DIINH[A]
[A]
[A]
[A]
TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TAP TOHP_TM1 TOHP_TM1
AC_INS[B]
AC_E2[B]
AC_S1[B] AC_D4TO1 AC_D1TO3 AC_F1[B]
AC_E1[B]
SBABLEIN _ERR_INS _REIL_INH
2[B]
[B]
S[B]
[B]
[B]
TOHP_TOH TOHP_SCR TOHP_TB1
_BYPASS[B
INH[B]
ERRINS[B]
]
TOHP_
TS1INS[A]
TOHP_TLO
C_LRDIINH
[A]
TOHP_
TS1INS[B]
TOHP_TLO
C_LRDIINH
[B]
TOHP_
TF1INS[C]
TOHP_
TS1INS[C]
TOHP_TB2 TOHP_TIM TOHP_TSF TOHP_TLAI TOHP_TLO TOHP_TOO TOHP_TLO
ERRINS[C] ER_LRDIIN _LRDIINH SMON_LR F_LRDIINH F_LRDIINH S_LRDIINH
H[C]
[C]
DIINH[C]
[C]
[C]
[C]
TOHP_TLO
C_LRDIINH
[C]
TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TAP TOHP_TM1 TOHP_TM1
AC_INS[D]
AC_E2[D]
AC_S1[D] AC_D4TO1 AC_D1TO3 AC_F1[D]
AC_E1[D]
SBABLEIN _ERR_INS _REIL_INH
2[D]
[D]
S[D]
[D]
[D]
TOHP_TOH TOHP_SCR TOHP_TB1
_BYPASS
INH[D]
ERRINS[D]
[D]
TOHP_
TF1INS[B]
TOHP_TB2 TOHP_TIM TOHP_TSF TOHP_TLAI TOHP_TLO TOHP_TOO TOHP_TLO
ERRINS[B] ER_LRDIIN _LRDIINH SMON_LR F_LRDIINH F_LRDIINH S_LRDIINH
H[B]
[B]
DIINH[B]
[B]
[B]
[B]
TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TTO TOHP_TAP TOHP_TM1 TOHP_TM1
AC_INS[C]
AC_E2[C]
AC_S1[C] AC_D4TO1 AC_D1TO3 AC_F1[C]
AC_E1[C]
SBABLEIN _ERR_INS _REIL_INH
2[C]
[C]
S[C]
[C]
[C]
TOHP_TOH TOHP_SCR TOHP_TB1
_BYPASS
INH[C]
ERRINS[C]
[C]
TOHP_
TF1INS[A]
TOHP_
TF1INS[D]
TOHP_
TS1INS[D]
TOHP_TB2 TOHP_TIM TOHP_TSF TOHP_TLAI TOHP_TLO TOHP_TOO TOHP_TLO
ERRINS[D] ER_LRDIIN _LRDIINH SMON_LR F_LRDIINH F_LRDIINH S_LRDIINH
H[D]
[D]
DIINH[D]
[D]
[D]
[D]
TOHP_TLO
C_LRDIINH
[D]
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Map (continued)
Table 93. TOHP-48 Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Signal Degrade Set/Clear Control Registers—R/W
0x083A
TOHP_SD_
SETRA1
0x083B
TOHP_SD_
SETRA2
0x083C
TOHP_SD_
SETRB1
0x083D
TOHP_SD_
SETRB2
0x083E
TOHP_SD_
SETRC1
0x083F
TOHP_SD_
SETRC2
0x0840
TOHP_SD_
SETRD1
0x0841
TOHP_SD_
SETRD2
0x0842
TOHP_SD_
SETRA3
TOHP_SDBSET[A][15:0]
0x0843
TOHP_SD_
SETRB3
TOHP_SDBSET[B][15:0]
0x0844
TOHP_SD_
SETRC3
TOHP_SDBSET[C][15:0]
0x0845
TOHP_SD_
SETRD3
TOHP_SDBSET[D][15:0]
0x0846
TOHP_SD_
CLEARRA1
TOHP_SDNSCLEAR[A][17:2]
0x0847
TOHP_SD_
CLEARRA2
0x0848
TOHP_SD_
CLEARRB1
0x0849
TOHP_SD_
CLEARRB2
0x084A
TOHP_SD_
CLEARRC1
0x084B
TOHP_SD_
CLEARRC2
0x084C
TOHP_SD_
CLEARRD1
0x084D
TOHP_SD_
CLEARRD2
Agere Systems Inc.
TOHP_SDNSSET[A][17:2]
TOHP_SDMSET[A][6:0]
TOHP_SDLSET[A][6:0]
TOHP_SDNSSET[A][1:0]
TOHP_SDLSET[B][6:0]
TOHP_SDNSSET[B][1:0]
TOHP_SDLSET[C][6:0]
TOHP_SDNSSET[C][1:0]
TOHP_SDLSET[D][6:0]
TOHP_SDNSSET[D][1:0]
TOHP_SDLCLEAR[A][6:0]
TOHP_SDNSCLEAR
[A][1:0]
TOHP_SDLCLEAR[B][6:0]
TOHP_SDNSCLEAR
[B][1:0]
TOHP_SDLCLEAR[C][6:0]
TOHP_SDNSCLEAR
[C][1:0]
TOHP_SDLCLEAR[D][6:0]
TOHP_SDNSCLEAR
[D][1:0]
TOHP_SDNSSET[B][17:2]
TOHP_SDMSET[B][6:0]
TOHP_SDNSSET[C][17:2]
TOHP_SDMSET[C][6:0]
TOHP_SDNSSET[D][17:2]
TOHP_SDMSET[D][6:0]
TOHP_SDMCLEAR[A][6:0]
TOHP_SDNSCLEAR[B][17:2]
TOHP_SDMCLEAR[B][6:0]
TOHP_SDNSCLEAR[C][17:2]
TOHP_SDMCLEAR[C][6:0]
TOHP_SDNSCLEAR[D][17:2]
TOHP_SDMCLEAR[D][6:0]
241
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Map (continued)
Table 93. TOHP-48 Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x084E
TOHP_SD_
CLEARRA3
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
TOHP_SDBCLEAR[A][15:0]
Bit 8
Bit 7
0x084F
TOHP_SD_
CLEARRB3
TOHP_SDBCLEAR[B][15:0]
0x0850
TOHP_SD_
CLEARRC3
TOHP_SDBCLEAR[C][15:0]
0x0851
TOHP_SD_
CLEARRD3
TOHP_SDBCLEAR[D][15:0]
0x0852
TOHP_SF_
SETRA1
0x0853
TOHP_SF_
SETRA2
0x0854
TOHP_SF_
SETRB1
0x0855
TOHP_SF_
SETRB2
0x0856
TOHP_SF_
SETRC1
0x0857
TOHP_SF_
SETRC2
0x0858
TOHP_SF_
SETRD1
0x0859
TOHP_SF_
SETRD2
0x085A
TOHP_SF_
SETRA3
TOHP_SFBSET[A][15:0]
0x085B
TOHP_SF_
SETRB3
TOHP_SFBSET[B][15:0]
0x085C
TOHP_SF_
SETRC3
TOHP_SFBSET[C][15:0]
0x085D
TOHP_SF_
SETRD3
TOHP_SFBSET[D][15:0]
0x085E
TOHP_SF_
CLEARRA1
TOHP_SFNSCLEAR[A][17:2]
0x085F
TOHP_SF_
CLEARRA2
0x0860
TOHP_SF_
CLEARRB1
0x0861
TOHP_SF_
CLEARRB2
0x0862
TOHP_SF_
CLEARRC1
0x0863
TOHP_SF_
CLEARRC2
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Signal Fail Set/Clear Control Registers—R/W
242
TOHP_SFNSSET[A][17:2]
TOHP_SFMSET[A][5:0] Applies for version 2.2 and 2.3 only.
TOHP_SFMSET[A][6:0] Applies for version 2.0 only.
TOHP_SFLSET[A][7:0] Applies for version 2.2 and 2.3 only.
TOHP_SFLSET[A][6:0] Applies for version 2.0 only.
TOHP_SFNSSET[A][1:0]
TOHP_SFNSSET[B][17:2]
TOHP_SFMSET[B][5:0] Applies for version 2.2 and 2.3 only.
TOHP_SFMSET[B][6:0] Applies for version 2.0 only.
TOHP_SFLSET[B][7:0] Applies for version 2.2 and 2.3 only.
TOHP_SFLSET[B][6:0] Applies for version 2.0 only.
TOHP_SFNSSET[B][1:0]
TOHP_SFNSSET[C][17:2]
TOHP_SFMSET[C][5:0] Applies for version 2.2 and 2.3 only.
TOHP_SFMSET[C][6:0] Applies for version 2.0 only.
TOHP_SFLSET[C][7:0] Applies for version 2.2 and 2.3 only.
TOHP_SFLSET[C][6:0] Applies for version 2.0 only.
TOHP_SFNSSET[C][1:0]
TOHP_SFNSSET[D][17:2]
TOHP_SFMSET[D][5:0] Applies for version 2.2 and 2.3 only.
TOHP_SFMSET[D][6:0] Applies for version 2.0 only.
TOHP_SFLSET[D][7:0] Applies for version 2.2 and 2.3 only.
TOHP_SFLSET[D][6:0] Applies for version 2.0 only.
TOHP_SFMCLEAR[A][6:0]
TOHP_SFNSSET[D][1:0]
TOHP_SFLCLEAR[A][6:0]
TOHP_SFNSCLEAR
[A][1:0]
TOHP_SFLCLEAR[B][6:0]
OHP_SFNSCLEAR
[B][1:0]
TOHP_SFLCLEAR[C][6:0]
OHP_SFNSCLEAR
[C][1:0]
TOHP_SFNSCLEAR[B][17:2]
TOHP_SFMCLEAR[B][6:0]
TOHP_SFNSCLEAR[C][17:2]
TOHP_SFMCLEAR[C][6:0]
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Map (continued)
Table 93. TOHP-48 Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x0864
TOHP_SF_
CLEARRD1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
0x0865
TOHP_SF_
CLEARRD2
0x0866
TOHP_SF_
CLEARRA3
TOHP_SFBCLEAR[A][15:0]
0x0867
TOHP_SF_
CLEARRB3
TOHP_SFBCLEAR[B][15:0]
0x0868
TOHP_SF_
CLEARRC3
TOHP_SFBCLEAR[C][15:0]
0x0869
TOHP_SF_
CLEARRD3
TOHP_SFBCLEAR[D][15:0]
0x086A
TOHP_
B1ECNTRA
TOHP_B1ECNT[A][15:0]
0x086B
TOHP_
B1ECNTRB
TOHP_B1ECNT[B][15:0]
0x086C
TOHP_
B1ECNTRC
TOHP_B1ECNT[C][15:0]
0x086D
TOHP_
B1ECNTRD
TOHP_B1ECNT[D][15:0]
0x086E
TOHP_
B2ECNTRA1
0x086F
TOHP_
B2ECNTRA2
0x0870
TOHP_
B2ECNTRB1
0x0871
TOHP_
B2ECNTRB2
0x0872
TOHP_
B2ECNTRC1
0x0873
TOHP_
B2ECNTRC2
0x0874
TOHP_
B2ECNTRD1
0x0875
TOHP_
B2ECNTRD2
0x0876
TOHP_
M1ECNTRA1
0x0877
TOHP_
M1ECNTRA2
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TOHP_SFNSCLEAR[D][17:2]
TOHP_SFMCLEAR[D][6:0]
TOHP_SFLCLEAR[D][6:0]
OHP_SFNSCLEAR
[D][1:0]
B1, B2, and M1 Error Counts—RO
Agere Systems Inc.
TOHP_B2ECNT[A][21:16]
TOHP_B2ECNT[A][15:0]
TOHP_B2ECNT[B][21:16]
TOHP_B2ECNT[B][15:0]
TOHP_B2ECNT[C][21:16]
TOHP_B2ECNT[C][15:0]
TOHP_B2ECNT[D][21:16]
TOHP_B2ECNT[D][15:0]
TOHP_M1ECNT[A][20:16]
TOHP_M1ECNT[A][15:0]
243
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Map (continued)
Table 93. TOHP-48 Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x0878
TOHP_
M1ECNTRB1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x0879
TOHP_
M1ECNTRB2
0x087A
TOHP_
M1ECNTRC1
0x087B
TOHP_
M1ECNTRC2
0x087C
TOHP_
M1ECNTRD1
0x087D
TOHP_
M1ECNTRD2
0x087E
TOHP_TOH_
INSRA1
TOHP_TF1DINS[A][7:0]
TOHP_TS1DINS[A][7:0]
0x087F
TOHP_TOH_
INSRA2
TOHP_TK2DINS[A][7:0]
TOHP_TK1DINS[A][7:0]
0x0880
TOHP_TOH_
INSRB1
TOHP_TF1DINS[B][7:0]
TOHP_TS1DINS[B][7:0]
0x0881
TOHP_TOH_
INSRB2
TOHP_TK2DINS[B][7:0]
TOHP_TK1DINS[B][7:0]
0x0882
TOHP_TOH_
INSRC1
TOHP_TF1DINS[C][7:0]
TOHP_TS1DINS[C][7:0]
0x0883
TOHP_TOH_
INSRC2
TOHP_TK2DINS[C][7:0]
TOHP_TK1DINS[C][7:0]
0x0884
TOHP_TOH_
INSRD1
TOHP_TF1DINS[D][7:0]
TOHP_TS1DINS[D][7:0]
0x0885
TOHP_TOH_
INSRD2
TOHP_TK2DINS[D][7:0]
TOHP_TK1DINS[D][7:0]
0x0886
TOHP_
RMONRA1
TOHP_F1DMON1[A][7:0]
TOHP_F1DMON0[A][7:0]
0x0887
TOHP_
RMONRA2
TOHP_K2DMON[A][7:0]
TOHP_K1DMON[A][7:0]
0x0888
TOHP_
RMONRA3
0x0889
TOHP_
RMONRB1
TOHP_F1DMON1[B][7:0]
TOHP_F1DMON0[B][7:0]
0x088A
TOHP_
RMONRB2
TOHP_K2DMON[B][7:0]
TOHP_K1DMON[B][7:0]
0x088B
TOHP_
RMONRB3
0x088C
TOHP_
RMONRC1
Bit 2
Bit 1
Bit 0
TOHP_M1ECNT[B][20:16]
TOHP_M1ECNT[B][15:0]
TOHP_M1ECNT[C][20:16]
TOHP_M1ECNT[C][15:0]
TOHP_M1ECNT[D][20:16]
TOHP_M1ECNT[D][15:0]
Transmit OH Insert Value—R/W
Receive Monitor Values—RO
244
TOHP_S1DMON[A][7:0]
TOHP_S1DMON[B][7:0]
TOHP_F1DMON1[C][7:0]
TOHP_F1DMON0[C][7:0]
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Map (continued)
Table 93. TOHP-48 Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x088D
TOHP_
RMONRC2
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
0x088E
TOHP_
RMONRC3
0x088F
TOHP_
RMONRD1
TOHP_F1DMON1[D][7:0]
TOHP_F1DMON0[D][7:0]
0x0890
TOHP_
RMONRD2
TOHP_K2DMON[D][7:0]
TOHP_K1DMON[D][7:0]
0x0891
TOHP_
RMONRD3
0x0892—
0x08B1
TOHP_RJ0DM
ONR[A][1—32]
TOHP_RJ0DMON[A][2, 4, 6, . . ., 64][7:0]
TOHP_RJ0DMON[A][1, 3, 5, . . ., 63][7:0]
0x08B2—
0x08D1
TOHP_RJ0DM
ONR[B][1—32]
TOHP_RJ0DMON[B][2, 4, 6, . . ., 64][7:0]
TOHP_RJ0DMON[B][1, 3, 5, . . ., 63][7:0]
0x08D2—
0x08F1
TOHP_RJ0DM
ONR[C][1—32]
TOHP_RJ0DMON[C][2, 4, 6, . . ., 64][7:0]
TOHP_RJ0DMON[C][1, 3, 5, . . ., 63][7:0]
0x08F2—
0x0911
TOHP_RJ0DM
ONR[D][1—32]
TOHP_RJ0DMON[D][2, 4, 6, . . ., 64][7:0]
TOHP_RJ0DMON[D][1, 3, 5, . . ., 63][7:0]
0x0912—
0x0931
TOHP_TJ0DIN
SR[A][1—32]
TOHP_TJ0DINS[A][2, 4, 6, . . ., 64][7:0]
TOHP_TJ0DINS[A][1, 3, 5, . . ., 63][7:0]
0x0932—
0x0951
TOHP_TJ0DIN
SR[B][1—32]
TOHP_TJ0DINS[B][2, 4, 6, . . ., 64][7:0]
TOHP_TJ0DINS[B][1, 3, 5, . . ., 63][7:0]
0x0952—
0x0971
TOHP_TJ0DIN
SR[C][1—32]
TOHP_TJ0DINS[C][2, 4, 6, . . ., 64][7:0]
TOHP_TJ0DINS[C][1, 3, 5, . . ., 63][7:0]
0x0972—
0x09A9
TOHP_TJ0DIN
SR[D][1—32]
TOHP_TJ0DINS[D][2, 4, 6, . . ., 64][7:0]
TOHP_TJ0DINS[D][1, 3, 5, . . ., 63][7:0]
TOHP_K2DMON[C][7:0]
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TOHP_K1DMON[C][7:0]
TOHP_S1DMON[C][7:0]
TOHP_S1DMON[D][7:0]
J0 Byte Receive Monitor (64 bytes)—RO
J0 Byte Transmit Insert (64 bytes)—R/W
Agere Systems Inc.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Transport Overhead Processor (TOHP-48) Block (continued)
TOHP-48 Register Map (continued)
Table 93. TOHP-48 Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Z0 Byte Transmit Insert—R/W
0x09AA
TOHP_TZ0DIN
SR[A][1]
TOHP_TZ0DINS[A][2][7:0]
0x09AB—
0x09AF
TOHP_TZ0DIN
SR[A][2—6]
TOHP_TZ0DINS[A][4, 6, 8, 10, 12][7:0]
0x09B0
TOHP_TZ0DIN
SR[B][1]
TOHP_TZ0DINS[B][2][7:0]
0x09B1—
0x09B5
TOHP_TZ0DIN
SR[B][2—6]
TOHP_TZ0DINS[B][4, 6, 8, 10, 12][7:0]
0x09B6
TOHP_TZ0DIN
SR[C][1]
TOHP_TZ0DINS[C][2][7:0]
0x09B7—
0x09BB
TOHP_TZ0DIN
SR[C][2—6]
TOHP_TZ0DINS[C][4, 6, 8, 10, 12][7:0]
0x09BC
TOHP_TZ0DIN
SR[D][1]
TOHP_TZ0DINS[D][2][7:0]
0x09BD—
0x09C1
TOHP_TZ0DIN
SR[D][2—6]
TOHP_TZ0DINS[D][4, 6, 8, 10, 12][7:0]
0x09C2
TOHP_
SCRATCHR
TOHP_TZ0DINS[A][3, 5, 7, 9, 11][7:0]
TOHP_TZ0DINS[B][3, 5, 7, 9, 11][7:0]
TOHP_TZ0DINS[C][3, 5, 7, 9, 11][7:0]
TOHP_TZ0DINS[D][3, 5, 7, 9, 11][7:0]
Scratch Register—R/W
TOHP_SCRATCH[15:0]
0x09C3—
0x09FF
246
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP)
Introduction
The pointer processor block handles one STS-48 stream (single-channel mode) or four STS-12 or STS-3 streams
(quad-channel mode).
The pointer processor performs pointer interpretation, path overhead (POH) monitoring, and generates a new STS
frame aligned to the system frame pulse. The pointer interpreter block interprets the incoming H1/H2 pointer of
each incoming STS channel. The pointer interpreter supports up to 48 channels and performs path overhead monitoring on each channel. Each channel may be either an STS-1, STS-3c, STS-6c, STS-9c, . . . , STS-45c, STS48c. An STS-3nc channel must start at time slots 1, 4, 7, 10, . . . , or 46 (assuming that it can fit). For example, an
STS-36c must start in time slots 1, 4, 7, 10, or 13; an STS-45c must start at time slot 1 or 4.
The pointer is validated according to Telcordia and ITU specifications. The H1/H2 pointer is used to determine the
location of the first path overhead (POH) byte (J1). The pointer interpreter consists of a finite state machine (FSM)
with four steady states. These states are defined as:
■
Normal state
■
Loss of pointer (LOP)
■
Alarm indication signal (AIS)
■
Concatenation
The transition between states will require several consecutive events to protect against transient conditions
caused by bit errors during high BER conditions.
This pointer processor block monitors for the following conditions and takes appropriate actions:
■
Pointer increment
■
Pointer decrement
■
Loss of pointer
■
AIS-P
■
New pointer
■
Invalid pointer
Receive Path Trace
The path trace message is extracted and stored in a 64-byte memory that can be accessed through the microprocessor interface. The first byte of the message can be provisioned to be either: the byte with the most significant bit
(MSB) set high, or the byte following a carriage return (0x0D) and line feed (0x0A) sequence. This frame synchronization can be disabled.
Agere Systems Inc.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
Introduction (continued)
Receive Error Monitor
The PBIP block counts path BIP-8 errors. A theoretical maximum of 64,000 (x concatenation level) errors may be
detected per second. A practical average of 32,000 errors per second will be detected under the worst error conditions. The PBIP block accumulates these errors in a 16-bit saturating counter. This counter is operated in latch and
clear mode to ensure Telcordia and ITU compliance with regard to not missing any events (bit errors). It is intended
that this counter be polled at least once per second to ensure that no error events are missed. The REI_P block
counts remote error indication (formally known as FEBE) block errors.
Receive Signal Label
The C2 block will extract and validate the signal label byte (C2) and store it in registers PP_TSC2R[1—24], Time
Slots 1—48 Path C2 Status (RO), Table 247, addresses 0x1930—0x1947.
Receive Path Status
The G1 block extracts the path remote error indication (REI-P) bits of G1 and accumulates the REI-P errors in a 16bit saturating counter. This counter is operated in latch and clear mode to ensure Telcordia and ITU compliance. It
is intended that this counter be polled at least once per second to ensure that no error events are missed.
This block will also validate the path remote defect indication (RDI-P) bits and store the result in registers
PP_TSRDIPR[1—48], Time Slots 1—48 Path RDI Status (RO), Table 246, addresses 0x1900—0x192F.
Elastic Store
For each STS channel, the SPE is placed into an elastic store buffer. The system (transmit) clock and 8 kHz frame
is used to generate a new STS frame with the SPE extracted from the elastic store. The level of the elastic store is
monitored and positive/negative stuffs are performed on the new STS frame in order to prevent elastic store overflows/underflows.
248
Agere Systems Inc.
Data Sheet
August 19, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
Introduction (continued)
Z5/N1, Z4/K4, Z3/F3, H4, and F2 Monitoring
Also monitored are the F2 user channel byte, the H4 VT multiframe indicator byte, Z3/F3 growth/user byte, Z4/K4
growth/APS path byte, and the Z5/N1 tandem connection byte. These bytes are stored in software registers. These
registers are updated when a provisionable number of detections of new values occurs on the associated incoming
byte. Note that there are four circuits—1 per STS-12 channel, each monitoring the Z5/N1, Z4/K4, Z3/F3, H4, and
F2 bytes of their selected STS-1 stream.
SS Bits Monitoring
Although the SS bits are not defined at the STS-N level in GR-253, SDH-based equipment supports the SS bits
monitoring feature. Therefore, for SDH conformance the SS bits, contained in the H1 byte, are stored in software
registers. These registers are updated when a provisionable number of mismatches occurs in the provisioned
mode. The same registers are updated when a provisionable number of detections of new values of the SS bits
occurs while in the validation mode. In both the provisioned and validation mode, the processor is interrupted when
a mismatch or a validation takes place. In SDH, only 16 channels need to be monitored (1 per STS-3 stream) and
the register space is extended to cover 48 STS-1s. SS bits monitoring is enabled only when the J1 message type
is set to SDH (register 0x1339, Table 181).
E1 and F1 Path Status Bytes
Each STS-1 time slot will contain an independent E1/F1 value. For each STS-1 time slot, the E1 and F1 bytes will
be identical (E1 = F1) and will contain a code indicating the status of that time slot. The following values are
defined for E1/F1. This is a priority encoder, only one status condition can be communicated at once, the higher
conditions in the following table having higher priority. Note that the PDI code received (if one is received) will not
be considered unless the PDI validate enable is set.
Table 94. E1/F1 Path Status Definition
E1/F1 Value
Definition
0011 1111
Loss of Pointer (LOP-P) repass AIS.
1111 1111
Concatenation Mismatch or Software Insertion of AIS.
0011 1110
Unequipped Signal Label (UNEQ-P).
0001 1100
Trace Identifier (J1) Mismatch (TIM-P).
0011 1101
Signal Fail (SF).
0011 1100
PDI code 28
to
0010 0001
to
PDI code 1
(This E1/F1 value will only occur if the corresponding bit in the PDI
VALIDATE ENABLE register is high).
0001 1111
Signal Degrade (SD).
0001 1110
Payload Label Mismatch (PLM-P).
0000 0000
No Alarms.
This value can be overwritten by software by setting the E1/F1_INSERT_CONTROL register for those individual
Sets one wishes to override and placing the desired byte in the corresponding E1/F1 INSERT register.
Agere Systems Inc.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
Detailed Description
The pointer processor is used to transfer input stream(s) to the system timing of the device. It can accept one STS48 or 4 STS-12 or STS-3 streams. In single-channel mode, the input stream is converted to four STS-12 signals, all
on system timing. In quad-channel mode, the same output is produced from four asynchronous input streams of
either STS-12 or STS-3 capacities. The four outgoing streams are synchronized to the system clock and system
frame sync. A block diagram is shown in Figure 36 on page 251.
The main blocks of this block are the time-slot interchange (TSI), four STS-12 pointer processor modules, and the
microprocessor interface. The TSI is required because the pointer processor operates at an STS-12 granularity.
The TSI is only used in the STS-48 mode.
In OC-3 mode, the pointer processor still operates at an STS-12 rate and data bytes are replicated four times to
achieve this as shown in Figure 35.
STS-3
STS-12
#1 STS-1
#2 STS-1
#3 STS-1
#1 STS-1
1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1
#1 STS-1s #2 STS-1s #3 STS-1s
5-8151(F)r.2
Figure 35. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of Pointer Processor
The pointer processor block requires a frame pulse for each input stream. In the MARS2G5 P-Pro device, these
four signals are provided from the transport overhead processor block. The pointer processor block performs intermediate performance monitoring of the input stream(s), and can interrupt the host microprocessor with alarms and
make available the collected results through a register set.
The pointer processor is SONET and SDH compliant.
250
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
Detailed Description (continued)
ADDRESS_BUS[7:0]
RX_LTE_STS_DATA[31:0]
FRAME_PULSE_PP_1
RX_CLK_1
BUS CONTROL SIGNALS
TSI
(TIME-SLOT
INTERCHANGE)
RX_RST_N1
MICROPROCESSOR
INTERFACE
WRITE_DATA_BUS[15:0]
READ_DATA_BUS[15:0]
INTERRUPTS
PP_STS_DATA_1[7:0]
RX_LTE_STS_DATA[31:24]
FRAME_PULSE_RX_LTE1
RX_CLK_1
RX_RST_N1
POINTER
INTERPRETER
ELASTIC
STORE
RX_CLK_1 TIMING
POINTER
GENERATOR
FRAME_PULSE_PP_1
SYSTEM TIMING
PP_STS_DATA_2[7:0]
RX_LTE_STS_DATA[23:16]
FRAME_PULSE_RX_LTE2
RX_CLK_2
RX_RST_N2
POINTER
INTERPRETER
ELASTIC
STORE
RX_CLK_2 TIMING
POINTER
GENERATOR
FRAME_PULSE_PP_2
SYSTEM TIMING
PP_STS_DATA_3[7:0]
RX_LTE_STS_DATA[15:8]
FRAME_PULSE_RX_LTE3
RX_CLK_3
RX_RST_N3
POINTER
INTERPRETER
ELASTIC
STORE
RX_CLK_3 TIMING
POINTER
GENERATOR
FRAME_PULSE_PP_3
SYSTEM TIMING
PP_STS_DATA_4[7:0]
RX_LTE_STS_DATA[7:0]
FRAME_PULSE_RX_LTE4
RX_CLK_4
RX_RST_N4
POINTER
INTERPRETER
ELASTIC
STORE
RX_CLK_4 TIMING
POINTER
GENERATOR
FRAME_PULSE_PP_4
SYSTEM TIMING
5-8152(F)r.1
Figure 36. Top Level Block Diagram of the Pointer Processor Block
The STS pointer processor is used for phase absorption and frequency synchronization of SONET payload from
one clock domain (the receive or line timing) to another (the transmit or system timing). This is accomplished in
three basic functions: pointer interpreter, elastic store, and pointer generator. The pointer interpreter extracts the
SONET synchronous payload envelope (SPE) from the incoming data by interpreting the H1 and H2 pointer bytes
of the line overhead. The SPE is then written to the elastic store. The pointer generator reads the SPE from the
elastic store and regenerates the H1 and H2 pointer bytes. Since the pointer processor does not terminate the
path, intermediate performance monitoring is performed (i.e., the path overhead is not modified). A block diagram
of the pointer processor is shown in Figure 36, above.
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
Detailed Description (continued)
Performance Monitoring
This block accepts the payload mapping information, status, and timing from the Rx pointer interpreter and extracts
the path overhead from up to 12 STS channels. The extracted overhead is then either stored internally or provided
externally on a serial output, and may also be further processed for alarm or performance-monitoring purposes.
While an STS channel is in AIS or LOP status, all path overhead processing for the channel is inhibited. The definition and associated storage or processing of each byte is detailed below.
Path Trace (J1). The path trace byte carries a repeating message that is defined in SONET as 64 bytes (ASCII,
<CR><LF> terminated) and in SDH as 16 bytes (E.164). The POH processor extracts either type of message from
one selectable STS-1 per channel and stores the message in an internal register bank. The contents of the message can then optionally be monitored for either a mismatch from a provisioned expected message or a sustained
change in the received message. A mismatch is declared if the received message differs from the expected message for ten consecutive messages. The mismatch clears when four out of five received messages match the
expected message. A sustained change is detected when the received message differs from the last stable message for ten consecutive messages. The new message then becomes the stable message and the processor starts
checking for a sustained change from this new stable message (i.e., there is no clearing criteria for a sustained
change). Both defects are indicated by corresponding latched alarm status bits in the memory map.
Selection of the message protocol, 16- or 64-byte, the content monitoring option, and the monitored STS channel
are provisionable on a per-channel basis through the path trace control registers (addresses 0x1330—0x133F,
Table 177—Table 181). The expected messages for all channels are provisioned through the microprocessor interface using a 64-byte data buffer. This data buffer is also used to read the contents of the expected, stable, or
received message buffers for all blocks. Accesses using the data buffer are paged according to channel and message buffer (expected/stable or received). Selection of paging, as well as access type (read or write), is done using
the path trace access control register. The actual access is triggered by writing a 0001 hex value to the path trace
access start register and is performed on a nonreal time basis. Completion of the access is indicated by the message buffer access complete bit in the path trace status register being set.
Note: There are four circuits (1 per STS-12 channel) each monitoring the path trace byte of their selected STS-1
stream.
Path BIP-8 (B3). The path BIP-8 byte carries the even parity of the data in the previous STS SPE frame (783 bytes
for STS-1, Nx783 for STS-Nc). Every frame, the received B3 value is extracted and compared to the calculated
BIP-8 for the previous frame. Detected errors are accumulated in an internal 16-bit counter based on either bit or
block errors as provisioned per channel through the microprocessor interface. If bit error mode is enabled for the
channel, each BIP-8 bit found in error causes the counter to increment. If block error mode is enabled for the channel, the counter is only incremented by one regardless of the number of BIP-8 bits in error. The value in the counter
is transferred to the path coding violation (CV-P) registers on the positive edge of the performance-monitoring
strobe (PMSTB input), at which point the counter is cleared.
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Pointer Processor (PP) (continued)
Detailed Description (continued)
Signal Fail Alarms. Each of the 48 STS-1s entering the PP can be automatically monitored for B3 errors against
a programmable threshold. Concatenated payloads are supported by programming the threshold values for the
head STS-1.
Each STS-1 or head of an STS-NC has a select to choose which threshold group’s parameters to compare
against. There are eight threshold groups available, each group consisting of:
■
Set Threshold. If the B3 errors is equal or greater than this value in the given time window, the signal fail alarm
for this STS-1 is set. The B3 count in subsequent window times must be less than the clear threshold listed
below to clear this error condition.
■
Set Threshold Window Select. There are four time windows available between the eight groups. The set
threshold window select can be set to one of these window sizes.
■
Clear Threshold. If the signal fail alarm has been previously set, it will be cleared if an entire clear window time
goes past with the B3 error count less than this value.
■
Clear Threshold Window Select. If the signal fail alarm has been previously set, this window size will be used
to measure B3 errors.
Each STS-1 has a 9-bit B3 counter, which is incremented every time a B3 error appears. If STSs are part of an
STS-Nc, there is one 14-bit counter for the entire concatenation. This counter is cleared at the end of the window
selected for the threshold group for which this STS-1 or STS-Nc is set to. This counter (9 or 14 bits) can be incremented by 0 (if no B3 errors occurred) or up to 8 counts (if all the bits in the B3’s BIP-8 calculation are opposite
from expected). Note there are no bit/block issues with the signal fail counters; only bit errors are counted. Bit/
block is only an option for the B3 counters in the path monitoring (PM).
The signal fail alarm is set if the number of B3 errors for an STS-1 or STS-Nc is above the set threshold within this
window time. The B3 error counter for each STS-1 or STS-Nc is cleared at the end of each window and counts up
again in the next window.
One can set an individual STS-1/STS-Nc to set an alarm on one BER and clear this alarm on another. For this, a
threshold count value and timing window is provided for both set and clear.
For each STS-1 or STS-Nc, its B3 counter is running for either the time set by the set threshold window or the time
set by the clear threshold window. If this STS-1/STS-Nc is in the clear state (the alarm bit is clear), then the signal
fail circuitry will be looking for the case when the number of B3 errors equals or exceeds the set threshold. The
counter will be running for the duration of the set threshold window. If this condition is reached, the alarm will be set
immediately and the system will switch to watching the desired clear window. It will wait until the clear window has
completed its current cycle and will start counting B3 errors again in the next cycle. The B3 counter will be cleared,
and B3 errors will be added; at the end of this window time (now the clear window time), the decision will be made
to clear the alarm condition or not. If the number of B3 errors in the counter is less than the clear threshold, the
alarm will be cleared and, during the next window of length = set threshold window size, the counter will be compared to the set threshold. Otherwise, this error condition will remain set and another window of duration = clear
threshold window size will commence.
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Data Sheet
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Pointer Processor (PP) (continued)
Detailed Description (continued)
The signal fail alarm can be set anywhere during the window, but can only be cleared at the end of a window time.
The PP is either checking for the set or clear condition for an STS-1/STS-Nc at a given time. One implication of this
is that if the clear threshold was set for a BER higher than the set threshold and an incoming signal of a constant
BER between the two was present, the signal fail alarm would oscillate, set, and clear with a period of zero to one
times the set window threshold window time plus one to two times the period of the clear window threshold window
time.
There are eight threshold groups available (see Table 197—Table 200); two are labelled as being used for STS-1s
(group 0 and 1) and six (groups 2—7) are labelled for use as STS-Ncs. Group 0 and 1 have set and clear thresholds of 9 bits (0—511) whereas groups 2—7 have set and clear thresholds of up to 14 bits (0—16383). This is to
accommodate the higher data rate of a concatenated payload and thus the higher number of bit errors one would
see in the same time window for the same BER. However, one could point an STS-1 to group 2—7 as long as the
thresholds are set to 511 or less to stay within the 9-bit size of an individual STS-1s counter.
There are four threshold window size registers, each 16 bits, in increments of 0.5 ms (for a maximum of window
size of 32 seconds).
Table 324 on page 403 shows the recommended set/clear threshold and window values for the BER they are
intended for.
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Pointer Processor (PP) (continued)
Detailed Description (continued)
Path Signal Label (C2). The path signal label byte is used to indicate either the type of payload carried in the STS
SPE or the status of the payload. Of the 256 possible values, only the codes 0x01 to 0x04 and 0x12 to 0x15 are
currently defined to identify payload types, while the codes E1 to FC are defined to indicate payload defects. The
code 0xFF is a special reserved code due to its appearance in an STS AIS and is treated as a don’t care during
any defect detection or clearing. The C2 byte is extracted each frame and stored in the receive signal label registers. If the locally provisioned value, configured in the expected signal label registers, is any equipped value (i.e.,
not 00), the extracted signal label is also processed for the following defects:
■
■
■
■
Payload Label Mismatch (PLM)—Detected if the extracted signal label is a valid payload-specific code and does
not match the locally provisioned value in the expected signal label registers for five consecutive frames.
Cleared if the extracted signal label matches the locally provisioned value, the equipped nonspecific code
(0x01), or a valid PDI code for five consecutive frames. If the locally provisioned value is the equipped nonspecific code, then it matches any valid equipped code (including PDI). The valid payload specific codes are by
default 0x02 to 0xE0, 0xFD and 0xFE, with the codes 0xE1 to 0xFB also included if the locally provisioned payload is VT structured (0x02 or 0x03). If payload defect indication detection is disabled, 0xE1 to 0xFC are always
included. Detection of a PLM defect is indicated by a latched alarm status bit in the memory map.
Path Unequipped (UNEQ)—Detected if the extracted signal label matches the unequipped code (0x00) for five
consecutive frames. Cleared if the extracted signal label does not match the unequipped code for five consecutive frames. Detection of an UNEQ defect is indicated by a latched alarm status bit and a one second PM in the
memory map.
Update—The C2 value is dumped into an MPU register. Each time the captured value changes, a delta bit is set.
Payload Defect Indication (PDI)—Detected if the extracted signal label matches a valid PDI code for five consecutive frames. Cleared if the extracted signal label does not match a valid PDI code for five consecutive frames.
Valid PDI codes are 0xE1 to 0xFC when the locally provisioned payload label is 0x01, 0x02, or 0x03 (VT-structured STS) or just 0xFC otherwise. PDI detection can be disabled per STS through the microprocessor interface.
Path Status (G1). The path status byte is used to convey the path termination status and performance back to the
originating STS PTE. This allows the performance of the full-duplex path to be monitored from any single point
along the path. Bits 1 to 4 are used as a remote error indication (formerly far-end block error or FEBE), while bits 5
to 7 are used as a remote defect indication. The G1 byte is extracted each frame and processed for these functions as described below.
■
Remote Error Indication (REI-P)—Indicates the count of bit errors detected at the far-end STS PTE using the
path BIP-8. The error count is a binary number from 0 to 8 (values above 8 are invalid and interpreted as 0) and
is accumulated in an internal 16-bit counter based on either bit or block errors as provisioned per channel
through the microprocessor interface. If bit error mode is enabled for the channel, the counter is incremented by
the actual error count. If block error mode is enabled for the channel the counter is only incremented by one,
when the error count is not 0, regardless of the actual value. The value in the counter accumulates until it is
transferred to the REI-P registers on the positive edge of the performance-monitoring strobe (PMSTB input) at
which point the counter is cleared.
■
Remote Defect Indication (RDI-P)—Indicates the detection of a defect at the far-end STS PTE. Initially RDI-P
was defined as a one bit value in bit 5, but has since been expanded to a 3-bit enhanced value (ERDI-P).
Table 95 on page 256 shows the valid codes and interpretation for both the one bit and enhanced RDI schemes.
As can be seen, bits 6 and 7 are always set to opposite values for ERDI while they are set to the same value for
1-bit RDI. The POH uses this fact to determine which RDI scheme is being used on a per STS basis. An RDI-P
defect is then detected if a valid defect code for one of the RDI schemes is received for ten consecutive frames.
The RDI-P defect is cleared when the no defects code for that scheme is received for ten consecutive frames.
The value of the last validated 3-bit RDI code is stored in the ERDI-P registers in the memory map. In addition,
detection of a 1-bit RDI defect or each of the three ERDI defects is indicated by a one second PM bit in the memory map.
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Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
Detailed Description (continued)
Table 95. RDI-P Codes and Interpretation
G1[5:7]
Priority of Enhanced
RDI-P Codes
Trigger
0xx*
Not applicable
No defects
1xx*
Not applicable
AIS-P, LOP-P
001†
4
No defects
010†
3
PLM-P, LCD-P
ERDI-P payload defect.
101†
1
AIS-P, LOP-P
ERDI-P server defect.
†
2
110
Interpretation
No RDI-P defect.
1-bit RDI-P defect.
NO ERDI-P defects.
UNEQ-P, TIM-P ERDI-P connectivity defect.
* These codes are transmitted by STS PTE that do not support enhanced RDI-P. If enhanced RDI-P is not supported, G1 bits 2 and 1 must be
set to the same value, and should be set to 00.
† These codes are transmitted by STS PTE that support enhanced RDI-P.
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155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map Overview
0x1000
ID REGISTER
0x100F
INTERRUPTS
0x120F
MASKS
PATH TRACE
0x1300
0x1382
PERSISTENCY
0x13C2
STATE
0x1400
SF DETECT/CLEAR
0x1502
CONCATENATION MAP
0x1542
AIS-P GENERAL CONTROL
0x1580
PP CONTROL
0x1600
PATH PROVISIONING
0x1690
RESERVED
PATH MAINTENANCE
0x1702
INTER INC/DEC (PM)
0x1742
GEN INC/DEC (PM)
0x1780
POH PM
CV COUNT PM
0x1800
0x1880
REI COUNT PM
0x1900
RDI, C2, PDI
5-8156(F).ar.1
Figure 37. Overview of Pointer Processor Register Map
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Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions
To access (read and write) registers RXCLK[A—D][P/N] (see Pin Descriptions—Line Interface Signals, Table 7, on
page 97) must always be present for a given application.
Table 96. PP_IDR, PP Identification Register (RO, Fixed Value)
Address
Bit
Name
0x1000
15:0
PP_ID[15:0]
Function
Reset
Default
Pointer Processor Identification Register.
0001
Table 97. PP_CORWR, PP Clear on Read/Write Register (R/W, Control)
Address
Bit
Name
0x1001
15:1
—
0
PP_CORW
Function
Reset
Default
Reserved.
0
PP Clear On Read/Write. Sets the mode for clearing alarm
bit in the PP block.
0
0 = Clear interrupt bits with writing 1 to that bit in the alarm
register.
1 = Clear all alarm bits in an interrupt alarm register by
reading that register.
Note:This affects only the pointer processor interrupt
alarms, i.e., only the ones listed in this section (pointer
processor) of the data sheet.
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155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Interrupts
Table 98. PP_POH_ALMBNR[1—2], Path Overhead Alarm Status Binning Register (RO)
Address
Bit
0x100F 15:10
9
Name
Function
Reset
Default
—
Reserved.
0
—
SS Mismatch Alarm.
0
0 = SS mismatch alarm has not been detected for any STS1 in any bytestream.
1 = SS mismatch alarm has been detected for one or more
STS-1s in one or more bytestreams.
8
—
SS Validated Alarm.
0
0 = SS validated alarm has not been detected for any STS1 in any bytestream.
1 = SS validated alarm has been detected for one or more
STS-1s in one or more bytestreams.
7
—
F2 Validated Alarm.
0
0 = F2 validated alarm has not been detected for the
selected STS-1 in any bytestream.
1 = F2 validated alarm has been detected for the selected
STS-1 in one or more bytestreams.
6
—
H4 Validated Alarm.
0
0 = H4 validated alarm has not been detected for the
selected STS-1 in any bytestream.
1 = H4 validated alarm has been detected for the selected
STS-1 in one or more bytestreams.
5
—
Z3 Validated Alarm.
0
0 = Z3 validated alarm has not been detected for the
selected STS-1 in any bytestream.
1 = Z3 validated alarm has been detected for the selected
STS-1 in one or more bytestreams.
4
—
Z4 Validated Alarm.
0
0 = Z4 validated alarm has not been detected for the
selected STS-1 in any bytestream.
1 = Z4 validated alarm has been detected for the selected
STS-1 in one or more bytestreams.
3
—
Z5 Validated Alarm.
0
0 = Z5 validated alarm has not been detected for the
selected STS-1 in any bytestream.
1 = Z5 validated alarm has been detected for the selected
STS-1 in one or more bytestreams.
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Data Sheet
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Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 98. PP_POH_ALMBNR[1—2], Path Overhead Alarm Status Binning Register (RO) (continued)
Address
Bit
Name
0x100F
2
PP_PDI_ALMDBN
Function
Reset
Default
Payload Defect Indicator (PDI) Alarm Delta Binning.
0
0 = PDI alarm delta has not been detected for any STS-1 in
any bytestream.
1 = PDI alarm delta has been detected for one or more
STS-1s in one or more bytestreams.
1
PP_PDI_ALMBN
0
Payload Defect Indicator (PDI) Alarm Binning.
0 = PDI alarm has not been detected for any STS-1 in any
bytestream.
1 = PDI alarm has been detected for one or more STS-1s in
one or more bytestreams.
0
0
PP_J1ACCMP_ALMBN J1 Access Complete Alarm Binning.
0 = J1 access complete alarm has not been detected for
any STS-1 in any bytestream.
1 = J1 access complete alarm has been detected for one or
more STS-1s in one or more bytestreams.
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155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 98. PP_POH_ALMBNR[1—2], Path Overhead Alarm Status Binning Register (RO) (continued)
Address
Bit
Name
0x1010
15
PP_RDI_ALMDBN
Function
Remote Defect Indicator Alarm Delta Binning.
Reset
Default
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
14
PP_PLM_ALMDBN Payload Label Mismatch Alarm Delta Binning.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
13
12
PP_UNEQR_
ALMDBN
Unequipped Received Alarm Delta Binning.
PP_AIS_ALMDBN
Alarm Indicator Signal Alarm Delta Binning.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
11
PP_LOP_ALMDBN Loss of Pointer Alarm Delta Binning.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
10
PP_J1MM_ALMBN J1 Mismatch Alarm Binning.
0
0 = No J1 mismatch alarm has been detected in any
bytestream.
1 = J1 mismatch alarm has been detected in one or more
bytestreams.
9
PP_J1VLD_ALMBN J1 Validated Alarm Binning.
0
0 = No new validated J1 has been detected in any bytestream.
1 = New validated J1 has been detected in one or more
bytestreams.
8
Agere Systems Inc.
PP_USCNCT_
ALMBN
Unsupported Concatenation Alarm Binning.
0
0 = None of the four bytestreams has an unsupported
concatenation.
1 = One of the four bytestreams has an unsupported
concatenation.
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Data Sheet
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Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 98. PP_POH_ALMBNR[1—2], Path Overhead Alarm Status Binning Register (RO) (continued)
Address
Bit
Name
0x1010
7
PP_CNCTMM_
ALMBN
Concatenation Mismatch Alarm Binning.
PP_ES_ALMBN
Elastic Store Overrun/Underrun Alarm Binning.
6
Function
Reset
Default
0
0 = None of the four bytestreams has a concatenation
mismatch.
1 = One of the four bytestreams has a concatenation mismatch.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
5
PP_SF_ALMBN
0
Signal Fail Alarm Binning.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
4
PP_RDI_ALMBN
0
Remote Defect Indicator Alarm Binning.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
3
PP_PLM_ALMBN
0
Payload Label Mismatch Alarm Binning.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
2
1
PP_UNEQR_
ALMBN
Unequipped Received Alarm Binning.
PP_AIS_ALMBN
Alarm Indicator Signal Alarm Binning.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
0
PP_LOP_ALMBN
0
Loss of Pointer Alarm Binning.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
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Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 99. PP_ES_ALMBNBSR, Elastic Store Overrun/Underrun Alarm Status Binning Bytestream A—D
(RO)
Address
Bit
Name
0x1021
15:4
—
3:0
Function
Reset
Default
Reserved.
0
0
PP_ES_ALMBNBS[A—D] Elastic Store Overrun/Underrun Binning Bytestream
A—D.
0 = Elastic store overrun/underrun has not been detected
for any STS-1s in bytestream A—D.
1 = Elastic store overrun/underrun has been detected for
one or more STS-1s in bytestream A—D.
Table 100. PP_TSES_ALMBSR[A—D], Time Slots 1—12 Elastic Store Overrun/Underrun Alarm
Bytestream A—D (RO, COR/COW)
Address
Bit
Name
0x1022, 15:12
0x1023, 11:0
0x1024,
0x1025
—
PP_TSES_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Elastic Store Overrun/
Underrun Bytestream A—D.
1
0 = Elastic store overrun/underrun has not been detected.
1 = Elastic store overrun/underrun has been detected.
Table 101. PP_SF_ALMBNBSR, Signal Fail Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x1031
15:4
—
3:0
Function
Reset
Default
Reserved.
0
0
PP_SF_ALMBNBS[A—D] Signal Fail Binning Bytestream A—D.
0 = Signal fail has not been detected for any STS-1s in
bytestream A—D.
1 = Signal fail has been detected for one or more STS-1s
in bytestream A—D.
Table 102. PP_TSSF_ALMBSR[A—D], Time Slots 1—12 Signal Fail Alarm Bytestream A—D (RO, COR/
COW)
Address
Bit
0x1032, 15:12
0x1033, 11:0
0x1034,
0x1035
Name
—
PP_TSSF_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Signal Fail Bytestream
A—D.
0
0 = Signal fail has not been detected.
1 = Signal fail has been detected.
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Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 103. PP_RDI_ALMBNBSR, Remote Defect Indicator Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x1041
15:4
—
3:0
PP_RDI_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Remote Defect Indicator Binning Bytestream A—D.
0
0 = Remote defect indicator has not been detected for any
STS-1s in bytestream A—D.
1 = Remote defect indicator has been detected for one or
more STS-1s in bytestream A—D.
Table 104. PP_TSRDI_ALMBSR[A—D], Time Slots 1—12 Remote Defect Indicator Alarm
Bytestream A—D (RO, COR/COW)
Address
Bit
0x1042, 15:12
0x1043, 11:0
0x1044,
0x1045
Name
—
PP_TSRDI_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Remote Defect Indicator
Bytestream A—D.
0
0 = Remote defect indicator has not been detected.
1 = Remote defect indicator has been detected.
Table 105. PP_PLM_ALMBNBSR, Payload Label Mismatch Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x1051
15:4
—
3:0
PP_PLM_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Payload Label Mismatch Binning Bytestream A—D.
0
0 = Payload label mismatch has not been detected for any
STS-1s in bytestream A—D.
1 = Payload label mismatch has been detected for one or
more STS-1s in bytestream A—D.
Table 106. PP_TSPLM_ALMBSR[A—D], Time Slots 1—12 Payload Label Mismatch Alarm
Bytestream A—D (RO, COR/COW)
Address
Bit
0x1052, 15:12
0x1053, 11:0
0x1054,
0x1055
Name
—
PP_TSPLM_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Payload Label Mismatch
Bytestream A—D.
0
0 = Payload label mismatch has not been detected.
1 = Payload label mismatch has been detected.
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155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 107. PP_UNEQR_ALMBNBSR, Unequipped Received Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x1061
15:4
—
3:0
PP_UNEQR_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Unequipped Received Binning Bytestream A—D.
0
0 = Unequipped received has not been detected for any
STS-1s in bytestream A—D.
1 = Unequipped received has been detected for one or
more STS-1s in bytestream A—D.
Table 108. PP_TSUNEQR_ALMBSR[A—D], Time Slots 1—12 Unequipped Received Alarm Bytestream A—D
(RO, COR/COW)
Address
Bit
Name
0x1062, 15:12
0x1063, 11:0
0x1064,
0x1065
—
PP_TSUNEQR_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Unequipped Received
Bytestream A—D.
0
0 = Unequipped received has not been detected.
1 = Unequipped received has been detected.
Table 109. PP_AIS_ALMBNBSR, Alarms Indicator Signal Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x1071
15:4
—
3:0
Function
Reserved.
Reset
Default
0
PP_AIS_ALMBNBS[A—D] Alarms Indicator Signal Binning Bytestream A—D.
0
0 = Alarms indicator signal has not been detected for any
STS-1s in bytestream A—D.
1 = Alarms indicator signal has been detected for one or
more STS-1s in bytestream A—D.
Table 110. PP_TSAIS_ALMBSR[A—D], Time Slots 1—12 Alarms Indicator Signal Alarm Bytestream A—D
(RO, COR/COW)
Address
Bit
0x1072, 15:12
0x1073, 11:0
0x1074,
0x1075
Name
—
PP_TSAIS_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Alarms Indicator Signal
Bytestream A—D.
1
0 = Alarms indicator signal has not been detected.
1 = Alarms indicator signal has been detected.
Agere Systems Inc.
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Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 111. PP_LOP_ALMBNBSR, Loss of Pointer Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x1081
15:4
—
3:0
PP_LOP_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Loss of Pointer Binning Bytestream A—D.
0
0 = Loss of pointer has not been detected for any STS-1s
in bytestream A—D.
1 = Loss of pointer has been detected for one or more
STS-1s in bytestream A—D.
Table 112. PP_TSLOP_ALMBSR[A—D], Time Slots 1—12 Loss of Pointer Alarm Bytestream A—D
(RO, COR/COW)
Address
Bit
0x1082, 15:12
0x1083, 11:0
0x1084,
0x1085
Name
—
PP_TSLOP_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Loss of Pointer Bytestream
A—D.
1
0 = Loss of pointer has not been detected.
1 = Loss of pointer has been detected.
266
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 113. PP_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning
Bytestream A—D (RO, COR/COW)
Address
Bit
Name
0x1091
15:4
—
3:0
PP_CNCTMM_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Concatenation Map Mismatch Binning
Bytestream A—D.
0
0 = No expected/received concatenation state
mismatches on any time slot.
1 = Expected/received concatenation state mismatch in at
least one time slot.
Table 114. PP_USCNCTM_ALMBNBSR, Channel Path Unsupported Concatenation Map Alarm Binning
Bytestream A—D (RO, COR/COW)
Address
Bit
Name
0x10A1
15:4
—
3:0
PP_USCNCTM_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Unsupported Concatenation Map Binning
Bytestream A—D.
0
0 = No path alarm.
1 = Alarm detected.
Table 115. PP_J1NVLDMSG_ALMBNBSR, Channel Path J1 New Validated Message Alarm Binning
Bytestream A—D (RO, COR/COW)
Address
Bit
Name
0x10C1
15:4
—
3:0
PP_J1NVLDMSG_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
J1 New Validated Message Binning Bytestream A—D.
0
0 = No path alarm.
1 = Alarm detected.
Table 116. PP_J1MSGMM_ALMBNBSR, Channel Path J1 Message Mismatch Alarm Status Binning
Bytestream A—D (RO, COR/COW)
Address
Bit
Name
0x10D1
15:4
—
3:0
PP_J1MSGMM_
ALMBNBS[A—D]
Agere Systems Inc.
Function
Reset
Default
Reserved.
0
J1 Message Mismatch Binning Bytestream A—D.
0
0 = No path alarm.
1 = Alarm detected.
267
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Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 117. PP_PDI_ALMBNBSR, Payload Defect Indicator Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x1101
15:4
—
3:0
Function
Reset
Default
Reserved.
0
0
PP_PDI_ALMBNBS[A—D] Payload Defect Indicator Binning Bytestream A—D.
0 = Payload defect indicator has not been detected for
any STS-1s in bytestream A—D.
1 = Payload defect indicator has been detected for one or
more STS-1s in bytestream A—D.
Table 118. PP_TSPDI_ALMBSR[A—D], Time Slots 1—12 Payload Defect Indicator Alarm Bytestream A—D
(RO, COR/COW)
Address
Bit
0x1102, 15:12
0x1103, 11:0
0x1104,
0x1105
Name
—
PP_TSPDI_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Payload Defect Indicator
Bytestream A—D.
0
0 = Payload defect indicator has not been detected.
1 = Payload defect indicator has been detected.
Table 119. PP_RDI_ALMDBNBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status
Binning Bytestream A—D (RO)
Address
Bit
Name
0x1111
15:4
—
3:0
PP_RDI_
ALMDBNBS[A—D]
Function
Reset
Default
Reserved.
0
Remote Defect Indicator Delta Binning
Bytestream A—D.
0
0 = Remote defect indicator delta has not been detected
for any STS-1s in bytestream A—D.
1 = Remote defect indicator delta has been detected for
one or more STS-1s in bytestream A—D.
Table 120. PP_TSRDI_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Remote Defect Indicator
Alarm Delta Bytestream A—D (RO, COR/COW)
Address
Bit
0x1112, 15:12
0x1113, 11:0
0x1114,
0x1115
Name
—
PP_TSRDI_ALMDBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Remote Defect Indicator
Delta Bytestream A—D.
0
0 = Remote defect indicator delta has not been detected.
1 = Remote defect indicator delta has been detected.
268
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 121. PP_PLM_ALMDBNBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status
Binning Bytestream A—D (RO)
Address
Bit
Name
0x1121
15:4
—
3:0
PP_PLM_
ALMDBNBS[A—D]
Function
Reset
Default
Reserved.
0
Payload Label Mismatch Delta Binning
Bytestream A—D.
6
0 = Payload label mismatch delta has not been detected
for any STS-1s in bytestream A—D.
1 = Payload label mismatch delta has been detected for
one or more STS-1s in bytestream A—D.
Table 122. PP_TSPLM_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Label Mismatch
Alarm Delta Bytestream A—D (RO, COR/COW)
Address
Bit
0x1122, 15:12
0x1123, 11:0
0x1124,
0x1125
Name
—
PP_TSPLM_ALMDBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Payload Label Mismatch
Delta Bytestream A—D.
0
0 = Payload label mismatch delta has not been detected.
1 = Payload label mismatch delta has been detected.
Table 123. PP_UNEQR_ALMDBNBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status
Binning Bytestream A—D (RO)
Address
Bit
Name
0x1131
15:4
—
3:0
PP_UNEQR_
ALMDBNBS[A—D]
Function
Reset
Default
Reserved.
0
Unequipped Received Delta Binning
Bytestream A—D.
0
0 = Unequipped received delta has not been detected for
any STS-1s in bytestream A—D.
1 = Unequipped received delta has been detected for one
or more STS-1s in bytestream A—D.
Table 124. PP_TSUNEQR_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Unequipped Received
Alarm Delta Bytestream A—D (RO, COR/COW)
Address
Bit
Name
Function
—
Reserved.
0x1132, 15:12
0x1133, 11:0 PP_TSUNEQR_ALMDBS Time Slot 1—Time Slot 12 Unequipped Received Delta
0x1134,
[A—D][1—12]
Bytestream A—D.
0x1135
0 = Unequipped received delta has not been detected.
1 = Unequipped received delta has been detected.
Agere Systems Inc.
Reset
Default
0
0
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Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 125. PP_AIS_ALMDBNBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status Binning
Bytestream A—D (RO)
Address
Bit
Name
0x1141
15:4
—
3:0
PP_AIS_
ALMDBNBS[A—D]
Function
Reset
Default
Reserved.
0
Alarm Indicator Signal Delta Binning
Bytestream A—D.
0
0 = Alarm indicator signal delta has not been detected for
any STS-1s in bytestream A—D.
1 = Alarm indicator signal delta has been detected for one
or more STS-1s in bytestream A—D.
Table 126. PP_TSAIS_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Alarm Indicator Signal
Alarm Delta Bytestream A—D (RO, COR/COW)
Address
Bit
0x1142, 15:12
0x1143, 11:0
0x1144,
0x1145
Name
—
PP_TSAIS_ALMDBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Alarm Indicator Signal Delta
Bytestream A—D.
1
0 = Alarm indicator signal delta has not been detected.
1 = Alarm indicator signal delta has been detected.
Table 127. PP_LOP_ALMDBNBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning
Bytestream A—D (RO)
Address
Bit
Name
0x1151
15:4
—
3:0
PP_LOP_
ALMDBNBS[A—D]
Function
Reset
Default
Reserved.
0
Loss of Pointer Delta Binning Bytestream A—D.
0
0 = Loss of pointer delta has not been detected for any
STS-1s in bytestream A—D.
1 = Loss of pointer delta has been detected for one or
more STS-1s in bytestream A—D.
Table 128. PP_TSLOP_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Loss of Pointer Alarm
Delta Bytestream A—D (RO, COR/COW)
Address
Bit
0x1152, 15:12
0x1153, 11:0
0x1154,
0x1155
Name
—
PP_TSLOP_ALMDBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Loss of Pointer Delta
Bytestream A—D.
1
0 = Loss of pointer delta has not been detected.
1 = Loss of pointer delta has been detected.
270
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 129. PP_PTRACCMPIR, Path Trace Access Complete Interrupt (RO, COR/COW)
Address
Bit
Name
0x1160
15:1
—
0
PP_J1BFACCMPI
Function
Reset
Default
Reserved.
0
J1 Buffer Access Complete Interrupt.
0
0 = No alarm.
1 = Alarm detected.
Table 130. PP_PDI_ALMDBNBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status
Binning Bytestream A—D (RO)
Address
Bit
Name
0x1171
15:4
—
3:0
PP_PDI_
ALMDBNBS[A—D]
Function
Reset
Default
Reserved.
0
Payload Defect Indicator Delta Binning
Bytestream A—D.
0
0 = Payload defect indicator delta has not been detected
for any STS-1s in bytestream A—D.
1 = Payload defect indicator delta has been detected for
one or more STS-1s in bytestream A—D.
Table 131. PP_TSPDI_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Defect Indicator
Alarm Delta Bytestream A—D (RO, COR/COW)
Address
Bit
0x1172, 15:12
0x1173, 11:0
0x1174,
0x1175
Name
—
PP_TSPDI_ALMDBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Payload Defect Indicator
Delta Bytestream A—D.
0
0 = Payload defect indicator delta has not been detected.
1 = Payload defect indicator delta has been detected.
Agere Systems Inc.
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 132. STS-1 #12 Channel Path Alarm Binning Status Registers (RO)
Address
Bit
Name
0x1177
15:4
—
Reserved.
0
3
—
Z5 New Validated Bytestream A.
0
2
—
Z5 New Validated Bytestream B.
0
1
—
Z5 New Validated Bytestream C.
0
0
—
Z5 New Validated Bytestream D.
0
15:4
—
Reserved.
0
3
—
Z4 New Validated Bytestream A.
0
2
—
Z4 New Validated Bytestream B.
0
1
—
Z4 New Validated Bytestream C.
0
0x1179
0x117B
0x117D
0x117F
272
Function
Reset
Default
0
—
Z4 New Validated Bytestream D.
0
15:4
—
Reserved.
0
3
—
Z3 New Validated Bytestream A.
0
2
—
Z3 New Validated Bytestream B.
0
1
—
Z3 New Validated Bytestream C.
0
0
—
Z3 New Validated Bytestream D.
0
15:4
—
Reserved.
0
3
—
H4 New Validated Bytestream A.
0
2
—
H4 New Validated Bytestream B.
0
1
—
H4 New Validated Bytestream C.
0
0
—
H4 New Validated Bytestream D.
0
15:4
—
Reserved.
0
3
—
F2 New Validated Bytestream A.
0
2
—
F2 New Validated Bytestream B.
0
1
—
F2 New Validated Bytestream C.
0
0
—
F2 New Validated Bytestream D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 133. STS-1 Channel Path SS New Validated Bits Alarm Status Binning Bytestream A—D (RO)
Address
Bits
Name
Description
Reset
Default
0x1181
15:4
—
Reserved.
0
3:0
—
SS New Validated Bits Bytestream A—D.
0
0 = SS new validated bits has not been detected for any
STS-1s in bytestream A—D.
1 = SS new validated bits has been detected for one or
more STS-1s in bytestream A—D.
Table 134. STS-1 Channel Path Time Slots 1—12 SS New Validated Bits Alarm Status Bytestream A—D
(RO, COR/COW)
Address
Bits
Name
Description
Reset
Default
0x1182,
0x1183,
0x1184,
0x1185
15:12
—
Reserved.
0
11:0
—
Time Slot 1—Time Slot 12 SS New Validated Bits
Bytestream A—D.
0
Table 135. STS-1 Channel Path SS Bits Mismatch Alarm Status Binning Bytestream A—D (RO)
Address
Bits
Name
Description
Reset
Default
0x1187
15:4
—
Reserved.
0
3:0
—
SS Bits Mismatch Bytestream A—D.
0
0 = SS bits mismatch has not been detected for any STS-1s
in bytestream A—D.
1 = SS bits mismatch has been detected for one or more
STS-1s in bytestream A—D.
Table 136. STS-1 Channel Path Time Slots 1—12 SS Bits Mismatch Alarm Status Bytestream A—D
(RO, COR/COW)
Address
Bits
Name
0x1188,
0x1189,
0x118A,
0x118B
15:12
—
Reserved.
0
11:0
—
Time Slot 1—Time Slot 12 SS Bits Mismatch Bytestream
A—D.
0
Agere Systems Inc.
Description
Reset
Default
273
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Masks
Table 137. PP_POH_ALMBNMR[1—2], Path Overhead Alarm Status Binning Masks (R/W)
Address
Bit
0x120F 15:10
9
Name
Function
Reset
Default
—
Reserved.
—
—
SS Mismatch Alarm Mask.
1
0 = SS mismatch alarm is passed through.
1 = SS mismatch alarm masked.
8
—
SS Validated Alarm Mask.
1
0 = SS validated alarm is passed through.
1 = SS validated alarm masked.
7
—
1
F2 Validated Alarm Mask.
0 = F2 validated alarm is passed through.
1 = F2 validated alarm masked.
6
—
1
H4 Validated Alarm Mask.
0 = H4 validated alarm is passed through.
1 = H4 validated alarm masked.
5
—
Z3 Validated Alarm Mask.
1
0 = Z3 validated alarm is passed through.
1 = Z3 validated alarm masked.
4
—
Z4 Validated Alarm Mask.
1
0 = Z4 validated is passed through.
1 = Z4 validated alarm masked.
3
—
Z5 Validated Alarm Mask.
1
0 = Z5 validated alarm is passed through.
1 = Z5 validated alarm masked.
2
PP_PDI_ALMDBNM
Payload Defect Indicator (PDI) Alarm Delta Binning
Mask.
1
0 = PDI delta alarm is passed through.
1 = PDI delta alarm masked.
1
PP_PDI_ALMBNM
Payload Defect Indicator (PDI) Alarm Binning Mask.
1
0 = PDI alarm is passed through.
1 = PDI alarm masked.
0
PP_J1ACCMP_ALMBNM J1 Access Complete Alarm Binning Mask.
1
0 = J1 access complete alarm is passed through.
1 = J1 access complete alarm masked.
274
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 137. PP_POH_ALMBNMR[1—2], Path Overhead Alarm Status Binning Masks (R/W) (continued)
Address
Bit
Name
0x1210
15
PP_RDI_ALMDBNM
Function
Remote Defect Indicator Alarm Delta Binning Mask.
Reset
Default
1
0 = Remote defect indicator delta alarm is passed
through.
1 = Remote defect indicator delta alarm masked.
14
PP_PLM_ALMDBNM
Payload Label Mismatch Alarm Delta Binning Mask.
1
0 = Payload label mismatch delta alarm is passed
through.
1 = Payload label mismatch delta alarm masked.
13
PP_UNEQR_ALMDBNM
Unequipped Received Alarm Delta Binning Mask.
1
0 = Unequipped received delta alarm is passed through.
1 = Unequipped received delta alarm masked.
12
PP_AIS_ALMDBNM
Alarm Indicator Signal Alarm Delta Binning Mask.
1
0 = Alarm indicator signal delta alarm is passed through.
1 = Alarm indicator signal delta alarm masked.
11
PP_LOP_ALMDBNM
Loss of Pointer Alarm Delta Binning Mask.
1
0 = Loss of pointer delta alarm is passed through.
1 = Loss of pointer delta alarm masked.
10
PP_J1MM_ALMM
J1 Mismatch Alarm Binning Mask.
1
0 = J1 mismatch alarm is passed through.
1 = J1 mismatch alarm masked.
9
PP_J1VLD_ALMBNM
J1 Validated Alarm Binning Mask.
1
0 = J1 validated alarm is passed through.
1 = J1 validated alarm masked.
8
PP_USCNCT_ALMBNM
Unsupported Concatenation Alarm Binning Mask.
1
0 = Unsupported concatenation alarm is passed through.
1 = Unsupported concatenation alarm masked.
7
PP_CNCTMM_ALMBNM Concatenation Mismatch Alarm Binning Mask.
1
0 = Concatenation mismatch alarm is passed through.
1 = Concatenation mismatch alarm masked.
6
PP_ES_ALMBNM
Elastic Store Overrun/Underrun Alarm Binning Mask.
1
0 = Elastic store overrun/underrun alarm is passed
through.
1 = Elastic store overrun/underrun alarm masked.
5
PP_SF_ALMBNM
Signal Fail Alarm Binning Mask.
1
0 = Signal fail alarm is passed through.
1 = Signal fail alarm masked.
Agere Systems Inc.
275
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 137. PP_POH_ALMBNMR[1—2], Path Overhead Alarm Status Binning Masks (R/W) (continued)
Address
Bit
Name
0x1210
4
PP_RDI_ALMBNM
Function
Reset
Default
Remote Defect Indicator Alarm Binning Mask.
1
0 = Remote defect indicator alarm is passed through.
1 = Remote defect indicator alarms masked.
3
PP_PLM_ALMBNM
Payload Label Mismatch Alarm Binning Mask.
1
0 = Payload label mismatch alarm is passed through.
1 = Payload label mismatch alarms masked.
2
PP_UNEQR_ALMBNM
Unequipped Received Alarm Binning Mask.
1
0 = Unequipped received alarm is passed through.
1 = Unequipped received alarms masked.
1
PP_AIS_ALMBNM
1
Alarm Indicator Signal Alarm Binning Mask.
0 = Alarm indicator signal alarm is passed through.
1 = Alarm indicator signal alarms masked.
0
PP_LOP_ALMBNM
Loss of Pointer Alarm Binning Mask.
1
0 = Loss of pointer alarm is passed through.
1 = Loss of pointer alarms masked.
276
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 138. PP_ES_ALMBNMBSR, Elastic Store Overrun/Underrun Alarm Status Binning Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x1211
15:4
—
3:0
PP_ES_
ALMMBSBN[A—D]
Function
Reserved.
Reset
Default
—
Elastic Store Overrun/Underrun Binning Masks
Bytestream A—D.
1111
0 = Elastic store overrun/underrun alarms in bytestream
A—D are passed through.
1 = Elastic store overrun/underrun alarms in bytestream
A—D are masked.
Table 139. PP_TSES_ALMMBSR[A—D], Time Slots 1—12 Elastic Store Overrun/Underrun Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x1212, 15:12
0x1213, 11:0
0x1214,
0x1215
Name
—
PP_TSES_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Elastic Store Overrun/
Underrun Masks Bytestream A—D.
1
Table 140. PP_SF_ALMBNMBSR, Signal Fail Alarm Status Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x1221
15:4
—
3:0
PP_SF_
ALMBNMBS[A—D]
Function
Reserved.
Reset
Default
—
Signal Fail Binning Masks Bytestream A—D.
1111
0 = Signal fail alarms in bytestream A—D are passed
through.
1 = Signal fail alarms in bytestream A—D are masked.
Table 141. PP_TSSF_ALMMBSR[A—D], Time Slots 1—12 Signal Fail Alarm Masks Bytestream A—D (R/W)
Address
Bit
0x1222, 15:12
0x1223, 11:0
0x1224,
0x1225
Agere Systems Inc.
Name
—
PP_TSSF_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Signal Fail Masks
Bytestream A—D.
1
277
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 142. PP_RDI_ALMBNMBSR, Remote Defect Indicator Alarm Status Binning Masks Bytestream A—D
(R/W)
Address
Bit
Name
0x1231
15:4
—
3:0
PP_RDI_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Remote Defect Indicator Binning Masks
Bytestream A—D.
1
0 = Remote defect indicator alarms in bytestream A—D
are passed through.
1 = Remote defect indicator alarms in bytestream A—D
are masked.
Table 143. PP_TSRDI_ALMMBSR[A—D], Time Slots 1—12 Remote Defect Indicator Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x1232, 15:12
0x1233, 11:0
0x1234,
0x1235
Name
—
PP_TSRDI_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Remote Defect Indicator
Masks Bytestream A—D.
1
Table 144. PP_PLM_ALMBNMBSR, Payload Label Mismatch Alarm Status Binning Masks Bytestream A—D
(R/W)
Address
Bit
Name
0x1241
15:4
—
3:0
PP_PLM_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Payload Label Mismatch Binning Masks
Bytestream A—D.
1
0 = Payload label mismatch alarms in bytestream A—D
are passed through.
1 = Payload label mismatch alarms in bytestream A—D
are masked.
Table 145. PP_TSPLM_ALMMBSR[A—D], Time Slots 1—12 Payload Label Mismatch Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x1242, 15:12
0x1243, 11:0
0x1244,
0x1245
278
Name
—
PP_TSPLM_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Payload Label Mismatch
Masks Bytestream A—D.
1
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 146. PP_UNEQR_ALMBNMBSR, Unequipped Received Alarm Status Binning Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x1251
15:4
—
3:0
PP_UNEQR_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Unequipped Received Binning Masks
Bytestream A—D.
1
0 = Unequipped received alarms in bytestream A—D are
passed through.
1 = Unequipped received alarms in bytestream A—D are
masked.
Table 147. PP_TSUNEQR_ALMMBSR[A—D], Time Slots 1—12 Unequipped Received Alarm Masks
Bytestream A—D (R/W)
Address
Bit
Name
Function
—
Reserved.
0x1252, 15:12
0x1253, 11:0 PP_TSUNEQR_ALMMBS Time Slot 1—Time Slot 12 Unequipped Received
0x1254,
[A—D][1—12]
Masks Bytestream A—D.
0x1255
Reset
Default
—
1
Table 148. PP_AIS_ALMBNMBSR, Alarms Indicator Signal Alarm Status Binning Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x1261
15:4
—
3:0
PP_AIS_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Alarms Indicator Signal Binning Masks
Bytestream A—D.
1
0 = Alarms indicator signal alarms in bytestream A—D are
passed through.
1 = Alarms indicator signal alarms in bytestream A—D are
masked.
Table 149. PP_TSAIS_ALMMBSR[A—D], Time Slots 1—12 Alarms Indicator Signal Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x1262, 15:12
0x1263, 11:0
0x1264,
0x1265
Agere Systems Inc.
Name
—
PP_TSAIS_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Alarms Indicator Signal
Masks Bytestream A—D.
1
279
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 150. PP_LOP_ALMBNMBSR, Loss of Pointer Alarm Status Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x1271
15:4
—
3:0
PP_LOP_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Loss of Pointer Binning Masks Bytestream A—D.
1
0 = Loss of pointer alarms in bytestream A—D are passed
through.
1 = Loss of pointer alarms in bytestream A—D are
masked.
Table 151. PP_TSLOP_ALMMBSR[A—D], Time Slots 1—12 Loss of Pointer Alarm Masks Bytestream A—D
(R/W)
Address
Bit
0x1272, 15:12
0x1273, 11:0
0x1274,
0x1275
280
Name
—
PP_TSLOP_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Loss of Pointer Masks
Bytestream A—D.
1
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 152. PP_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x1277
15:4
—
3:0
PP_CNCTMM_
ALMMBS[A—D]
Function
Reset
Default
Reserved.
—
Concatenation Map Mismatch Mask Bytestream A—D.
1
0 = Path alarm is passed through.
1 = Path alarm is masked.
Table 153. PP_USCNCTM_ALMMBSR, Channel Path Unsupported Concatenation Map Alarm Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x1279
15:4
—
3:0
PP_USCNCTM_
ALMMBS[A—D]
Function
Reset
Default
Reserved.
—
Unsupported Concatenation Map Mask Bytestream
A—D.
1
0 = Alarm is passed through.
1 = Alarm is masked.
Table 154. PP_J1NVLDMSG_ALMMBSR, Channel Path J1 New Validated Message Alarm Masks
Bytestream A—D(R/W)
Address
Bit
Name
0x127B
15:4
—
3:0
PP_J1NVLDMSG
ALMMBS[A—D]
Function
Reset
Default
Reserved.
—
J1 New Validated Message Mask Bytestream A—D.
1
0 = Alarm is passed through.
1 = Alarm is masked.
Table 155. PP_J1MSGMM_ALMMBSR, Channel Path J1 Message Mismatch Alarm Status Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x127D
15:4
—
3:0
PP_J1MSGMM_
ALMMBS[A—D]
Agere Systems Inc.
Function
Reset
Default
Reserved.
—
J1 Message Mismatch Mask Bytestream A—D.
1
0 = Alarm is passed through.
1 = Alarm is masked.
281
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 156. PP_PDI_ALMBNMBSR, Payload Defect Indicator Alarm Status Binning Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x1281
15:4
—
3:0
PP_PDI_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
0
Payload Defect Indicator Binning Masks
Bytestream A—D.
1
0 = Payload defect indicator alarms in bytestream A—D
are passed through.
1 = Payload defect indicator alarms in bytestream A—D
are masked.
Table 157. PP_TSPDI_ALMMBSR[A—D], Time Slots 1—12 Payload Defect Indicator Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x1282, 15:12
0x1283, 11:0
0x1284,
0x1285
282
Name
—
PP_TSPDI_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Payload Defect Indicator
Masks Bytestream A—D.
1
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 158. PP_RDI_ALMDBNMBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status
Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x1291
15:4
—
3:0
PP_RDI_ALMDBNMBS
[A—D]
Function
Reset
Default
Reserved.
—
Remote Defect Indicator Delta Binning Masks
Bytestream A—D.
1
0 = Remote defect indicator delta alarms in bytestream
A—D are passed through.
1 = Remote defect indicator delta alarms in bytestream
A—D are masked.
Table 159. PP_TSRDI_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Remote Defect Indicator
Alarm Delta Masks Bytestream A—D (R/W)
Address
Bit
0x1292, 15:12
0x1293, 11:0
0x1294,
0x1295
Name
—
PP_TSRDI_ALMDMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Remote Defect Indicator
Delta Masks Bytestream A—D.
1
Table 160. PP_PLM_ALMDBNMBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status
Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x12A1
15:4
—
3:0
PP_PLM_ALMDBNMBS
[A—D]
Function
Reset
Default
Reserved.
—
Payload Label Mismatch Delta Binning Masks
Bytestream A—D.
1
0 = Payload label mismatch delta alarms in bytestream
A—D are passed through.
1 = Payload label mismatch delta alarms in bytestream
A—D are masked.
Table 161. PP_TSPLM_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Label
Mismatch Alarm Delta Masks Bytestream A—D (R/W)
Address
Bit
0x12A2, 15:12
0x12A3, 11:0
0x12A4,
0x12A5
Agere Systems Inc.
Name
—
PP_TSPLM_ALMDMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Payload Label Mismatch
Delta Masks Bytestream A—D.
1
283
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 162. PP_UNEQR_ALMDBNMBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status
Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x12B1
15:4
—
3:0
PP_UNEQR_
ALMDBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Unequipped Received Delta Binning Masks
Bytestream A—D.
1
0 = Unequipped received delta alarms in bytestream
A—D are passed through.
1 = Unequipped received delta alarms in bytestream
A—D are masked.
Table 163. PP_TSUNEQR_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Unequipped
Received Alarm Delta Masks Bytestream A—D (R/W)
Address
Bit
0x12B2, 15:12
0x12B3, 11:0
0x12B4,
0x12B5
284
Name
—
Function
Reset
Default
Reserved.
—
PP_TSUNEQR_
Time Slot 1—Time Slot 12 Unequipped Received Delta
ALMDMBS[A—D][1—12] Masks Bytestream A—D.
1
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 164. PP_AIS_ALMDBNMBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status
Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x12C1
15:4
—
3:0
PP_AIS_ALMDBNMBS
[A—D]
Function
Reset
Default
Reserved.
—
Alarm Indicator Signal Delta Binning Masks
Bytestream A—D.
1
0 = Alarm indicator signal delta alarms in bytestream
A—D are passed through.
1 = Alarm indicator signal delta alarms in bytestream
A—D are masked.
Table 165. PP_TSAIS_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Alarm Indicator Signal
Alarm Delta Masks Bytestream A—D (R/W)
Address
Bit
0x12C2, 15:12
0x12C3, 11:0
0x12C4,
0x12C5
Name
—
PP_TSAIS_ALMDMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Alarm Indicator Signal
Delta Masks Bytestream A—D.
1
Table 166. PP_LOP_ALMDBNMBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning
Masks Bytestream A—D (R/W)
Address
Bit
Name
0x12D1
15:4
—
3:0
PP_LOP_ALMDBNMBS
[A—D]
Function
Reset
Default
Reserved.
—
Loss of Pointer Delta Binning Masks
Bytestream A—D.
1
0 = Loss of pointer delta alarms in bytestream A—D are
passed through.
1 = Loss of pointer delta alarms in bytestream A—D are
masked.
Table 167. PP_TSLOP_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Loss of Pointer Alarm
Delta Masks Bytestream A—D (R/W)
Address
Bit
0x12D2, 15:12
0x12D3, 11:0
0x12D4,
0x12D5
Agere Systems Inc.
Name
—
PP_TSLOP_ALMDMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Loss of Pointer Delta Masks
Bytestream A—D.
1
285
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 168. PP_PTRACCMPIR, Path Trace Access Complete Interrupt Mask (R/W)
Address
Bit
Name
0x12E0
15:1
—
0
PP_J1BFACCMPIM
Function
Reset
Default
Reserved.
—
J1 Buffer Access Complete Mask.
1
0 = Alarm is passed through.
1 = Alarm is masked.
Table 169. STS-1 Channel Path SS Bits Mismatch Alarm Status Binning Masks Bytestream A—D (R/W)
Address Bits
0x12E2
Name
Function
Reset
Default
15:4
—
Reserved.
—
3:0
—
SS Bits Mismatch Mask Bytestream A—D.
1
0 = SS bits mismatch alarms in bytestream A—D are
passed through.
1 = SS bits mismatch alarms in bytestream A—D are
masked.
Table 170. STS-1 Channel Path Time Slots 1—12 SS Bits Mismatch Alarm Status Binning Masks
Bytestream A—D (R/W)
Address
Bit
0x12E3, 15:12
0x12E4, 11:0
0x12E5,
0x12E6
286
Name
Function
Reset
Default
—
Reserved.
—
—
Time Slot 1—Time Slot 12 SS Bits Mismatch Mask
Bytestream A—D.
1
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 171. PP_PDI_ALMDBNMBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status
Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x12E9
15:4
—
3:0
PP_PDI_ALMDBNMBS
[A—D]
Function
Reset
Default
Reserved.
—
Payload Defect Indicator Delta Binning Masks
Bytestream A—D.
1
0 = Payload defect indicator delta alarms in bytestream
A—D are passed through.
1 = Payload defect indicator delta alarms in bytestream
A—D are masked.
Table 172. PP_TSPDI_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Defect Indicator
Alarm Delta Masks Bytestream A—D (R/W)
Address
Bit
0x12EA, 15:12
0x12EB, 11:0
0x12EC,
0x12ED
Agere Systems Inc.
Name
—
PP_TSPDI_ALMDMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Payload Defect Indicator
Delta Masks Bytestream A—D.
1
287
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 173. STS-1 #12 Channel Path Alarm Binning Mask Status Registers (R/W)
Address
Bit
Name
0x12EF
15:4
—
Reserved.
—
3
—
Z5 New Validated Mask Bytestream A.
1
2
—
Z5 New Validated Mask Bytestream B.
1
1
—
Z5 New Validated Mask Bytestream C.
1
0
—
Z5 New Validated Mask Bytestream D.
1
15:4
—
Reserved.
—
3
—
Z4 New Validated Mask Bytestream A.
1
2
—
Z4 New Validated Mask Bytestream B.
1
1
—
Z4 New Validated Mask Bytestream C.
1
0
—
Z4 New Validated Mask Bytestream D.
1
15:4
—
Reserved.
—
3
—
Z3 New Validated Mask Bytestream A.
1
2
—
Z3 New Validated Mask Bytestream B.
1
1
—
Z3 New Validated Mask Bytestream C.
1
0
—
Z3 New Validated Mask Bytestream D.
1
15:4
—
Reserved.
—
3
—
H4 New Validated Mask Bytestream A.
1
2
—
H4 New Validated Mask Bytestream B.
1
1
—
H4 New Validated Mask Bytestream C.
1
0
—
H4 New Validated Mask Bytestream D.
1
15:4
—
Reserved.
—
3
—
F2 New Validated Mask Bytestream A.
1
2
—
F2 New Validated Mask Bytestream B.
1
1
—
F2 New Validated Mask Bytestream C.
1
0
—
F2 New Validated Mask Bytestream D.
1
0x12F1
0x12F3
0x12F5
0x12F7
288
Function
Reset
Default
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 174. STS-1 Channel Path SS New Validated Bits Alarm Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
Function
Reset
Default
0x12F9
15:4
—
Reserved.
—
3:0
—
SS New Validated Bits Masks Bytestream A—D.
1
0 = SS new validated bits alarms in bytestream A—D are
passed through.
1 = SS new validated bits alarms in bytestream A—D are
masked.
Table 175. STS-1 Channel Path Time Slots 1—12 SS New Validated Bits Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x12FA, 15:12
0x12FB, 11:0
0x12FC,
0x12FD
Agere Systems Inc.
Name
Function
Reset
Default
—
Reserved.
—
—
Time Slot 1—Time Slot 12 SS New Validated Bits
Masks Bytestream A—D.
1
289
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Path Trace
Table 176. PP_PTRBFR[1—32], Path Trace Buffer Registers 1—32 (R/W)
Address
Bit
Name
Function
Reset
Default
0x1300
—
0x131F
15:8
PP_J1BYTE1[7:0]
J1 Byte 1, 3, 5, . . . , 63 Path Trace Buffer.
0
7:0
PP_J1BYTE0[7:0]
J1 Byte 0, 2, 4, . . . , 62 Path Trace Buffer.
0
Table 177. PP_PTRACCTLR1, Path Trace Access Control Register 1 (R/W)
Address
Bit
Name
0x1330
15:2
—
1:0
PP_J1TS1_CHSEL[1:0]
Function
Reset
Default
Reserved.
0
J1 Time Slot 1 Channel Select.
0
00 = Bytestream A.
01 = Bytestream B.
10 = Bytestream C.
11 = Bytestream D.
Table 178. PP_PTRACCTLR2, Path Trace Access Control Register 2 (R/W)
Address
Bit
Name
0x1331
15:1
—
0
PP_J1BF_MSGSEL
Function
Reset
Default
Reserved.
0
J1 Buffer Message Type Select (Compare/ Received
Message).
0
0 = Received message.
1 = Compare.
Table 179. PP_PTRACCTLR3, Path Trace Access Control Register 3 (R/W)
Address
Bit
Name
0x1332
15:1
—
0
PP_J1BF_ACTYP
Function
Reset
Default
Reserved.
0
J1 Buffer Access Type (Read/ Write).
0
0 = Read.
1 = Write.
Table 180. PP_PTRACBGR, Path Trace Access Begin (WO)
Address
Bit
Name
0x1333
15:1
—
0
PP_J1_ACBG
290
Function
Reset
Default
Reserved.
0
J1 Access Begin. Write to 1 to start J1 access.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 181. PP_STS12PTRCTLR[1—6], STS-12 Channel Path Trace Control Registers 1—6 (R/W)
Address
Bit
Name
0x1338
15:4
—
3:0
Function
Reserved.
PP_J1MSG_MSEL[A—D] J1 Message Mode Select (Validated/Provisioned)
Bytestream A—D.
Reset
Default
0
1
0 = Provisioned.
1 = Validated.
0x1339
15:4
—
3:0
PP_J1MSG_TYPSEL
[A—D]
Reserved.
0
J1 Message Type Select (SDH/SONET) Bytestream
A—D. SS bits monitoring (page 249) is enabled only when
the J1 message type SDH is selected. When the J1
message type SONET is selected, SS bits monitoring is
disabled.
0
0 = SONET.
1 = SDH.
0x133C,
0x133D,
0x133E,
0x133F
15:4
3:0
—
Reserved.
PP_TSSEL_J1[A—D][3:0] Time Slots 1—12 Select for J1 Accumulation
Bytestream A—D.
0
0
1111 = Reserved.
1110 = Reserved.
1101 = Reserved.
1100 = STS-1 #12 time slot 12.
1011 = STS-1 #11 time slot 8.
1010 = STS-1 #10 time slot 4.
1001 = STS-1 #9 time slot 11.
1000 = STS-1 #8 time slot 7.
0111 = STS-1 #7 time slot 3.
0110 = STS-1 #6 time slot 10.
0101 = STS-1 #5 time slot 6.
0100 = STS-1 #4 time slot 2.
0011 = STS-1 #3 time slot 9.
0010 = STS-1 #2 time slot 5.
0001 = STS-1 #1 time slot 1.
0000 = Reserved.
Agere Systems Inc.
291
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 182. STS-12 F2, H4, Z3, Z4, and Z5 Status (RO)
Note: For registers 0x1344, 0x1348, 0x134C, and 0x1350 see Table 183.
Address
Bit
Name
0x1341
15:8
—
F2 Byte—Bytestream A.
0
7:0
—
H4 Byte—Bytestream A.
0
15:8
—
Z3 Byte—Bytestream A.
0
7:0
—
Z4 Byte—Bytestream A.
0
15:8
—
Reserved.
0
7:0
—
Z5 Byte—Bytestream A.
0
15:8
—
F2 Byte—Bytestream B.
0
7:0
—
H4 Byte—Bytestream B.
0
15:8
—
Z3 Byte—Bytestream B.
0
7:0
—
Z4 Byte—Bytestream B.
0
15:8
—
Reserved.
0
7:0
—
Z5 Byte—Bytestream B.
0
15:8
—
F2 Byte—Bytestream C.
0
7:0
—
H4 Byte—Bytestream C.
0
15:8
—
Z3 Byte—Bytestream C.
0
7:0
—
Z4 Byte—Bytestream C.
0
15:8
—
Reserved.
0
7:0
—
Z5 Byte—Bytestream C.
0
15:8
—
F2 Byte—Bytestream D.
0
7:0
—
H4 Byte—Bytestream D.
0
15:8
—
Z3 Byte—Bytestream D.
0
7:0
—
Z4 Byte—Bytestream D.
0
15:8
—
Reserved.
0
7:0
—
Z5 Byte—Bytestream D.
0
0x1342
0x1343
0x1345
0x1346
0x1347
0x1349
0x134A
0x134B
0x134D
0x134E
0x134F
292
Function
Reset
Default
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Monitoring the Received F2, H4, Z3, Z4, and Z5 Bytes in Terms of Individual Time Slots. First select which
time slot within the slice that you want to monitor; the CNTD counter must be set. To do this, use the 0x1344 (slice
A), 0x1348 (slice B), 0x134C (slice C), and 0x1350 (slice D) register. The lower 4 bits of each of these registers
holds a time-slot number, in the range 1—12. The upper 12 bits of these four registers hold the CNTD counters for
each of these values. The default values of zero will produce no capture of Z3, H4, etc. The appropriate CNTD
counter must be written to a value with a minimum of 3, and a maximum of 15. In the following examples, all three
CNTD counters are written to a value of 3. The time-slot number is the STS-1 number of the time slot, not its position. Therefore, the SONET 1, 4, 7, 10 convention is used, and a value of 1 will capture the first time slot, 4 will capture the second, etc.
Three examples:
1) To monitor STS-1 # 4 in OC-48 mode.
■
Write 0x1344 to a value of 0x3334.
■
Wait for the number of frames required by the CNTD counters (three frames in this example).
■
Read 0x1341, 0x1342, and/or 0x1343. Extract the value from the appropriate register (0x1341—F2/H4,
0x1342—Z3/Z4, 0x1343—Z5).
2) To monitor STS-1 # 20 in OC-48 mode.
■
MARS2G5 P-Pro assumes each stream is 12 STS-1s, which are within an STS-12 group, i.e., stream A = STS1 #1 to STS-1 #12, stream B = STS-1 #13 to STS-1 #24, etc.
■
STS-1 # 20 is in stream B, and it is the STS-1 number 8 in that stream.
■
Write 0x1348 to a value of 0x3338.
■
Wait for the number of frames required by the CNTD counters (three frames in this example).
■
Read 0x1345, 0x1346, and/or 0x1347. Extract the value from the appropriate register (0x1345—F2/H4,
0x1346—Z3/Z4, 0x1347—Z5).
3) To monitor STS-1 # 7 on line B in quad OC-12 mode.
■
Write 0x1348 to a value of 0x3337.
■
Wait for the number of frames required by the CNTD counters (three frames in this example).
■
Read 0x1345, 0x1346, and/or 0x1347. Extract the value from the appropriate register (0x1345—F2/H4,
0x1346—Z3/Z4, 0x1347—Z5).
As well as waiting, there is a new validated value interrupt. If the new validated value is the same as the old value
when changing time slots, this interrupt may not get set. It is recommended to wait for the three-frame duration,
since this is a short time.
Table 183. Path F2, H4, Z3, Z4, and Z5 Provisioning Bytestream A—D (R/W, Control)
Address
Bit
Name
0x1344,
0x1348,
0x134C,
0x1350
15:12
—
F2 Validated Period Bytestream A—D.
0
11:8
—
H4/Z3/Z4 Validated Period Bytestream A—D.
0
7:4
—
Z5 Validated Period Bytestream A—D.
0
3:0
—
STS-1 Channel Select for F2/H4/Z3/Z4/Z5
Bytes Monitoring Bytestream A—D.
0
Agere Systems Inc.
Function
Reset
Default
293
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 184. STS-12 SS Bits Status (RO)
Address
Bit
Name
0x1351
15:12
—
Reserved.
0
11:10
—
Time Slot 1 Received SS Bits—Bytestream A.
0
9:8
—
Time Slot 2 Received SS Bits—Bytestream A.
0
7:6
—
Time Slot 3 Received SS Bits—Bytestream A.
0
5:4
—
Time Slot 4 Received SS Bits—Bytestream A.
0
3:2
—
Time Slot 5 Received SS Bits—Bytestream A.
0
1:0
—
Time Slot 6 Received SS Bits—Bytestream A.
0
15:12
—
Reserved.
0
11:10
—
Time Slot 7 Received SS Bits—Bytestream A.
0
9:8
—
Time Slot 8 Received SS Bits—Bytestream A.
0
7:6
—
Time Slot 9 Received SS Bits—Bytestream A.
0
5:4
—
Time Slot 10 Received SS Bits—Bytestream A.
0
3:2
—
Time Slot 11 Received SS Bits—Bytestream A.
0
1:0
—
Time Slot 12 Received SS Bits—Bytestream A.
0
15:12
—
Reserved.
0
11:10
—
Time Slot 1 Received SS Bits—Bytestream B.
0
9:8
—
Time Slot 2 Received SS Bits—Bytestream B.
0
7:6
—
Time Slot 3 Received SS Bits—Bytestream B.
0
5:4
—
Time Slot 4 Received SS Bits—Bytestream B.
0
3:2
—
Time Slot 5 Received SS Bits—Bytestream B.
0
1:0
—
Time Slot 6 Received SS Bits—Bytestream B.
0
15:12
—
Reserved.
0
11:10
—
Time Slot 7 Received SS Bits—Bytestream B.
0
9:8
—
Time Slot 8 Received SS Bits—Bytestream B.
0
7:6
—
Time Slot 9 Received SS Bits—Bytestream B.
0
5:4
—
Time Slot 10 Received SS Bits—Bytestream B.
0
3:2
—
Time Slot 11 Received SS Bits—Bytestream B.
0
1:0
—
Time Slot 12 Received SS Bits—Bytestream B.
0
15:12
—
Reserved.
0
11:10
—
Time Slot 1 Received SS Bits—Bytestream C.
0
9:8
—
Time Slot 2 Received SS Bits—Bytestream C.
0
7:6
—
Time Slot 3 Received SS Bits—Bytestream C.
0
5:4
—
Time Slot 4 Received SS Bits—Bytestream C.
0
3:2
—
Time Slot 5 Received SS Bits—Bytestream C.
0
1:0
—
Time Slot 6 Received SS Bits—Bytestream C.
0
0x1352
0x1353
0x1354
0x1355
294
Function
Reset
Default
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 184. STS-12 SS Bits Status (RO) (continued)
Address
Bit
Name
0x1356
15:12
—
Reserved.
0
11:10
—
Time Slot 7 Received SS Bits—Bytestream C.
0
9:8
—
Time Slot 8 Received SS Bits—Bytestream C.
0
7:6
—
Time Slot 9 Received SS Bits—Bytestream C.
0
5:4
—
Time Slot 10 Received SS Bits—Bytestream C.
0
3:2
—
Time Slot 11 Received SS Bits—Bytestream C.
0
1:0
—
Time Slot 12 Received SS Bits—Bytestream C.
0
15:12
—
Reserved.
0
11:10
—
Time Slot 1 Received SS Bits—Bytestream D.
0
9:8
—
Time Slot 2 Received SS Bits—Bytestream D.
0
7:6
—
Time Slot 3 Received SS Bits—Bytestream D.
0
5:4
—
Time Slot 4 Received SS Bits—Bytestream D.
0
3:2
—
Time Slot 5 Received SS Bits—Bytestream D.
0
1:0
—
Time Slot 6 Received SS Bits—Bytestream D.
0
15:12
—
Reserved.
0
11:10
—
Time Slot 7 Received SS Bits—Bytestream D.
0
9:8
—
Time Slot 8 Received SS Bits—Bytestream D.
0
7:6
—
Time Slot 9 Received SS Bits—Bytestream D.
0
5:4
—
Time Slot 10 Received SS Bits—Bytestream D.
0
3:2
—
Time Slot 11 Received SS Bits—Bytestream D.
0
1:0
—
Time Slot 12 Received SS Bits—Bytestream D.
0
0x1357
0x1358
Agere Systems Inc.
Function
Reset
Default
295
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Persistency
Table 185. PP_TSRDI_ALMPSBSR[A—D], Time Slots 1—12 RDI Alarm Persistency Bytestream A—D (RO)
Address
Bit
0x1382, 15:12
0x1383, 11:0
0x1384,
0x1385
Name
—
PP_TSRDI_ALMPSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 RDI Alarm Persistency Bytestream
A—D.
0
Table 186. PP_TSPLM_ALMPSBSR[A—D], Time Slots 1—12 PLM Alarm Persistency Bytestream A—D (RO)
Address
Bit
0x138A, 15:12
0x138B, 11:0
0x138C,
0x138D
Name
—
PP_TSPLM_ALMPSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 Payload Label Mismatch Alarm
Persistency Bytestream A—D.
0
Table 187. PP_TSPUNEQ_ALMPSBSR[A—D], Time Slots 1—12 Path Unequipped Alarm Persistency
Bytestream A—D (RO)
Address
Bit
0x1392, 15:12
0x1393, 11:0
0x1394,
0x1395
296
Name
—
PP_TSPUNEQ_
ALMPSBS[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 Path Unequipped Alarm Persistency
Bytestream A—D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 188. PP_TSAIS_ALMPSBSR[A—D], Time Slots 1—12 AIS Alarm Persistency Bytestream A—D (RO)
Address
Bit
0x139A, 15:12
0x139B, 11:0
0x139C,
0x139D
Name
—
PP_TSAIS_ALMPSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 AIS Alarm Persistency Bytestream
A—D.
0
Table 189. PP_TSLOP_ALMPSBSR[A—D], Time Slots 1—12 LOP Alarm Persistency Bytestream A—D (RO)
Address
Bit
0x13A2, 15:12
0x13A3, 11:0
0x13A4,
0x13A5
Name
—
PP_TSLOP_ALMPSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 LOP Alarm Persistency Bytestream
A—D.
0
Table 190. PP_TSPDI_ALMPSBSR[A—D], Time Slots 1—12 PDI Alarm Persistency Bytestream A—D (RO)
Address
Bit
0x13AA, 15:12
0x13AB, 11:0
0x13AC,
0x13AD
Agere Systems Inc.
Name
—
PP_TSPDI_ALMPSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 PDI Alarm Persistency Bytestream
A—D.
0
297
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
State
Table 191. PP_TSRDI_STBSR[A—D], Time Slots 1—12 RDI State Bytestream A—D (RO)
Address
Bit
0x13C2, 15:12
0x13C3, 11:0
0x13C4,
0x13C5
Name
—
PP_TSRDI_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 RDI State Bytestream A—D.
0
Table 192. PP_TSPLM_STBSR[A—D], Time Slots 1—12 PLM State Bytestream A—D (RO)
Address
Bit
0x13CA, 15:12
0x13CB, 11:0
0x13CC,
0x13CD
Name
—
PP_TSPLM_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 Payload Label Mismatch State
Bytestream A—D.
0
Table 193. PP_TSPUNEQ_STBSR[A—D], Time Slots 1—12 Path Unequipped State Bytestream A—D (RO)
Address
Bit
0x13D2, 15:12
0x13D3, 11:0
0x13D4,
0x13D5
298
Name
—
PP_TSRDI_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 Path Unequipped State Bytestream
A—D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 194. PP_TSAIS_STBSR[A—D], Time Slots 1—12 AIS State Bytestream A—D (RO)
Address
Bit
0x13DA, 15:12
0x13DB, 11:0
0x13DC,
0x13DD
Name
—
PP_TSAIS_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 AIS State Bytestream A—D.
0
Table 195. PP_TSLOP_STBSR[A—D], Time Slots 1—12 LOP State Bytestream A—D (RO)
Address
Bit
0x13E2, 15:12
0x13E3, 11:0
0x13E4,
0x13E5
Name
—
PP_TSLOP_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 LOP State Bytestream A—D.
0
Table 196. PP_TSPDI_STBSR[A—D], Time Slots 1—12 PDI State Bytestream A—D (RO)
Address
Bit
0x13EA, 15:12
0x13EB, 11:0
0x13EC,
0x13ED
Agere Systems Inc.
Name
—
PP_TSPDI_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 PDI State Bytestream A—D.
0
299
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Signal Fail
Table 197. PP_SFWSZ_SELR[1—2], Signal Fail Window Size Select Registers 1—2 (R/W, Control)
Address
Bit
Name
0x1400
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
PP_SFWSZ_SELSET
[0—7][1:0]
Window Size Select Set Threshold 0—7.
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
PP_SFWSZ_SELCLR
[0—7][1:0]
Window Size Select Clear Threshold 0—7.
0x1401
300
Function
00 = Window size 0.
01 = Window size 1.
10 = Window size 2.
11 = Window size 3.
00 = Window size 0.
01 = Window size 1.
10 = Window size 2.
11 = Window size 3.
Reset
Default
1
2
1
2
1
2
1
2
2
3
2
3
2
3
2
3
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 198. PP_SFDR[0—7], Signal Fail Detect Threshold Registers 0—7 (R/W, Control)
Address
Bit
Name
0x1410
15:9
—
8:0
PP_SFD0[8:0]
Function
Reserved.
STS-1 Signal Fail Detect Threshold 0.
Reset
Default
0
0x0CF
Number of bit/block errors within detection window
required to trigger a signal fail.
0x1411
0x1412
0x1413
0x1414
0x1415
0x1416
0x1417
15:9
—
8:0
PP_SFD1[8:0]
15:14
—
13:0
PP_SFD2[13:0]
15:14
—
13:0
PP_SFD3[13:0]
15:14
—
13:0
PP_SFD4[13:0]
15:14
—
13:0
PP_SFD5[13:0]
15:14
—
13:0
PP_SFD6[13:0]
15:14
—
13:0
PP_SFD7[13:0]
Agere Systems Inc.
Reserved.
STS-1 Signal Fail Detect Threshold 1.
Reserved.
STS-Nc Signal Fail Detect Threshold 2.
Reserved.
STS-Nc Signal Fail Detect Threshold 3.
Reserved.
STS-Nc Signal Fail Detect Threshold 4.
Reserved.
STS-Nc Signal Fail Detect Threshold 5.
Reserved.
STS-Nc Signal Fail Detect Threshold 6.
Reserved.
STS-Nc Signal Fail Detect Threshold 7.
0
0x0DE
0
0x0233
0
0x02B2
0
0x3A3
0
0x055E
0
0x51D
0
0x0A62
301
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 199. PP_SFCLRR[0—7], Signal Fail Clear Threshold Registers 0—7 (R/W, Control)
Address
Bit
Name
0x1418
15:9
—
8:0
PP_SFCLR0[8:0]
Function
Reset
Default
Reserved.
0
STS-1 Signal Fail Clear Threshold 0.
0x113
Number of bit/block errors within detection window
permitted when clearing a signal fail.
0x1419
15:9
—
8:0
PP_SFCLR1[8:0]
0x141A 15:14
13:0
0x141B 15:14
13:0
0x141C 15:14
13:0
0x141D 15:14
13:0
0x141E 15:14
13:0
0x141F 15:14
13:0
—
PP_SFCLR2[13:0]
—
PP_SFCLR3[13:0]
—
PP_SFCLR4[13:0]
—
PP_SFCLR5[13:0]
—
PP_SFCLR6[13:0]
—
PP_SFCLR7[13:0]
Reserved.
0
STS-1 Signal Fail Clear Threshold 1.
0x115
Reserved.
0
STS-Nc Signal Fail Clear Threshold 2.
0x030B
Reserved.
0
STS-Nc Signal Fail Clear Threshold 3.
0x031B
Reserved.
0
STS-Nc Signal Fail Clear Threshold 4.
0x5D8
Reserved.
0
STS-Nc Signal Fail Clear Threshold 5.
0x0618
Reserved.
0
STS-Nc Signal Fail Clear Threshold 6.
0x0B08
Reserved.
0
STS-Nc Signal Fail Clear Threshold 7.
0x0BFC
Table 200. PP_SFWSZR[0—3], Signal Fail Window Size 0/1/2/3 Registers (R/W, Control)
Address
Bit
Name
Function
Reset
Default
0x1420
15:0
PP_SFWSZ0[15:0]
Signal Fail Window Size 0 (in 0.5 ms Increments). A
setting of zero is the same as 1; will produce a 0.5 ms
window size.
0x000A
0x1430
15:0
PP_SFWSZ1[15:0]
Signal Fail Window Size 1 (in 0.5 ms Increments). A
setting of zero is the same as 1; will produce a 0.5 ms
window size.
0x0064
0x1440
15:0
PP_SFWSZ2[15:0]
Signal Fail Window Size 2 (in 0.5 ms Increments). A
setting of zero is the same as 1; will produce a 0.5 ms
window size.
0x03E8
0x1450
15:0
PP_SFWSZ3[15:0]
Signal Fail Window Size 3 (in 0.5 ms Increments). A
setting of zero is the same as 1; will produce a 0.5 ms
window size.
0x2710
Signal Fail Window Size Registers: Above are the settings for the length of the four free-running windows that
are used in conjunction with the set and clear thresholds for the signal fail detection. This time unit depends on the
number of columns in a frame setting. The time unit is four times an STS-frame size, which is 0.5 ms for a system
setting of 90 columns.
After changing one of these window registers, it will take two time unit pules to occur before this new value is used,
i.e., the old window will come to a halt and the new one will begin from 0.5 ms to 1 ms (assuming 90 columns).
302
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Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Concatenation
The expected concatenation map register is programmed via programmable registers (Table 201) on a per timeslot (STS-1) basis. The concatenation state of each time slot can be read from the received concatenation map
register (PP_RCNCTM_TSBSR[A—D], Received Concatenation Map Time Slots 1—12 in Bytestream A—D (RO),
Table 203). Comparison of the expected and received concatenation state is enabled on a per time-slot basis by
software setting of the concatenation compare enable register (PP_CNCTCPREN_TSBSR[A—D], Concatenation
Compare Enable Time Slots 1—12 in Bytestream A—D (R/W), Table 202). Alarms are binned on a per bytestream
(STS-12) basis in the concatenation map mismatch register (PP_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning Bytestream A—D (RO, COR/COW), Table 113), and resulting interrupts can be masked by the concatenation map mismatch mask register (see PP_CNCTMM_ALMMBSR, Channel
Path Concatenation Map Mismatch Alarm Status Masks Bytestream A—D (R/W), Table 152) mismatches in the
first time slot of a bytestream are special cases. When the expected state of a bytestream is concatenation and the
received state is normal, the mismatch status bit for the previous bytestream will be set since the errored time slot
is trying to concatenate to an STS-1 in the previous bytestream.
Table 201. PP_ECNCTM_TSBSR[A—D], Expected Concatenation Map Time Slots 1—12 in
Bytestream A—D (R/W)
Address
Bit
0x1502, 15:12
0x1503, 11:0
0x1504,
0x1505
Name
—
PP_ECNCT_STTSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Expected Concatenation State for Time Slots 1—12 in
Bytestream A—D.
0
0 = Time slot not expected to be in concatenation.
1 = Time slot expected to be in concatenation.
Table 202. PP_CNCTCPREN_TSBSR[A—D], Concatenation Compare Enable Time Slots 1—12 in
Bytestream A—D (R/W)
Address
Bit
0x1507, 15:12
0x1508, 11:0
0x1509,
0x150A
Name
—
PP_CNCTCPREN_
TSBS[A—D][1—12]
Function
Reset
Default
Reserved.
0
Concatenation Compare Enable Time Slots 1—12 in
Bytestream A—D.
0
0 = Inhibit comparison of received and expected
concatenation states.
1 = Compare received and expected concatenation
states.
Table 203. PP_RCNCTM_TSBSR[A—D], Received Concatenation Map Time Slots 1—12 in
Bytestream A—D (RO)
Address
Bit
0x1512, 15:12
0x1513, 11:0
0x1514,
0x1515
Name
—
PP_RCNCT_STTSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Received Concatenation State for Time Slots 1—12 in
Bytestream A—D.
0
0 = Concatenation state not detected.
1 = Concatenation state detected.
Agere Systems Inc.
303
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
AIS Insert Control
Table 204. PP_SWAIS_ISRTR, Software AIS Insert (R/W)
Address
Bit
0x1542, 15:12
0x1543, 11:0
0x1544,
0x1545
Name
—
PP_SWAIS_ISRT
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 STS AIS Insert Bytestream
A—D.
0
0 = No AIS insert.
1 = AIS insert.
Pointer Processor Control
Table 205. PP_STS12_PINCDECR, STS-12 Pointer Increment/Decrement (R/W)
Address
Bit
Name
0x1580
15:4
—
3:0
PP_PINCDEC[A—D]
Function
Reset
Default
Reserved.
—
Pointer Increment/Decrement Rules to Use (SONET/
SDH) Bytestream A—D.
1111
Table 206. PP_TSSS_ISRTBSR[A—D], Time Slot 1—Time Slot 12 SS Bits Insert Bytestream A—D (R/W)
Address
Bit
0x1582, 15:12
0x1583, 11:0
0x1584,
0x1585
Name
—
PP_TSSS_ISRTBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 SS Bits Insert Bytestream
A—D.
0
0 = Pass through.
1 = Insert.
Table 207. PP_TSE1F1_ISRTBSR[A—D], Time Slot 1—Time Slot 12 E1/F1 Insert Bytestream A—D (R/W)
Address
Bit
0x1587, 15:12
0x1588, 11:0
0x1589,
0x158A
Name
—
PP_TSE1F1_ISRTBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 E1/F1 Insert Bytestream
A—D.
0
0 = Path status byte.
1 = Insert.
304
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 208. PP_E2_ISRTCTLR[A—D], E2 Insert Control Bytestream A—D (R/W)
Address
Bit
Name
0x158C,
0x158D,
0x158E,
0x158F
15:1
—
0
PP_E2_ISRTCTL[A—D]
Function
Reset
Default
Reserved.
—
E2 Insert Control Bytestream A—D.
0
0 = Line status byte.
1 = Software insert.
Table 209. PP_TS_INCDECBNR[A—D], Time Slots 1—12 Increment/Decrement Binning Select
Bytestream A—D (R/W)
Address
Bit
Name
0x1590,
0x1591,
0x1592,
0x1593
15:4
—
3:0
PP_TS_INCDECBN
[A—D][3:0]
Function
Reserved.
Reset
Default
—
Time Slots 1—12 Increment/Decrement Binning
Select Bytestream A—D.
1111 = None selected counter disabled (see note below).
1110 = None selected counter disabled (see note below).
1101 = None selected counter disabled (see note below).
1100 = STS-1 #12 time slot 12.
1011 = STS-1 #11 time slot 8.
1010 = STS-1 #10 time slot 4.
1001 = STS-1 #9 time slot 11.
1000 = STS-1 #8 time slot 7.
0111 = STS-1 #7 time slot 3.
0110 = STS-1 #6 time slot 10.
0101 = STS-1 #5 time slot 6.
0100 = STS-1 #4 time slot 2.
0011 = STS-1 #3 time slot 9.
0010 = STS-1 #2 time slot 5.
0001 = STS-1 #1 time slot 1.
0000 = None selected counter disabled (see note below).
0000
(Disabl
ed)
Note:Selecting 0, 13, 14, 15 will cause the increment/
decrement counter to remain at its last count until
the next PM 1-second pulse when it will clear and
remain at 0 thereafter.
Table 210. PP_AISONTIM_ISRTR[A—D], STS-12 Pointer Processor Control (R/W)
Address
Bit
0x1594, 15:12
0x1595, 11:0
0x1596,
0x1597
Name
—
PP_AISONTIM_ISRT
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 TIM Insert
Bytestream A—D.
0
0 = No TIM insert.
1 = TIM insert.
Agere Systems Inc.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 211. PP_TSPDIVLD_CTLBSR[A—D], Time Slot 1—Time Slot 12 PDI Validate Control Bytestream A—D
(R/W)
Address
Bit
Name
Function
Reset
Default
Note: There are four PM increment/decrement counters; increment and decrement for both the interpreter and
generator for each STS-12 group. For a concatenation spanning STS-12 blocks, the select should be set to
the head of the concatenation. It is suggested for clarity that counters not being used be disabled by setting
them to 0; for example, in an STS-48C, bytestream A increment/decrement binning select should be set to
STS-1 #1 and the selects for streams B, C, and D should be set to 0. The increments and decrements for
the entire concatenation should then be read from the stream A registers.
0x15A2, 15:12
0x15A3, 11:0
0x15A4,
0x15A5
—
PP_TSPDIVLD_CTLBS
[A—D][1—12]
Reserved.
—
Time Slot 1—Time Slot 12 PDI Validate Control
Bytestream A—D.
0
0 = Disables PDI codes.
1 = Enables PDI codes to affect path status byte.
Provisioning
Table 212. PP_EXPC2_PVSNR[1—24], Expected C2 Byte Provisioning (R/W)
Address
Bit
Name
Function
Reset
Default
0x1600
—
0x1617
15:8
PP_EXPC2
[1, 3, 5, . . . , 47][7:0]
Time Slot 1, 3, 5, 7, 9, . . ., 47 Expected C2 Byte.
0
7:0
PP_EXPC2
[2, 4, 6, . . . , 48][7:0]
Time Slot 2, 4, 6, 8, 10, . . ., 48 Expected C2 Byte.
0
Note: The expected C2 byte is only a programming mode and changing them does not affect the validation
counters.
Table 213. PP_TSCBB_ERRBSR[A—D], Time Slot 1—Time Slot 12 Count Block/Bit Errors Bytestream A—D
Address
Bit
0x1618, 15:12
0x1619,
11:0
0x161A,
0x161B
306
Name
—
PP_TSCBB_ERRBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Count Block/Bit Errors
Bytestream A—D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 214. PP_TS1_6_SSBSRA, PP_TS7_12_SSBSRA, Time Slots 1—12 SS Bits Insertion Value
Bytestream A (R/W)
Address
Bit
Name
0x1620
15:12
—
11:10
0x1621
Function
Reset
Default
Reserved.
0
PP_TS_SSA1
Time Slot 1 SS Bits Setting—Stream A.
0
9:8
PP_TS_SSA2
Time Slot 2 SS Bits Setting—Stream A.
0
7:6
PP_TS_SSA3
Time Slot 3 SS Bits Setting—Stream A.
0
5:4
PP_TS_SSA4
Time Slot 4 SS Bits Setting—Stream A.
0
3:2
PP_TS_SSA5
Time Slot 5 SS Bits Setting—Stream A.
0
1:0
PP_TS_SSA6
Time Slot 6 SS Bits Setting—Stream A.
0
15:12
—
Reserved.
0
11:10
PP_TS_SSA7
Time Slot 7 SS Bits Setting—Stream A.
0
9:8
PP_TS_SSA8
Time Slot 8 SS Bits Setting—Stream A.
0
7:6
PP_TS_SSA9
Time Slot 9 SS Bits Setting—Stream A.
0
5:4
PP_TS_SSA10
Time Slot 10 SS Bits Setting—Stream A.
0
3:2
PP_TS_SSA11
Time Slot 11 SS Bits Setting—Stream A.
0
1:0
PP_TS_SSA12
Time Slot 12 SS Bits Setting—Stream A.
0
Table 215. PP_TS1_6_SSBSRB, PP_TS7_12_SSBSRB, Time Slots 1—12 SS Bits Insertion Value
Bytestream B (R/W)
Address
Bit
Name
0x1622
15:12
—
11:10
0x1623
Function
Reset
Default
Reserved.
0
PP_TS_SSB1
Time Slot 1 SS Bits Setting—Stream B.
0
9:8
PP_TS_SSB2
Time Slot 2 SS Bits Setting—Stream B.
0
7:6
PP_TS_SSB3
Time Slot 3 SS Bits Setting—Stream B.
0
5:4
PP_TS_SSB4
Time Slot 4 SS Bits Setting—Stream B.
0
3:2
PP_TS_SSB5
Time Slot 5 SS Bits Setting—Stream B.
0
1:0
PP_TS_SSB6
Time Slot 6 SS Bits Setting—Stream B.
0
15:12
—
Reserved.
0
11:10
PP_TS_SSB7
Time Slot 7 SS Bits Setting—Stream B.
0
9:8
PP_TS_SSB8
Time Slot 8 SS Bits Setting—Stream B.
0
7:6
PP_TS_SSB9
Time Slot 9 SS Bits Setting—Stream B.
0
5:4
PP_TS_SSB10
Time Slot 10 SS Bits Setting—Stream B.
0
3:2
PP_TS_SSB11
Time Slot 11 SS Bits Setting—Stream B.
0
1:0
PP_TS_SSB12
Time Slot 12 SS Bits Setting—Stream B.
0
Agere Systems Inc.
307
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 216. PP_TS1_6_SSBSRC, PP_TS7_12_SSBSRC, Time Slots 1—12 SS Bits Insertion Value
Bytestream C (R/W)
Address
Bit
Name
0x1624
15:12
—
11:10
0x1625
Function
Reset
Default
Reserved.
0
PP_TS_SSC1
Time Slot 1 SS Bits Setting—Stream C.
0
9:8
PP_TS_SSC2
Time Slot 2 SS Bits Setting—Stream C.
0
7:6
PP_TS_SSC3
Time Slot 3 SS Bits Setting—Stream C.
0
5:4
PP_TS_SSC4
Time Slot 4 SS Bits Setting—Stream C.
0
3:2
PP_TS_SSC5
Time Slot 5 SS Bits Setting—Stream C.
0
1:0
PP_TS_SSC6
Time Slot 6 SS Bits Setting—Stream C.
0
15:12
—
Reserved.
0
11:10
PP_TS_SSC7
Time Slot 7 SS Bits Setting—Stream C.
0
9:8
PP_TS_SSC8
Time Slot 8 SS Bits Setting—Stream C.
0
7:6
PP_TS_SSC9
Time Slot 9 SS Bits Setting—Stream C.
0
5:4
PP_TS_SSC10
Time Slot 10 SS Bits Setting—Stream C.
0
3:2
PP_TS_SSC11
Time Slot 11 SS Bits Setting—Stream C.
0
1:0
PP_TS_SSC12
Time Slot 12 SS Bits Setting—Stream C.
0
Table 217. PP_TS1_6_SSBSRD, PP_TS7_12_SSBSRD, Time Slots 1—12 SS Bits Insertion Value
Bytestream D (R/W)
Address
Bit
Name
0x1626
15:12
—
11:10
0x1627
308
Function
Reset
Default
Reserved.
0
PP_TS_SSD1
Time Slot 1 SS Bits Setting—Stream D.
0
9:8
PP_TS_SSD2
Time Slot 2 SS Bits Setting—Stream D.
0
7:6
PP_TS_SSD3
Time Slot 3 SS Bits Setting—Stream D.
0
5:4
PP_TS_SSD4
Time Slot 4 SS Bits Setting—Stream D.
0
3:2
PP_TS_SSD5
Time Slot 5 SS Bits Setting—Stream D.
0
1:0
PP_TS_SSD6
Time Slot 6 SS Bits Setting—Stream D.
0
15:12
—
Reserved.
0
11:10
PP_TS_SSD7
Time Slot 7 SS Bits Setting—Stream D.
0
9:8
PP_TS_SSD8
Time Slot 8 SS Bits Setting—Stream D.
0
7:6
PP_TS_SSD9
Time Slot 9 SS Bits Setting—Stream D.
0
5:4
PP_TS_SSD10
Time Slot 10 SS Bits Setting—Stream D.
0
3:2
PP_TS_SSD11
Time Slot 11 SS Bits Setting—Stream D.
0
1:0
PP_TS_SSD12
Time Slot 12 SS Bits Setting—Stream D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 218. SS Bits Provisioning (R/W)
Address
Bit
Name
0x1629
15:4
3:0
—
—
Function
—
SS Bits Monitoring Mode Bytestream A—D.
Reset
Default
—
—
0 = Compare mode.
1 = Validation mode.
Table 219. SS Bits Validation/Compare Period (R/W)
Address
Bit
Name
Function
0x162A
15:4
—
—
3:0
—
SS Bits Validation/Compare Period Bytestream A—D.
Reset
Default
—
0x5
Table 220. Elastic Store Decrement and Increment (R/W)
Address
Bit
Name
Function
Reset
Default
0x162C
15:8
PP_ES_DEC_MAX[7:0]
Elastic Store Decrement Region Maximum. Must be set
to 0x03.
0x03
7:0
PP_ES_INC_MIN[7:0]
Elastic Store Increment Region Minimum. Must be set
to 0xC3.
0xA4
Table 221. Elastic Store Overflow Region (R/W)
Address
Bit
Name
Function
Reset
Default
0x162D
15:8
PP_ES_OVR_MAX[7:0]
Elastic Store Overflow Region Maximum.
0x03
7:0
PP_ES_OVR_MIN[7:0]
Elastic Store Increment Region Minimum.
0x66
Table 222. PP_TS_E1F1ISRTR[1—24], Time Slots 1—48 E1/F1 Insert
Address
Bit
Name
Function
Reset
Default
0x1650
—
0x1667
15:8
PP_TS_E1F1ISRT
[1, 3, 5, . . ., 47]
Time Slot 1—Time Slot 47 E1/F1 Insert Byte.
0
7:0
PP_TS_E1F1ISRT
[2, 4, 6, . . ., 48]
Time Slot 2—Time Slot 48 E1/F1 Insert Byte.
0
Table 223. PP_E2_ISRTBSR[A—D], E2 Byte Insert Bytestream A—D
Address
Bit
Name
0x1668,
0x1669,
0x166A,
0x166B
15:8
—
7:0
PP_E2_ISRTBS
[A—D][7:0]
Agere Systems Inc.
Function
Reset
Default
Reserved.
0
E2 Byte Insert Bytestream A—D.
0
309
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Maintenance
Table 224. PP_TSMNTR[1—48], Time Slots 1—48 Maintenance (R/W)
Address
Bit
Name
0x1690
—
0x16BF
15:3
—
2:0
Function
Reset
Default
Reserved.
0
PP_TSSF_TH[1—48][2:0] Time Slot 1—Time Slot 48 Signal Fail Threshold
Select. This value sets the signal fail threshold for the
respective time slot.
0
Interpreter Increment/Decrement PM
Table 225. PP_PI_LSECINCR[A—D], Pointer Interpreter Last Second Increments Bytestream A—D (RO)
Address
Bit
0x1702, 15:11
0x1703, 10:0
0x1704,
0x1705
Name
—
PP_PI_LSECINC
[A—D][10:0]
Function
Reset
Default
Reserved.
0
Last Second Increments in Pointer Interpreter
Bytestream A—D.
0
Table 226. PP_PI_LSECDECR[A—D], Pointer Interpreter Last Second Decrements Bytestream A—D (RO)
Address
Bit
0x1712, 15:11
0x1713, 10:0
0x1714,
0x1715
Name
—
PP_PI_LSECDEC
[A—D][10:0]
Function
Reset
Default
Reserved.
0
Last Second Decrements in Pointer Interpreter
Bytestream A—D.
0
Generator Increment/Decrement PM
Table 227. PP_PG_LSECINCR[A—D], Pointer Generator Last Second Increments Bytestream A—D (RO)
Address
Bit
0x1742, 15:11
0x1743, 10:0
0x1744,
0x1745
Name
—
PP_PG_LSECINCR
[A—D][10:0]
Function
Reset
Default
Reserved.
0
Last Second Increments in Pointer Generator
Bytestream A—D.
0
Table 228. PP_PG_LSECDECR[A—D], Pointer Generator Last Second Decrements Bytestream A—D (RO)
Address
Bit
0x1752, 15:11
0x1753, 10:0
0x1754,
0x1755
310
Name
—
PP_PG_LSECDECR
[A—D][10:0]
Function
Reset
Default
Reserved.
0
Last Second Decrements in Pointer Generator
Bytestream A—D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Performance Monitoring
Table 229. PP_POH_ALMPMR, Path Overhead Alarm Performance Monitoring (RO)
Address
Bit
Name
0x1780
15:7
—
6
PP_1BRDI_DPM
Function
Reset
Default
Reserved.
0
One-Bit RDI Defect PM.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
5
PP_ERDI_PDPM
ERDI Payload Defect PM.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
4
PP_ERDI_CDPM
ERDI Connectivity Defect PM.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
3
PP_ERDI_SDPM
ERDI Server Defect PM.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
2
PP_UNEQR_ALMPM
Unequipped Received Alarm PM.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
1
PP_AIS_ALMPM
Alarm Indicator Signal Alarm PM.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
0
PP_LOP_ALMPM
Loss of Pointer Alarm PM.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
Agere Systems Inc.
311
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 230. PP_1BRDI_DPMBSR, Path Overhead One-Bit RDI Defect PM Bytestream A—D (RO)
Address
Bit
Name
0x1781
15:4
—
3:0
PP_1BRDI_DPMBS
[A—D]
Function
Reset
Default
Reserved.
0
One-Bit RDI Defect PM Bytestream A—D.
0
0 = One-bit RDI defect PM has not been detected for any
STS-1s in bytestream A—D.
1 = One-bit RDI defect PM has been detected for one or
more STS-1s in bytestream A—D.
Table 231. PP_TS1BRDI_DPMBSR[A—D], Path Overhead Time Slots 1—12 One-Bit RDI Defect PM
Bytestream A—D (RO)
Address
Bit
0x1782, 15:12
0x1783, 11:0
0x1784,
0x1785
Name
—
PP_TS1BRDI_DPMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 One-Bit RDI Defect PM
Bytestream A—D.
0
Table 232. PP_ERDI_PDPMBSR, Path Overhead ERDI Payload Defect PM Bytestream A—D (RO)
Address
Bit
Name
0x1791
15:4
—
3:0
PP_ERDI_PDPMBS
[A—D]
Function
Reset
Default
Reserved.
0
ERDI Payload Defect PM Bytestream A—D.
0
0 = ERDI payload defect PM has not been detected for
any STS-1s in bytestream A—D.
1 = ERDI payload defect PM has been detected for one or
more STS-1s in bytestream A—D.
Table 233. PP_TSERDI_PDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Payload Defect PM
Bytestream A—D (RO)
Address
Bit
0x1792, 15:12
0x1793, 11:0
0x1794,
0x1795
312
Name
—
PP_TSERDI_PDPMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 ERDI Payload Defect PM
Bytestream A—D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 234. PP_ERDI_CDPMBSR, Path Overhead ERDI Connectivity Defect PM Bytestream A—D (RO)
Address
Bit
Name
0x17A1
15:4
—
3:0
PP_ERDI_CDPMBS
[A—D]
Function
Reset
Default
Reserved.
0
ERDI Connectivity Defect PM Bytestream A—D.
0
0 = ERDI connectivity defect PM has not been detected
for any STS-1s in bytestream A—D.
1 = ERDI connectivity defect PM has been detected for
one or more STS-1s in bytestream A—D.
Table 235. PP_TSERDI_CDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Connectivity Defect PM
Bytestream A—D (RO)
Address
Bit
0x17A2, 15:12
0x17A3, 11:0
0x17A4,
0x17A5
Name
—
PP_TSERDI_CDPMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 ERDI Connectivity Defect
PM Bytestream A—D.
0
Table 236. PP_ERDI_SDPMBSR, Path Overhead ERDI Server Defect PM Bytestream A—D (RO)
Address
Bit
Name
0x17B1
15:4
—
3:0
PP_ERDI_SDPMBS
[A—D]
Function
Reset
Default
Reserved.
0
ERDI Server Defect PM Bytestream A—D.
0
0 = ERDI server defect PM has not been detected for any
STS-1s in bytestream A—D.
1 = ERDI server defect PM has been detected for one or
more STS-1s in bytestream A—D.
Table 237. PP_TSERDI_SDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Server Defect PM
Bytestream A—D (RO)
Address
Bit
0x17B2 15:12
0x17B3 11:0
0x17B4
0x17B5
Agere Systems Inc.
Name
—
PP_TSERDI_SDPMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 ERDI Server Defect PM
Bytestream A—D.
0
313
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 238. PP_UNEQR_PMBSR, Path Overhead Unequipped Received PM Bytestream A—D (RO)
Address
Bit
Name
0x17C1
15:4
—
3:0
Function
Reset
Default
Reserved.
0
0
PP_UNEQR_PMBS[A—D] Unequipped Received PM Bytestream A—D.
0 = Unequipped received PM has not been detected for
any STS-1s in bytestream A—D.
1 = Unequipped received PM has been detected for one
or more STS-1s in bytestream A—D.
Table 239. PP_TSUNEQR_PMBSR[A—D], Path Overhead Time Slots 1—12 Unequipped Received PM
Bytestream A—D (RO)
Address
Bit
0x17C2 15:12
0x17C3 11:0
0x17C4
0x17C5
Name
—
PP_TSUNEQR_PMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Unequipped Received PM
Bytestream A—D.
0
Table 240. PP_AIS_PMBSR, Path Overhead Alarm Indicator Signal PM Bytestream A—D (RO)
Address
Bit
Name
0x17D1
15:4
—
3:0
PP_AIS_PMBS[A—D]
Function
Reset
Default
Reserved.
0
Alarm Indicator Signal PM Bytestream A—D.
0
0 = Alarm indicator signal PM has not been detected for
any STS-1s in bytestream A—D.
1 = Alarm indicator signal PM has been detected for one
or more STS-1s in bytestream A—D.
Table 241. PP_TSAIS_PMBSR[A—D], Path Overhead Time Slots 1—12 Alarm Indicator Signal PM
Bytestream A—D (RO)
Address
Bit
0x17D2 15:12
0x17D3 11:0
0x17D4
0x17D5
314
Name
—
PP_TSAIS_PMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Alarm Indicator Signal PM
Bytestream A—D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
Table 242. PP_LOP_PMBSR, Path Overhead Loss of Pointer PM Bytestream A—D (RO)
Address
Bit
Name
0x17E1
15:4
—
3:0
PP_LOP_PMBSR[A—D]
Function
Reset
Default
Reserved.
0
Loss of Pointer PM Bytestream A—D.
0
0 = Loss of pointer PM has not been detected for any
STS-1s in bytestream A—D.
1 = Loss of pointer PM has been detected for one or more
STS-1s in bytestream A—D.
Table 243. PP_TSLOP_PMBSR[A—D], Path Overhead Time Slots 1—12 Loss of Pointer PM
Bytestream A—D (RO)
Address
Bit
0x17E2, 15:12
0x17E3, 11:0
0x17E4,
0x17E5
Name
—
PP_TSLOP_PMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Loss of Pointer PM
Bytestream A—D.
0
Table 244. PP_LSECCVP_CPMR[1—48], Last Second CV-P Count Time Slot 1—Time Slot 48 PM (RO)
Address
Bit
Name
0x1800
—
0x182F
15:0
PP_LSECCVP_CPM
[1—48][15:0]
Function
Reset
Default
Time Slot 1—Time Slot 48 CV Count PM.
0
Table 245. PP_LSECREIP_CPMR[1—48], Last Second REI-P Count Time Slot 1—Time Slot 48 PM (RO)
Address
Bit
Name
0x1880
—
0x18AF
15:0
PP_LSECREIP_CPM
[1—48][15:0]
Agere Systems Inc.
Function
Time Slot 1—Time Slot 48 REI Count PM.
Reset
Default
0
315
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Descriptions (continued)
RDI, C2, and PDI Status
Table 246. PP_TSRDIPR[1—48], Time Slots 1—48 Path RDI Status (RO)
Address
Bit
Name
0x1900
—
0x192F
15:3
—
2:0
Function
Reset
Default
Reserved.
0
PP_TS_RRDI[1—48][2:0] Time Slot 1—Time Slot 48 Received RDI Code.
0
Table 247. PP_TSC2R[1—24], Time Slots 1—48 Path C2 Status (RO)
Address
Bit
Name
Function
Reset
Default
0x1930
—
0x1947
15:8
PP_TSRC2
[1, 3, . . ., 47][7:0]
Time Slot 1, 3, 5, 7, . . ., 47 Received C2 Byte.
0
7:0
PP_TSRC2
[2, 4, . . ., 48][7:0]
Time Slot 2, 4, 6, 8, . . ., 48 Received C2 Byte.
0
Table 248. PP_TSPDIR[1—24], Time Slots 1—48 Path PDI Status (RO)
Address
Bit
Name
0x1960
—
0x1977
15:8
PP_TSRPDI
[1, 3, . . ., 47][7:0]
Time Slot 1, 3, 5, 7, . . ., 47 Received PDI Byte.
0
7:0
PP_TSRPDI
[2, 4, . . ., 48][7:0]
Time Slot 2, 4, 6, 8, . . ., 48 Received PDI Byte.
0
316
Function
Reset
Default
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map
Table 249. Pointer Processor Register Map
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Version Control (RO)
0x1000
PP_IDR
0x1001
PP_CORWR
PP_ID[15:0]
0x1002
—
0x100E
—
0x100F
PP_POH_ALMBNR1
0x1010
PP_POH_ALMBNR2
0x1011
—
0x1020
—
0x1021
PP_ES_ALMBNBSR
0x1022
PP_TSES_ALMBSRA
Elastic Store Overrun/Underrun Alarm per STS-1 Bytestream A
0x1023
PP_TSES_ALMBSRB
Elastic Store Overrun/Underrun Alarm per STS-1 Bytestream B
0x1024
PP_TSES_ALMBSRC
Elastic Store Overrun/Underrun Alarm per STS-1 Bytestream C
0x1025
PP_TSES_ALMBSRD
Elastic Store Overrun/Underrun Alarm per STS-1 Bytestream D
0x1026
—
0x1030
—
0x1031
PP_SF_ALMBNBSR
PP_
CORW
Interrupts
—
PP_RDI_A
LMDBN
PP_PLM_
ALMDBN
PP_
UNEQR_
ALMDBN
PP_AIS_A
LMDBN
PP_LOP_
ALMDBN
PP_J1MM
_ALMBN
—
PP_J1VLD
PP_
_ALMBN USCNCT_
ALMBN
—
—
—
—
—
PP_PDI_A
LMDBN
PP_PDI_A
LMBN
PP_
J1ACCMP
_ALMBN
PP_
CNCTMM
_ALMBN
PP_ES_
ALMBN
PP_SF_
ALMBN
PP_RDI_
ALMBN
PP_PLM_
ALMBN
PP_
UNEQR_
ALMBN
PP_AIS_
ALMBN
PP_LOP_
ALMBN
Elastic Store Overrun/Underrun Alarm Binning
PP_ES_ALMBNBS[A—D]
PP_TSES_ALMBSA[1—12]
PP_TSES_ALMBSB[1—12]
PP_TSES_ALMBSC[1—12]
PP_TSES_ALMBSD[1—12]
Signal Fail Binning
PP_SF_ALMBNBS[A—D]
0x1032
PP_TSSF_ALMBSRA
Signal Fail Alarm per STS-1 Bytestream A
0x1033
PP_TSSF_ALMBSRB
Signal Fail Alarm per STS-1 Bytestream B
0x1034
PP_TSSF_ALMBSRC
Signal Fail Alarm per STS-1 Bytestream C
0x1035
PP_TSSF_ALMBSRD
Signal FAil Alarm per STS-1 Bytestream D
0x1036
—
0x1040
—
PP_TSSF_ALMBSA[1—12]
PP_TSSF_ALMBSB[1—12]
PP_TSSF_ALMBSC[1—12]
PP_TSSF_ALMBSD[1—12]
Agere Systems Inc.
317
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x1041
PP_RDI_ALMBNBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x1042
PP_TSRDI_ALMBSRA
Remote Defect Indicator Alarm per STS-1 Bytestream A
0x1043
PP_TSRDI_ALMBSRB
Remote Defect Indicator Alarm per STS-1 Bytestream B
0x1044
PP_TSRDI_ALMBSRC
Remote Defect Indicator Alarm per STS-1 Bytestream C
0x1045
PP_TSRDI_ALMBSRD
Remote Defect Indicator Alarm per STS-1 Bytestream D
0x1046
—
0x1050
—
0x1051
PP_PLM_ALMBNBSR
0x1052
PP_TSPLM_ALMBSRA
Payload Label Mismatch Alarm per STS-1 Bytestream A
0x1053
PP_TSPLM_ALMBSRB
Payload Label Mismatch Alarm per STS-1 Bytestream B
0x1054
PP_TSPLM_ALMBSRC
Payload Label Mismatch Alarm per STS-1 Bytestream C
0x1055
PP_TSPLM_ALMBSRD
Payload Label Mismatch Alarm per STS-1 Bytestream D
0x1056
—
0x1060
—
0x1061
PP_UNEQR_ALMBNBSR
0x1062
PP_TSUNEQR_ALMBSRA
Unequipped Received Alarm per STS-1 Bytestream A
0x1063
PP_TSUNEQR_ALMBSRB
Unequipped Received Alarm per STS-1 Bytestream B
0x1064
PP_TSUNEQR_ALMBSRC
Unequipped Received Alarm per STS-1 Bytestream C
0x1065
PP_TSUNEQR_ALMBSRD
Unequipped Received Alarm per STS-1 Bytestream D
0x1066
—
0x1070
—
Bit 2
Bit 1
Bit 0
Remote Defect Indicator Alarm Binning
PP_RDI_ALMBNBS[A—D]
PP_TSRDI_ALMBSA[1—12]
PP_TSRDI_ALMBSB[1—12]
PP_TSRDI_ALMBSC[1—12]
PP_TSRDI_ALMBSD[1—12]
Payload Label Mismatch Alarm Binning
PP_PLM_ALMBNBS[A—D]
PP_TSPLM_ALMBSA[1—12]
PP_TSPLM_ALMBSB[1—12]
PP_TSPLM_ALMBSC[1—12]
PP_TSPLM_ALMBSD[1—12]
Unequipped Received Alarm Binning
PP_UNEQR_ALMBNBS[A—D)
PP_TSUNEQR_ALMBSA[1—12]
PP_TSUNEQR_ALMBSB[1—12]
PP_TSUNEQR_ALMBSC[1—12]
PP_TSUNEQR_ALMBSD[1—12]
318
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x1071
PP_AIS_ALMBNBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
0x1072
PP_TSAIS_ALMBSRA
Alarm Indicator Signal Alarm per STS-1 Bytestream A
0x1073
PP_TSAIS_ALMBSRB
Alarm Indicator Signal Alarm per STS-1 Bytestream B
0x1074
PP_TSAIS_ALMBSRC
Alarm Indicator Signal Alarm per STS-1 Bytestream C
0x1075
PP_TSAIS_ALMBSRD
Alarm Indicator Signal Alarm per STS-1 Bytestream D
0x1076
—
0x1080
—
0x1081
PP_LOP_ALMBNBSR
0x1082
PP_TSLOP_ALMBSRA
Loss of Pointer Alarm per STS-1 Bytestream A
0x1083
PP_TSLOP_ALMBSRB
Loss of Pointer Alarm per STS-1 Bytestream B
0x1084
PP_TSLOP_ALMBSRC
Loss of Pointer Alarm per STS-1 Bytestream C
0x1085
PP_TSLOP_ALMBSRD
Loss of Pointer Alarm per STS-1 Bytestream D
0x1086
—
0x1090
—
0x1091
PP_CNCTMM_ALMBNBSR
0x1092
—
0x10A0
—
0x10A1
PP_USCNCTM_ALMBNBSR
0x10A2
—
0x10C0
—
0x10C1
PP_J1NVLDMSG_ALMBNBSR
0x10C2
—
0x10D0
—
Bit 3
Bit 2
Bit 1
Bit 0
Alarm Indicator Signal Alarm Binning
PP_AIS_ALMBNBS[A—D]
PP_TSAIS_ALMBSA[1—12]
PP_TSAIS_ALMBSB[1—12]
PP_TSAIS_ALMBSC[1—12]
PP_TSAIS_ALMBSD[1—12]
Loss of Pointer Alarm Binning
PP_LOP_ALMBNBS[A—D]
PP_TSLOP_ALMBSA[1—12]
PP_TSLOP_ALMBSB[1—12]
PP_TSLOP_ALMBSC[1—12]
PP_TSLOP_ALMBSD[1—12]
Concatenation Map Mismatch Alarm Binning
PP_CNCTMM_ALMBNBS[A—D]
Unsupported Concatenation Map Alarm Binning
PP_USCNCTM_ALMBNBS[A—D]
J1 New Validated Message Alarm Binning
PP_J1NVLDMSG_ALMBNBS[A—D]
Agere Systems Inc.
319
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x10D1
PP_J1MSGMM_ALMBNBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x10D2
—
0x1100
—
0x1101
PP_PDI_ALMBNBSR
0x1102
PP_TSPDI_ALMBSRA
Payload Defect Indicator Alarm per STS-1 Bytestream A
0x1103
PP_TSPDI_ALMBSRB
Payload Defect Indicator Alarm per STS-1 Bytestream B
0x1104
PP_TSPDI_ALMBSRC
Payload Defect Indicator Alarm per STS-1 Bytestream C
0x1105
PP_TSPDI_ALMBSRD
Payload Defect Indicator Alarm per STS-1 Bytestream D
0x1106
—
0x1110
—
0x1111
PP_RDI_ALMDBNBSR
0x1112
PP_TSRDI_ALMDBSRA
Remote Defect Indicator Alarm Delta per STS-1 Bytestream A
0x1113
PP_TSRDI_ALMDBSRB
Remote Defect Indicator Alarm Delta per STS-1 Bytestream B
0x1114
PP_TSRDI_ALMDBSRC
Remote Defect Indicator Alarm Delta per STS-1 Bytestream C
0x1115
PP_TSRDI_ALMDBSRD
Remote Defect Indicator Alarm Delta per STS-1 Bytestream D
0x1116
—
0x1120
—
0x1121
PP_PLM_ALMDBNBSR
0x1122
PP_TSPLM_ALMDBSRA
Payload Label Mismatch Alarm Delta per STS-1 Bytestream A
0x1123
PP_TSPLM_ALMDBSRB
Payload Label Mismatch Alarm Delta per STS-1 Bytestream B
0x1124
PP_TSPLM_ALMDBSRC
Payload Label Mismatch Alarm Delta per STS-1 Bytestream C
0x1125
PP_TSPLM_ALMDBSRD
Payload Label Mismatch Alarm Delta per STS-1 Bytestream D
Bit 2
Bit 1
Bit 0
J1 Message Mismatch Alarm Binning
PP_J1MSGMM_ALMBNBS[A—D]
Payload Defect Indicator Alarm Binning
PP_PDI_ALMBNBS[A—D]
PP_TSPDI_ALMBSA[1—12]
PP_TSPDI_ALMBSB[1—12]
PP_TSPDI_ALMBSC[1—12]
PP_TSPDI_ALMBSD[1—12]
Remote Defect Indicator Alarm Delta Binning
PP_RDI_ALMDBNBS[A—D]
PP_TSRDI_ALMDBSA[1—12]
PP_TSRDI_ALMDBSB[1—12]
PP_TSRDI_ALMDBSC[1—12]
PP_TSRDI_ALMDBSD[1—12]
Payload Label Mismatch Alarm Delta Binning
PP_PLM_ALMDBNBS[A—D]
PP_TSPLM_ALMDBSA[1—12]
PP_TSPLM_ALMDBSB[1—12]
PP_TSPLM_ALMDBSC[1—12]
PP_TSPLM_ALMDBSD[1—12]
320
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x1126
—
0x1130
—
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
0x1131
PP_UNEQR_ALMDBNBSR
0x1132
PP_TSUNEQR_ALMDBSRA
Unequipped Received Alarm Delta per STS-1 Bytestream A
0x1133
PP_TSUNEQR_ALMDBSRB
Unequipped Received Alarm Delta per STS-1 Bytestream B
0x1134
PP_TSUNEQR_ALMDBSRC
Unequipped Received Alarm Delta per STS-1 Bytestream C
0x1135
PP_TSUNEQR_ALMDBSRD
Unequipped Received Alarm Delta per STS-1 Bytestream D
0x1136
—
0x1140
—
0x1141
PP_AIS_ALMDBNBSR
0x1142
PP_TSAIS_ALMDBSRA
Alarm Indicator Signal Alarm Delta per STS-1 Bytestream A
0x1143
PP_TSAIS_ALMDBSRB
Alarm Indicator Signal Alarm Delta per STS-1 Bytestream B
0x1144
PP_TSAIS_ALMDBSRC
Alarm Indicator Signal Alarm Delta per STS-1 Bytestream C
0x1145
PP_TSAIS_ALMDBSRD
Alarm Indicator Signal Alarm Delta per STS-1 Bytestream D
0x1146
—
0x1150
—
0x1151
PP_LOP_ALMDBNBSR
0x1152
PP_TSLOP_ALMDBSRA
Loss of Pointer Alarm Delta per STS-1 Bytestream A
0x1153
PP_TSLOP_ALMDBSRB
Loss of Pointer Alarm Delta per STS-1 Bytestream B
0x1154
PP_TSLOP_ALMDBSRC
Loss of Pointer Alarm Delta per STS-1 Bytestream C
0x1155
PP_TSLOP_ALMDBSRD
Loss of Pointer Alarm Delta per STS-1 Bytestream D
0x1156
—
0x115F
—
Bit 3
Bit 2
Bit 1
Bit 0
Unequipped Received Alarm Delta Binning
PP_UNEQR_ALMDBNBS[A—D]
PP_TSUNEQR_ALMDBSA[1—12]
PP_TSUNEQR_ALMDBSB[1—12]
PP_TSUNEQR_ALMDBSC[1—12]
PP_TSUNEQR_ALMDBSD[1—12]
Alarm Indicator Signal Alarm Delta Binning
PP_AIS_ALMDBNBS[A—D]
PP_TSAIS_ALMDBSA[1—12]
PP_TSAIS_ALMDBSB[1—12]
PP_TSAIS_ALMDBSC[1—12]
PP_TSAIS_ALMDBSD[1—12]
Loss of Pointer Alarm Delta Binning
PP_LOP_ALMDBNBS[A—D]
PP_TSLOP_ALMDBSA[1—12]
PP_TSLOP_ALMDBSB[1—12]
PP_TSLOP_ALMDBSC[1—12]
PP_TSLOP_ALMDBSD[1—12]
Agere Systems Inc.
321
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x1160
PP_PTRACCMPIR
0x1161
—
0x1170
—
0x1171
PP_PDI_ALMDBNBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PP_J1BFA
CCMPI
PDI Alarm Delta Binning
PP_PDI_ALMDBNBS[A—D]
0x1172
PP_TSPDI_ALMDBSRA
PDI Alarm Delta per STS-1 Bytestream A
0x1173
PP_TSPDI_ALMDBSRB
PDI Alarm Delta per STS-1 Bytestream B
0x1174
PP_TSPDI_ALMDBSRC
PDI Alarm Delta per STS-1 Bytestream C
0x1175
PP_TSPDI_ALMDBSRD
PDI Alarm Delta per STS-1 Bytestream D
0x1176
—
0x1177
PP_
PP_TSPDI_ALMDBSA[1—12]
PP_TSPDI_ALMDBSB[1—12]
PP_TSPDI_ALMDBSC[1—12]
PP_TSPDI_ALMDBSD[1—12]
0x1178
—
0x1179
PP_
0x117A
—
0x117B
PP_
0x117C
—
0x117D
PP_
0x117E
—
0x117F
PP_
0x1180
—
0x1181
PP_
STS-1 #12 Channel Path Alarms Binning
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STS-1 Channel Path Alarms
—
—
—
—
0x1182
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1183
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1184
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1185
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1186
—
0x1187
PP_
STS-1 Channel Path Alarms
—
—
—
—
0x1188
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1189
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x118A
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x118B
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x118C
—
0x120E
—
322
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
PP_PDI_A
LMDBNM
PP_PDI_A
LMBNM
PP_
J1ACCMP_
ALMBNM
PP_
J1VLD_
ALMBNM
PP_
USCNCT_
ALMBNM
PP_
CNCTMM_
ALMBNM
PP_ES_
ALMBNM
PP_SF_
ALMBNM
PP_RDI_
ALMBNM
PP_PLM_A
LMBNM
PP_
UNEQR_
ALMBNM
PP_AIS_
ALMBNM
PP_LOP_
ALMBNM
Masks
0x120F
PP_POH_ALMBNMR1
0x1210
PP_POH_ALMBNMR2
0x1211
PP_ES_ALMBNMBSR
0x1212
PP_TSES_ALMMBSRA
Elastic Store Overrun/Underrun Alarm Mask per STS-1 Bytestream A
0x1213
PP_TSES_ALMMBSRB
Elastic Store Overrun/Underrun Alarm Mask per STS-1 Bytestream B
0x1214
PP_TSES_ALMMBSRC
Elastic Store Overrun/Underrun Alarm Mask per STS-1 Bytestream C
0x1215
PP_TSES_ALMMBSRD
Elastic Store Overrun/Underrun Alarm Mask per STS-1 Bytestream D
0x1216
—
0x1220
—
0x1221
PP_SF_ALMBNMBSR
0x1222
PP_TSSF_ALMMBSRA
Signal Fail Alarm Mask per STS-1 Bytestream A
0x1223
PP_TSSF_ALMMBSRB
Signal Fail Alarm Mask per STS-1 Bytestream B
0x1224
PP_TSSF_ALMMBSRC
Signal Fail Alarm Mask per STS-1 Bytestream C
0x1225
PP_TSSF_ALMMBSRD
Signal FAil Alarm Mask per STS-1 Bytestream D
0x1226
—
0x1230
—
0x1231
PP_RDI_ALMBNMBSR
0x1232
PP_TSRDI_ALMMBSRA
Remote Defect Indicator Alarm Mask per STS-1 Bytestream A
0x1233
PP_TSRDI_ALMMBSRB
Remote Defect Indicator Alarm Mask per STS-1 Bytestream B
0x1234
PP_TSRDI_ALMMBSRC
Remote Defect Indicator Alarm Mask per STS-1 Bytestream C
PP_RDI_A PP_PLM_A
LMDBNM LMDBNM
PP_
PP_AIS_
PP_LOP_ PP_J1MM_
UNEQR_ ALMDBNM ALMDBNM ALMBNM
ALMDBNM
Elastic Store Overrun/Underrun Alarm Binning Mask
PP_ES_ALMBNMBS[A—D]
PP_TSES_ALMMBSA[1—12]
PP_TSES_ALMMBSB[1—12]
PP_TSES_ALMMBSC[1—12]
PP_TSES_ALMMBSD[1—12]
Signal Fail Alarm Binning Mask
PP_SF_ALMBNMBS[A—D]
PP_TSSF_ALMMBSA[1—12]
PP_TSSF_ALMMBSB[1—12]
PP_TSSF_ALMMBSC[1—12]
PP_TSSF_ALMMBSD[1—12]
Remote Defect Indicator Alarm Binning Mask
PP_RDI_ALMBNMBS[A—D]
PP_TSRDI_ALMMBSA[1—12]
PP_TSRDI_ALMMBSB[1—12]
PP_TSRDI_ALMMBSC[1—12]
Agere Systems Inc.
323
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
0x1235
PP_TSRDI_ALMMBSRD
0x1236
—
0x1240
—
0x1241
PP_PLM_ALMBNMBSR
0x1242
PP_TSPLM_ALMMBSRA
Payload Label Mismatch Alarm Mask per STS-1 Bytestream A
0x1243
PP_TSPLM_ALMMBSRB
Payload Label Mismatch Alarm Mask per STS-1 Bytestream B
0x1244
PP_TSPLM_ALMMBSRC
Payload Label Mismatch Alarm Mask per STS-1 Bytestream C
0x1245
PP_TSPLM_ALMMBSRD
Payload Label Mismatch Alarm Mask per STS-1 Bytestream D
0x1246
—
0x1250
—
0x1251
PP_UNEQR_ALMBNMBSR
0x1252
PP_TSUNEQR_ALMMBSRA
Unequipped Received Alarm Mask per STS-1 Bytestream A
0x1253
PP_TSUNEQR_ALMMBSB
Unequipped Received Alarm Mask per STS-1 Bytestream B
0x1254
PP_TSUNEQR_ALMMBSC
Unequipped Received Alarm Mask per STS-1 Bytestream C
0x1255
PP_TSUNEQR_ALMMBSD
Unequipped Received Alarm Mask per STS-1 Bytestream D
0x1256
—
0x1260
—
0x1261
PP_AIS_ALMBNMBSR
0x1262
PP_TSAIS_ALMMBSRA
Alarm Indicator Signal Alarm Mask per STS-1 Bytestream A
0x1263
PP_TSAIS_ALMMBSRB
Alarm Indicator Signal Alarm Mask per STS-1 Bytestream B
0x1264
PP_TSAIS_ALMMBSRC
Alarm Indicator Signal Alarm Mask per STS-1 Bytestream C
0x1265
PP_TSAIS_ALMMBSRD
Alarm Indicator Signal Alarm Mask per STS-1 Bytestream D
2
1
0
Remote Defect Indicator Alarm Mask per STS-1 Bytestream D
PP_TSRDI_ALMMBSD[1—12]
Payload Label Mismatch Alarm Binning Mask
PP_PLM_ALMBNMBS[A—D]
PP_TSPLM_ALMMBSA[1—12]
PP_TSPLM_ALMMBSB[1—12]
PP_TSPLM_ALMMBSC[1—12]
PP_TSPLM_ALMMBSD[1—12]
Unequipped Received Alarm Binning Mask
PP_UNEQR_ALMBNMBS[A—D]
PP_TSUNEQR_ALMMBSA[1—12]
PP_TSUNEQR_ALMMBSB[1—12]
PP_TSUNEQR_ALMMBSC[1—12]
PP_TSUNEQR_ALMMBSD[1—12]
Alarm Indicator Signal Alarm Binning Mask
PP_AIS_ALMBNMBS[A—D]
PP_TSAIS_ALMMBSA[1—12]
PP_TSAIS_ALMMBSB[1—12]
PP_TSAIS_ALMMBSC[1—12]
PP_TSAIS_ALMMBSD[1—12]
324
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
0x1266
—
0x1270
—
0x1271
PP_LOP_ALMBNMBSR
0x1272
PP_TSLOP_ALMMBSRA
Loss of Pointer Alarm Mask per STS-1 Bytestream A
0x1273
PP_TSLOP_ALMMBSRB
Loss of Pointer Alarm Mask per STS-1 Bytestream B
0x1274
PP_TSLOP_ALMMBSRC
Loss of Pointer Alarm Mask per STS-1 Bytestream C
0x1275
PP_TSLOP_ALMMBSRD
Loss of Pointer Alarm Mask per STS-1 Bytestream D
0x1276
—
0x1277
PP_CNCTMM_ALMMBSR
0x1278
—
0x1279
PP_USCNCTM_ALMMBSR
0x127A
—
0x127B
PP_J1NVLDMSG_ALMMBSR
0x127C
—
0x127D
PP_J1MSGMM_ALMMBSR
0x127E
—
0x1280
—
0x1281
PP_PDI_ALMBNMBSR
0x1282
PP_TSPDI_ALMMBSRA
Payload Defect Indicator Alarm Mask per STS-1 Bytestream A
0x1283
PP_TSPDI_ALMMBSRB
Payload Defect Indicator Alarm Mask per STS-1 Bytestream B
0x1284
PP_TSPDI_ALMMBSRC
Payload Defect Indicator Alarm Mask per STS-1 Bytestream C
0x1285
PP_TSPDI_ALMMBSRD
Payload Defect Indicator Alarm Mask per STS-1 Bytestream D
2
1
0
Loss of Pointer Alarm Binning Mask
PP_LOP_ALMBNMBS[A—D]
PP_TSLOP_ALMMBSA[1—12]
PP_TSLOP_ALMMBSB[1—12]
PP_TSLOP_ALMMBSC[1—12]
PP_TSLOP_ALMMBSD[1—12]
Concatenation Map Mismatch Alarm Mask
PP_CNCTMM_ALMMBS[A—D]
Unsupported Concatenation Map Alarm Mask
PP_USCNCTM_ALMMBS[A—D]
J1 New Validated Message Alarm Mask
PP_J1NVLDMSG_ALMMBS[A—D]
J1 Message Mismatch Alarm Mask
PP_J1MSGMM_ALMMBS[A—D]
Payload Defect Indicator Alarm Binning Mask
PP_PDI_ALMBNMBS[A—D]
PP_TSPDI_ALMMBSA[1—12]
PP_TSPDI_ALMMBSB[1—12]
PP_TSPDI_ALMMBSC[1—12]
PP_TSPDI_ALMMBSD[1—12]
Agere Systems Inc.
325
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
0x1286
—
0x1290
—
0x1291
PP_RDI_ALMDBNMBSR
0x1292
PP_TSRDI_ALMDMBSRA
Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream A
0x1293
PP_TSRDI_ALMDMBSRB
Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream B
0x1294
PP_TSRDI_ALMDMBSRC
Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream C
0x1295
PP_TSRDI_ALMDMBSRD
Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream D
0x1296
—
0x12A0
—
0x12A1
PP_PLM_ALMDBNMBSR
0x12A2
PP_TSPLM_ALMDMBSRA
Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream A
0x12A3
PP_TSPLM_ALMDMBSRB
Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream B
0x12A4
PP_TSPLM_ALMDMBSRC
Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream C
0x12A5
PP_TSPLM_ALMDMBSRD
Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream D
0x12A6
—0x12B
—
0x12B1
PP_UNEQR_ALMDBNMBSR
0x12B2
PP_TSUNEQR_ALMDMBSRA
Unequipped Received Alarm Delta Mask per STS-1 Bytestream A
0x12B3
PP_TSUNEQR_ALMDMBSRB
Unequipped Received Alarm Delta Mask per STS-1 Bytestream B
0x12B4
PP_TSUNEQR_ALMDMBSRC
Unequipped Received Alarm Delta Mask per STS-1 Bytestream C
0x12B5
PP_TSUNEQR_ALMDMBSRD
Unequipped Received Alarm Delta Mask per STS-1 Bytestream D
0x12B6
—
0x12C0
—
2
1
0
Remote Defect Indicator Alarm Delta Binning Mask
PP_RDI_ALMDBNMBS[A—D]
PP_TSRDI_ALMDMBSA[1—12]
PP_TSRDI_ALMDMBSB[1—12]
PP_TSRDI_ALMDMBSC[1—12]
PP_TSRDI_ALMDMBSD[1—12]
Payload Label Mismatch Alarm Delta Binning Mask
PP_PLM_ALMDBNMBS[A—D]
PP_TSPLM_ALMDMBSA[1—12]
PP_TSPLM_ALMDMBSB[1—12]
PP_TSPLM_ALMDMBSC[1—12]
PP_TSPLM_ALMDMBSD[1—12]
Unequipped Received Alarm Delta Binning Mask
PP_UNEQR_ALMDBNMBS[A—D]
PP_TSUNEQR_ALMDMBSA[1—12]
PP_TSUNEQR_ALMDMBSB[1—12]
PP_TSUNEQR_ALMDMBSC[1—12]
PP_TSUNEQR_ALMDMBSD[1—12]
326
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0x12C1
PP_AIS_ALMDBNMBSR
0x12C2
PP_TSAIS_ALMDMBSRA
Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream A
0x12C3
PP_TSAIS_ALMDMBSRB
Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream B
0x12C4
PP_TSAIS_ALMDMBSRC
Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream C
0x12C5
PP_TSAIS_ALMDMBSRD
Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream D
0x12C6
—
0x12D0
—
0x12D1
PP_LOP_ALMDBNMBSR
0x12D2
PP_TSLOP_ALMDMBSRA
Loss of Pointer Alarm Delta Mask per STS-1 Bytestream A
0x12D3
PP_TSLOP_ALMDMBSRB
Loss of Pointer Alarm Delta Mask per STS-1 Bytestream B
0x12D4
PP_TSLOP_ALMDMBSRC
Loss of Pointer Alarm Delta Mask per STS-1 Bytestream C
0x12D5
PP_TSLOP_ALMDMBSRD
Loss of Pointer Alarm Delta Mask per STS-1 Bytestream D
0x12D6
—
0x12DF
—
0x12E0
PP_PTRACCMPIR
0x12E1
—
0x12E2
PP_
1
0
Alarm Indicator Signal Alarm Delta Binning Mask
PP_AIS_ALMDBNMBS[A—D]
PP_TSAIS_ALMDMBSA[1—12]
PP_TSAIS_ALMDMBSB[1—12]
PP_TSAIS_ALMDMBSC[1—12]
PP_TSAIS_ALMDMBSD[1—12]
Loss of Pointer Alarm Delta Binning Mask
PP_LOP_ALMDBNMBS[A—D]
PP_TSLOP_ALMDMBSA[1—12]
PP_TSLOP_ALMDMBSB[1—12]
PP_TSLOP_ALMDMBSC[1—12]
PP_TSLOP_ALMDMBSD[1—12]
PP_J1BFACCMPIM
STS-1 Channel Path Alarm Masks
—
—
—
0x12E3
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x12E4
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x12E5
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x12E6
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x12E7
—
0x12E8
—
Agere Systems Inc.
—
327
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
0x12E9
PP_PDI_ALMDBNMBSR
0x12EA
PP_TSPDI_ALMDMBSRA
PDI Alarm Delta Mask per STS-1 Bytestream A
0x12EB
PP_TSPDI_ALMDMBSRB
PDI Alarm Delta Mask per STS-1 Bytestream B
0x12EC
PP_TSPDI_ALMDMBSRC
PDI Alarm Delta Mask per STS-1 Bytestream C
0x12ED
PP_TSPDI_ALMDMBSRD
PDI Alarm Delta Mask per STS-1 Bytestream D
0x12EE
—
0x12EF
PP_
3
2
1
0
PDI Alarm Delta Binning Mask
PP_PDI_ALMDBNMBS[A—D]
PP_TSPDI_ALMDMBSA[1—12]
PP_TSPDI_ALMDMBSB[1—12]
PP_TSPDI_ALMDMBSC[1—12]
PP_TSPDI_ALMDMBSD[1—12]
0x12F0
—
0x12F1
PP_
0x12F2
—
0x12F3
PP_
0x12F4
—
0x12F5
PP_
0x12F6
—
0x12F7
PP_
0x12F8
—
0x12F9
PP_
STS-1 #12 Channel Path Alarm Masks
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STS-1 Channel Path Alarm Masks
—
—
—
0x12FA
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x12FB
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x12FC
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x12FD
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x12FE
—
0x12FF
—
328
—
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Path Trace
—
—
J1 Byte 1, 3, 5, . . . , 63 Path Trace Buffer
J1 Byte 0, 2, 4, . . . , 62 Path Trace Buffer
0x1300
—
0x131F
PP_PTRBFR[1—32]
PP_J1BYTE[1, 3, 5, . . . , 63][7:0]
PP_J1BYTE[0, 2, 4, . . . , 62][7:0]
0x1330
PP_PTRACCTLR1
PP_J1TS1_CHSEL[1:0]
0x1331
PP_PTRACCTLR2
PP_J1BF_
MSGSEL
0x1332
PP_PTRACCTLR3
PP_J1BF_
ACTYP
0x1333
PP_PTRACBGR
PP_J1_
ACBG
0x1334
—
0x1337
—
0x1338
PP_STS12PTRCTLR1
J1 Message Mode Select
PP_J1MSG_MSEL[A—D]
0x1339
PP_STS12PTRCTLR2
J1 Message Type Select
PP_J1MSG_TYPSEL[A—D]
0x133A
—
0x133B
—
0x133C
PP_STS12PTRCTLR3
Time Slots 1—12 Select for J1 Accumulation
PP_TSSEL_J1A[3:0]
0x133D
PP_STS12PTRCTLR4
PP_TSSEL_J1B[3:0]
0x133E
PP_STS12PTRCTLR5
PP_TSSEL_J1C[3:0]
0x133F
PP_STS12PTRCTLR6
PP_TSSEL_J1D[3:0]
0x1340
—
0x1341
PP_
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1342
PP_
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1343
PP_
—
—
—
—
—
—
—
—
0x1344
—
0x1345
PP_
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1346
PP_
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1347
PP_
—
—
—
—
—
—
—
—
0x1348
—
F2 Validation Period
H4/Z3/Z4 Validation Period
F2 Validation Period
Z5 Validation Period
H4/Z3/Z4 Validation Period
STS-1 Channel Select for F2/H4/Zi Bytes Monitoring
Z5 Validation Period
STS-1 Channel Select for F2/H4/Zi Bytes Monitoring
0x1349
PP_
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x134A
PP_
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x134B
PP_
—
—
—
—
—
—
—
—
0x134C
—
Agere Systems Inc.
F2 Validation Period
H4/Z3/Z4 Validation Period
Z5 Validation Period
STS-1 Channel Select for F2/H4/Zi Bytes Monitoring
329
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
0x134D
PP_
—
—
—
—
—
—
—
—
0x134E
PP_
—
—
—
—
—
—
—
—
0x134F
PP_
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1350
—
0x1351
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1352
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1353
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1354
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1355
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1356
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1357
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1358
PP_
—
—
—
—
—
—
—
—
—
—
—
—
0x1359
—
0x137F
—
330
F2 Validation Period
—
—
H4/Z3/Z4 Validation Period
Z5 Validation Period
STS-1 Channel Select for F2/H4/Zi Bytes Monitoring
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Persistency
0x1380
—
0x1381
—
0x1382
PP_TSRDI_ALMPSBSRA
RDI Alarm Persistency per STS-1 Bytestream A
0x1383
PP_TSRDI_ALMPSBSRB
RDI Alarm Persistency per STS-1 Bytestream B
0x1384
PP_TSRDI_ALMPSBSRC
RDI Alarm Persistency per STS-1 Bytestream C
0x1385
PP_TSRDI_ALMPSBSRD
RDI Alarm Persistency per STS-1 Bytestream D
0x1386
—
0x1389
—
0x138A
PP_TSPLM_ALMPSBSRA
Payload Label Mismatch Alarm Persistency per STS-1 Bytestream A
0x138B
PP_TSPLM_ALMPSBSRB
Payload Label Mismatch Alarm Persistency per STS-1 Bytestream B
0x138C
PP_TSPLM_ALMPSBSRC
Payload Label Mismatch Alarm Persistency per STS-1 Bytestream C
0x138D
PP_TSPLM_ALMPSBSRD
Payload Label Mismatch Alarm Persistency per STS-1 Bytestream D
0x138E
—
0x1391
—
0x1392
PP_TSPUNEQ_ALMPSBSRA
Path Unequipped Alarm Persistency per STS-1 Bytestream A
0x1393
PP_TSPUNEQ_ALMPSBSRB
Path Unequipped Alarm Persistency per STS-1 Bytestream B
0x1394
PP_TSPUNEQ_ALMPSBSRC
Path Unequipped Alarm Persistency per STS-1 Bytestream C
0x1395
PP_TSPUNEQ_ALMPSBSRD
Path Unequipped Alarm Persistency per STS-1 Bytestream D
0x1396
—
0x1399
—
PP_TSRDI_ALMPSBSA[1—12]
PP_TSRDI_ALMPSBSB[1—12]
PP_TSRDI_ALMPSBSC[1—12]
PP_TSRDI_ALMPSBSD[1—12]
PP_TSPLM_ALMPSBSA[1—12]
PP_TSPLM_ALMPSBSB[1—12]
PP_TSPLM_ALMPSBSC[1—12]
PP_TSPLM_ALMPSBSD[1—12]
PP_TSPUNEQ_ALMPSBSA[1—12]
PP_TSPUNEQ_ALMPSBSB[1—12]
PP_TSPUNEQ_ALMPSBSC[1—12]
PP_TSPUNEQ_ALMPSBSD[1—12]
Agere Systems Inc.
331
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
0x139A
PP_TSAIS_ALMPSBSRA
AIS Alarm Persistency per STS-1 Bytestream A
0x139B
PP_TSAIS_ALMPSBSRB
AIS Alarm Persistency per STS-1 Bytestream B
0x139C
PP_TSAIS_ALMPSBSRC
AIS Alarm Persistency per STS-1 Bytestream C
0x139D
PP_TSAIS_ALMPSBSRD
AIS Alarm Persistency per STS-1 Bytestream D
0x139E
—
0x13A1
—
0x13A2
PP_TSLOP_ALMPSBSRA
LOP Alarm Persistency per STS-1 Bytestream A
0x13A3
PP_TSLOP_ALMPSBSRB
LOP Alarm Persistency per STS-1 Bytestream B
0x13A4
PP_TSLOP_ALMPSBSRC
LOP Alarm Persistency per STS-1 Bytestream C
0x13A5
PP_TSLOP_ALMPSBSRD
LOP Alarm Persistency per STS-1 Bytestream D
0x13A6
—
0x13A9
—
0x13AA
PP_TSPDI_ALMPSBSRA
PDI Alarm Persistency per STS-1 Bytestream A
0x13AB
PP_TSPDI_ALMPSBSRB
PDI Alarm Persistency per STS-1 Bytestream B
0x13AC
PP_TSPDI_ALMPSBSRC
PDI Alarm Persistency per STS-1 Bytestream C
0x13AD
PP_TSPDI_ALMPSBSRD
PDI Alarm Persistency per STS-1 Bytestream D
0x13AE
—
0x13BF
—
3
2
1
PP_TSAIS_ALMPSBSA[1—12]
PP_TSAIS_ALMPSBSB[1—12]
PP_TSAIS_ALMPSBSC[1—12]
PP_TSAIS_ALMPSBSD[1—12]
PP_TSLOP_ALMPSBSA[1—12]
PP_TSLOP_ALMPSBSB[1—12]
PP_TSLOP_ALMPSBSC[1—12]
PP_TSLOP_ALMPSBSD[1—12]
PP_TSPDI_ALMPSBSA[1—12]
PP_TSPDI_ALMPSBSB[1—12]
PP_TSPDI_ALMPSBSC[1—12]
PP_TSPDI_ALMPSBSD[1—12]
332
Agere Systems Inc.
0
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
State
0x13C0
—
0x13C1
—
0x13C2
PP_TSRDI_STBSRA
RDI State per STS-1 Bytestream A
0x13C3
PP_TSRDI_STBSRB
RDI State per STS-1 Bytestream B
0x13C4
PP_TSRDI_STBSRC
RDI State per STS-1 Bytestream C
0x13C5
PP_TSRDI_STBSRD
RDI State per STS-1 Bytestream D
0x13C6
—
0x13C9
—
0x13CA
PP_TSPLM_STBSRA
Payload Label Mismatch State per STS-1 Bytestream A
0x13CB
PP_TSPLM_STBSRB
Payload Label Mismatch State per STS-1 Bytestream B
0x13CC
PP_TSPLM_STBSRC
Payload Label Mismatch State per STS-1 Bytestream C
0x13CD
PP_TSPLM_STBSRD
Payload Label Mismatch State per STS-1 Bytestream D
0x13CE
—
0x13D1
—
0x13D2
PP_TSPUNEQ_STBSRA
Path Unequipped State per STS-1 Bytestream A
0x13D3
PP_TSPUNEQ_STBSRB
Path Unequipped State per STS-1 Bytestream B
0x13D4
PP_TSPUNEQ_STBSRC
Path Unequipped State per STS-1 Bytestream C
0x13D5
PP_TSPUNEQ_STBSRD
Path Unequipped State per STS-1 Bytestream D
0x13D6
—
0x13D9
—
PP_TSRDI_STBSA[1—12]
PP_TSRDI_STBSB[1—12]
PP_TSRDI_STBSC[1—12]
PP_TSRDI_STBSD[1—12]
PP_TSPLM_STBSA[1—12]
PP_TSPLM_STBSB[1—12]
PP_TSPLM_STBSC[1—12]
PP_TSPLM_STBSD[1—12]
PP_TSPUNEQ_STBSA[1—12]
PP_TSPUNEQ_STBSB[1—12]
PP_TSPUNEQ_STBSC[1—12]
PP_TSPUNEQ_STBSD[1—12]
Agere Systems Inc.
333
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
0x13DA
PP_TSAIS_STBSRA
AIS State per STS-1 Bytestream A
0x13DB
PP_TSAIS_STBSRB
AIS State per STS-1 Bytestream B
0x13DC
PP_TSAIS_STBSRC
AIS State per STS-1 Bytestream C
0x13DD
PP_TSAIS_STBSRD
AIS State per STS-1 Bytestream D
0x13DE
—
0x13E1
—
0x13E2
PP_TSLOP_STBSRA
LOP State per STS-1 Bytestream A
0x13E3
PP_TSLOP_STBSRB
LOP State per STS-1 Bytestream B
0x13E4
PP_TSLOP_STBSRC
LOP State per STS-1 Bytestream C
0x13E5
PP_TSLOP_STBSRD
LOP State per STS-1 Bytestream D
0x13E6
—
0x13E9
—
0x13EA
PP_TSPDI_STBSRA
PDI State per STS-1 Bytestream A
0x13EB
PP_TSPDI_STBSRB
PDI State per STS-1 Bytestream B
0x13EC
PP_TSPDI_STBSRC
PDI State per STS-1 Bytestream C
0x13ED
PP_TSPDI_STBSRD
LOP State per STS-1 Bytestream D
0x13EE
—
0x13FF
—
4
3
2
1
PP_TSAIS_STBSA[1—12]
PP_TSAIS_STBSB[1—12]
PP_TSAIS_STBSC[1—12]
PP_TSAIS_STBSD[1—12]
PP_TSLOP_STBSA[1—12]
PP_TSLOP_STBSB[1—12]
PP_TSLOP_STBSC[1—12]
PP_TSLOP_STBSD[1—12]
PP_TSPDI_STBSA[1—12]
PP_TSPDI_STBSB[1—12]
PP_TSPDI_STBSC[1—12]
PP_TSPDI_STBSD[1—12]
334
Agere Systems Inc.
0
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Signal Fail
0x1400
PP_SFWSZ_SELR1
PP_SFWSZ_SELSET[0—7][1:0]
0x1401
PP_SFWSZ_SELR2
PP_SFWSZ_SELCLR[0—7][1:0]
0x1402
—
0x140F
—
0x1410
PP_SFDR0
0x1411
PP_SFDR1
PP_SFD0[8:0]
0x1412
PP_SFDR2
PP_SFD2[13:0]
0x1413
PP_SFDR3
PP_SFD3[13:0]
0x1414
PP_SFDR4
PP_SFD4[13:0]
0x1415
PP_SFDR5
PP_SFD5[13:0]
0x1416
PP_SFDR6
PP_SFD6[13:0]
0x1417
PP_SFDR7
PP_SFD7[13:0]
0x1418
PP_SFCLRR0
0x1419
PP_SFCLRR1
0x141A
PP_SFCLRR2
PP_SFCLR2[13:0]
PP_SFD1[8:0]
PP_SFCLR0[8:0]
PP_SFCLR1[8:0]
0x141B
PP_SFCLRR3
PP_SFCLR3[13:0]
0x141C
PP_SFCLRR4
PP_SFCLR4[13:0]
0x141D
PP_SFCLRR5
PP_SFCLR5[13:0]
0x141E
PP_SFCLRR6
PP_SFCLR6[13:0]
0x141F
PP_SFCLRR7
0x1420
PP_SFWSZR0
0x1421
—
0x142F
—
0x1430
PP_SFWSZR1
0x1431
—
0x143F
—
0x1440
PP_SFWSZR2
0x1441
—
0x144F
—
0x1450
PP_SFWSZR3
0x1451
—
0x1501
—
Agere Systems Inc.
PP_SFCLR7[13:0]
PP_SFWSZ0[15:0]
PP_SFWSZ1[15:0]
PP_SFWSZ2[15:0]
PP_SFWSZ3[15:0]
335
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Concatenation
0x1502
PP_ECNCTM_TSBSRA
Expected Concatenation Map Bytestream A
0x1503
PP_ECNCTM_TSBSRB
Expected Concatenation Map Bytestream B
0x1504
PP_ECNCTM_TSBSRC
Expected Concatenation Map Bytestream C
0x1505
PP_ECNCTM_TSBSRD
Expected Concatenation Map Bytestream D
0x1506
—
0x1507
PP_CNCTCPREN_TSBSRA
Software Concatenation Compare Enable Bytestream A
0x1508
PP_CNCTCPREN_TSBSRB
Software Concatenation Compare Enable Bytestream B
0x1509
PP_CNCTCPREN_TSBSRC
Software Concatenation Compare Enable Bytestream C
0x150A
PP_CNCTCPREN_TSBSRD
Software Concatenation Compare Enable Bytestream D
0x150B
—
0x1511
—
0x1512
PP_RCNCTM_TSBSRA
Received Concatenation Map Bytestream A
0x1513
PP_RCNCTM_TSBSRB
Received Concatenation Map Bytestream B
0x1514
PP_RCNCTM_TSBSRC
Received Concatenation Map Bytestream C
0x1515
PP_RCNCTM_TSBSRD
Received Concatenation Map Bytestream D
0x1516
—
0x1541
—
PP_ECNCT_STTSBSA[1—12]
PP_ECNCT_STTSBSB[1—12]
PP_ECNCT_STTSBSC[1—12]
PP_ECNCT_STTSBSD[1—12]
PP_CNCTCPREN_TSBSA[1—12]
PP_CNCTCPREN_TSBSB[1—12]
PP_CNCTCPREN_TSBSC[1—12]
PP_CNCTCPREN_TSBSD[1—12]
PP_RCNCT_STTSBSA[1—12]
PP_RCNCT_STTSBSB[1—12]
PP_RCNCT_STTSBSC[1—12]
PP_RCNCT_STTSBSD[1—12]
336
Agere Systems Inc.
0
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AIS Insert Control
0x1542
PP_SWAIS_ISRTRA
AIS Insert Bytestream A
PP_SWAIS_ISRTA[1—12]
0x1543
PP_SWAIS_ISRTRB
AIS Insert Bytestream B
PP_SWAIS_ISRTB[1—12]
0x1544
AIS Insert Bytestream C
PP_SWAIS_ISRTRC
PP_SWAIS_ISRTC[1—12]
0x1545
PP_SWAIS_ISRTRD
AIS Insert Bytestream D
PP_SWAIS_ISRTD[1—12]
0x1546
—
0x157F
—
0x1580
PP_STS12_PINCDECR
0x1581
—
0x1582
PP_TSSS_ISRTBSRA
SS Bits Insert Control Bytestream A
0x1583
PP_TSSS_ISRTBSRB
SS Bits Insert Control Bytestream B
0x1584
PP_TSSS_ISRTBSRC
SS Bits Insert Control Bytestream C
0x1585
PP_TSSS_ISRTBSRD
SS Bits Insert Control Bytestream D
0x1586
—
0x1587
PP_TSE1F1_ISRTBSRA
E1/F1 Insert Control Bytestream A
0x1588
PP_TSE1F1_ISRTBSRB
E1/F1 Insert Control Bytestream B
0x1589
PP_TSE1F1_ISRTBSRC
E1/F1 Insert Control Bytestream C
0x158A
PP_TSE1F1_ISRTBSRD
E1/F1 Insert Control Bytestream D
0x158B
—
Pointer Processor Control
SONET/SDH Pointer Inc/Dec Rules
PP_PINCDEC[A—D]
PP_TSSS_ISRTBSA[1—12]
PP_TSSS_ISRTBSB[1—12]
PP_TSSS_ISRTBSC[1—12]
PP_TSSS_ISRTBSD[1—12]
PP_TSE1F1_ISRTBSA[1—12]
PP_TSE1F1_ISRTBSB[1—12]
PP_TSE1F1_ISRTBSC[1—12]
PP_TSE1F1_ISRTBSD[1—12]
Agere Systems Inc.
337
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x158C
PP_E2_ISRTCTLRA
PP_E2_IS
RTCTLA
0x158D
PP_E2_ISRTCTLRB
PP_E2_IS
RTCTLB
0x158E
PP_E2_ISRTCTLRC
PP_E2_IS
RTCTLC
0x158F
PP_E2_ISRTCTLRD
PP_E2_IS
RTCTLD
0x1590
PP_TS_INCDECBNRA
STS-1 Inc/Dec Binning Select Bytestream A
PP_TS_INCDECBNA[3:0]
0x1591
PP_TS_INCDECBNRB
STS-1 Inc/Dec Binning Select Bytestream B
PP_TS_INCDECBNB[3:0]
0x1592
PP_TS_INCDECBNRC
STS-1 Inc/Dec Binning Select Bytestream C
PP_TS_INCDECBNC[3:0]
0x1593
PP_TS_INCDECBNRD
STS-1 Inc/Dec Binning Select Bytestream D
PP_TS_INCDECBND[3:0]
0x1594
PP_AISONTIM_ISRTRA
0x1595
PP_AISONTIM_ISRTRB
TIM Insert Control Bytestream B
0x1596
PP_AISONTIM_ISRTRC
TIM Insert Control Bytestream C
0x1597
PP_AISONTIM_ISRTRD
0x1598
—
0x15A1
—
0x15A2
PP_TSPDIVLD_CTLBSRA
PDI Validate Control Bytestream A
0x15A3
PP_TSPDIVLD_CTLBSRB
PDI Validate Control Bytestream B
0x15A4
PP_TSPDIVLD_CTLBSRC
PDI Validate Control Bytestream C
0x15A5
PP_TSPDIVLD_CTLBSRD
PDI Validate Control Bytestream D
0x15A6
—
0x15FF
—
TIM Insert Control Bytestream A
PP_AISONTIM_ISRT_ A[1—12]
PP_ AISONTIM_ISRT_B[1—12]
PP_ AISONTIM_ISRT_C[1—12]
TIM Insert Control Bytestream D
PP_ AISONTIM_ISRT_D[1—12]
PP_TSPDIVLD_CTLBSA[1—12]
PP_TSPDIVLD_CTLBSB[1—12]
PP_TSPDIVLD_CTLBSC[1—12]
PP_TSPDIVLD_CTLBSD[1—12]
338
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Provisioning
—
—
Time Slots 1, 3, 5, . . ., 47 Expected C2 Bytes
Time Slot 2, 4, 6, . . ., 48 Expected C2 Bytes
0x1600
—
0x1617
PP_EXPC2_PVSNR[1—24]
PP_EXPC2[1, 3, 5, . . ., 47][7:0]
PP_EXPCP[2, 4, 6, . . ., 48][7:0]
0x1618
PP_TSCBB_ERRBSRA
Count Bit/Block Errors Bytestream A
0x1619
PP_TSCBB_ERRBSRB
Count Bit/Block Errors Bytestream B
0x161A
PP_TSCBB_ERRBSRC
Count Bit/Block Errors Bytestream C
0x161B
PP_TSCBB_ERRBSRD
Count Bit/Block Errors Bytestream D
0x161C
—
0x161F
—
0x1620
PP_TS1_6_SSBSRA
PP_TSCBB_ERRBSA[1—12]
PP_TSCBB_ERRBSB[1—12]
PP_TSCBB_ERRBSC[1—12]
PP_TSCBB_ERRBSD[1—12]
0x1621
PP_TS7_12_SSBSRA
0x1622
PP_TS1_6_SSBSRB
0x1623
PP_TS7_12_SSBSRB
0x1624
PP_TS1_6_SSBSRC
0x1625
PP_TS7_12_SSBSRC
0x1626
PP_TS1_6_SSBSRD
0x1627
PP_TS7_12_SSBSRD
SS Bits Setting Bytestream A
PP_TS_SSA1[1:0]
PP_TS_SSA2[1:0]
PP_TS_SSA3[1:0]
PP_TS_SSA4[1:0]
PP_TS_SSA5[1:0]
PP_TS_SSA6[1:0]
PP_TS_SSA7[1:0]
PP_TS_SSA8[1:0]
PP_TS_SSA9[1:0]
PP_TS_SSA10[1:0]
PP_TS_SSA11[1:0]
PP_TS_SSA12[1:0]
PP_TS_SSB1[1:0]
PP_TS_SSB2[1:0]
PP_TS_SSB3[1:0]
PP_TS_SSB4[1:0]
PP_TS_SSB5[1:0]
PP_TS_SSB6[1:0]
PP_TS_SSB7[1:0]
PP_TS_SSB8[1:0]
PP_TS_SSB9[1:0]
PP_TS_SSB10[1:0]
PP_TS_SSB11[1:0]
PP_TS_SSB12[1:0]
PP_TS_SSC1[1:0]
PP_TS_SSC2[1:0]
PP_TS_SSC3[1:0]
PP_TS_SSC4[1:0]
PP_TS_SSC5[1:0]
PP_TS_SSC6[1:0]
PP_TS_SSC7[1:0]
PP_TS_SSC8[1:0]
PP_TS_SSC9[1:0]
PP_TS_SSC10[1:0]
PP_TS_SSC11[1:0]
PP_TS_SSC12[1:0]
PP_TS_SSD1[1:0]
PP_TS_SSD2[1:0]
PP_TS_SSD3[1:0]
PP_TS_SSD4[1:0]
PP_TS_SSD5[1:0]
PP_TS_SSD6[1:0]
PP_TS_SSD7[1:0]
PP_TS_SSD8[1:0]
PP_TS_SSD9[1:0]
PP_TS_SSD10[1:0]
PP_TS_SSD11[1:0]
PP_TS_SSD12[1:0]
SS Bits Setting Bytestream B
SS Bits Setting Bytestream C
SS Bits Setting Bytestream D
0x1628
—
0x1629
—
[A—D]
0x162A
—
[A—D]
0x162B
—
0x162C
—
PP_ES_DEC_MAX[7:0]
PP_ES_INC_MIN[7:0]
0x162D
—
PP_ES_OVR_MAX[7:0]
PP_ES_OVR_MIN[7:0]
0x162F
—
0x164F
—
Agere Systems Inc.
339
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
—
—
Time Slots 1, 3, 5, . . ., 47 E1/F1 insert byte
Time Slots 2, 4, 6, . . ., 48 E1/F1 insert byte
0x1650
—
0x1667
PP_TS_E1F1ISRTR[1—24]
PP_TS_E1F1ISRT[1, 3, 5, . . ., 47][7:0]
PP_TS_E1F1ISRT[2, 4, 6, . . ., 48][7:0]
0x1668
PP_E2_ISRTBSRA
Stream A E2 insert byte
PP_E2_ISRTBSA[7:0]
0x1669
PP_E2_ISRTBSRB
Stream B E2 insert byte
PP_E2_ISRTBSB[7:0]
0x166A
PP_E2_ISRTBSRC
Stream C E2 insert byte
PP_E2_ISRTBSC[7:0]
0x166B
PP_E2_ISRTBSRD
Stream D E2 insert byte
PP_E2_ISRTBSD[7:0]
0x166C
—
0x1681
—
0x1682
—
0x168F
—
0x1690
—
0x16BF
PP_TSMNTR[1—48]
0x16C0
—
0x1701
—
1
0
Maintenance
340
PP_TSSF_TH[1—48][2:0]
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interpreter Inc/Dec (PM)
0x1702
PP_PI_LSECINCRA
0x1703
PP_PI_LSECINCRB
PP_PI_LSECINCA[10:0]
PP_PI_LSECINCB[10:0]
0x1704
PP_PI_LSECINCRC
PP_PI_LSECINCC[10:0]
0x1705
PP_PI_LSECINCRD
PP_PI_LSECINCD[10:0]
0x1706
—
0x1711
—
0x1712
PP_PI_LSECDECRA
0x1713
PP_PI_LSECDECRB
PP_PI_LSECDECB[10:0]
0x1714
PP_PI_LSECDECRC
PP_PI_LSECDECC[10:0]
0x1715
PP_PI_LSECDECRD
PP_PI_LSECDECD[10:0]
0x1716
—
0x1741
—
0x1742
PP_PG_LSECINCRA
0x1743
PP_PG_LSECINCRB
PP_PG_LSECINCB[10:0]
0x1744
PP_PG_LSECINCRC
PP_PG_LSECINCC[10:0]
0x1745
PP_PG_LSECINCRD
PP_PG_LSECINCD[10:0]
0x1746
—
0x1751
—
PP_PI_LSECDECA[10:0]
Generator Inc/Dec (PM)
PP_PG_LSECINCA[10:0]
0x1752
PP_PG_LSECDECRA
0x1753
PP_PG_LSECDECRB
PP_PG_LSECDECB[10:0]
0x1754
PP_PG_LSECDECRC
PP_PG_LSECDECC[10:0]
0x1755
PP_PG_LSECDECRD
PP_PG_LSECDECD[10:0]
0x1756
—
0x177F
—
Agere Systems Inc.
PP_PG_LSECDECA[10:0]
341
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PP_AIS_A
LMPM
PP_LOP_
ALMPM
Performance Monitoring
0x1780
PP_POH_ALMPMR
0x1781
PP_1BRDI_DPMBSR
PP_1BRDI PP_ERDI_ PP_ERDI_ PP_ERDI_ PP_UNEQ
_DPM
PDPM
CDPM
SDPM
R_ALMPM
One Bit RDI Alarm PM
PP_1BRDI_DPMBS[A—D]
0x1782
PP_TS1BRDI_DPMBSRA
One Bit RDI Alarm PM per STS-1 Bytestream A
0x1783
PP_TS1BRDI_DPMBSRB
One Bit RDI Alarm PM per STS-1 Bytestream B
0x1784
PP_TS1BRDI_DPMBSRC
One Bit RDI Alarm PM per STS-1 Bytestream C
0x1785
PP_TS1BRDI_DPMBSRD
One Bit RDI Alarm PM per STS-1 Bytestream D
0x1786
—
0x1790
—
0x1791
PP_ERDI_PDPMBSR
PP_TS1BRDI_DPMBSA[1—12]
PP_TS1BRDI_DPMBSB[1—12]
PP_TS1BRDI_DPMBSC[1—12]
PP_TS1BRDI_DPMBSD[1—12]
ERDI Payload Alarm PM
PP_ERDI_PDPMBS[A—D]
0x1792
PP_ERDI_PDPMBSRA
ERDI Payload Alarm PM per STS-1 Bytestream A
0x1793
PP_ERDI_PDPMBSRB
ERDI Payload Alarm PM per STS-1 Bytestream B
0x1794
PP_ERDI_PDPMBSRC
ERDI Payload Alarm PM per STS-1 Bytestream C
0x1795
PP_ERDI_PDPMBSRD
ERDI Payload Alarm PM per STS-1 Bytestream D
0x1796
—
0x17A0
—
0x17A1
PP_ERDI_CDPMBSR
0x17A2
PP_TSERDI_CDPMBSRA
ERDI Connectivity Alarm PM per STS-1 Bytestream A
0x17A3
PP_TSERDI_CDPMBSRB
ERDI Connectivity Alarm PM per STS-1 Bytestream B
0x17A4
PP_TSERDI_CDPMBSRC
ERDI Connectivity Alarm PM per STS-1 Bytestream C
0x17A5
PP_TSERDI_CDPMBSRD
ERDI Connectivity Alarm PM per STS-1 Bytestream D
0x17A6
—
0x17B0
—
PP_TSERDI_PDPMBSA[1—12]
PP_TSERDI_PDPMBSB[1—12]
PP_TSERDI_PDPMBSC[1—12]
PP_TSERDI_PDPMBSD[1—12]
ERDI Connectivity Alarm PM
PP_ERDI_CDPMBS[A—D]
PP_TSERDI_CDPMBSA[1—12]
PP_TSERDI_CDPMBSB[1—12]
PP_TSERDI_CDPMBSC[1—12]
PP_TSERDI_CDPMBSD[1—12]
342
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
0x17B1
PP_ERDI_SDPMBSR
0x17B2
PP_TSERDI_SDPMBSRA
ERDI Server Alarm PM per STS-1 Bytestream A
0x17B3
PP_TSERDI_SDPMBSRB
ERDI Server Alarm PM per STS-1 Bytestream B
0x17B4
PP_TSERDI_SDPMBSRC
ERDI Server Alarm PM per STS-1 Bytestream C
0x17B5
PP_TSERDI_SDPMBSRD
ERDI Server Alarm PM per STS-1 Bytestream D
0x17B6
—
0x17C0
—
0x17C1
PP_UNEQR_PMBSR
0x17C2
PP_TSUNEQR_PMBSRA
Unequipped Received Alarm PM per STS-1 Bytestream A
0x17C3
PP_TSUNEQR_PMBSRB
Unequipped Received Alarm PM per STS-1 Bytestream B
0x17C4
PP_TSUNEQR_PMBSRC
Unequipped Received Alarm PM per STS-1 Bytestream C
0x17C5
PP_TSUNEQR_PMBSRD
Unequipped Received Alarm PM per STS-1 Bytestream D
0x17C6
—
0x17D0
—
0x17D1
PP_AIS_PMBSR
0x17D2
PP_TSAIS_PMBSRA
Alarm Indicator Signal Alarm PM per STS-1 Bytestream A
0x17D3
PP_TSAIS_PMBSRB
Alarm Indicator Signal Alarm PM per STS-1 Bytestream B
0x17D4
PP_TSAIS_PMBSRC
Alarm Indicator Signal Alarm PM per STS-1 Bytestream C
0x17D5
PP_TSAIS_PMBSRD
Alarm Indicator Signal Alarm PM per STS-1 Bytestream D
0x17D6
—
0x17E0
—
3
2
1
0
ERDI Server Alarm PM
PP_ERDI_SDPMBS[A—D]
PP_TSERDI_SDPMBSA[1—12]
PP_TSERDI_SDPMBSB[1—12]
PP_TSERDI_SDPMBSC[1—12]
PP_TSERDI_SDPMBSD[1—12]
Unequipped Received Alarm PM
PP_UNEQR_PMBS[A—D]
PP_TSUNEQR_PMBSA[1—12]
PP_TSUNEQR_PMBSB[1—12]
PP_TSUNEQR_PMBSC[1—12]
PP_TSUNEQR_PMBSD[1—12]
Alarm Indicator Signal Alarm PM
PP_AIS_PMBS[A—D]
PP_TSAIS_PMBSA[1—12]
PP_TSAIS_PMBSB[1—12]
PP_TSAIS_PMBSC[1—12]
PP_TSAIS_PMBSD[1—12]
Agere Systems Inc.
343
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Pointer Processor (PP) (continued)
PP Register Map (continued)
Table 249. Pointer Processor Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
0x17E1
PP_LOP_PMBSR
0x17E2
PP_TSLOP_PMBSRA
Loss of Pointer Alarm PM per STS-1 Bytestream A
0x17E3
PP_TSLOP_PMBSRB
Loss of Pointer Alarm PM per STS-1 Bytestream B
0x17E4
PP_TSLOP_PMBSRC
Loss of Pointer Alarm PM per STS-1 Bytestream C
0x17E5
PP_TSLOP_PMBSRD
Loss of Pointer Alarm PM per STS-1 Bytestream D
0x17E6
—
0x17FF
—
0x1800
—
0x182F
PP_LSECCVP_CPMR[1—48]
0x1830
—
0x187F
—
0x1880
—
0x18AF
PP_LSECREIP_CPMR[1—48]
0x18B0
—
0x18FF
—
0x1900
—
0x192F
PP_TSRDIPR[1—48]
0x1930
—
0x1947
PP_TSC2R[1—24]
0x1948
—
0x195F
—
0x1960
—
0x1977
PP_TSPDIR[1—24]
0x1968
—
0x1FFF
—
3
2
1
0
Loss of Pointer Alarm PM
PP_LOP_PMBS[A—D]
PP_TSLOP_PMBSA[1—12]
PP_TSLOP_PMBSB[1—12]
PP_TSLOP_PMBSC[1—12]
PP_TSLOP_PMBSD[1—12]
Time Slots 1, 2, 3, 4, . . ., 48 CV Count PM
PP_LSECCVP_CPM[1—48][15:0]
Time Slots 1, 2, 3, 4, . . ., 48 REI Count PM
PP_LSECREIP_CPM[1—48][15:0]
RDI, C2 Status
Time Slot 1—Time Slot 48 Received
RDI Code
PP_TS_RRDI[1—48][2:0]
Time Slots 1, 3, 5, . . ., 47 Received C2 Byte
PP_TSRC2[1, 3, 5, . . ., 47][7:0]
Time Slots 2, 4, 6, . . ., 48 Received C2 Byte
PP_TSRC2[2, 4, 6, . . ., 48][7:0]
PDI Status
344
Time Slots 1, 3, 5, . . ., 47 Received PDI Byte
PP_TSRPDI[1, 3, 5, . . ., 47][7:0]
Time Slots 2, 4, 6, . . ., 48 Received PDI Byte
PP_TSRPDI[2, 4, 6, . . ., 48][7:0]
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT)
Introduction
This section describes the interfaces of the path terminator (PT) block, including the register map description. A
block diagram showing the major subblocks is given.
The PT has the following subblocks:
■
Receive terminator (RXT)
■
SPE mapper (SPE)
■
Transpose block (TR)
■
Microprocessor interface (PT_MP)
PATH TERMINATOR (PT)
TO
CROSS CONNECT
TRANSPOSE
(TR)
FROM
DS3 MAPPER
SPE_MAPPER
MPU REGISTER SIGNALS
LOOPBACK
MPU
PT_MP
FROM
CROSS CONNECT
RECEIVE
TERMINATOR
(RXT)
TRANSPOSE
(TR)
TO
DS3 MAPPER
5-8706(F)r.3
Figure 38. Path Terminator Block Diagram
Agere Systems Inc.
345
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
SPE Mapper
B3ERR
TIM
PLM
UNEQ
AIS
LOP
LCD
TOH/
POH
PBIP
x48
INSERT
TO CROSS CONNECT
TRANSPOSE
x48
DS3/E3
MAPPER
4x8
DS3 MAPPER
SPE_FIFO
5-8707(F).b
Figure 39. Block Diagram of SPE Mapper Block
Time-Slot Assignments
The required STS-1 time-slot assignments for one STS-48 signal on a 32-bit data bus is summarized in Table 250.
The time slots repeat every 12 clock cycles.
Table 250. STS-48 Time-Slot Assignments
Data Bus
Control
STS-48—32-Bit Input/Output Bus Format (STS-1 Numbers, Time ->)
1
2
3
4
5
6
7
8
9
10
11
12
D[31:24]
Port A
1*
4*
7*
10*
2
5
8
11
3
6
9
12
D[23:16]
Port B
13*
16*
19*
22*
14
17
20
23
15
18
21
24
D[15:8]
Port C
25*
28*
31*
34*
26
29
32
35
27
30
33
36
D[7:0]
Port D
37*
40*
43*
46*
38
41
44
47
39
42
45
48
* Indicates valid starting time slots for concatenated signals from STS-3c to STS-48c.
346
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
SPE Mapper (continued)
The required STS-1 time-slot assignment for four STS-12 signals on a 32-bit data bus is summarized in Table 251.
The time slots repeat every 12 clock cycles. Each input stream is independent of the others.
Table 251. STS-12 Time-Slot Assignments
Data Bus
Control
STS-12—32-Bit Input/Output Bus Format (STS-1 Numbers, Time ->)
1
2
3
4
5
6
7
8
9
10
11
12
D[31:24]
Port A
1*
4*
7*
10*
2
5
8
11
3
6
9
12
D[23:16]
Port B
1*
4*
7*
10*
2
5
8
11
3
6
9
12
D[15:8]
Port C
1*
4*
7*
10*
2
5
8
11
3
6
9
12
D[7:0]
Port D
1*
4*
7*
10*
2
5
8
11
3
6
9
12
* Indicates valid starting time slots for concatenated signals from STS-3c to STS-12c.
The required STS-1 time-slot assignment for four STS-3 signals on a 32-bit data bus is summarized in Table 252.
The time slots repeat three additional clock cycles. Each input stream is independent of the others.
Table 252. STS-3 Time-Slot Assignments
Data Bus
Control
STS-12—32-Bit Input/Output Bus Format (STS-1 Numbers, Time ->)
1
2
3
4
5
6
7
8
9
10
11
12
D[31:24]
Port A
1*
1*
1*
1*
2
2
2
2
3
3
3
3
D[23:16]
Port B
1*
1*
1*
1*
2
2
2
2
3
3
3
3
D[15:8]
Port C
1*
1*
1*
1*
2
2
2
2
3
3
3
3
D[7:0]
Port D
1*
1*
1*
1*
2
2
2
2
3
3
3
3
* Indicates valid starting time slots for concatenated signals from STS-1c to STS-3c.
Any combination of STS up to STS-48c can be generated using up to 16-logical channels. Valid starting positions
are indicated by an *.
Agere Systems Inc.
347
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
SPE Mapper (continued)
Example of Channel-to-Time-Slot Mapping for a 16-Channel Configuration with Channel STS Sizes Indicated in Table 254
Table 253. Sequence Register Map TS[0—23]_PM_[A—D]
Sequence Register Map TS[0—23]_PM_[A—D]
Slot #
ch_id Slot # ch_id Slot # ch_id Slot # ch_id
A1
0
B1
3
C1
6
D1
9
A2
10
B2
10
C2
10
D2
10
A3
11
B3
11
C3
11
D3
11
A4
11
B4
11
C4
11
D4
11
A5
1
B5
4
C5
7
D5
9
A6
10
B6
10
C6
10
D6
10
A7
11
B7
11
C7
11
D7
11
A8
11
B8
11
C8
11
D8
11
A9
2
B9
5
C9
8
D9
9
A10
10
B10
10
C10
10
D10
10
A11
11
B11
11
C11
11
D11
11
A12
11
B12
11
C12
11
D12
11
Table 254. Logical 16-Channel Configuration Concatenation Register Map CH[0—15]_NC
Logical 16-Channel Configuration
Concatenation Register Map CH[0—15]_NC
348
ch_id
Size
ch0
1
ch1
1
ch2
1
ch3
1
ch4
1
ch5
1
ch6
1
ch7
1
ch8
1
ch9
3
ch10
12
ch11
24
ch12
—
ch13
—
ch14
—
ch15
—
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
Supported SPE Formats
Direct Mapping into STS-1 SPE
PAYLOAD
PAYLOAD
1 COL
28 COL’S
STUFF
1 COL
28 COL’S
STUFF
POH
1 COL
Figure 40 shows direct mapping into STS-1 SPE, as per GR-253 (R3-6). This mapping can be set per time slot
(PT_TX_STS1_[A—D] (Table 292)).
28 COL’S
PAYLOAD
5-8298(F)
Figure 40. Direct Mapping into STS SPE
STS-Nc SPE
Figure 41 shows the structure of an STS-Nc SPE, as per GR-353 (R3-9). N is valid for N = 3 to 48, where N is a
multiple of 3.
FIXED STUFF (3N – 9 BYTES)
9 ROWS
STS POH (9 BYTES)
N/3-1
COL.
STS-NC PAYLOAD CAPACITY
(N x 780 BYTES)
N x 87 COLUMNS
5-8299(F)r.2
Figure 41. STS-Nc SPE
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Data Sheet
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Path Terminator (PT) (continued)
Supported SPE Formats (continued)
Asynchronous Mapping of DS3 (44.736 Mbits/s) Payload into STS-1
The DS3 frame insertion into an SPE is done as per GR253, section 3.4.2.1. The overhead communication bits
(O bits) and R bits are programmable to either 0 or 1 (PT_TX_MODE[7] (Table 263)).
The stuff opportunity bit (S bit) will contain a data bit every third subframe, starting on the first subframe. During a
row when the S bit is data the 5 C bits must be set to 1; otherwise, if the S bit is a justification bit, the 5 C bits are
set to zero. A justification will always set the S bit to zero.
28 BYTES
R C1 25 I
R C2
28 BYTES
I
25 I
R C3
28 BYTES
I
25 I
R
R C1
25 I
R C2
I
25 I
R C3
I
25 I
R
R C1
25 I
R C2
I
25 I
R C3
I
25 I
R
R C1
25 I
R C2
I
25 I
R C3
I
25 I
R
R C1
25 I
R C2
I
25 I
R C3
I
25 I
R
R C1
25 I
R C2
I
25 I
R C3
I
25 I
R
R C1
25 I
R C2
I
25 I
R C3
I
25 I
R
R C1
25 I
R C2
I
25 I
R C3
I
25 I
R
R C1
25 I
R C2
I
25 I
R C3
I
25 I
FIXED STUFF
R
FIXED STUFF
SPE POH
The DS3 rate is 44,736,000 bits/s. This is equal to 5592 bits per 125 µs frame. The mapping into DS3 gives
5589 bits per 125 µs frame. Therefore, three extra bits are added per frame using the stuff opportunity bits.
5-8300(F)
Note:
I = ii ii ii ii
R = rr rr rr rr
C1 = rr ci ii ii
C2 = cc rr rr rr
C3 = cc rr oo rs
i = info bit.
r = fixed stuff bit.
c = stuff control bit.
s = stuff opportunity bit.
o = overhead common bit.
Figure 42. Asynchronous Mapping of DS3 into STS-1 SPE
350
Agere Systems Inc.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
Supported SPE Formats (continued)
Asynchronous Mapping of E3 (34.368 Mbits/s) Payload into STS-1
The E3 frame insertion into an SPE is done as per ITU-T G.707, Section 10.1.2.2. The r bits are programmably set
to either 0 or 1.
28 bytes
R 3I R 3I R 3I R 3I R R 3I R 3I R 2I
I R 3I R 3I R C 3I R 3I R 3I R 3I R I
2I R R 3I R 3I R 3I R 3I R 3I R C
3I
R 3I R 3I R 3I R 3I R R 3I R 3I R 2I
I R 3I R 3I R C 3I R 3I R 3I R 3I R I
2I R R 3I R 3I R 3I R 3I R 3I R C
3I
R 3I R 3I R 3I R 3I R R 3I R 3I R 2I
I R 3I R 3I R C 3I R 3I R 3I R 3I R I
2I R R 3I R 3I R 3I R 3I R 3I R R A B I
R 3I R 3I R 3I R 3I R R 3I R 3I R 2I
R 3I R 3I R 3I R 3I R R 3I R 3I R 2I
R 3I R 3I R 3I R 3I R R 3I R 3I R 2I
I R 3I R 3I R C 3I R 3I R 3I R 3I R I
I R 3I R 3I R C 3I R 3I R 3I R 3I R I
I R 3I R 3I R C 3I R 3I R 3I R 3I R I
28 bytes
FIXED STUFF
28 bytes
FIXED STUFF
SPE POH
The E3 rate is 34.368 Mbits/s. This is equal to 4293 bits per 125 µs frame. The mapping into E3 gives 4296 bits per
125 µs frame. Therefore, three extra bits must be added per frame using the stuff opportunity bits. The stuff opportunity bit S2 will always contain a data bit (i.e., every third subframe). Thus, C2 will always be set to 1. S1 will
always contain a stuff bit, thus C1 will always be set to 0.
2I R R 3I R 3I R 3I R 3I R 3I R C
3I
2I R R 3I R 3I R 3I R 3I R 3I R C
3I
2I R R 3I R 3I R 3I R 3I R 3I R R A B I
2I R R 3I R 3I R 3I R 3I R 3I R C
3I
R 3I R 3I R 3I R 3I R R 3I R 3I R 2I
I R 3I R 3I R C 3I R 3I R 3I R 3I R I
2I R R 3I R 3I R 3I R 3I R 3I R C
3I
R 3I R 3I R 3I R 3I R R 3I R 3I R 2I
I R 3I R 3I R C 3I R 3I R 3I R 3I R I
2I R R 3I R 3I R 3I R 3I R 3I R R A B I
R 3I R 3I R 3I R 3I R R 3I R 3I R 2I
I R 3I R 3I R C 3I R 3I R 3I R 3I R I
1623(F)r.1
Note: I = ii ii ii ii where i = information bit.
R = rr rr rr rr where r = fixed stuff bit.
C = rr rr rr c1c2 where c1 and c2 = stuff control bits.
A = rr rr rr rr rs1 where s1 = first stuff opportunity bit.
B = s2 ii ii ii i where s2 = second stuff opportunity bit.
Figure 43. Asynchronous Mapping of E3 into STS-1 SPE
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Data Sheet
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Path Terminator (PT) (continued)
SPE Mapper Architecture
SPE Generator
The SPE generator block has the following functions: this block will send a complete frame with all the transport
overhead bytes set to the appropriate default value based on the rate mode (PT_TX_MODE[4:3] (Table 263)) input
signal and the H1, H2, H3, POH bytes, and SPE bytes set correctly. The SPE generator will accept data with the
correct byte interleaving for the type of signal provisioned from the data engine.
The SPE generator operates in three timing modes: one STS-48 signal, four STS-12 signals, or four STS-3 signals. Shown in Figure 44 below is the frame structure of the data sent out of the SPE mapper when in STS-48
mode. This figure indicates the various TOH locations, and the SPE location numbers. Each location consists of 48
octets, whose numbering is also indicated (see Table 250, STS-48 Time-Slot Assignments on page 346 for more
information on how the 48 octets are mapped in time and space). When the SPE generator operates in STS-12
mode, the frame structure is shown in Figure 45, STS-12 Frame Structure on page 353. This figure indicates the
various TOH locations and the SPE location numbers. Each location consists of 12 octets, whose numbering is
also indicated (see Table 251, STS-12 Time-Slot Assignments on page 347 for more information on how the 12
octets are mapped in time and space).
A1 (48 OCTETS TOTAL)
1
4
A1
A2
7
10
13
16
19
22
25
28
31
34
37
40
43
46
...
27
30
33
36
39
42
45
48
27
30
33
36
39
42
45
48
J0 522 523
781 782
H1 H2
H3
0
1
520 521
1
4
7
10
13
16
19
22
25
28
31
34
37
40
43
46
...
SPE LOCATION 521 (48 OCTETS TOTAL)
5-8301(F)
Figure 44. STS-48 Frame Structure
352
Agere Systems Inc.
Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
SPE Mapper Architecture (continued)
A1 (12 OCTETS TOTAL)
1
4
A1
A2
7
10
2
5
8
11
3
6
9
12
J0 522 523
781 782
H1 H2 H3
0
1
520 521
1
4
7
10
2
5
8
11
3
6
9
12
SPE LOCATION 521 (12 OCTETS TOTAL)
5-8303(F)
Figure 45. STS-12 Frame Structure
H1, H2 Pointer Value
The generated H1, H2 value is determined by the time-slot configuration settings (PT_TX_Cnfg_[A—D] high/low
(Table 293—Table 300). There are 48 settings, one per STS-48 location (in STS-12, the first 12 are used, and in
STS-3, the first 3 are used). If the setting indicates normal pointer (00 encoding), an H1 value of 8’b0110_ss_10,
and an H2 value of 8’b0000_1010 is sent, where ss is dependent on the SS setting configuration (there are 2 bits
per channel, used to indicate SS bit insertion, 00 = SONET, 11 = SDH). This corresponds to a normal NDF, and an
offset of 522 decimal.
If the settings indicates concatenation (01 encoding), an H1 value of 8’b1001_ss_11 and an H2 value of
8’b1111_1111 is sent.
If the settings indicates unequipped (10 encoding), an H1 value of 8’b0110_ss_00 and an H2 value of
8’b0000_0000 is sent. Additionally, the entire corresponding payload is set to 8’h00.
If the settings indicate AIS (11 encoding), an H1 value of 8’b1111_11_11 and an H2 value of 8’b1111_1111 is sent.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
SPE Mapper Architecture (continued)
Selective STS-1 Path Insert Functions
Sixteen path overheads can be inserted (one per channel). The valid starting locations for an STS-Nc are shown in
Table 250, STS-48 Time-Slot Assignments on page 346, Table 251, STS-12 Time-Slot Assignments on page 347,
and Table 252, STS-3 Time-Slot Assignments on page 347.
J1 Byte Trace. The insertion of the path trace for a selected STS-1 for both SONET and SDH systems is provided.
For SONET, a 64-byte microprocessor registers are provisioned to transmit the 64-byte path trace message. For
SDH, a repeated 16-byte message is inserted from the 64-byte path trace microprocessor registers.
Note: For simplicity, the 16-byte SDH message is repeated four times in the 64-byte path trace microprocessor registers. A control bit is used to start the insertion of the path trace message; otherwise, all 0s are inserted into
the outgoing J1 byte.
B3 Insertion. The SPE mapper calculates the BIP-8 even parity over all bits (783 bytes for an STS-1 SPE or
Nx783 bytes for an STS-Nc SPE), regardless of any pointer adjustments of the previous STS SPE before scrambling, and inserts in the B3 byte location of the current STS SPE before scrambling. The calculated B3 values can
be inverted per time slot for test purposes (PT_TX_RW1_[0—47][12] (Table 280)). Additionally, the B3 values can
be disabled (i.e., forced to 0) per time slot for testing purposes (PT_TX_RW1_[0—47][14]).
C2: Path Signal Label. The C2 byte is inserted per channel (PT_TX_RW2_[0—15][7:0] (Table 281)).
If the unequipped value of 0x00 is programmed, the SPE mapper will generate an all 0s SPE with a valid payload
pointer (H1 = 0110_SS00, H2 = 0000_0000, H3 = 0000_0000) and B3 value before scrambling.
Table 255 shows the various codes for C2 as per (GR-253, Table 3.2).
Table 255. C2 Path Signal Label
Code
354
Content of the STS SPE
Support
0x00
Unequipped
Yes
0x01
Equipped—Nonspecific Payload
Yes
0x02
VT-Structured STS-1 SPE
No
0x03
Locked VT Mode
No
0x04
Asynchronous Mapping DS3
No
0x12
Asynchronous Mapping for DS4NA
No
0x13
Mapping for ATM
Yes
0x14
Mapping for DQDB
No
0x15
Asynchronous Mapping for FDDI
No
0x16
Mapping for HDLC—PPP
Yes
Agere Systems Inc.
Data Sheet
August 19, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
SPE Mapper Architecture (continued)
G1: Path Status. The G1 byte is used to convey path condition and performance parameters back to the far end.
■
G1[7:4]—known as the remote error indication-path (REI-P) are used to report the number of B3 BIP-8 errors
seen by the current received frames. The valid values for these 4 bits are 0000—1000. This 4-bit REI-P can be
software overridden, on a per-channel basis by setting a control bit (PT_TX_RW1_[47—0][4] (Table 280)) and
provisioning the value (PT_TX_RW1_[47—0][3:0]).
■
G1[3:1]—known as the path remote defect indication (RDI-P) are used to report the received defects as shown
in Table 256. Note that when detecting two or more of the listed defects, the block generates the higher-priority
RDI-P enhanced code based on the priorities listed in the table. It is required to generate the RDI-P signal for at
least 20 frames before changing the value or terminating the generation. A 3-bit state is provided to monitor the
status of RDI-P insertion (PT_TX_TS_[A—D][0—2] (Table 270—Table 272)). Each time this value changes, a
delta bit is set (PT_TX_TS_DELTA[A—D][11:0]D (Table 268), PT_TX_TS_MASK[A—D][11:0]M (Table 262)):
— Hardware Control. The SPE mapper receives from the receive pointer interpreter four signals, on a per-port
basis, used to configure the RDI-P bits. These are AIS, LOP, UNEQUIP, TIM_P (i.e., trace mismatch), and
PLM. Additionally, the SPE mapper receives a loss of cell delineation (LCD) signal on a per-port basis, from
the receive data engine processor. Each contribution to the generation of an RDI-P failure can be inhibited from
contributing to the RDI-P generation, on a per time-slot basis. The SPE mapper must be provisioned to generate a 1-bit RDI-P or enhanced RDI-P on a per time-slot basis (PT_TX_RW1_[47—0][13]).
— Software Control. Insertion of a user-defined value is provided by setting control bit (PT_TX_RW1_[47—0][8])
and provisioning register bits (PT_TX_RW1_[47—0][7:5]) on a per time-slot basis.
— Trace Mismatch (TIM-P). As per ANSI T1.231, the TIM-P is supported via a programmable bit on a per timeslot basis.
— Enhanced or 1-bit RDI-P Mode. When PT_TX_RW1_[47—0][13] is set to 0, one bit RDI-P mode is selected;
G1[3] = 1 when either AIS, LOP, UNEQUIP, TIM_P, or PLM is detected; otherwise, when no defects are detected, set to 0.
Also, when 1-bit RDI-P mode is selected, G1[2:1] are undefined in GR-253, so these bits will be used to indicated SONET or SDH mode. Therefore, when PT_TX_MODE[0] (Table 263) = 0, G1[2:1] = 00. But in
SDH_MODE, (PT_TX_MODE][0] = 1), G1[2:1] = 11.
■
G1[0]—This is also set to 1 if SDH_MODE is set (PT_TX_MODE[0]); otherwise, set to 0.
Table 256. G1 RDI-P Codes
G1[3:1]
Priority of
Enhanced
RDI-P Codes
Trigger
Interpretation
0xx*
Not applicable
No defects
No RDI-P defect
1xx*
Not applicable
AIS-P, LOP-P,
UNEQ-P
RDI-P (1-bit RDI-P)
001†
4
No defects
No RDI-P defects
010†
3
PLM-P, LCD-P
RDI-P payload defect
101†
1
AIS-P, LOP-P
RDI-P server defect
110†
2
UNEQ-P, TIM-P
RDI-P connectivity defect
* These codes are transmitted by STS PTE that do not support enhanced RDI-P. If enhanced RDI-P is not supported, G1 bits 2 and 1 must be
set to the same value, and should be set to 00.
† This code is transmitted by STS PTE that support enhanced RDI-P.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
Transpose Block
■
Reorder STS-48 time-slot assignments for output processing.
■
Input order is as shown in Table 257 below.
■
Output order as shown in Table 250, STS-48 Time-Slot Assignments on page 346.
It is recommended that the time slots be configured in SONET order (Table 257), transposed in the transmit direction, and sent out in time order (Table 250). In the receive direction, time slots can be received in time order and
then transposed back into SONET order.
Table 257. STS-48 Time-Slot Internal Ordering
Data Bus
Control
STS-48—32-Bit Input/Output Bus Format (STS-1 Numbers, Time ->)
1
2
3
4
5
6
7
8
9
10
11
12
D[31:24]
Port A
1*
13*
25*
37*
2
14
26
38
3
15
27
39
D[23:16]
Port B
4*
16*
28*
40*
5
17
29
41
6
18
30
42
D[15:8]
Port C
7*
19*
31*
43*
8
20
32
44
9
21
33
45
D[7:0]
Port D
10*
22*
34*
46*
11
23
35
47
12
24
36
48
* Indicates valid starting time slots for concatenated signals from STS-3c to STS-48c.
356
Agere Systems Inc.
Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions
This section describes the MPU accessible registers in the PT block.
Global Registers
Table 258. (PT_TX_VERSION), Version Control (RO)
Address
Bit
Name
0x4000
15:8
—
7:0
VERSION
Function
Reserved.
Reset
Default
—
Version Number. Indicates version number of PT block.
0x01
Table 259. (PT_TX_CH_INT), Tx Channel Composite Interrupt (RO)
Address
Bit
Name
Function
Reset
Default
0x4001
15:0
Ch_Int
Transmit Channel Interrupt. Active-high interrupt bit on a
per-channel basis. These bits are the ORing of all event and
delta bits associated with a particular transmit channel. An
event or delta bit contribution can be inhibited from contributing to the interrupt by setting the appropriate mask bit.
0x0000
Table 260. (PT_TX_TS_[A—D]_INT), Tx Time-Slot Composite Interrupt (RO)
Address
Bit
0x4004— 15:12
0x4007
11:0
Names
—
TX_TS_A_Int
TX_TS_B_Int
TX_TS_C_Int
TX_TS_D_Int
Function
Reserved.
Reset
Default
0x0000
Transmit Time-Slot Interrupt. Active-high interrupt, per
time slot for slices A, B, C, and D.
Table 261. (PT_TX_CH_INTMASK), Tx Channel Composite Interrupt Mask (R/W)
Address
Bit
Name
Function
Reset
Default
0x4008
15:0
Ch[15:0]
Composite Channel Interrupt Mask. If set, the interrupt will
not occur for that channel.
0xFFFF
Table 262. (PT_TX_TS[A—D]_INTMASK), Tx Time-Slot Composite Interrupt Mask (R/W)
Address
Bit
0x400B— 15:12
0x400E
11:0
Agere Systems Inc.
Name
—
TS[11:0]
Function
Reserved.
Composite Interrupt Mask. If set, the interrupt will not
occur, per time slot, for slices A, B, C, and D.
Reset
Default
0xF
0xFFF
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Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 263. (PT_TX_MODE), Mode (R/W)
Address
Bit
Name
Function
Reset
Default
0x400F
15
STUFFBYTE_
FORCE
Stuff Byte Force. If set to 0, the default is to put stuff bytes
in the first four STS time slots of column 4. This is the recommended setting.
0
If set to 1, stuff byte locations are programmed using the
Stuffbyte_Config register. This may be used when configuring an STS-Nc, where N is not a multiple of 3.
14
Stuffbyte_1or0
Stuff Byte 1 or 0.
0
0 = All stuff bytes are set to 0 (i.e., SONET).
1 = All stuff bytes are set to 1 (i.e., SDH).
13
RX_TRANSPOSE_ Rx Transpose Enable.
ENB
0 = Transpose disabled.
1 = Transpose enabled.
0
12
TX_TRANSPOSE_ Tx Transpose Enable.
ENB
0 = Transpose disabled.
1 = Transpose enabled.
0
11:8
—
7
DS3_RO_VALUE
6
CORWN
Reserved. For Internal Use Only.
—
DS3 RO Bit Values. This is the value that all R and O bits
will be set to in DS3 mapped frames.
0
Clear-On-Read/Write.
0
0 = Clear-on-write, writing a COW register will clear
whatever bits were written with 1.
1 = Clear-on-read, reading a COR register will clear the
entire register.
5
POF_ENB
Packet-Over-Fiber Enable.
0
0 = POF disabled.
1 = POF enabled.
4:3
RATE_MODE
Rate Mode.
0
00 = STS-3.
01 = STS-12.
10 = STS-48.
11 = STS-1.
2
LOOP_MODE
Loopback Mode.
0
1 = Loopback Tx output data to Rx input data.
358
1
—
0
SDH_MODE
Reserved.
0
SDH Mode. 0 = SONET; 1 = SDH.
0
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 264. (PT_TX_BANKAorB), Tx_BANKAorB (R/W)
Address
Bit
Name
0x4010
15:1
—
0
BANKAorB_SEL
Function
Reset
Default
Reserved.
—
Tx BANKAorB_SEL Register.
0
0 = Bank A is selected for sequence map.
1 = Bank B is selected for sequence map.
Table 265. (PT_TX_SCRATCH), SCRATCH (R/W)
Address
Bit
Name
Function
Reset
Default
0x4011
15:0
SCRATCH
Tx Scratchpad Register. Diagnostic register used by microprocessor. Has no effect on the PT function.
0x0000
Table 266. (PT_TX_SOFTRST), Tx Channel FIFO Reset (R/W)
Address
Bit
Name
Function
Reset
Default
0x4013
15:0
SOFTRST
Channel FIFO, Soft Reset. Software reset is necessary
whenever a channel is initialized, after all other setups have
been performed. A software reset should be performed at
the end of configuration for a channel. To perform this reset,
write a 1 to reset and then write a 0 to release the reset.
0
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Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 267. (PT_TX_CH_DELTA [0—15]), Tx Channel Delta/Event (COR/W)
Address
Bit
Name
0x4016—
0x4025
15:2
—
1
FIFO emptyD
0
FIFO FullD
Function
Reset
Default
Reserved.
0
Delta Bit Indicating Change of Associated SPE FIFO Empty
Status.
1
Delta Bit Indicating Change of Associated SPE FIFO Full Status.
0
Table 268. (PT_Tx_TS_[A—D]_Delta), Tx Delta/Event Register (COR/W)
Address
Bit
0x4046— 15:12
0x4049
11:0
Name
—
RDIPD
Function
Reset
Default
Reserved.
0
Delta Bit Indicating Change of RDI-P, per Time Slot.
0
Table 269. (PT_Tx_CH_Status_[0—15]), Transmit Status Register (RO)
Address
Bit
Name
0x404A—
0x4059
15:2
—
1
0
360
Function
Reset
Default
Reserved.
0
FIFO empty
FIFO Empty Status. A 1 indicates that the SPE FIFO is
empty. A 0 indicates that there is data in the FIFO.
1
FIFO Full
FIFO Full Status. A 1 indicates that the SPE FIFO is full.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 270. (PT_TX_TS_[A—D]0_Status), Transmit Status Register (RO)
Address
Bit
Name
0x407A,
0x407D,
0x4080,
0x4083
15
14:12
11
10:8
7
6:4
3
2:0
—
RDIP3
—
RDIP2
—
RDIP1
—
RDIP0
Function
Reserved.
RDIP Status, Time Slot 3.
Reserved.
RDIP Status, Time Slot 2.
Reserved.
RDIP Status, Time Slot 1.
Reserved.
RDIP Status, Time Slot 0.
Reset
Default
0
000
0
000
0
000
0
000
0xx = No defects.
1xx = AIS, LOP, or UNEQ.
001 = No defects.
010 = PLM, LCD.
101 = AIS, LOP.
110 = UNEQ, TIM.
Table 271. (PT_TX_TS_[A—D]1_Status), Transmit Status Register (RO)
Address
Bit
Name
0x407B,
0x407E,
0x4081,
0x4084
15
14:12
11
10:8
7
6:4
3
2:0
—
RDIP7
—
RDIP6
—
RDIP5
—
RDIP4
Function
Reserved.
RDIP Status, Time Slot 7.
Reserved.
RDIP Status, Time Slot 6.
Reserved.
RDIP Status, Time Slot 5.
Reserved.
RDIP Status, Time Slot 4.
Reset
Default
0
000
0
000
0
000
0
000
Table 272. (PT_TX_TS_[A—D]2_Status), Transmit Status Register (RO)
Address
Bit
Name
0x407C,
0x407F,
0x4082,
0x4085
15
14:12
11
10:8
7
6:4
3
2:0
—
RDIP11
—
RDIP10
—
RDIP9
—
RDIP8
Agere Systems Inc.
Function
Reserved.
RDIP Status, Time Slot 11.
Reserved.
RDIP Status, Time Slot 10.
Reserved.
RDIP Status, Time Slot 9.
Reserved.
RDIP Status, Time Slot 8.
Reset
Default
0
000
0
000
0
000
0
000
361
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 273. (PT_Tx_CH_Mask_[0—15]), Tx Channel Mask Register (R/W)
Address
Bit
Name
0x4086—
0x4095
15:2
—
1
FIFO empty
0
FIFO Full
Function
Reset
Default
Reserved.
0xFFFF
SPE FIFO Empty Status Mask, Per Channel. A 1 will mask
the associated delta bit from contributing to the interrupt signal.
SPE FIFO Full Status Mask, Per Channel. A 1 will mask the
associated delta bit from contributing to the interrupt signal.
Table 274. (PT_Tx_TS_[A—D]_Mask), Tx Mask Register (COR/W)
Address
Bit
0x40B6— 15:12
0x40B9
11:0
362
Name
—
RDIPM[11:0]
Function
Reset
Default
Reserved.
0
RDI-P Status Mask, per Time Slot.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 275. (PT_Tx_Mask_A_[1—6]), Transmit Provisioning Register (R/W)
Address
Bit
0x4112— 15:14
0x4117
13
Name
—
Function
Reserved.
RDIPM_TIM
A[1, 3, 5, 7, 9, 11]
Mask TIMP, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P.
12
RDIPM_LCD
A[1, 3, 5, 7, 9, 11]
Mask LCD, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P.
11
RDIPM_PLM
A[1, 3, 5, 7, 9, 11]
Mask PLM, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P.
10
RDIPM_UNEQ
A[1, 3, 5, 7, 9, 11]
Mask UNEQ, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable UNEQ from
contributing to RDI-P.
9
RDIPM_LOP
A[1, 3, 5, 7, 9, 11]
Mask LOP, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P.
8
RDIPM_AIS
A[1, 3, 5, 7, 9, 11]
Mask AIS, slice A time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P.
7:6
—
5
RDIPM_TIM
A[0, 2, 4, 6, 8, 10]
Mask TIMP, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P.
4
RDIPM_LCD
A[0, 2, 4, 6, 8, 10]
Mask LCD, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P.
3
RDIPM_PLM
A[0, 2, 4, 6, 8, 10]
Mask PLM, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P.
2
RDIPM_UNEQ
A[0, 2, 4, 6, 8, 10]
Mask UNEQ, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable UNEQ from
contributing to RDI-P.
1
RDIPM_LOP
A[0, 2, 4, 6, 8, 10]
Mask LOP, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P.
0
RDIPM_AIS
A[0, 2, 4, 6, 8, 10]
Mask AIS, slice A time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P.
Agere Systems Inc.
Reset
Default
0xFFFF
Reserved.
363
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 276. (PT_Tx_Mask_B_[1—6]), Transmit Provisioning Register (R/W)
Address
Bit
0x4118— 15:14
0x411D
13
364
Name
—
Function
Reset
Default
Reserved.
0xFFFF
RDIPM_TIM
B[1, 3, 5, 7, 9, 11]
Mask TIMP, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P.
12
RDIPM_LCD
B[1, 3, 5, 7, 9, 11]
Mask LCD, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P.
11
RDIPM_PLM
B[1, 3, 5, 7, 9, 11]
Mask PLM, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P.
10
RDIPM_UNEQ
B[1, 3, 5, 7, 9, 11]
Mask UNEQ, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable UNEQ from
contributing to RDI-P.
9
RDIPM_LOP
B[1, 3, 5, 7, 9, 11]
Mask LOP, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P.
8
RDIPM_AIS
B[1, 3, 5, 7, 9, 11]
Mask AIS, slice B time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P.
7:6
—
5
RDIPM_TIM
B[0, 2, 4, 6, 8, 10]
Mask TIMP, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P.
4
RDIPM_LCD
B[0, 2, 4, 6, 8, 10]
Mask LCD, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P.
3
RDIPM_PLM
B[0, 2, 4, 6, 8, 10]
Mask PLM, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P.
2
RDIPM_UNEQ
B[0, 2, 4, 6, 8, 10]
Mask UNEQ, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable UNEQ from
contributing to RDI-P.
1
RDIPM_LOP
B[0, 2, 4, 6, 8, 10]
Mask LOP, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P.
0
RDIPM_AIS
B[0, 2, 4, 6, 8, 10]
Mask AIS, slice B time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P.
Reserved.
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 277. (PT_Tx_Mask_C_[1—6]), Transmit Provisioning Register (R/W)
Address
Bit
0x411E— 15:14
0x4123
13
Name
—
Function
Reserved.
RDIPM_TIM
C[1, 3, 5, 7, 9, 11]
Mask TIMP, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P.
12
RDIPM_LCD
C[1, 3, 5, 7, 9, 11]
Mask LCD, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P.
11
RDIPM_PLM
C[1, 3, 5, 7, 9, 11]
Mask PLM, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P.
10
RDIPM_UNEQ
C[1, 3, 5, 7, 9, 11]
Mask UNEQ, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable UNEQ from
contributing to RDI-P.
9
RDIPM_LOP
C[1, 3, 5, 7, 9, 11]
Mask LOP, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P.
8
RDIPM_AIS
C[1, 3, 5, 7, 9, 11]
Mask AIS, slice C time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P.
7:6
—
0xFFFF
Reserved.
5
RDIPM_TIM
Mask TIMP, slice C time slots [0, 2, 4, 6, 8, 10], from contribC[0, 2, 4, 6, 8, 10] uting to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P.
4
RDIPM_LCD
Mask LCD, slice C time slots [0, 2, 4, 6, 8, 10], from contributC[0, 2, 4, 6, 8, 10] ing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P.
3
RDIPM_PLM
Mask PLM, slice C time slots [0, 2, 4, 6, 8, 10], from contribC[0, 2, 4, 6, 8, 10] uting to RDI_P generation. A 1 will disable PLM from contributing to RDI-P.
2
RDIPM_UNEQ
Mask UNEQ, slice C time slots [0, 2, 4, 6, 8, 10], from conC[0, 2, 4, 6, 8, 10] tributing to RDI_P generation. A 1 will disable UNEQ from
contributing to RDI-P.
1
RDIPM_LOP
Mask LOP, slice C time slots [0, 2, 4, 6, 8, 10], from contributC[0, 2, 4, 6, 8, 10] ing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P.
0
RDIPM_AIS
Mask AIS, slice C time slots [0, 2, 4, 6, 8, 10], from contributC[0, 2, 4, 6, 8, 10] ing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P.
Agere Systems Inc.
Reset
Default
365
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 278. (PT_Tx_Mask_D_[1—6]), Transmit Provisioning Register (R/W)
Address
Bit
0x4124— 15:14
0x4129
13
366
Name
—
Function
Reset
Default
Reserved.
0xFFFF
RDIPM_TIM
D[1, 3, 5, 7, 9, 11]
Mask TIMP, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P.
12
RDIPM_LCD
D[1, 3, 5, 7, 9, 11]
Mask LCD, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P.
11
RDIPM_PLM
D[1, 3, 5, 7, 9, 11]
Mask PLM, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P.
10
RDIPM_UNEQ
D[1, 3, 5, 7, 9, 11]
Mask UNEQ, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable UNEQ from
contributing to RDI-P.
9
RDIPM_LOP
D[1, 3, 5, 7, 9, 11]
Mask LOP, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P.
8
RDIPM_AIS
D[1, 3, 5, 7, 9, 11]
Mask AIS, slice D time slots [1, 3, 5, 7, 9, 11], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P.
7:6
—
5
RDIPM_TIM
D[0, 2, 4, 6, 8, 10]
Mask TIMP, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable TIMP from contributing to RDI-P.
4
RDIPM_LCD
D[0, 2, 4, 6, 8, 10]
Mask LCD, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LCD from contributing to RDI-P.
3
RDIPM_PLM
D[0, 2, 4, 6, 8, 10]
Mask PLM, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable PLM from contributing to RDI-P.
2
RDIPM_UNEQ
D[0, 2, 4, 6, 8, 10]
Mask UNEQ, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable UNEQ from
contributing to RDI-P.
1
RDIPM_LOP
D[0, 2, 4, 6, 8, 10]
Mask LOP, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable LOP from contributing to RDI-P.
0
RDIPM_AIS
D[0, 2, 4, 6, 8, 10]
Mask AIS, slice D time slots [0, 2, 4, 6, 8, 10], from contributing to RDI_P generation. A 1 will disable AIS from contributing to RDI-P.
Reserved.
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 279. (PT_Tx_RW4_[0—15]), Transmit Provisioning Register 4 (R/W)
Address
Bit
Name
Function
0x4132—
0x4141
15:8
Z4_Byte
Value of Z4 byte to insert.
7:0
Z3_Btye
Value of Z3 byte to insert.
Reset
Default
0x0000
Table 280. (PT_Tx_RW1_[0—47]), Transmit Provisioning Register, Per Time Slot (R/W)
Note: RW1_[0] is slice A, time slot 0; RW1_[47] is slice D, time slot 11.
Address
Bit
Name
Function
0x4142—
0x4171
15
—
14
B3_Disable
1 = B3 POH byte is set to 0.
13
RDIP_Enh_Mode
0 = RDI_P 1-bit mode.
1 = RDI_P enhanced mode.
12
B3_Invert
11:9
—
8
RDIP_Force
7:5
RDIP_Bits
4
REIP_Force
3:0
REIP_Bits
Reserved.
Reset
Default
0x0000
1 = Invert B3 POH byte.
Reserved.
When RDIP_Force = 1, override RDI_P value with
RDIP_Bits.
When REIP_Force = 1, override REI_P value with
REIP_Bits.
Table 281. (PT_Tx_RW2_[0—15]), Transmit Provisioning Register, Per Channel (R/W)
Address
Bit
0x4172— 15:14
0x4181 13:12
Name
—
ss_bits
Function
Reset
Default
Reserved.
0
ss value (i.e., H1[3:2]).
0
Reserved.
0
11:9
—
8
J1_enb
1 = Enable J1 message.
0
7:0
C2_Byte
Value of C2 byte to insert.
0
Table 282. (PT_Tx_RW3_[0—15]), Transmit Provisioning Register 3 (R/W)
Address
Bit
Name
0x4182—
0x4191
15:8
Z5_Byte
Value of Z5 byte to insert.
7:0
H4_Byte
Value of H4 byte to insert.
Agere Systems Inc.
Function
Reset
Default
0x0000
367
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 283. (PT_Tx_alarm_[A—D]_[1]]), TX Alarm Mapper Register 1 (R/W)
Note: The Rx alarm addresses per time slot are slice A = 0—11, B = 12—23, C = 24—35, D = 36—47.
Address
Bit
0x4192— 15:14
0x4195
13:8
Name
—
sel_alarm1
7:6
—
5:0
sel_alarm0
Function
Reset
Default
Reserved.
0x0
Rx Alarm Which Maps to Slot 1.
A: 0x01,
B: 0x0D,
C: 0x19,
D: 0x25
Reserved.
0x0
Rx Alarm Which Maps to Slot 0.
A: 0x00,
B: 0x0C,
C: 0x18,
D: 0x24
Table 284. (PT_Tx_alarm_[A—D]_[2]]), TX Alarm Mapper Register 2 (R/W)
Note: The Rx alarm addresses per time slot are slice A = 0—11, B = 12—23, C = 24—35, D = 36—47.
Address
Bit
0x4196— 15:14
0x4199
13:8
368
Name
—
sel_alarm3
7:6
—
5:0
sel_alarm2
Function
Reserved.
Rx Alarm Which Maps to Slot 3.
Reserved.
Tx Alarm Which Maps to Slot 2.
Reset
Default
0x0
A: 0x03,
B: 0x0F,
C: 0x01B,
D: 0x27
0x0
A: 0x02,
B: 0x0E,
C: 0x1A,
D: 0x26
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 285. (PT_Tx_alarm_[A—D]_[3]]), TX Alarm Mapper Register 3 (R/W)
Note: The Rx alarm addresses per time slot are slice A = 0—11, B = 12—23, C = 24—35, D = 36—47.
Address
Bit
0x419A— 15:14
0x419D
13:8
Name
—
sel_alarm5
7:6
—
5:0
sel_alarm4
Function
Reserved.
Reset
Default
0x0
Rx Alarm Which Maps to Slot 5.
Reserved.
A: 0x05,
B: 0x11,
C: 0x1D,
D: 0x29
0x0
Rx Alarm Which Maps to Slot 4.
A: 0x04,
B: 0x10,
C: 0x1C,
D: 0x28
Table 286. (PT_Tx_alarm_[A—D]_[4]]), TX Alarm Mapper Register 4 (R/W)
Note: The Rx alarm addresses per time slot are slice A = 0—11, B = 12—23, C = 24—35, D = 36—47.
Address
Bit
0x419E— 15:14
0x41A1
13:8
Name
—
sel_alarm7
7:6
—
5:0
sel_alarm6
Agere Systems Inc.
Function
Reserved.
Rx Alarm Which Maps to Slot 7.
Reserved.
Rx Alarm Which Maps to Slot 6.
Reset
Default
0x0
A: 0x07,
B: 0x13,
C: 0x1F,
D: 0x2B
0x0
A: 0x06,
B: 0x12,
C: 0x1E,
D: 0x2A
369
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 287. (PT_Tx_alarm_[A—D]_[5]]), TX Alarm Mapper Register 5 (R/W)
Note: The Rx alarm addresses per time slot are slice A = 0—11, B = 12—23, C = 24—35, D = 36—47.
Address
Bit
0x41A2— 15:14
0x41A5
13:8
Name
—
sel_alarm9
7:6
—
5:0
sel_alarm8
Function
Reset
Default
Reserved.
0x0
Rx Alarm Which Maps to Slot 9.
A: 0x09,
B: 0x15,
C: 0x21,
D: 0x2D
Reserved.
0x0
Rx Alarm Which Maps to Slot 8.
A: 0x08,
B: 0x14,
C: 0x20,
D: 0x2C
Table 288. (PT_Tx_alarm_[A—D]_[6]]), TX Alarm Mapper Register 6 (R/W)
Note: The Rx alarm addresses per time slot are slice A = 0—11, B = 12—23, C = 24—35, D = 36—47.
Address
Bit
0x41A6— 15:14
0x41A9
13:8
370
Name
—
sel_alarm11
7:6
—
5:0
sel_alarm10
Function
Reserved.
Rx Alarm Which Maps to Slot 11.
Reserved.
Rx Alarm Which Maps to Slot 10.
Reset
Default
0x0
A: 0x0B,
B: 0x17,
C: 0x23,
D: 0x2F
0x0
A: 0x0A,
B: 0x16,
C: 0x22,
D: 0x2E
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 289. (PT_Tx_RW5_[0—15]), Transmit Provisioning Register 5 (R/W)
Address
Bit
0x41B2— 15:13
0x41C1
12:8
Name
—
FIFO_Over_Value
Function
Reserved.
Reset
Default
0x1802
Channel FIFO Overthreshold Value. When the SPE FIFO
is over threshold, backpressure will be sent upstream to the
DS3 block to prevent an overflow.
Backpressure will be released once the SPE FIFO has less
words than the overthreshold value.
This value should always be programmed to 0x16.
Note: The reset default value of 0x18 needs to be overwritten with 0x16 after powerup.
7:5
4:0
—
Reserved.
FIFO_Under_Value Channel FIFO Underthreshold Value. When the SPE FIFO
is underthreshold, the FIFO will not be read. This allows the
FIFO to fill up to the underthreshold value before being read
after initialization.
This value should always be programmed to 0x02.
Table 290. (PT_Tx_TIMP_[A—D]), TX TIMP Alarm Register, Per Time Slot (R/W)
Address
Bit
0x41E6— 15:12
0x41E9
11:0
Name
—
TIMP[11:0]
Function
Reserved.
Reset
Default
0x0000
Tx TIMP is used to insert a trace mismatch error into RDI-P.
This is because the Rx path doesn't automatically relay a
trace mismatch to the Tx path. Tx TIMP must be set/unset
within 30 seconds of a trace mismatch/match. A trace mismatch occurs when J1 mismatches for more than 2.5 seconds, and a trace mismatch error can be cleared when a
match occurs for more than 10 seconds.
1 = TIMP alarm is set, per channel.
Agere Systems Inc.
371
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 291. (PT_Tx_DS3E3_[A—B]), Transmit Provisioning Register (R/W)
Address
Bit
0x41EE— 15:12
0x41EF
11:0
Name
—
DS3E3[11:0]
Function
Reset
Default
Reserved.
0x0000
If TX_SEQMAP[PType] is set to 1, this bit selects to either
map a DS3 or E3 signal to an STS-1.
0 = DS3.
1 = E3.
Table 292. (PT_Tx_STS1_[A—D]), Transmit Provisioning Register (R/W)
Address
Bit
0x41FA— 15:12
0x41FD
11:0
372
Name
—
STS1[11:0]
Function
Reset
Default
Reserved.
0x0000
This bit must be set for an STS-1 or DS3 signal, per time
slot. This will force the stuff bytes to be in columns 33 and
62, instead of columns 2—4.
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 293. (PT_Tx_Cnfg_Alow), Transmit STS Configuration, Time Slots 0—5 (R/W)
Address
Bit
Name
0x4276
15:12
—
11:10
TS_A0
Function
Reset
Default
Reserved.
—
STS Configuration for Time Slot 0.
00
00 = Normal.
01 = CONC.
10 = UNEQ.
11 = AIS.
9:8
TS_A1
STS Configuration for Time Slot 1.
00
7:6
TS_A2
STS Configuration for Time Slot 2.
00
5:4
TS_A3
STS Configuration for Time Slot 3.
00
3:2
TS_A4
STS Configuration for Time Slot 4.
00
1:0
TS_A5
STS Configuration for Time Slot 5.
00
Table 294. (PT_Tx_Cnfg_Ahigh), Transmit STS Configuration, Time Slots 6—11 (R/W)
Address
Bit
Name
0x4277
15:12
—
11:10
TS_A6
Function
Reset
Default
Reserved.
—
STS Configuration for Time Slot 6.
00
00 = Normal.
01 = CONC.
10 = UNEQ.
11 = AIS.
9:8
TS_A7
STS Configuration for Time Slot 7.
00
7:6
TS_A8
STS Configuration for Time Slot 8.
00
5:4
TS_A9
STS Configuration for Time Slot 9.
00
3:2
TS_A10
STS Configuration for Time Slot 10.
00
1:0
TS_A11
STS Configuration for Time Slot 11.
00
Agere Systems Inc.
373
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 295. (PT_Tx_Cnfg_Blow), Transmit STS Configuration, Time Slots 0—5 (R/W)
Address
Bit
Name
0x4278
15:12
—
11:10
TS_B0
Function
Reset
Default
Reserved.
—
STS Configuration for Time Slot 0.
00
00 = Normal.
01 = CONC.
10 = UNEQ.
11 = AIS.
9:8
TS_B1
STS Configuration for Time Slot 1.
00
7:6
TS_B2
STS Configuration for Time Slot 2.
00
5:4
TS_B3
STS Configuration for Time Slot 3.
00
3:2
TS_B4
STS Configuration for Time Slot 4.
00
1:0
TS_B5
STS Configuration for Time Slot 5.
00
Table 296. (PT_Tx_Cnfg_Bhigh), Transmit STS Configuration, Time Slots 6—11 (R/W)
Address
Bit
Name
0x4279
15:12
—
11:10
TS_B6
Function
Reset
Default
Reserved.
—
STS Configuration for Time Slot 6.
00
00 = Normal.
01 = CONC.
10 = UNEQ.
11 = AIS.
374
9:8
TS_B7
STS Configuration for Time Slot 7.
00
7:6
TS_B8
STS Configuration for Time Slot 8.
00
5:4
TS_B9
STS Configuration for Time Slot 9.
00
3:2
TS_B10
STS Configuration for Time Slot 10.
00
1:0
TS_B11
STS Configuration for Time Slot 11.
00
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 297. (PT_Tx_Cnfg_Clow), Transmit STS Configuration, Time Slots 0—5 (R/W)
Address
Bit
Name
0x427A
15:12
—
11:10
TS_C0
Function
Reset
Default
Reserved.
—
STS Configuration for Time Slot 0.
00
00 = Normal.
01 = CONC.
10 = UNEQ.
11 = AIS.
9:8
TS_C1
STS Configuration for Time Slot 1.
00
7:6
TS_C2
STS Configuration for Time Slot 2.
00
5:4
TS_C3
STS Configuration for Time Slot 3.
00
3:2
TS_C4
STS Configuration for Time Slot 4.
00
1:0
TS_C5
STS Configuration for Time Slot 5.
00
Table 298. (PT_Tx_Cnfg_Chigh), Transmit STS Configuration, Time Slots 6—11 (R/W)
Address
Bit
Name
0x427B
15:12
—
11:10
TS_C6
Function
Reset
Default
Reserved.
—
STS Configuration for Time Slot 6.
00
00 = Normal.
01 = CONC.
10 = UNEQ.
11 = AIS.
9:8
TS_C7
STS Configuration for Time Slot 7.
00
7:6
TS_C8
STS Configuration for Time Slot 8.
00
5:4
TS_C9
STS Configuration for Time Slot 9.
00
3:2
TS_C10
STS Configuration for Time Slot 10.
00
1:0
TS_C11
STS Configuration for Time Slot 11.
00
Agere Systems Inc.
375
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 299. (PT_Tx_Cnfg_Dlow), Transmit STS Configuration, Time Slots 0—5 (R/W)
Address
Bit
Name
0x427C
15:12
—
11:10
TS_D0
Function
Reset
Default
Reserved.
—
STS Configuration for Time Slot 0.
00
00 = Normal.
01 = CONC.
10 = UNEQ.
11 = AIS.
9:8
TS_D1
STS Configuration for Time Slot 1.
00
7:6
TS_D2
STS Configuration for Time Slot 2.
00
5:4
TS_D3
STS Configuration for Time Slot 3.
00
3:2
TS_D4
STS Configuration for Time Slot 4.
00
1:0
TS_D5
STS Configuration for Time Slot 5.
00
Table 300. (PT_Tx_Cnfg_Dhigh), Transmit STS Configuration, Time Slots 6—11 (R/W)
Address
Bit
Name
0x427D
15:12
—
11:10
TS_D6
Function
Reset
Default
Reserved.
—
STS Configuration for Time Slot 6.
00
00 = Normal.
01 = CONC.
10 = UNEQ.
11 = AIS.
376
9:8
TS_D7
STS Configuration for Time Slot 7.
00
7:6
TS_D8
STS Configuration for Time Slot 8.
00
5:4
TS_D9
STS Configuration for Time Slot 9.
00
3:2
TS_D10
STS Configuration for Time Slot 10.
00
1:0
TS_D11
STS Configuration for Time Slot 11.
00
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 301. (PT_Tx_Stuffbyte_cnfg]), Tx Stuff Byte Configuration Register (R/W)
Note: If STUFFBYTE_FORCE = 1 (i.e., tx_mode[15] = 1), then stuff byte locations in time slots 0—3 will be determined by this register; otherwise, stuff bytes are per SONET GR-253.
Address
Bit
Name
0x429F
15
TS_A_0
1 = Put stuff byte in time slot 0, slice A.
14
TS_A_1
1 = Put stuff byte in time slot 1, slice A.
13
TS_A_2
1 = Put stuff byte in time slot 2, slice A.
12
TS_A_3
1 = Put stuff byte in time slot 3, slice A.
11
TS_B_0
1 = Put stuff byte in time slot 0, slice B.
10
TS_B_1
1 = Put stuff byte in time slot 1, slice B.
9
TS_B_2
1 = Put stuff byte in time slot 2, slice B.
8
TS_B_3
1 = Put stuff byte in time slot 3, slice B.
7
TS_C_0
1 = Put stuff byte in time slot 0, slice C.
6
TS_C_1
1 = Put stuff byte in time slot 1, slice C.
5
TS_C_2
1 = Put stuff byte in time slot 2, slice C.
4
TS_C_3
1 = Put stuff byte in time slot 3, slice C.
3
TS_D_0
1 = Put stuff byte in time slot 0, slice D.
2
TS_D_1
1 = Put stuff byte in time slot 1, slice D.
1
TS_D_2
1 = Put stuff byte in time slot 2, slice D.
0
TS_D_3
1 = Put stuff byte in time slot 3, slice D.
Agere Systems Inc.
Function
Reset
Default
0x0000
377
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 302. (PT_TX_SEQMAP_A_AB[0—11]), Sequence Map, Bank A, Slices A and B, Per Time Slot (R/W)
Address
Bit
Name
Function
Reset
Default
Bank A Is Active Whenever PT_TX_MODE[0] = 0.
0x4300—
0x430B
15
BankA_Ptype_B
Payload Type, Slice B.
0x0000
0 = STS-Nc.
1 = DS3 or E3, determined by TX_DS3E3 register.
14
BankA_PM_B
Payload Marker, Slice B. Valid/invalid indicator, i.e., if set to
0, then that time slot is not expected to contain data, e.g., in
the case where the payload is not completely full, e.g., when
there is only one STS-12c within an STS-48.
13:8
BankA_CHID_B
Channel ID, Slice B. Indicates which channel [0—15] gets
mapped to this time slot.
7
BankA_Ptype_A
Payload Type, Slice A.
0 = STS-Nc.
1 = DS3 or E3, determined by TX_DS3E3 register.
378
6
BankA_PM_A
Payload Marker, Slice A. Valid/invalid indicator, i.e., if set to
0, then that time slot is not expected to contain data, e.g., in
the case where the payload is not completely full, e.g., when
there is only one STS-12c within an STS-48.
5:0
BankA_CHID_A
Channel ID, Slice A. Indicates which channel [0—15] gets
mapped to this time slot.
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 303. (PT_TX_SEQMAP_B_AB[0—11]), Sequence Map, Bank B, Slices A and B, Per Time Slot (R/W)
Address
Bit
Name
Function
Reset
Default
Bank B Is Active Whenever PT_TX_MODE[0] = 1.
0x4310—
0x431B
15
BankB_Ptype_B
Payload Type, Slice B.
0x0000
0 = STS-Nc.
1 = DS3 or E3, determined by TX_DS3E3 register.
14
BankB_PM_B
Payload Marker, Slice B. Valid/invalid indicator, i.e., if set to
0, then that time slot is not expected to contain data, e.g., in
the case where the payload is not completely full, e.g., when
there is only one STS-12c within an STS-48.
13:8
BankB_CHID_B
Channel ID, Slice B. Indicates which channel [0—15] gets
mapped to this time slot.
7
BankB_Ptype_A
Payload Type, Slice A.
0 = STS-Nc.
1 = DS3 or E3, determined by TX_DS3E3 register.
6
BankB_PM_A
Payload Marker, Slice A. Valid/invalid indicator, i.e., if set to
0, then that time slot is not expected to contain data, e.g., in
the case where the payload is not completely full, e.g., when
there is only one STS-12c within an STS-48.
5:0
BankB_CHID_A
Channel ID, Slice A. Indicates which channel [0—15] gets
mapped to this time slot.
Agere Systems Inc.
379
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 304. (PT_TX_SEQMAP_A_CD[0—11]), Sequence Map, Bank A, Slices C and D, Per Time Slot (R/W)
Address
Bit
Name
Function
Reset
Default
Bank A Is Active Whenever PT_TX_MODE[0] = 0.
0x4320—
0x432B
15
BankA_Ptype_D
Payload Type, Slice D.
0x0000
0 = STS-Nc.
1 = DS3 or E3, determined by TX_DS3E3 register.
14
BankA_PM_D
Payload Marker, Slice D. Valid/invalid indicator, i.e., if set to
0, then that time slot is not expected to contain data, e.g., in
the case where the payload is not completely full, e.g., when
there is only one STS-12c within an STS-48.
13:8
BankA_CHID_D
Channel ID, Slice D. Indicates which channel [0—15] gets
mapped to this time slot.
7
BankA_Ptype_C
Payload Type, Slice C.
0 = STS-Nc.
1 = DS3 or E3, determined by TX_DS3E3 register.
380
6
BankA_PM_C
Payload Marker, Slice C. Valid/invalid indicator, i.e., if set to
0, then that time slot is not expected to contain data, e.g., in
the case where the payload is not completely full, e.g., when
there is only one STS-12c within an STS-48.
5:0
BankA_CHID_C
Channel ID, Slice C. Indicates which channel [0—15] gets
mapped to this time slot.
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 305. (PT_TX_SEQMAP_B_CD[0—11]), Sequence Map, Bank B, Slices C and D, Per Time Slot (R/W)
Address
Bit
Name
Function
Reset
Default
Bank B Is Active Whenever PT_TX_MODE[0] = 0.
0x4330—
0x433B
15
BankB_Ptype_D
Payload Type, Slice D.
0x0000
0 = STS-Nc.
1 = DS3 or E3, determined by TX_DS3E3 register.
14
BankB_PM_D
Payload Marker, Slice D. Valid/invalid indicator, i.e., if set to
0, then that time slot is not expected to contain data, e.g., in
the case where the payload is not completely full, e.g., when
there is only one STS-12c within an STS-48.
13:8
BankB_CHID_D
Channel ID, Slice D. Indicates which channel [0—15] gets
mapped to this time slot.
7
BankB_Ptype_C
Payload Type, Slice C.
0 = STS-Nc.
1 = DS3 or E3, determined by TX_DS3E3 register.
6
BankB_PM_C
Payload Marker, Slice C. Valid/invalid indicator, i.e., if set to
0, then that time slot is not expected to contain data, e.g., in
the case where the payload is not completely full, e.g., when
there is only one STS-12c within an STS-48.
5:0
BankB_CHID_C
Channel ID, Slice C. Indicates which channel [0—15] gets
mapped to this time slot.
Agere Systems Inc.
381
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 306. (PT_Tx_J1Byte_start_0_[0—31]), Transmit J1 Byte Message Channel 0 (R/W)
Address
Bit
Name
Function
Reset
Default
0x4380—
0x439F
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 307. (PT_Tx_J1Byte_start_1_[0—31]), Transmit J1 Byte Message Channel 1 (R/W)
Address
Bit
Name
Function
Reset
Default
0x43A0—
0x43BF
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 308. (PT_Tx_J1Byte_start_2_[0—31]), Transmit J1 Byte Message Channel 2 (R/W)
Address
Bit
Name
Function
Reset
Default
0x43C0—
0x43DF
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 309. (PT_Tx_J1Byte_start_3_[0—31]), Transmit J1 Byte Message Channel 3 (R/W)
Address
Bit
Name
Function
Reset
Default
0x43E0—
0x43FF
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 310. (PT_Tx_J1Byte_start_4_[0—31]), Transmit J1 Byte Message Channel 4 (R/W)
Address
Bit
Name
0x4400—
0x441F
15:8
7:0
382
Function
Reset
Default
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 311. (PT_Tx_J1Byte_start_5_[0—31]), Transmit J1 Byte Message Channel 5 (R/W)
Address
Bit
Name
Function
Reset
Default
0x4420—
0x443F
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 312. (PT_Tx_J1Byte_start_6_[0—31]), Transmit J1 Byte Message Channel 6 (R/W)
Address
Bit
Name
Function
Reset
Default
0x4440—
0x445F
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 313. (PT_Tx_J1Byte_start_7_[0—31]), Transmit J1 Byte Message Channel 7 (R/W)
Address
Bit
Name
Function
Reset
Default
0x4460—
0x447F
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 314. (PT_Tx_J1Byte_start_8_[0—31]), Transmit J1 Byte Message Channel 8 (R/W)
Address
Bit
Name
Function
Reset
Default
0x4480—
0x449F
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 315. (PT_Tx_J1Byte_start_9_[0—31]), Transmit J1 Byte Message Channel 9 (R/W)
Address
Bit
Name
Function
Reset
Default
0x44A0—
0x44BF
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 316. (PT_Tx_J1Byte_start_10_[0—31]), Transmit J1 Byte Message Channel 10 (R/W)
Address
Bit
Name
0x44C0—
0x44DF
15:8
7:0
Agere Systems Inc.
Function
Reset
Default
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
383
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Descriptions (continued)
Table 317. (PT_Tx_J1Byte_start_11_[0—31]), Transmit J1 Byte Message Channel 11 (R/W)
Address
Bit
Name
Function
Reset
Default
0x44E0—
0x44FF
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 318. (PT_Tx_J1Byte_start_12_[0—31]), Transmit J1 Byte Message Channel 12 (R/W)
Address
Bit
Name
Function
Reset
Default
0x4500—
0x451F
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 319. (PT_Tx_J1Byte_start_13_[0—31]), Transmit J1 Byte Message Channel 13 (R/W)
Address
Bit
Name
Function
Reset
Default
0x4520—
0x453F
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 320. (PT_Tx_J1Byte_start_14_[0—31]), Transmit J1 Byte Message Channel 14 (R/W)
Address
Bit
Name
Function
Reset
Default
0x4540—
0x455F
15:8
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
7:0
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Table 321. (PT_Tx_J1Byte_start_15_[0—31]), Transmit J1 Byte Message Channel 15 (R/W)
Address
Bit
Name
0x4560—
0x457F
15:8
7:0
384
Function
Reset
Default
J1_Byte_1
J1 byte, odd bytes 1, 3, 5, . . . , 63.
0x0000
J1_Byte_0
J1 byte, even bytes 0, 2, 4, . . . , 62.
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Map (Entire PT Except RXT Block)
Table 322. PT Register Map
Note: Shading denotes reserved bits.
Address
Symbol
Type
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Version Register
0x4000
TX_VERSION
RO
VERSION[7:0]
Composite Interrupts
0x4001
TX_CH_INT
RO
0x4002
—
—
Ch15
Ch14
Ch13
Ch12
Ch11
Ch10
Ch9
Ch8
Ch7
Ch6
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
0x4003
—
—
0x4004
TX_TS_A_INT
RO
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
0x4005
TX_TS_B_INT
RO
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
0x4006
TX_TS_C_INT
RO
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
0x4007
TX_TS_D_INT
RO
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
Composite Interrupt Masks
0x4008
TX_CH_INTMASK
R/W
0x4009
—
—
Ch15
Ch14
Ch13
Ch12
Ch11
Ch10
Ch9
Ch8
Ch7
Ch6
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
0x400A
—
—
0x400B
TX_TS_A_INTMASK
R/W
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
0x400C
TX_TS_B_INTMASK
R/W
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
0x400D
TX_TS_C_INTMASK
R/W
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
0x400E
TX_TS_D_INTMASK
R/W
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
DS3_RO_
VALUE
CORWN
POF_ENB
Mode, Scratch, and GPO Select Registers
0x400F
TX_MODE
R/W
0x4010
TX_BANKAORB
R/W
0x4011
TX_SCRATCH
R/W
0x4012
—
—
0x4013
TX_SOFTRST
R/W
0x4014
—
—
Agere Systems Inc.
STUFFBYT
E_FORCE
Stuffbyte_
1or0
RX_
TRNSPOS
E_ENB
TX_
TRNSPOS
E_ENB
RATE_MODE
LOOPBAC
K_MODE
SDH_
MODE
BankAorB_
SEL
SCRATCH
Ch15
Ch14
Ch13
Ch12
Ch11
Ch10
Ch9
Ch8
Ch7
Ch6
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
385
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Map (Entire PT Except RXT Block) (continued)
Table 322. PT Register Map (continued)
Note: Shading denotes reserved bits.
Address
Symbol
Type
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIFO_
EmptyD
FIFO_
FullD
Delta/Event Registers
0x4016
—
0x4025
TX_CH_DELTA_0—
TX_CH_DELTA_15]
COR/W
0x4026
—
0x4045
—
—
0x4046
TX_TS_A_Delta
COR/W
RDIPD11
RDIPD10
RDIPD9
RDIPD8
RDIPD7
RDIPD6
RDIPD5
RDIPD4
RDIPD3
RDIPD2
RDIPD1
RDIPD0
0x4047
TX_TS_B_Delta
COR/W
RDIPD11
RDIPD10
RDIPD9
RDIPD8
RDIPD7
RDIPD6
RDIPD5
RDIPD4
RDIPD3
RDIPD2
RDIPD1
RDIPD0
0x4048
TX_TS_C_Delta
COR/W
RDIPD11
RDIPD10
RDIPD9
RDIPD8
RDIPD7
RDIPD6
RDIPD5
RDIPD4
RDIPD3
RDIPD2
RDIPD1
RDIPD0
0x4049
TX_TS_D_Delta
COR/W
RDIPD11
RDIPD10
RDIPD9
RDIPD8
RDIPD7
RDIPD6
RDIPD5
RDIPD4
RDIPD3
RDIPD2
RDIPD1
RDIPD0
FIFO_
Empty
FIFO_
Full
Status Registers
0x404A
—
0x4059
TX_CH_STATUS_0—
TX_CH_STATUS_15]
RO
0x405A
—
0x4079
—
—
0x407A
TX_TS_A0_STATUS
RO
RDIP3
RDIP2
RDIP1
RDIP0
0x407B
TX_TS_A1_STATUS
RO
RDIP7
RDIP6
RDIP5
RDIP4
0x407C
TX_TS_A2_STATUS
RO
RDIP11
RDIP10
RDIP9
RDIP8
0x407D
TX_TS_B0_STATUS
RO
RDIP3
RDIP2
RDIP1
RDIP0
0x407E
TX_TS_B1_STATUS
RO
RDIP7
RDIP6
RDIP5
RDIP4
0x407F
TX_TS_B2_STATUS
RO
RDIP11
RDIP10
RDIP9
RDIP8
0x4080
TX_TS_C0_STATUS
RO
RDIP3
RDIP2
RDIP1
RDIP0
0x4081
TX_TS_C1_STATUS
RO
RDIP7
RDIP6
RDIP5
RDIP4
0x4082
TX_TS_C2_STATUS
RO
RDIP11
RDIP10
RDIP9
RDIP8
0x4083
TX_TS_D0_STATUS
RO
RDIP3
RDIP2
RDIP1
RDIP0
0x4084
TX_TS_D1_STATUS
RO
RDIP7
RDIP6
RDIP5
RDIP4
0x4085
TX_TS_D2_STATUS
RO
RDIP11
RDIP10
RDIP9
RDIP8
386
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Map (Entire PT Except RXT Block) (continued)
Table 322. PT Register Map (continued)
Note: Shading denotes reserved bits.
Address
Symbol
Type
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FIFO_
EmptyM
FIFO_
FullM
Mask Registers
0x4086
—
0x4095
TX_CH_Mask_0—
TX_CH_Mask_15
R/W
0x4096
—
0x40B5
—
—
0x40B6
TX_TS_A_Mask
R/W
RDIPM11
RDIPM10
RDIPM9
RDIPM8
RDIPM7
RDIPM6
RDIPM5
RDIPM4
RDIPM3
RDIPM2
RDIPM1
RDIPM0
0x40B7
TX_TS_B_Mask
R/W
RDIPM11
RDIPM10
RDIPM9
RDIPM8
RDIPM7
RDIPM6
RDIPM5
RDIPM4
RDIPM3
RDIPM2
RDIPM1
RDIPM0
0x40B8
TX_TS_C_Mask
R/W
RDIPM11
RDIPM10
RDIPM9
RDIPM8
RDIPM7
RDIPM6
RDIPM5
RDIPM4
RDIPM3
RDIPM2
RDIPM1
RDIPM0
0x40B9
TX_TS_D_Mask
R/W
RDIPM11
RDIPM10
RDIPM9
RDIPM8
RDIPM7
RDIPM6
RDIPM5
RDIPM4
RDIPM3
RDIPM2
RDIPM1
RDIPM0
0x40BA
—
0x4111
—
—
0x4112
—
0x4117
TX_Mask_A_1—
TX_Mask_A_6
R/W
RDIPM_TI
MA[1, 3, 5,
7, 9, 11]
RDIPM_LC
DA[1, 3, 5,
7, 9, 11]
RDIPM_PL
MA[1, 3, 5,
7, 9, 11]
RDIPM_UN
EQA[1, 3,
5, 7, 9, 11]
RDIPM_LO
PA[1, 3, 5,
7, 9, 11]
RDIPM_AIS
A[1, 3, 5, 7,
9, 11]
RDIPM_TI
MA[0, 2, 4,
6, 8, 10]
RDIPM_LC
DA[0, 2, 4,
6, 8, 10]
RDIPM_PL
MA[0, 2, 4,
6, 8, 10]
RDIPM_UN
EQA[0, 2,
4, 6, 8, 10]
RDIPM_LO
PA[0, 2, 4,
6, 8, 10]
RDIPM_AI
SA[0, 2, 4,
6, 8, 10]
0x4118
—
0x411D
TX_Mask_B_1
tiTX_Mask_B_6
R/W
RDIPM_TI
MB[1, 3, 5,
7, 9, 11]
RDIPM_LC
DB[1, 3, 5,
7, 9, 11]
RDIPM_PL
MB[1, 3, 5,
7, 9, 11]
RDIPM_UN
EQB[1, 3,
5, 7, 9, 11]
RDIPM_LO
PB[1, 3, 5,
7, 9, 11]
RDIPM_AIS
B[1, 3, 5, 7,
9, 11]
RDIPM_TI
MB[0, 2, 4,
6, 8, 10]
RDIPM_LC
DB[0, 2, 4,
6, 8, 10]
RDIPM_PL
MB[0, 2, 4,
6, 8, 10]
RDIPM_UN
EQB[0, 2,
4, 6, 8, 10]
RDIPM_LO
PB[0, 2, 4,
6, 8, 10]
RDIPM_AI
SB[0, 2, 4,
6, 8, 10]
0x411E
—
0x4123
TX_Mask_C_1—
TX_Mask_C_6
R/W
RDIPM_TI
MC[1, 3, 5,
7, 9, 11]
RDIPM_LC
DC[1, 3, 5,
7, 9, 11]
RDIPM_PL
MC[1, 3, 5,
7, 9, 11]
RDIPM_UN
EQC[1, 3,
5, 7, 9, 11]
RDIPM_LO
PC[1, 3, 5,
7, 9, 11]
RDIPM_AIS
C[1, 3, 5, 7,
9, 11]
RDIPM_TI
MC[0, 2, 4,
6, 8, 10]
RDIPM_LC
DC[0, 2, 4,
6, 8, 10]
RDIPM_PL
MC[0, 2, 4,
6, 8, 10]
RDIPM_UN
EQC[0, 2,
4, 6, 8, 10]
RDIPM_LO
PC[0, 2, 4,
6, 8, 10]
RDIPM_AI
SC[0, 2, 4,
6, 8, 10]
0x4124
—
0x4129
TX_Mask_D_1—
TX_Mask_D_6
R/W
RDIPM_TI
MD[1, 3, 5,
7, 9, 11]
RDIPM_LC
DD[1, 3, 5,
7, 9, 11]
RDIPM_PL
MD[1, 3, 5,
7, 9, 11]
RDIPM_UN
EQD[1, 3,
5, 7, 9, 11]
RDIPM_LO
PD[1, 3, 5,
7, 9, 11]
RDIPM_AIS
D[1, 3, 5, 7,
9, 11]
RDIPM_TI
MD[0, 2, 4,
6, 8, 10]
RDIPM_LC
DD[0, 2, 4,
6, 8, 10]
RDIPM_PL
MD[0, 2, 4,
6, 8, 10]
RDIPM_UN
EQD[0, 2,
4, 6, 8, 10]
RDIPM_LO
PD[0, 2, 4,
6, 8, 10]
RDIPM_AI
SD[0, 2, 4,
6, 8, 10]
0x412A
—
0x4131
—
—
0x4132
—
0x4141
TX_RW4_0—
TX_RW4_15
R/W
0x4142
—
0x4171
TX_RW1_0—
TX_RW1_47
R/W
0x4172
—
0x4181
TX_RW2_0—
TX_RW2_15
R/W
0x4182
—
0x4191
TX_RW3_0—
TX_RW3_15
R/W
Channel Provisioning Registers
Agere Systems Inc.
Z4_Byte
B3_disable
RDIP_Enh
_Mode
B3_Invert
SS_Bits
Z3_Byte
RDIP_Force
J1_Enb
Z5_Byte
RDIP_Bits
REIP_Force
REIP_Bits
C2_Byte
H4_Byte
387
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Map (Entire PT Except RXT Block) (continued)
Table 322. PT Register Map (continued)
Note: Shading denotes reserved bits.
Address
Symbol
Type
0x4192
—
0x4195
TX_alarm_A_1
TX_alarm_B_1
TX_alarm_C_1
TX_alarm_D_1
R/W
sel_alarm_1
sel_alarm_0
0x4196
—
0x4199
TX_alarm_A_2
TX_alarm_B_2
TX_alarm_C_2
TX_alarm_D_2
R/W
sel_alarm_3
sel_alarm_2
0x419A
—
0x419D
TX_alarm_A_3
TX_alarm_B_3
TX_alarm_C_3
TX_alarm_D_3
R/W
sel_alarm_5
sel_alarm_4
0x419E
—
0x41A1
TX_alarm_A_4
TX_alarm_B_4
TX_alarm_C_4
TX_alarm_D_4
R/W
sel_alarm_7
sel_alarm_6
0x41A2
—
0x41A5
TX_alarm_A_5
TX_alarm_B_5
TX_alarm_C_5
TX_alarm_D_5
R/W
sel_alarm_9
sel_alarm_8
0x41A6
—
0x41A9
TX_alarm_A_6
TX_alarm_B_6
TX_alarm_C_6
TX_alarm_D_6
R/W
sel_alarm_11
sel_alarm_10
0x41AA
—
0x41B1
—
—
0x41B2
—
0x41C1
TX_RW5_0—
TX_RW5_15
R/W
0x14C2
—
0x41E5
—
—
0x41E6
—
0x41E9
TX_TIMP_A—D
R/W
0x41EA
—
0x41ED
—
—
0x41EE
—
0x41EF
PT_Tx_DS3E3_[A—B]
R/W
0x41F0
—
0x41F9
—
—
0x41FA
—
0x41FD
TX_STS1_A—D
R/W
388
15
14
13
12
11
10
9
8
7
6
5
4
3
2
FIFO_Over_Value
1
0
FIFO_Under_Value
TIMP11
TIMP10
TIMP9
TIMP8
TIMP7
TIMP6
TIMP5
TIMP4
TIMP3
TIMP2
TIMP1
TIMP0
DS3E3[11]
DS3E3[10]
DS3E3[9]
DS3E3[8]
DS3E3[7]
DS3E3[6]
DS3E3[5]
DS3E3[4]
DS3E3[3]
DS3E3[2]
DS3E3[1]
DS3E3[0]
STS1_11
STS1_10
STS1_9
STS1_8
STS1_7
STS1_6
STS1_5
STS1_4
STS1_3
STS1_2
STS1_1
STS1_0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Path Terminator (PT) (continued)
PT Register Map (Entire PT Except RXT Block) (continued)
Table 322. PT Register Map (continued)
Note: Shading denotes reserved bits.
Address
Symbol
Type
0x41FE
—
0x4275
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x4276
TX_Cnfg_Alow
R/W
TS_A0
TS_A1
TS_A2
TS_A3
TS_A4
TS_A5
0x4277
TX_Cnfg_Ahigh
R/W
TS_A6
TS_A7
TS_A8
TS_A9
TS_A10
TS_A11
0x4278
TX_Cnfg_Blow
R/W
TS_B0
TS_B1
TS_B2
TS_B3
TS_B4
TS_B5
0x4279
TX_Cnfg_Bhigh
R/W
TS_B6
TS_B7
TS_B8
TS_B9
TS_B10
TS_B11
0x427A
TX_Cnfg_Clow
R/W
TS_C0
TS_C1
TS_C2
TS_C3
TS_C4
TS_C5
0x427B
TX_Cnfg_Chigh
R/W
TS_C6
TS_C7
TS_C8
TS_C9
TS_C10
TS_C11
0x427C
TX_Cnfg_Dlow
R/W
TS_D0
TS_D1
TS_D2
TS_D3
TS_D4
TS_D5
0x427D
TX_Cnfg_Dhigh
R/W
TS_D6
TS_D7
TS_D8
TS_D9
TS_D10
TS_D11
0x427E
—
0x429E
—
—
0x429F
TX_Stuffbyte_Cnfg
R/W
Time-Slot Configuration Registers
Stuffbyte Configuration Register
TS_A_0
TS_A_1
TS_A_2
TS_A_3
TS_B_0
TS_B_1
TS_B_2
TS_B_3
TS_C_0
TS_C_1
TS_C_2
TS_C_3
TS_D_0
TS_D_1
TS_D_2
TS_D_3
Transmit Sequence Map Registers (Bank A)
0x4300
—
0x430B
PT_TX_SEQMAP_A_AB
_[0—11]
R/W
PType_B
PM_B
CHID_B
PType_A
PM_A
CHID_A
0x4310
—
0x431B
PT_TX_SEQMAP_B_AB
_[0—11]
R/W
PType_B
PM_B
CHID_B
PType_A
PM_A
CHID_A
0x4320
—
0x432B
PT_TX_SEQMAP_A_CD
_[0—11]
R/W
PType_D
PM_D
CHID_D
PType_C
PM_C
CHID_C
0x4330
—
0x433B
PT_TX_SEQMAP_B_CD
_[0—11]
R/W
PType_D
PM_D
CHID_D
PType_C
PM_C
CHID_C
0x433C
—
0x437F
—
—
Transmit Sequence Map Registers (Bank B)
Agere Systems Inc.
389
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
Path Terminator (PT) (continued)
PT Register Map (Entire PT Except RXT Block) (continued)
Table 322. PT Register Map (continued)
Note: Shading denotes reserved bits.
Address
Symbol
Type
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
J1 Message Registers
0x4380
—
0x439F
Tx_J1Byte_0_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x43A0
—
0x43BF
Tx_J1Byte_1_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x43C0
—
0x43DF
Tx_J1Byte_2_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x43E0
—
0x43FF
Tx_J1Byte_3_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x4400
—
0x441F
Tx_J1Byte_4_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x4420
—
0x443F
Tx_J1Byte_5_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x4440
—
0x445F
Tx_J1Byte_6_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x4460
—
0x447F
Tx_J1Byte_7_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x4480
—
0x449F
Tx_J1Byte_8_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x44A0
—
0x44BF
Tx_J1Byte_9_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x44C0
—
0x44DF
Tx_J1Byte_10_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x44E0
—
0x44FF
Tx_J1Byte_11_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x4500
—
0x451F
Tx_J1Byte_12_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x4520
—
0x453F
Tx_J1Byte_13_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x4540
—
0x455F
Tx_J1Byte_14_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x4560
—
0x457F
Tx_J1Byte_15_[0—31]
R/W
J1_Byte_1
J1_Byte_0
0x4580
—
0x4587
—
—
390
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block
Introduction
This section describes the functions of the receive terminator block in the MARS2G5 P-Pro device. It is designed
to handle one STS-48 stream (single-channel mode) or four STS-12 or STS-3 streams (quad-channel mode) and
pass the data to the data engine block of the MARS2G5 P-Pro.
The RXT contains all the functionality of a pointer interpreter including path alarms, signal-fail detection,
performance monitoring, and path trace.
In OC-3 mode, the RXT still operates at an STS-12 rate and data bytes are replicated four times to achieve this as
shown in Figure 46.
STS-3
STS-12
#1 STS-1
#2 STS-1
#3 STS-1
#1 STS-1
1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1
#1 STS-1s #2 STS-1s #3 STS-1s
5-8151(F)r.2
Figure 46. Replication of STS-3 in OC-3 Mode into STS-12 Prior to Input of STS Receive Terminator
The RXT block requires a frame pulse for each input stream. In the MARS2G5 P-Pro device, these four signals are
provided from the pointer processor block. The RXT block performs performance monitoring of the input stream(s),
and can interrupt the host microprocessor with alarms and make available the collected results through a register
set.
The RXT is SONET and SDH compliant.
The pointer interpreter extracts the SONET synchronous payload envelope (SPE) from the incoming data by
interpreting the H1 and H2 pointer bytes of the line overhead. The SPE is then provided as an output of the RXT
block as a 32-bit bus. Since the RXT terminates the path, performance monitoring is performed and the RDI and
ERDI codes are passed to the SPE block (which accompanies the RXT block in MARS2G5 P-Pro) for insertion in
the outgoing stream. A detailed block diagram of the RXT is shown in Figure 47 on page 392. A brief description of
each block follows the diagram. For more detail on each block, refer to the appropriate section detailing the block.
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STS Receive Terminator (RXT) Block (continued)
Introduction (continued)
PATH
MONITOR
ALL 1s
DATA OUT
DATA IN
POINTER
INTERPRETER
AIS INSERT
J1 MARKER
SYNC PULSE
RECEIVE
TIMING
MICROPROCESSOR
INTERFACE
PERFORMANCE
MONITORING
5-8708(F)r.1
Figure 47. STS Receive Terminator (RXT) Functional Block Diagram
■
The pointer interpreter interprets the H1 and H2 bytes and determined the offset of each STS-1, as well as the
state of the STS-1 (AIS, LOP, concatenated, normal).
■
The receive timing block extracts the H1, H2, and H3 bytes from the incoming data for the pointer interpreter, and
uses the offset determined by the interpreter to create signals that are used to extract the SPE and the path overhead from the incoming data.
■
The path monitor implements the performance monitoring on the path overhead.
■
The AIS insert block allows AIS insertion under microprocessor control.
■
The microprocessor interface provides microprocessor registers to control the operation of the RXT and to read
the performance monitor data and RXT status.
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STS Receive Terminator (RXT) Block (continued)
Receive Timing Functions
The timing block generates the signals required by the pointer interpreter, elastic store, and performancemonitoring blocks. This block uses the frame pulse to create H1, H2, and STS indicators for the pointer interpreter.
The pointer interpreter provides increment, decrement, valid, and current pointer information for each STS which
allows the timing block to produce multiplexed POH indicators (i.e., J1, B3, etc.) and the associated valid SPE
signal for all STSs (SPE_VLD). The timing block has no indications of concatenation and thus produces POH
indicators for all STSs regardless of their concatenation state. The path overhead bytes are extracted by
subtracting the offset value for an STS-1 from an SPE byte counter (that counts from 0 to 782) to produce an 11-bit
signed number that indicates how far from J1 the current byte is. This value is compared to predetermined values
to find the individual overhead bytes. The compare values for each overhead byte are shown in Table 323 below.
Table 323. Path Overhead Extraction Compare Values
Overhead
Byte
Compare Value
(SPE byte offset)
J1
0
B3
+87 or –696
C2
+174 or –609
G1
+261 or –522
F2
+348 or –435
H4
+435 or –348
Z3
+522 or –261
Z4
+609 or –174
Z5
+696 or –87
The receive timing block also generates a POH byte signal, indicating that the current byte is part of the path
overhead. Because the drop interface may need indications of SPE and path overhead even when an STS-1 is in
AIS (to keep a FIFO from overrunning, for example), generic indications of SPE and POH are created. The generic
SPE indication is asserted for bytes in columns 4 through 90 inclusive and the generic POH indication is asserted
for bytes in column 4. The AIS insert block determines whether the actual or generic indications will be used for a
particular STS-1. If the pointer generator is not being bypassed, the equivalent signals will be created in the pointer
generator.
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STS Receive Terminator (RXT) Block (continued)
Pointer Interpreter Functions
The STS pointer interpreter interprets the H1 and H2 bytes for each incoming STS-1. The interpreter has four
states: loss of pointer (LOP), alarm indication signal (AIS), normal (NORM), and concatenation indication (CONC).
The state diagram is shown in Figure 48 on page 394.
3xAIS
CONC
AIS
3xCONC
NC
AI
S
8x
I
RM
NO DF
x
3 xN
1
8xInvalid
3x
3xAIS
CO
3xNORM
3xCONC
3x
nv
al
id
8xINVALID
8xNDF
NORM
LOP
3xNORM
5-8709(F)
Figure 48. Interpreter State Machine
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STS Receive Terminator (RXT) Block (continued)
Pointer Interpreter Functions (continued)
Incoming pointers are categorized into one or more of the following categories:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Normal pointer (NDF is not set and the offset is in range).
Normal pointer (offset = validated offset).
Normal pointer (offset = old offset—i.e., the same offset as in the last frame).
Valid NDF pointer (NDF set and offset is in range).
Concatenation indicator (NDF set with an all ones offset).
AIS pointer (all ones).
Increment indicator (compared to validated offset).
Decrement indicator (compared to validated offset).
Other (unrecognized pointer).
Note: A given pointer can be classified as belonging to more than one of the above groups. There are only a few
valid combinations:
■
1 and 2
■
1 and 3
■
1, 2, and 3
■
1 and 7
■
1 and 8
■
1, 3, and 7 (if the same pointer that created (1 and 7) repeats the next frame)
■
1, 3, and 8 (if the same pointer that created (1 and 8) repeats the next frame)
Increments and decrements can be evaluated in either SONET or SDH modes. In SONET mode, the 8 of 10 rule is
used, where 8 of the 10 I and D bits must be evaluated to be an increment or decrement for the pointer to be considered an increment or decrement. In SDH mode, the 3 of 5 rule is used, where 3 of the 5 I bits and 3 of the 5 D
bits must be evaluated to be an increment or decrement for the pointer to be considered and increment or decrement.
Note: In SDH mode, it is possible for a stuck input pointer to cause a repeating increment then decrement pattern.
To avoid this situation, increment and decrement pointers that are not perfect (10 of 10) are considered
invalid. See the description of the invalid counter for more details.
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STS Receive Terminator (RXT) Block (continued)
Pointer Interpreter Functions (continued)
Five counters are used in conjunction with the pointer categories to determine the state of the state machine.
These counters are the following:
■
norm_cnt—counts how many consecutive times condition 3 occurs (condition (1 and !3) will preset this counter
to 1).
■
ndf_cnt—counts how many consecutive times condition 4 occurs.
■
ais_cnt—counts how many consecutive times condition 6 occurs.
■
invalid_cnt—counts how many consecutive times conditions.
(next state is NORM and !2 and !4 and !6 and !7* and !8* and !((norm_cnt ==2) and 3)) or
(next state is AIS and !6) or
(next state is CONC and !5 and !6) occurs.
■
concat_cnt—counts how many consecutive times condition 5 occurs.
* See details below.
The norm_cnt counter will be preset to 1 when condition 1 occurs and condition 3 doesn’t occur. In other words, if
a normal pointer is received that is not the same offset as the last pointer received, the norm_cnt is set to 1.
Note: Invalid_cnt counts increments and decrements as being invalid while in the NORM state if there is less than
a 10 of 10 match in the I and D bits. For example, a pointer with all of the I bits inverted and 4 of the D bits not
inverted would be counted as an invalid pointer, and an increment would be performed. NDF pointers are
considered valid while in the NORM state. NDF pointers are counted separately with ndf_cnt. In AIS state,
any pointer that is not an AIS pointer is considered invalid. In CONC state, any pointer that is not a concatenation indication or an AIS pointer is considered invalid.
The count condition is evaluated at the same time as the state is evaluated. Therefore, the counter is not actually
incremented or cleared until after the state has been evaluated. Thus, the pointer condition must also be used to
evaluate the state.
If any of the conditions for a counter do not occur, the counter is cleared.
The state machine will change states based on the following conditions.
Note: If the conditions indicate that there are two possible states to change to, the one listed first will be taken.
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STS Receive Terminator (RXT) Block (continued)
Pointer Interpreter Functions (continued)
The state changes from LOP to:
■
AIS—when (ais_cnt == 2) and condition 6 occurs.
■
NORM—when (norm_cnt == 2) and condition 3 occurs.
■
CONC—when (concat_cnt == 2) and condition 5 occurs.
The state changes from AIS to:
■
NORM—when (norm_cnt == 2) and condition 3 occurs or condition 4 occurs.
■
CONC—when (concat_cnt == 2) and condition 5 occurs.
■
LOP—when (invalid_cnt == 7) and condition 6 does not occur.
The state changes from NORM to:
■
AIS—when (ais_cnt == 2) and condition 6 occurs.
■
CONC—when (concat_cnt == 2) and condition 5 occurs.
■
LOP—when (invalid_cnt == 7) and condition 2 does not occur or (ndf_cnt == 7) and condition 4 occurs.
The state changes from CONC to:
■
AIS—when (ais_cnt == 2) and condition 6 occurs.
■
NORM—when (norm_cnt == 2) and condition 3 occurs.
■
LOP—when (invalid_cnt == 7) and condition 5 does not occur.
Note: When changing states, NORM, CONC, and AIS always take precedence over LOP (NORM, CONC, and AIS
being mutually exclusive).
The pointer interpreter provides outputs to indicate the following:
■
AIS-P and LOP-P defect indications on a per-STS-1 basis (RAW_AIS_P, RAW_LOP_P).
■
A per-STS-1 indication of CONC state (RECD_CONC_MAP).
■
A per-STS-1 indication of pointer state (STS_OK)—indicates that an STS-1 is in NORM state, or if it is in CONC
state and the first STS-1 in the concatenated STS-Nc is in NORM state.
■
A per-STS-1 indication of receipt of an all 1s pointer—this is used by the pointer generator to generate and allones pointer in order to meet the all-ones pointer relay objective in GR-253.
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STS Receive Terminator (RXT) Block (continued)
Concatenation
In the diagrams, the squares represent bytes coming into the RXT. Each diagram represents a different RXT
configuration. The numbers in the squares represent the order in which the bytes are received. The numbers to the
left of each square represent the SONET ordering. Each byte belongs to a separate STS-1 signal. The shaded
squares represent the possible starting points for concatenated STS signals (these are the N,1 STS-1 numbers
shown in GR-253 in Chapter 5).
1
1
4
2
7
3
10
4
2
5
5
6
8
7
11
8
3
9
6
10
9
11
12
12
STS-12
POINTER
5-8710(F)
Figure 49. STS-12 RXT Concatenated Offset Passing
1
1
4
2
2
3
5
4
3
5
6
6
STS-6
POINTER
5-8711(F)
Figure 50. STS-6 RXT Concatenated Offset Passing
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STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
1
1
2
2
3
3
STS-3
POINTER
1
STS-1
POINTER
1
5-8712(F)
Figure 51. STS-3 and STS-1 RXT Concatenated Offset Passing
The arrows indicate how offsets are propagated between concatenated STS-1s. Offsets are propagated during the
H2 time. If an STS-1 is in concatenation state, it will use the offset from the STS-1 indicated by the arrow. For
example, if an STS-6c were constructed in an STS-12 RXT starting with STS-1 number 4 (SONET ordering) in the
STS-12 diagram, then STS-1 number 4 will be in NORM state, and STS-1 numbers 5, 6, 7, 8, and 9 would be in
CONC state. STS-1 numbers 5 and 7 would get their offset from STS-1 number 4. STS-1 number 8 would get its
offset from STS-1 number 7. STS-1 number 6 would get its offset from STS-1 number 5 and STS-1 number 9
would get its offset from STS-1 number 8. This example is shown in Figure 52 below. Note that in this situation, offsets are always passed to STS-1s that arrive later in time. This method will work for constructing any size and
number of concatenated streams within an STS-12.
1
1
4
2
7
3
10
4
STS-12
POINTER
2
5
5
6
8
7
11
8
3
9
6
10
9
11
12
12
5-8713(F)r.1
Figure 52. STS-6c Offset Passing in an STS-12 RXT
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STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
The propagated offset for an STS-1 in the CONC state is stored in the same register as the validated offset is
stored if the STS-1 is in the NORM state. In addition to the offset itself, increment, decrement, and valid offset indications are propagated to concatenated STS-1s.
If any STS-1s are concatenated with STS-1s from a different STS-12 processing block, the offset must be passed
between blocks. Also, if any STS-1s from other blocks are concatenated to STS-1s in this block, an offset must be
passed to the next block. More specifically, if STS-1 number 1 is concatenated, it will receive its offset from STS-1
number 10 (SONET ordering) from the previous block. Note that the offset for STS-1 number 10 is not valid until
after the fourth clock of the H2 byte, which occurs after the state machine for STS-1 number 1 of the next STS-12
block has been processed. Thus, the offset for STS-1 number 1 and any subsequent concatenated STS-1s cannot
be processed until after the fourth byte. This means that the offsets of concatenated STS-1s must be updated after
that STS-1s state machine has been processed. This is accomplished by enabling the register that stores the propagated offset just before the H3 byte of that STS-1. This means the offset must be able to reach all STS-1s in the
concatenation in at least two thirds of a byte time (approximately 100 ns). RXTs configured as STS-1 or STS-3 will
have a whole byte time (approximately 150 ns).
A further problem occurs when several STS-12 blocks contain one large STS-Nc signal. Each block after the first
would have to wait until the previous block has a valid offset for STS-1 number 10, then propagate the offset
through to the next STS-12 block, which would take another four clocks (to propagate from STS-1 number 1 to
STS-1 number 10 and out). For an STS-192c, it would take 66 clocks to propagate the offset to the last STS-1,
using an STS-12 RXT. This is considerably more than the 12 clocks during which the H2 byte is being received for
all STS-1s. To alleviate this problem, a MUX is added such that if all possible STS-1s are concatenated in a block
(numbers 1, 4, 7, and 10 for an STS-12 block or 1 and 4 for an STS-6 block), the output offset comes directly from
the concatenation input offset rather than from STS-1 number 10. This way, once the fourth STS-1 state machine is
processed in each STS-12 block (STS-1 number 10), the offset is made available to all subsequent STS-12 blocks.
This does, however, result in significant combinational logic between flip-flops; the offset may go through up to 14
2:1 MUXes. Thus, in the actual implementation, a 4:1 MUX is used, which can take the output offset from any one
of the previous three RXTs. This results in a maximum of five 4:1 MUXes the offset may go through for an STS192c, using STS-12 RXTs. The passing of the offsets for concatenation is illustrated in Figure 53. The MUXes are
selected to pass the offset from as close to the head of the concatenation as possible.
RXT N
RXT N + 1
RXT N + 2
RXT N + 3
5-8714(F)r.2
Figure 53. Concatenated Offset Passing
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STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
To ensure that concatenated payloads go through the elastic store in the correct order, the address counter of a
concatenated STS-1 is synchronized to the address counter of the STS-1 at the head of the concatenation. Within
an RXT, the address of the head of the concatenation is simply passed to the concatenated STS-1s. When the
STS-1 at the head of the concatenation is in a different RXT, a synchronization signal is passed from the last STS1 of the previous RXT (actually, the last STS-1 on an STS-3 boundary) that indicates that the first STS-1 in the
RXT should go to address 0 on the next byte. In this way, all of the STS-1s in the concatenation will have the same
elastic store address at the same time. The synchronization signal is passed through a 4:1 MUX structure in the
same way that concatenation offsets are passed in the pointer interpreter.
Path Trace (J1)
The path trace byte carries a repeating message that is defined in SONET as 64 bytes (ASCII, <CR><LF> terminated) and in SDH as 16 bytes (E.164). The POH processor extracts either type of message from one selectable
STS-1 per channel and stores the message in an internal register bank. The contents of the message can then
optionally be monitored for either a mismatch from a provisioned expected message or a sustained change in the
received message. A mismatch is declared if the received message differs from the expected message for ten consecutive messages. The mismatch clears when 4-out-of-5 received messages match the expected message. A
sustained change is detected when the received message differs from the last stable message for ten consecutive
messages. The new message then becomes the stable message and the processor starts checking for a sustained change from this new stable message (i.e., there is no clearing criteria for a sustained change). Both defects
are indicated by corresponding latched alarm status bits in the memory map. The detection of a mismatch could
result in AIS insertion if provisioned through software.
Selection of the message protocol, 16-byte or 64-byte, the content monitoring option and the monitored STS channel are provisionable on a per-channel basis through the path trace control register in the microprocessor interface. The expected messages for all channels are provisioned through the microprocessor interface using a 64byte data buffer. This data buffer is also used to read the contents of the expected, stable or received message
buffers for all blocks. Accesses using the data buffer are paged according to channel and message buffer
(expected/stable or received). Selection of paging as well as access type (read or write) is done using the path
trace access control register. The actual access is triggered by writing a 0x0001 (hex) value to the path trace
access start register and is performed on a non-real-time basis. Completion of the access is indicated by the message buffer access complete bit in the path trace status register being set.
Path BIP-8 (B3)
The path BIP-8 byte carries the even parity of the data in the previous STS SPE frame (783 bytes for STS-1,
Nx783 for STS-Mc). Every frame the received B3 value is extracted and compared to the calculated BIP-8 for the
previous frame. Detected errors are accumulated in an internal 16-bit counter based on either bit or block errors as
provisioned per channel through the microprocessor interface. If bit error mode is enabled for the channel, each
BIP-8 bit found in error causes the counter to increment. If block error mode is enabled for the channel, the counter
is only incremented by one regardless of the number of BIP-8 bits in error. The value in the counter is transferred
to the path coding violation (CV-P) registers on the positive edge of the performance-monitoring strobe (PMSTB
input) at which point the counter is cleared.
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STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
Signal Fail Alarms. Each of the 48 STS-1s entering the RXT can be automatically monitored for B3 errors against
a programmable threshold. Concatenated payloads are supported by programming the threshold values for the
head STS-1.
Each STS-1 or head of an STS-NC has a select to choose which threshold group’s parameters to compare against.
There are eight threshold groups available, each group consisting of:
■
Set Threshold. If the B3 errors is equal or greater than this value in the given time window, the signal fail alarm
for this STS-1 is set. The B3 count in subsequent window times must be less than the clear threshold listed
below to clear this error condition.
■
Set Threshold Window Select. There are four time windows available between the eight groups. The set
threshold window select can be set to one of these window sizes.
■
Clear Threshold. If the signal fail alarm has been previously set, it will be cleared if an entire clear window time
goes past with the B3 error count less than this value.
■
Clear Threshold Window Select. If the signal fail alarm has been previously set, this window size will be used
to measure B3 errors.
Each STS-1 has a 9-bit B3 counter, which is incremented every time a B3 error appears. If STSs are part of an
STS-Nc, there is one 14-bit counter for the entire concatenation. This counter is cleared at the end of the window
selected for the threshold group for which this STS-1 or STS-Nc is set to. This counter (9 or 14 bits) can be incremented by 0 (if no B3 errors occurred) or up to eight counts (if all the bits in the B3’s BIP-8 calculation are opposite
from expected). Note there are no bit/block issues with the signal fail counters; only bit errors are counted. Bit/block
is only an option for the B3 counters in the path monitoring (PM).
The signal fail alarm is set if the number of B3 errors for an STS-1 or STS-Nc is above the set threshold within this
window time. The B3 error counter for each STS-1 or STS-Nc is cleared at the end of each window and counts up
again in the next window.
One can set an individual STS-1/STS-Nc to set an alarm on one BER and clear this alarm on another. For this, a
threshold count value and timing window is provided for both set and clear.
For each STS-1 or STS-Nc, its B3 counter is running for either the time set by the set threshold window or the time
set by the clear threshold window. If this STS-1/STS-Nc is in the clear state (the alarm bit is clear), then the signal
fail circuitry will be looking for the case when the number of B3 errors equals or exceeds the set threshold. The
counter will be running for the duration of the set threshold window. If this condition is reached, the alarm will be set
immediately and the system will switch to watching the desired clear window. It will wait until the clear window has
completed its current cycle and will start counting B3 errors again in the next cycle. The B3 counter will be cleared
and B3 errors will be added, and at the end of this window time (now the clear window time), the decision will be
made to clear the alarm condition or not. If the number of B3 errors in the counter is less than the clear threshold,
the alarm will be cleared and during the next window of length = set threshold window size the counter will be compared to the set threshold. Otherwise, this error condition will remain set and another window of duration = clear
threshold window size will commence.
The signal fail alarm can be set anywhere during the window, but can only be cleared at the end of a window time.
The RXT is either checking for the set or clear condition for an STS-1/STS-Nc at a given time. One implication of
this is that if the clear threshold was set for a BER higher than the set threshold and an incoming signal of a constant BER between the two was present, the signal fail alarm would oscillate, set, and clear with a period of zero to
one times the set window threshold window time plus one to two times the period of the clear window threshold
window time.
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STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
There are eight threshold groups available (see Table 413—Table 416); two are labelled as being used for STS-1s
(group 0 and 1) and six (groups 2—7) are labelled for use as STS-Ncs. Group 0 and 1 have set and clear thresholds of 9 bits (0—511) whereas groups 2—7 have set and clear thresholds of up to 14 bits (0—16383). This is to
accommodate the higher data rate of a concatenated payload and thus the higher number of bit errors one would
see in the same time window for the same BER. However, one could point an STS-1 to group 2—7 as long as the
thresholds are set to 511 or less to stay within the 9-bit size of an individual STS-1s counter.
There are four threshold window size registers, each 16 bits, in increments of 0.5 ms (for a maximum of window
size of 32 seconds).
The table below shows the recommended set/clear threshold and window values for the BER they are intended for.
Table 324. Set/Clear Threshold and Window Settings
Intended
for STS-1
or STS-Nc
Threshold
Type
Desired BER to
Detect
Threshold
Threshold Window
Select
STS-1
Set
BER = 10–3
0x6C
0xA
Clear
BER = 10–4
0x22
0xA
Set
BER = 10–4
0xC9
0x64
Clear
BER = 10–5
0x27
0x64
Set
BER = 10–5
0xCF
0x3E8
Clear
BER = 10–6
0x24
0x3E8
Set
BER = 10–3
0x8A
0xA
Clear
BER = 10–4
0x49
0xA
Set
BER = 10–4
0x226
0x64
Clear
BER = 10–5
0x59
0x64
Set
BER = 10–5
0x2B0
0x3E8
Clear
BER = 10–6
0x60
0x3E8
Set
BER = 10–3
0x89
0xA
Clear
BER = 10–4
0x76
0xA
Set
BER = 10–4
0x39B
0x64
Clear
BER = 10–5
0xA8
0x64
Set
BER = 10–5
0x53A
0x3E8
Clear
BER = 10–6
0xAC
0x3E8
STS-1
STS-1
STS-3c
STS-3c
STS-3c
STS-6c
STS-6c
STS-6c
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Data Sheet
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STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
Table 324. Set/Clear Threshold and Window Settings (continued)
Intended
for STS-1
or STS-Nc
Threshold
Type
Desired BER to
Detect
Threshold
Threshold Window
Select
STS-9c
Set
BER = 10–3
0x8D
0xA
Clear
BER = 10–4
0x89
0xA
Set
BER = 10–4
0x47E
0x64
Clear
BER = 10–5
0xED
0x64
Set
BER = 10–5
0x7CA
0x3E8
Clear
BER = 10–6
0x103
0x3E8
Set
BER = 10–3
0x8D
0xA
Clear
BER = 10–4
0x9D
0xA
Set
BER = 10–4
0x50B
0x64
Clear
BER = 10–5
0x139
0x64
Set
BER = 10–5
0xA3F
0x3E8
Clear
BER = 10–6
0x14C
0x3E8
Set
BER = 10–3
0x8E
0xA
Clear
BER = 10–4
0xA4
0xA
Set
BER = 10–4
0x573
0x64
Clear
BER = 10–5
0x178
0x64
Set
BER = 10–5
0xC92
0x3E8
Clear
BER = 10–6
0x199
0x3E8
Set
BER = 10–3
0x89
0xA
Clear
BER = 10–4
0xA9
0xA
Set
BER = 10–4
0x5A4
0x64
Clear
BER = 10–5
0x1B5
0x64
Set
BER = 10–5
0xEE2
0x3E8
Clear
BER = 10–6
0x1E5
0x3E8
STS-9c
STS-9c
STS-12c
STS-12c
STS-12c
STS-15c
STS-15c
STS-15c
STS-18c
STS-18c
STS-18c
404
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
Table 324. Set/Clear Threshold and Window Settings (continued)
Intended
for STS-1
or STS-Nc
Threshold
Type
Desired BER to
Detect
Threshold
Threshold Window
Select
STS-21c
Set
BER = 10–3
0x8E
0xA
Clear
BER = 10–4
0xB2
0xA
Set
BER = 10–4
0x5C8
0x64
Clear
BER = 10–5
0x1E8
0x64
Set
BER = 10–5
0x10F8
0x3E8
Clear
BER = 10–6
0x23F
0x3E8
Set
BER = 10–3
0x8D
0xA
Clear
BER = 10–4
0xB0
0xA
Set
BER = 10–4
0x5D1
0x64
Clear
BER = 10–5
0x224
0x64
Set
BER = 10–5
0x1317
0x3E8
Clear
BER = 10–6
0x280
0x3E8
Set
BER = 10–3
0x8C
0xA
Clear
BER = 10–4
0xAF
0xA
Set
BER = 10–4
0x5F2
0x64
Clear
BER = 10–5
0x253
0x64
Set
BER = 10–5
0x151B
0x3E8
Clear
BER = 10–6
0x2C0
0x3E8
Set
BER = 10–3
0x8C
0xA
Clear
BER = 10–4
0xB0
0xA
Set
BER = 10–4
0x5E9
0x64
Clear
BER = 10–5
0x27E
0x64
Set
BER = 10–5
0x16D6
0x3E8
Clear
BER = 10–6
0x316
0x3E8
STS-21c
STS-21c
STS-24c
STS-24c
STS-24c
STS-27c
STS-27c
STS-27c
STS-30c
STS-30c
STS-30c
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Data Sheet
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STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
Table 324. Set/Clear Threshold and Window Settings (continued)
Intended
for STS-1
or STS-Nc
Threshold
Type
Desired BER to
Detect
Threshold
Threshold Window
Select
STS-33c
Set
BER = 10–3
0x8C
0xA
Clear
BER = 10–4
0xB2
0xA
Set
BER = 10–4
0x5FC
0x64
Clear
BER = 10–5
0x2CC
0x64
Set
BER = 10–5
0x189C
0x3E8
Clear
BER = 10–6
0x366
0x3E8
Set
BER = 10–3
0x90
0xA
Clear
BER = 10–4
0xB0
0xA
Set
BER = 10–4
0x603
0x64
Clear
BER = 10–5
0x2DB
0x64
Set
BER = 10–5
0x1A65
0x3E8
Clear
BER = 10–6
0x3AF
0x3E8
Set
BER = 10–3
0x8B
0xA
Clear
BER = 10–4
0xB4
0xA
Set
BER = 10–4
0x601
0x64
Clear
BER = 10–5
0x312
0x64
Set
BER = 10–5
0x1BC9
0x3E8
Clear
BER = 10–6
0x3EF
0x3E8
Set
BER = 10–3
0x93
0xA
Clear
BER = 10–4
0xB6
0xA
Set
BER = 10–4
0x601
0x64
Clear
BER = 10–5
0x336
0x64
Set
BER = 10–5
0x1D5F
0x3E8
Clear
BER = 10–6
0x436
0x3E8
STS-33c
STS-33c
STS-36c
STS-36c
STS-36c
STS-39c
STS-39c
STS-39c
STS-42c
STS-42c
STS-42c
406
Agere Systems Inc.
Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
Table 324. Set/Clear Threshold and Window Settings (continued)
Intended
for STS-1
or STS-Nc
Threshold
Type
Desired BER to
Detect
Threshold
Threshold Window
Select
STS-45c
Set
BER = 10–3
0x8A
0xA
Clear
BER = 10–4
0xB3
0xA
Set
BER = 10–4
0x607
0x64
Clear
BER = 10–5
0x363
0x64
Set
BER = 10–5
0x1EEF
0x3E8
Clear
BER = 10–6
0x488
0x3E8
Set
BER = 10–3
0x8E
0xA
Clear
BER = 10–4
0xB3
0xA
Set
BER = 10–4
0x5FF
0x64
Clear
BER = 10–5
0x38D
0x64
Set
BER = 10–5
0x3E8
0x3E8
Clear
BER = 10–6
0x4C8
0x3E8
STS-45c
STS-45c
STS-48c
STS-48c
STS-48c
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Data Sheet
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STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
Below are the default threshold window sizes.
Table 325. Default Signal Fail Window Size Settings
Window Size Register
Time
Register Setting
Window Size 0
5 ms
0x000A
Window Size 1
50 ms
0x0064
Window Size 2
500 ms
0x03e8
Window Size 3
5s
0x2710
Note 1: If the window size is set to 0x0000, it will provide a 0.5 ms window, the same as if it was set to 0x0001.
Note 2: If a window size register is changed, each current window will be cut short and will finish from one to two
time units (0.5 ms to 1 ms if the block is running in 90 columns) before the new window size is loaded. For
example, if the column size is 90, and window size 3 was changed, it will not take from 0 to up to 5 seconds
to start running with the new window size, but rather 0.5 ms to 1 ms.
Note 3: The unit of time in the window size register is 0.5 ms if the block is running in 90 column mode. This unit of
time is equal to four STS-frame sizes (4 x 125 µs = 0.5 ms). If the user is operating with a number of columns other than 90, such as the so-called short frame mode (where the number of columns in a frame is
less than 90 columns for reduced simulation and testing time), then the unit of time for the window size
registers is no longer 0.5 ms, but rather four times the frame size.
B3 Calculation. The B3 is calculated on the TDM data stream coming from the pointer interpreter. It is calculated
using a continuously cycling 8-bit wide shift register that is N bytes deep (where N is the number of STS-1s being
handled by the RXT). Incoming data is XORed with the value coming out the end of the shift register, if the
SPE_VLD signal from the receive timing module is asserted, and loaded into the input of the shift register. If
SPE_VLD is not asserted, the value coming out of the end of the shift register is not modified before loading it into
the input of the shift register. If the J1 indication is present from the receive timing module, the data value (J1 byte)
is loaded directly into the input of the shift register to begin the calculation for the next frame, and the value coming
out of the shift register is loaded into a holding register. This is the calculated BIP-8 for the last SPE frame.
In the case of concatenation, each STS-1 in the STS-Nc stream calculates a BIP-8 for its part of the concatenated
SPE. After the J1 byte, the last STS-1 in the concatenation will pass its BIP calculation to the previous STS-1 in the
concatenation, which will XOR the incoming BIP with its own and pass the result on to the next previous STS-1,
and so on. When the first STS-1 in the concatenation is reached, the BIP is not passed on. The concatenation is
determined by the pointer interpreter received concatenation map. Thus, if an STS-1 erroneously enters the CONC
state, the B3 calculation will cause errors on the previous STS-1, which is assumed to be the first STS-1 in the concatenation.
When the B3 byte arrives in the next SPE, it is compared to the calculated B3 and the result is loaded back into the
holding register. The contents of the holding register are then shifted out serially to be used as the enable for the
binning counter.
408
Agere Systems Inc.
Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
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STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
Path Signal Label (C2)
The path signal label byte is used to indicate either the type of payload carried in the STS SPE or the status of the
payload. Of the 256 possible values, only the codes 0x01 to 0x04 and 0x12 to 0x15 are currently defined to identify
payload types, while the codes 0xE1 to 0xFC are defined to indicate payload defects (see STS Path Signal Label
Assignments, Table 326, on page 410). The code 0xFF is a special reserved code due to its appearance in an STS
AIS and is treated as a don’t care during any defect detection or clearing. The C2 byte is extracted each frame and
stored in the receive signal label registers. If the locally provisioned value, configured in the expected signal label
registers, is any equipped value (i.e., not 0x00), the extracted signal label is also processed for the following
defects:
■
Payload Label Mismatch (PLM). Detected if the extracted signal label is a valid payload specific code and does
not match the locally provisioned value in the expected signal label registers for five consecutive frames.
Cleared if the extracted signal label matches the locally provisioned value, the equipped nonspecific code
(0x01), or a valid PDI code for five consecutive frames. If the locally provisioned value is the equipped nonspecific code, then it matches any valid equipped code. The valid payload specific codes are by default 0x02 to
0xE0, 0xFD and 0xFE, with the codes 0xE1 to 0xFB also included if the locally provisioned payload is VT-structured (0x02 or 0x03). If payload defect indication detection is disabled, 0xE1 to 0xFC are always included.
Detection of a PLM defect is indicated by a latched alarm status bit in the memory map, and could result in AIS
insertion if provisioned through software.
■
Path Unequipped (UNEQ). Detected if the extracted signal label matches the unequipped code (0x00) for five
consecutive frames. Cleared if the extracted signal label does not match the unequipped code for five consecutive frames. Detection of an UNEQ defect is indicated by a latched alarm status bit and a one second PM in the
memory map, and could result in AIS insertion if provisioned through software.
■
Payload Defect Indication (PDI). Detected if the extracted signal label matches a valid PDI code for five consecutive frames. Cleared if the extracted signal label does not match a valid PDI code for five consecutive
frames. Valid PDI codes are 0xE1 to 0xFC when the locally provisioned payload label is 0x01, 0x02, or 0x03
(VT-structured STS) or just 0xFC otherwise. PDI detection can be disabled per STS through the microprocessor
interface.
■
Update. The C2 value is dumped into an MPU register. Each time the captured value changes, a delta bit is set.
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Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
Table 326. STS Path Signal Label Assignments
Code (Hex)
410
Content of the STS SPE
Code (Hex)
Content of the STS SPE
0x00
Unequipped
0x12
Asynchronous mapping for DS4NA
0x01
Equipped—nonspecific payload
0x13
Mapping for ATM
0x02
VT-structured STS-1 SPE
0x14
Mapping for DQDB
0x03
Locked VT mode
0x15
Asynchronous mapping for FDDI
0x04
Asynchronous mapping DS3
0x16
Mapping for HDLC-PPP (proposed)
0xE1
VT-structured STS-1 SPE with 1 VTx
payload defect (STS-1 w/1 VTx PD)
0xEF
STS-1 w/15 VTx PDs
0xF0
STS-1 w/16 VTx PDs
0xF1
STS-1 w/17 VTx PDs
0xE2
STS-1 w/2 VTx PDs
0xF2
STS-1 w/18 VTx PDs
0xE3
STS-1 w/3 VTx PDs
0xF3
STS-1 w/19 VTx PDs
0xE4
STS-1 w/4 VTx PDs
0xF4
STS-1 w/20 VTx PDs
0xE5
STS-1 w/5 VTx PDs
0xF5
STS-1 w/21 VTx PDs
0xE6
STS-1 w/6 VTx PDs
0xF6
STS-1 w/22 VTx PDs
0xE7
STS-1 w/7 VTx PDs
0xF7
STS-1 w/23 VTx PDs
0xE8
STS-1 w/8 VTx PDs
0xF8
STS-1 w/24 VTx PDs
0xE9
STS-1 w/9 VTx PDs
0xF9
STS-1 w/25 VTx PDs
0xEA
STS-1 w/10 VTx PDs
0xFA
STS-1 w/26 VTx PDs
0xEB
STS-1 w/11 VTx PDs
0xFB
STS-1 w/27 VTx PDs
0xEC
STS-1 w/12 VTx PDs
0xFC
0xED
STS-1 w/13 VTx PDs
0xEE
STS-1 w/14 VTx PDs
VT-structured STS-1 SPE with
28 VT1.5 payload defects, or a nonVT-structured STS-1 or STS-Nc SPE
with a payload defect
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
Below is a table detailing the conditions and alarms created by different states of the provisioned (expected) and
received (incoming) path label found in the C2 byte.
Table 327. Payload Label Conditions
Expected C2 Value Set in Microprocessor Register
—
Incoming C2 Byte
0x00
0x01
0x02 or
0x03
0x04—0xE0 0xE1—0xFB
0xFD—0xFE
Received
C2 Value
(incoming)
Unequipped
Nonspecific
equipped
VT
structured
payload
Non-VT
structured
payload
0x00
None
UNEQ-P
UNEQ-P
UNEQ-P
0x01
None
Match
Match
Match
0x02 or 0x03
None
Match
Match or
PLM-P
PLM-P
0x04—0xE0
0xFD—0xFE
None
Match
PLM-P
Match or
PLM-P
0xE1—0xFB
None
PDI-P
PDI-P
PLM-P
0xFC
None
PDI-P
PDI-P
PDI-P
0xFF
None
Hold
Hold
Hold
1—27
VT path
defects
0xFC
0xFF
28-VT path
defects
AIS
Nonsensical provisioning
Note: The expected C2 byte is only used as a programming mode, i.e., changing the value does not reset the validation counters (unequipped and payload mismatch).
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Data Sheet
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STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
Path Status (G1)
The path status byte is used to convey the path termination status and performance back to the originating STS
PTE. This allows the performance of the full-duplex path to be monitored from any single point along the path. Bits
1 to 4 are used as a remote error indication (formerly far end block error or FEBE), while bits 5 to 7 are used as a
remote defect indication. The G1 byte is extracted each frame and processed for these functions as described
below.
■
Remote Error Indication (REI-P). Indicates the count of bit errors detected at the far-end STS PTE using the
path BIP-8. The error count is a binary number from 0 to 8 (values above 8 are invalid and interpreted as 0) and
is accumulated in an internal 16-bit counter based on either bit or block errors as provisioned per channel
through the microprocessor interface. If bit error mode is enabled for the channel, the counter is incremented by
the actual error count. If block error mode is enabled for the channel, the counter is only incremented by one,
when the error count is not 0, regardless the actual value. The value in the counter accumulates until it is transferred to the REI-P registers on the positive edge of the performance-monitoring strobe (PMSTB input) at which
point the counter is cleared.
■
Remote Defect Indication (RDI-P). Indicates the detection of a defect at the far-end STS PTE. Initially, RDI-P
was defined as a one-bit value in bit 5, but has since been expanded to a 3-bit enhanced value (ERDI-P).
Table 328 shows the valid codes and interpretation for both the 1-bit and enhanced RDI schemes. As can be
seen, bits 6 and 7 are always set to opposite values for ERDI while they are set to the same value for 1-bit RDI.
The POH uses this fact to determine which RDI scheme is being used on a per STS basis. An RDI-P defect is
then detected if a valid defect code for one of the RDI schemes is received for ten consecutive frames. The RDIP defect is cleared when the no defects code for that scheme is received for ten consecutive frames. The value
of the last validated 3-bit RDI code is stored in the ERDI-P registers in the memory map. In addition, detection of
a 1-bit RDI defect or each of the three ERDI defects is indicated by a one second PM bit in the memory map.
Table 328. RDI-P Codes and Interpretation
G1[5:7]
Priority of Enhanced RDI-P Codes
Trigger
Interpretation
0xx*
Not applicable
No defects
No RDI-P defect
1xx*
Not applicable
AIS-P, LOP-P
1-bit RDI-P defect
001†
4
No defects
No ERDI-P defects
010†
3
PLM-P, LCD-P
ERDI-P payload defect
101†
1
AIS-P, LOP-P
ERDI-P server defect
110†
2
UNEQ-P, TIM-P
ERDI-P connectivity defect
* These codes are transmitted by STS PTE that do not support enhanced RDI-P. If enhanced RDI-P is not supported, G1 bits 2 and 1 must be
set to the same value, and should be set to 00.
† These codes are transmitted by STS PTE that support enhanced RDI-P.
412
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155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
Concatenation (continued)
Interrupt Alarms and Masks
The following path conditions create alarms and set bits in the alarm registers. There is a bit for each STS-1.
■
Path LOP.
■
Path AIS.
■
Path UNEQ—unequipped alarm.
■
Path PLM—path label mismatch.
■
Path RDI—remote defect indicator.
■
SF—path signal fail.
■
Elastic store overrun, underrun.
The following conditions also create alarms:
■
Concatenation mismatch—the received concatenation map does not match the expected map.
■
Unsupported concatenation.
■
J1 validated—a new path trace message has come in and is validated. This occurs when the stream is set to
receive mode.
■
J1 mismatch—the path trace message that has come in does not match the provisioned one. This alarm occurs
when the stream is set to provision mode.
There is a control bit that sets whether the alarm registers are cleared by writing a one to that bit or by just reading
the register. This control bit is in the clear on read/write register.
The alarms can be masked so they do not cause an interrupt by setting the corresponding interrupt alarm mask bit
to 1. A 0 in the mask bit allows the interrupt to be generated.
The interrupt registers are categorized into three levels, a base level, and two levels of binning registers, which
accumulate alarm conditions that were not masked from the previous level. These binning registers facilitate a
faster identification of the alarm condition by the controlling software. Each level has a corresponding interrupt
mask register.
On the bottom level, there are alarm registers which have a bit per STS-1 for each path status condition. There is a
matching alarm mask to mask out individual bits. If the alarm condition for that STS-1 occurs and the alarm mask
bit is not set, then an interrupt is generated and the bit in the binning register above will read set. If the interrupt
mask is not set for that binning register, then the condition will appear in the top-level register.
Only the bottom-level registers have storage, and to remove the alarm flag, it is necessary only to clear the bottomlevel register (either with a write-one-clear or a read depending on the clear read/write control bit).
If the interrupt alarm mask bits are set for the bottom level, then no interrupts can be caused, but that condition can
be detected by polling this bottom-level register.
Note: If an error condition occurs for an STS-Nc, the condition will be reflected in the head STS-1 of the concatenation.
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Data Sheet
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STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions
0x8000
ID REGISTER
0x800F
INTERRUPTS
0x820F
MASKS
0x8300
PATH TRACE
PERSISTENCY
STATE
0x8382
0x83C2
0x8400
SF DETECT/CLEAR
CONCATENATION MAP
0x8502
0x8542
AIS-P GENERAL CONTROL
0x8580
PP CONTROL
0x8600
PATH PROVISIONING
0x8690
PATH MAINTENANCE
INTERPRETER
INCREMENT/DECREMENT (PM)
0x8702
0x8780
POH PM
0x8800
CV COUNT PM
0x8880
REI COUNT PM
0x8900
RESERVED
RDI, C2, PDI
1699(F).ar.1
Figure 54. Overview of RXT Register Map
414
Agere Systems Inc.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 329. RXT_IDR, RXT Identification Register (RO, Fixed Value)
Address
Bit
Name
0x8000
15:0
RXT_ID[15:0]
Function
RXT Identification Register.
Reset
Default
0001
Table 330. PP_CORWR, PP Clear on Read/Write Register (R/W, Control)
Address
Bit
Name
0x8001
15:1
—
0
RXT_CORW
Function
Reset
Default
Reserved.
0
RXT Clear on Read/Write. Sets the mode for clearing alarm
bit in the RXT block.
0
0 = Clear interrupt bits by writing 1 to that bit in the alarm
register.
1 = Clear all alarm bits in an interrupt alarm register by
reading that register.
Note: This affects only the RXT interrupt alarms, i.e., only
the ones listed in this section (RXT) of the data sheet.
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Data Sheet
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STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Interrupts
Table 331. RXT_POH_ALMBNR[1—2], Path Overhead Alarm Status Binning Register (RO)
Address
Bit
Name
0x800F
15:3
—
2
1
0
Function
Reset
Default
0
Reserved.
RXT_PDI_ALMDBN Payload Defect Indicator (PDI) Alarm Delta Binning.
RXT_PDI_ALMBN
RXT_J1ACCMP_
ALMBN
0 = PDI alarm delta has not been detected for any STS-1 in any
bytestream.
1 = PDI alarm delta has been detected for one or more STS-1s
in one or more bytestreams.
Payload Defect Indicator (PDI) Alarm Binning.
0 = PDI alarm has not been detected for any STS-1 in any
bytestream.
1 = PDI alarm has been detected for one or more STS-1s in one
or more bytestreams.
J1 Access Complete Alarm Binning. The alarm can be
masked from contributing to the RXT interrupt by either
registers 0x820F bit 0 (Table 363) or 0x82E0 bit 0 (Table 392).
0
0
0
0 = J1 access complete alarm has not been detected for any
STS-1 in any bytestream.
1 = J1 access complete alarm has been detected for one or
more STS-1s in one or more bytestreams.
416
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 331. RXT_POH_ALMBNR[1—2], Path Overhead Alarm Status Binning Register (RO) (continued)
Address
Bit
0x8010
15
Name
Function
RXT_RDI_ALMDBN Remote Defect Indicator Alarm Delta Binning.
Reset
Default
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
Payload Label Mismatch Alarm Delta Binning.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
Unequipped Received Alarm Delta Binning.
0
12
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
RXT_AIS_ALMDBN Alarm Indicator Signal Alarm Delta Binning.
0
11
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
Loss of Pointer Alarm Delta Binning.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
J1 Mismatch Alarm Binning.
0
0 = J1 buffer access not complete.
1 = J1 buffer access complete.
J1 Validated Alarm Binning.
0
0 = J1 buffer access not complete.
1 = J1 buffer access complete.
Unsupported Concatenation Alarm Binning.
0
0 = None of the four bytestreams has an unsupported
concatenation.
1 = One of the four bytestreams has an unsupported
concatenation.
Concatenation Mismatch Alarm Binning.
0
14
RXT_PLM_
ALMDBN
13
10
9
8
7
Agere Systems Inc.
RXT_UNEQR_
ALMDBN
RXT_LOP_
ALMDBN
RXT_J1MM_
ALMBN
RXT_J1VLD_
ALMBN
RXT_USCNCT_
ALMBN
RXT_CNCTMM_
ALMBN
0 = None of the four bytestreams has a concatenation
mismatch.
1 = One of the four bytestreams has a concatenation mismatch.
417
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 331. RXT_POH_ALMBNR[1—2], Path Overhead Alarm Status Binning Register (RO) (continued)
Address
Bit
Name
0x8010
6
—
5
RXT_SF_ALMBN
Function
Reset
Default
Reserved.
—
Signal Fail Alarm Binning.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
4
RXT_RDI_ALMBN
0
Remote Defect Indicator Alarm Binning.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
3
0
RXT_PLM_ALMBN Payload Label Mismatch Alarm Binning.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
2
1
RXT_UNEQR_
ALMBN
Unequipped Received Alarm Binning.
RXT_AIS_ALMBN
Alarm Indicator Signal Alarm Binning.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
0
0
RXT_LOP_ALMBN Loss of Pointer Alarm Binning.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in one or
more bytestreams.
418
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 332. RXT_SF_ALMBNBSR, Signal Fail Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x8031
15:4
—
3:0
RXT_SF_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Signal Fail Binning Bytestream A—D.
0
0 = Signal fail has not been detected for any STS-1s in
bytestream A—D.
1 = Signal fail has been detected for one or more STS-1s
in bytestream A—D.
Table 333. RXT_TSSF_ALMBSR[A—D], Time Slots 1—12 Signal Fail Alarm Bytestream A—D
(RO, COR/COW)
Address
Bit
0x8032, 15:12
0x8033, 11:0
0x8034,
0x8035
Name
—
RXT_TSSF_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Signal Fail Bytestream
A—D.
0
0 = Signal fail has not been detected.
1 = Signal fail has been detected.
Table 334. RXT_RDI_ALMBNBSR, Remote Defect Indicator Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x8041
15:4
—
3:0
RXT_RDI_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Remote Defect Indicator Binning Bytestream A—D.
0
0 = Remote defect indicator has not been detected for any
STS-1s in bytestream A—D.
1 = Remote defect indicator has been detected for one or
more STS-1s in bytestream A—D.
Table 335. RXT_TSRDI_ALMBSR[A—D], Time Slots 1—12 Remote Defect Indicator Alarm
Bytestream A—D (RO, COR/COW)
Address
Bit
0x8042, 15:12
0x8043, 11:0
0x8044,
0x8045
Name
—
RXT_TSRDI_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Remote Defect Indicator
Bytestream A—D.
0
0 = Remote defect indicator has not been detected.
1 = Remote defect indicator has been detected.
Agere Systems Inc.
419
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 336. RXT_PLM_ALMBNBSR, Payload Label Mismatch Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x8051
15:4
—
3:0
RXT_PLM_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Payload Label Mismatch Binning Bytestream A—D.
0
0 = Payload label mismatch has not been detected for any
STS-1s in bytestream A—D.
1 = Payload label mismatch has been detected for one or
more STS-1s in bytestream A—D.
Table 337. RXT_TSPLM_ALMBSR[A—D], Time Slots 1—12 Payload Label Mismatch Alarm
Bytestream A—D (RO, COR/COW)
Address
Bit
0x8052, 15:12
0x8053, 11:0
0x8054,
0x8055
Name
—
RXT_TSPLM_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Payload Label Mismatch
Bytestream A—D.
0
0 = Payload label mismatch has not been detected.
1 = Payload label mismatch has been detected.
Table 338. RXT_UNEQR_ALMBNBSR, Unequipped Received Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x8061
15:4
—
3:0
RXT_UNEQR_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Unequipped Received Binning Bytestream A—D.
0
0 = Unequipped received has not been detected for any
STS-1s in bytestream A—D.
1 = Unequipped received has been detected for one or
more STS-1s in bytestream A—D.
Table 339. RXT_TSUNEQR_ALMBSR[A—D], Time Slots 1—12 Unequipped Received Alarm Bytestream A—
D (RO, COR/COW)
Address
Bit
Name
Function
Reset
Default
—
Reserved.
0x8062, 15:12
0x8063, 11:0 RXT_TSUNEQR_ALMBS Time Slot 1—Time Slot 12 Unequipped Received
0x8064,
[A—D][1—12]
Bytestream A—D.
0x8065
0 = Unequipped received has not been detected.
1 = Unequipped received has been detected.
420
0
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 340. RXT_AIS_ALMBNBSR, Alarms Indicator Signal Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x8071
15:4
—
3:0
RXT_AIS_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Alarms Indicator Signal Binning Bytestream A—D.
0
0 = Alarms indicator signal has not been detected for any
STS-1s in bytestream A—D.
1 = Alarms indicator signal has been detected for one or
more STS-1s in bytestream A—D.
Table 341. PP_TSAIS_ALMBSR[A—D], Time Slots 1—12 Alarms Indicator Signal Alarm Bytestream A—D
(RO, COR/COW)
Address
Bit
0x8072, 15:12
0x8073, 11:0
0x8074,
0x8075
Name
—
PP_TSAIS_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Alarms Indicator Signal
Bytestream A—D.
1
0 = Alarms indicator signal has not been detected.
1 = Alarms indicator signal has been detected.
Table 342. RXT_LOP_ALMBNBSR, Loss of Pointer Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x8081
15:4
—
3:0
RXT_LOP_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Loss of Pointer Binning Bytestream A—D.
0
0 = Loss of pointer has not been detected for any STS-1s
in bytestream A—D.
1 = Loss of pointer has been detected for one or more
STS-1s in bytestream A—D.
Table 343. RXT_TSLOP_ALMBSR[A—D], Time Slots 1—12 Loss of Pointer Alarm Bytestream A—D
(RO, COR/COW)
Address
Bit
0x8082, 15:12
0x8083, 11:0
0x8084,
0x8085
Name
—
RXT_TSLOP_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Loss of Pointer Bytestream
A—D.
1
0 = Loss of pointer has not been detected.
1 = Loss of pointer has been detected.
Agere Systems Inc.
421
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 344. RXT_CNCTMM_ALMBNBSR, Channel Path Concatenation Map Mismatch Alarm Status Binning
Bytestream A—D (RO, COR/COW)
Address
Bit
Name
0x8091
15:4
—
3:0
RXT_CNCTMM_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Concatenation Map Mismatch Binning
Bytestream A—D.
0
0 = No expected/received concatenation state
mismatches on any time slot.
1 = Expected/received concatenation state mismatch in at
least one time slot.
Table 345. RXT_USCNCTM_ALMBNBSR, Channel Path Unsupported Concatenation Map Alarm Binning
Bytestream A—D (RO, COR/COW)
Address
Bit
Name
0x80A1
15:4
—
3:0
RXT_USCNCTM_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Unsupported Concatenation Map Binning
Bytestream A—D.
0
0 = No path alarm.
1 = Alarm detected.
Table 346. RXT_J1NVLDMSG_ALMBNBSR, Channel Path J1 New Validated Message Alarm Binning
Bytestream A—D (RO, COR/COW)
Address
Bit
Name
0x80C1
15:4
—
3:0
RXT_J1NVLDMSG_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
J1 New Validated Message Binning Bytestream A—D.
0
0 = No path alarm.
1 = Alarm detected.
Table 347. RXT_J1MSGMM_ALMBNBSR, Channel Path J1 Message Mismatch Alarm Status Binning
Bytestream A—D (RO, COR/COW)
Address
Bit
Name
0x80D1
15:4
—
3:0
RXT_J1MSGMM_
ALMBNBS[A—D]
422
Function
Reset
Default
Reserved.
0
J1 Message Mismatch Binning Bytestream A—D.
0
0 = No path alarm.
1 = Alarm detected.
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 348. RXT_PDI_ALMBNBSR, Payload Defect Indicator Alarm Status Binning Bytestream A—D (RO)
Address
Bit
Name
0x8101
15:4
—
3:0
RXT_PDI_
ALMBNBS[A—D]
Function
Reset
Default
Reserved.
0
Payload Defect Indicator Binning Bytestream A—D.
0
0 = Payload defect indicator has not been detected for
any STS-1s in bytestream A—D.
1 = Payload defect indicator has been detected for one or
more STS-1s in bytestream A—D.
Table 349. RXT_TSPDI_ALMBSR[A—D], Time Slots 1—12 Payload Defect Indicator Alarm Bytestream A—D
(RO, COR/COW)
Address
Bit
0x8102, 15:12
0x8103, 11:0
0x8104,
0x8105
Name
—
RXT_TSPDI_ALMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Payload Defect Indicator
Bytestream A—D.
0
0 = Payload defect indicator has not been detected.
1 = Payload defect indicator has been detected.
Table 350. RXT_RDI_ALMDBNBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status
Binning Bytestream A—D (RO)
Address
Bit
Name
0x8111
15:4
—
3:0
RXT_RDI_ALMDBNBS
[A—D]
Function
Reset
Default
Reserved.
0
Remote Defect Indicator Delta Binning
Bytestream A—D.
0
0 = Remote defect indicator delta has not been detected
for any STS-1s in bytestream A—D.
1 = Remote defect indicator delta has been detected for
one or more STS-1s in bytestream A—D.
Table 351. RXT_TSRDI_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Remote Defect Indicator
Alarm Delta Bytestream A—D (RO, COR/COW)
Address
Bit
0x8112, 15:12
0x8113, 11:0
0x8114,
0x8115
Name
—
RXT_TSRDI_ALMDBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Remote Defect Indicator
Delta Bytestream A—D.
0
0 = Remote defect indicator delta has not been detected.
1 = Remote defect indicator delta has been detected.
Agere Systems Inc.
423
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 352. RXT_PLM_ALMDBNBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status
Binning Bytestream A—D (RO)
Address
Bit
Name
0x8121
15:4
—
3:0
RXT_PLM_ALMDBNBS
[A—D]
Function
Reset
Default
Reserved.
0
Payload Label Mismatch Delta Binning
Bytestream A—D.
6
0 = Payload label mismatch delta has not been detected
for any STS-1s in bytestream A—D.
1 = Payload label mismatch delta has been detected for
one or more STS-1s in bytestream A—D.
Table 353. RXT_TSPLM_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Label Mismatch
Alarm Delta Bytestream A—D (RO, COR/COW)
Address
Bit
0x8122, 15:12
0x8123, 11:0
0x8124,
0x8125
Name
—
RXT_TSPLM_ALMDBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Payload Label Mismatch
Delta Bytestream A—D.
0
0 = Payload label mismatch delta has not been detected.
1 = Payload label mismatch delta has been detected.
Table 354. RXT_UNEQR_ALMDBNBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status
Binning Bytestream A—D (RO)
Address
Bit
Name
0x8131
15:4
—
3:0
RXT_UNEQR_
ALMDBNBS[A—D]
Function
Reset
Default
Reserved.
0
Unequipped Received Delta Binning
Bytestream A—D.
0
0 = Unequipped received delta has not been detected for
any STS-1s in bytestream A—D.
1 = Unequipped received delta has been detected for one
or more STS-1s in bytestream A—D.
Table 355. RXT_TSUNEQR_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Unequipped
Received Alarm Delta Bytestream A—D (RO, COR/COW)
Address
Bit
0x8132, 15:12
0x8133, 11:0
0x8134,
0x8135
Name
—
RXT_TSUNEQR_
ALMDBS[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Unequipped Received Delta
Bytestream A—D.
0
0 = Unequipped received delta has not been detected.
1 = Unequipped received delta has been detected.
424
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 356. RXT_AIS_ALMDBNBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status
Binning Bytestream A—D (RO)
Address
Bit
Name
0x8141
15:4
—
3:0
RXT_AIS_
ALMDBNBS[A—D]
Function
Reset
Default
Reserved.
0
Alarm Indicator Signal Delta Binning
Bytestream A—D.
0
0 = Alarm indicator signal delta has not been detected for
any STS-1s in bytestream A—D.
1 = Alarm indicator signal delta has been detected for one
or more STS-1s in bytestream A—D.
Table 357. RXT_TSAIS_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Alarm Indicator Signal
Alarm Delta Bytestream A—D (RO, COR/COW)
Address
Bit
0x8142, 15:12
0x8143, 11:0
0x8144,
0x8145
Name
—
RXT_TSAIS_ALMDBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Alarm Indicator Signal Delta
Bytestream A—D.
1
0 = Alarm indicator signal delta has not been detected.
1 = Alarm indicator signal delta has been detected.
Table 358. RXT_LOP_ALMDBNBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning
Bytestream A—D (RO)
Address
Bit
Name
0x8151
15:4
—
3:0
RXT_LOP_
ALMDBNBS[A—D]
Function
Reset
Default
Reserved.
0
Loss of Pointer Delta Binning Bytestream A—D.
0
0 = Loss of pointer delta has not been detected for any
STS-1s in bytestream A—D.
1 = Loss of pointer delta has been detected for one or
more STS-1s in bytestream A—D.
Table 359. RXT_TSLOP_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Loss of Pointer Alarm
Delta Bytestream A—D (RO, COR/COW)
Address
Bit
0x8152, 15:12
0x8153, 11:0
0x8154,
0x8155
Name
—
RXT_TSLOP_ALMDBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Loss of Pointer Delta
Bytestream A—D.
1
0 = Loss of pointer delta has not been detected.
1 = Loss of pointer delta has been detected.
Agere Systems Inc.
425
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 360. RXT_PTRACCMPIR, Path Trace Access Complete Interrupt (RO, COR/COW)
Address
Bit
Name
0x8160
15:1
—
0
RXT_J1BFACCMPI
Function
Reset
Default
Reserved.
0
J1 Buffer Access Complete Interrupt.
0
0 = No alarm.
1 = Alarm detected.
Table 361. RXT_PDI_ALMDBNBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status
Binning Bytestream A—D (RO)
Address
Bit
Name
0x8171
15:4
—
3:0
RXT_PDI_
ALMDBNBS[A—D]
Function
Reset
Default
Reserved.
0
Payload Defect Indicator Delta Binning
Bytestream A—D.
0
0 = Payload defect indicator delta has not been detected
for any STS-1s in bytestream A—D.
1 = Payload defect indicator delta has been detected for
one or more STS-1s in bytestream A—D.
Table 362. RXT_TSPDI_ALMDBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Defect Indicator
Alarm Delta Bytestream A—D (RO, COR/COW)
Address
Bit
0x8172, 15:12
0x8173, 11:0
0x8174,
0x8175
Name
—
RXT_TSPDI_ALMDBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Payload Defect Indicator
Delta Bytestream A—D.
0
0 = Payload defect indicator delta has not been detected.
1 = Payload defect indicator delta has been detected.
426
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Masks
Table 363. RXT_POH_ALMBNMR[1—2], Path Overhead Alarm Status Binning Masks (R/W)
Address
Bit
Name
0x820F
15:3
—
2
RXT_PDI_ALMDBNM
Function
Reset
Default
Reserved.
—
Payload Defect Indicator (PDI) Alarm Delta Binning
Mask.
1
0 = PDI delta alarm is passed through.
1 = PDI delta alarm masked.
1
RXT_PDI_ALMBNM
Payload Defect Indicator (PDI) Alarm Binning Mask.
1
0 = PDI alarm is passed through.
1 = PDI alarm masked.
0
RXT_J1ACCMP_
ALMBNM
J1 Access Complete Alarm Binning Mask. Setting this
bit to a 1 masks the interrupt from contributing to the RXT
interrupt. Setting this bit to a 0 and register 0x82E0 bit 0
(Table 392) to a 0 allows the interrupt to contribute to the
RXT interrupt.
1
0 = J1 access complete alarm is passed through.
1 = J1 access complete alarm masked.
Agere Systems Inc.
427
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 363. RXT_POH_ALMBNMR[1—2], Path Overhead Alarm Status Binning Masks (R/W) (continued)
Address
Bit
Name
0x8210
15
RXT_RDI_ALMDBNM
Function
Reset
Default
Remote Defect Indicator Alarm Delta Binning Mask.
1
0 = Remote defect indicator delta alarm is passed
through.
1 = Remote defect indicator delta alarm masked.
14
RXT_PLM_ALMDBNM
Payload Label Mismatch Alarm Delta Binning Mask.
1
0 = Payload label mismatch delta alarm is passed
through.
1 = Payload label mismatch delta alarm masked.
13
RXT_UNEQR_ALMDBNM Unequipped Received Alarm Delta Binning Mask.
1
0 = Unequipped received delta alarm is passed through.
1 = Unequipped received delta alarm masked.
12
RXT_AIS_ALMDBNM
Alarm Indicator Signal Alarm Delta Binning Mask.
1
0 = Alarm indicator signal delta alarm is passed through.
1 = Alarm indicator signal delta alarm masked.
11
RXT_LOP_ALMDBNM
Loss of Pointer Alarm Delta Binning Mask.
1
0 = Loss of pointer delta alarm is passed through.
1 = Loss of pointer delta alarm masked.
10
RXT_J1MM_ALMBNM
J1 Mismatch Alarm Binning Mask.
1
0 = J1 mismatch alarm is passed through.
1 = J1 mismatch alarm masked.
9
RXT_J1VLD_ALMBNM
J1 Validated Alarm Binning Mask.
1
0 = J1 validated alarm is passed through.
1 = J1 validated alarm masked.
8
RXT_USCNCT_ALMM
Unsupported Concatenation Alarm Binning Mask.
1
0 = Unsupported concatenation alarm is passed through.
1 = Unsupported concatenation alarm masked.
7
RXT_CNCTMM_ALMBNM Concatenation Mismatch Alarm Binning Mask.
1
0 = Concatenation mismatch alarm is passed through.
1 = Concatenation mismatch alarm masked.
6
—
5
RXT_SF_ALMBNM
Reserved.
—
Signal Fail Alarm Binning Mask.
1
0 = Signal fail alarm is passed through.
1 = Signal fail alarm masked.
428
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 363. RXT_POH_ALMBNMR[1—2], Path Overhead Alarm Status Binning Masks (R/W) (continued)
Address
Bit
Name
0x8210
4
RXT_RDI_ALMBNM
Function
Remote Defect Indicator Alarm Binning Mask.
Reset
Default
1
0 = Remote defect indicator alarm is passed through.
1 = Remote defect indicator alarms masked.
3
RXT_PLM_ALMBNM
Payload Label Mismatch Alarm Binning Mask.
1
0 = Payload label mismatch alarm is passed through.
1 = Payload label mismatch alarms masked.
2
RXT_UNEQR_ALMBNM
Unequipped Received Alarm Binning Mask.
1
0 = Unequipped received alarm is passed through.
1 = Unequipped received alarms masked.
1
RXT_AIS_ALMBNM
Alarm Indicator Signal Alarm Binning Mask.
1
0 = Alarm indicator signal alarm is passed through.
1 = Alarm indicator signal alarms masked.
0
RXT_LOP_ALMBNM
Loss of Pointer Alarm Binning Mask.
1
0 = Loss of pointer alarm is passed through.
1 = Loss of pointer alarms masked.
Table 364. RXT_SF_ALMBNMBSR, Signal Fail Alarm Status Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x8221
15:4
—
3:0
RXT_SF_
ALMBNMBS[A—D]
Function
Reserved.
Reset
Default
—
Signal Fail Binning Masks Bytestream A—D.
1111
0 = Signal fail alarms in bytestream A are passed through.
1 = Signal fail alarms in bytestream A are masked.
Table 365. RXT_TSSF_ALMMBSR[A—D], Time Slots 1—12 Signal Fail Alarm Masks Bytestream A—D (R/W)
Address
Bit
0x8222, 15:12
0x8223, 11:0
0x8224,
0x8225
Agere Systems Inc.
Name
—
RXT_TSSF_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Signal Fail Masks
Bytestream A—D.
1
429
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 366. RXT_RDI_ALMBNMBSR, Remote Defect Indicator Alarm Status Binning Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x8231
15:4
—
3:0
RXT_RDI_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Remote Defect Indicator Binning Masks
Bytestream A—D.
1
0 = Remote defect indicator alarms in bytestream A—D
are passed through.
1 = Remote defect indicator alarms in bytestream A—D
are masked.
Table 367. RXT_TSRDI_ALMMBSR[A—D], Time Slots 1—12 Remote Defect Indicator Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x8232, 15:12
0x8233, 11:0
0x8234,
0x8235
Name
—
RXT_TSRDI_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Remote Defect Indicator
Masks Bytestream A—D.
1
Table 368. RXT_PLM_ALMBNMBSR, Payload Label Mismatch Alarm Status Binning Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x8241
15:4
—
3:0
RXT_PLM_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Payload Label Mismatch Binning Masks
Bytestream A—D.
1
0 = Payload label mismatch alarms in bytestream A—D
are passed through.
1 = Payload label mismatch alarms in bytestream A—D
are masked.
Table 369. RXT_TSPLM_ALMMBSR[A—D], Time Slots 1—12 Payload Label Mismatch Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x8242, 15:12
0x8243, 11:0
0x8244,
0x8245
430
Name
—
RXT_TSPLM_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Payload Label Mismatch
Masks Bytestream A—D.
1
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 370. RXT_UNEQR_ALMBNMBSR, Unequipped Received Alarm Status Binning Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x8251
15:4
—
3:0
RXT_UNEQR_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Unequipped Received Binning Masks
Bytestream A—D.
1
0 = Unequipped received alarms in bytestream A—D are
passed through.
1 = Unequipped received alarms in bytestream A—D are
masked.
Table 371. RXT_TSUNEQR_ALMMBSR[A—D], Time Slots 1—12 Unequipped Received Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x8252, 15:12
0x8253, 11:0
0x8254,
0x8255
Name
—
RXT_TSUNEQR_
ALMMBS[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Unequipped Received
Masks Bytestream A—D.
1
Table 372. RXT_AIS_ALMBNMBSR, Alarms Indicator Signal Alarm Status Binning Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x8261
15:4
—
3:0
RXT_AIS_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Alarms Indicator Signal Binning Masks
Bytestream A—D.
1
0 = Alarms indicator signal alarms in bytestream A—D are
passed through.
1 = Alarms indicator signal alarms in bytestream A—D are
masked.
Table 373. RXT_TSAIS_ALMMBSR[A—D], Time Slots 1—12 Alarms Indicator Signal Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x8262, 15:12
0x8263, 11:0
0x8264,
0x8265
Agere Systems Inc.
Name
—
RXT_TSAIS_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Alarms Indicator Signal
Masks Bytestream A—D.
1
431
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 374. RXT_LOP_ALMBNMBSR, Loss of Pointer Alarm Status Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x8271
15:4
—
3:0
RXT_LOP_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Loss of Pointer Binning Masks Bytestream A—D.
1
0 = Loss of pointer alarms in bytestream A—D are passed
through.
1 = Loss of pointer alarms in bytestream A—D are
masked.
Table 375. RXT_TSLOP_ALMMBSR[A—D], Time Slots 1—12 Loss of Pointer Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x8272, 15:12
0x8273, 11:0
0x8274,
0x8275
Name
—
RXT_TSLOP_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Loss of Pointer Masks
Bytestream A—D.
1
Table 376. RXT_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x8277
15:4
—
3:0
RXT_CNCTMM_
ALMMBS[A—D]
Function
Reset
Default
Reserved.
—
Concatenation Map Mismatch Mask Bytestream A—D.
1
0 = Path alarm is passed through.
1 = Path alarm is masked.
Table 377. RXT_USCNCTM_ALMMBSR, Channel Path Unsupported Concatenation Map Alarm Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x8279
15:4
—
3:0
RXT_USCNCTM_
ALMMBS[A—D]
Function
Reset
Default
Reserved.
—
Unsupported Concatenation Map Mask Bytestream
A—D.
1
0 = Alarm is passed through.
1 = Alarm is masked.
432
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 378. RXT_J1NVLDMSG_ALMMBSR, Channel Path J1 New Validated Message Alarm Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x827B
15:4
—
3:0
RXT_J1NVLDMSG
ALMMBS[A—D]
Function
Reset
Default
Reserved.
—
J1 New Validated Message Mask Bytestream A—D.
1
0 = Alarm is passed through.
1 = Alarm is masked.
Table 379. RXT_J1MSGMM_ALMMBSR, Channel Path J1 Message Mismatch Alarm Status Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x827D
15:4
—
3:0
RXT_J1MSGMM_
ALMMBS[A—D]
Function
Reset
Default
Reserved.
—
J1 Message Mismatch Mask Bytestream A—D.
1
0 = Alarm is passed through.
1 = Alarm is masked.
Table 380. RXT_PDI_ALMBNMBSR, Payload Defect Indicator Alarm Status Binning Masks
Bytestream A—D (R/W)
Address
Bit
Name
0x8281
15:4
—
3:0
RXT_PDI_
ALMBNMBS[A—D]
Function
Reset
Default
Reserved.
0
Payload Defect Indicator Binning Masks
Bytestream A—D.
1
0 = Payload defect indicator alarms in bytestream A—D
are passed through.
1 = Payload defect indicator alarms in bytestream A—D
are masked.
Table 381. RXT_TSPDI_ALMMBSR[A—D], Time Slots 1—12 Payload Defect Indicator Alarm Masks
Bytestream A—D (R/W)
Address
Bit
0x8282, 15:12
0x8283, 11:0
0x8284,
0x8285
Agere Systems Inc.
Name
—
RXT_TSPDI_ALMMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Payload Defect Indicator
Masks Bytestream A—D.
1
433
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 382. RXT_RDI_ALMDBNMBSR, Path Overhead STS-1 Remote Defect Indicator Alarm Delta Status
Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x8291
15:4
—
3:0
Function
Reset
Default
Reserved.
—
RXT_RDI_ALMDBNMBS Remote Defect Indicator Delta Binning Masks
[A—D]
Bytestream A—D.
1
0 = Remote defect indicator delta alarms in bytestream
A—D are passed through.
1 = Remote defect indicator delta alarms in bytestream
A—D are masked.
Table 383. RXT_TSRDI_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Remote Defect
Indicator Alarm Delta Masks Bytestream A—D (R/W)
Address
Bit
0x8292, 15:12
0x8293, 11:0
0x8294,
0x8295
Name
—
RXT_TSRDI_ALMDMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Remote Defect Indicator
Delta Masks Bytestream A—D.
1
Table 384. RXT_PLM_ALMDBNMBSR, Path Overhead STS-1 Payload Label Mismatch Alarm Delta Status
Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x82A1
15:4
—
3:0
Function
Reset
Default
Reserved.
—
RXT_PLM_ALMDBNMBS Payload Label Mismatch Delta Binning Masks
[A—D]
Bytestream A—D.
1
0 = Payload label mismatch delta alarms in bytestream
A—D are passed through.
1 = Payload label mismatch delta alarms in bytestream
A—D are masked.
Table 385. RXT_TSPLM_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Label
Mismatch Alarm Delta Masks Bytestream A—D (R/W)
Address
Bit
Name
Function
Reset
Default
—
Reserved.
0x82A2, 15:12
0x82A3, 11:0 RXT_TSPLM_ALMDMBS Time Slot 1—Time Slot 12 Payload Label Mismatch
0x82A4,
[A—D][1—12]
Delta Masks Bytestream A—D.
0x82A5
434
—
1
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 386. RXT_UNEQR_ALMDBNMBSR, Path Overhead STS-1 Unequipped Received Alarm Delta Status
Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x82B1
15:4
—
3:0
RXT_UNEQR_
ALMDBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Unequipped Received Delta Binning Masks
Bytestream A—D.
1
0 = Unequipped received delta alarms in bytestream
A—D are passed through.
1 = Unequipped received delta alarms in bytestream
A—D are masked.
Table 387. RXT_TSUNEQR_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Unequipped
Received Alarm Delta Masks Bytestream A—D (R/W)
Address
Bit
0x82B2, 15:12
0x82B3, 11:0
0x82B4,
0x82B5
Name
—
Function
Reset
Default
Reserved.
—
RXT_TSUNEQR_
Time Slot 1—Time Slot 12 Unequipped Received Delta
ALMDMBS[A—D][1—12] Masks Bytestream A—D.
1
Table 388. RXT_AIS_ALMDBNMBSR, Path Overhead STS-1 Alarm Indicator Signal Alarm Delta Status
Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x82C1
15:4
—
3:0
RXT_AIS_
ALMDBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Alarm Indicator Signal Delta Binning Masks
Bytestream A—D.
1
0 = Alarm indicator signal delta alarms in bytestream
A—D are passed through.
1 = Alarm indicator signal delta alarms in bytestream
A—D are masked.
Table 389. RXT_TSAIS_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Alarm Indicator Signal
Alarm Delta Masks Bytestream A—D (R/W)
Address
Bit
0x82C2, 15:12
0x82C3, 11:0
0x82C4,
0x82C5
Agere Systems Inc.
Name
—
RXT_TSAIS_ALMDMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Alarm Indicator Signal
Delta Masks Bytestream A—D.
1
435
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 390. RXT_LOP_ALMDBNMBSR, Path Overhead STS-1 Loss of Pointer Alarm Delta Status Binning
Masks Bytestream A—D (R/W)
Address
Bit
Name
0x82D1
15:4
—
3:0
RXT_LOP_
ALMDBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Loss of Pointer Delta Binning Masks
Bytestream A—D.
1
0 = Loss of pointer delta alarms in bytestream A—D are
passed through.
1 = Loss of pointer delta alarms in bytestream A—D are
masked.
Table 391. RXT_TSLOP_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Loss of Pointer Alarm
Delta Masks Bytestream A—D (R/W)
Address
Bit
Name
Function
Reset
Default
—
Reserved.
0x82D2, 15:12
0x82D3, 11:0 RXT_TSLOP_ALMDMBS Time Slot 1—Time Slot 12 Loss of Pointer Delta Masks
0x82D4,
[A—D][1—12]
Bytestream A—D.
0x82D5
—
1
Table 392. RXT_PTRACCMPIR, Path Trace Access Complete Interrupt Mask (R/W)
Address
Bit
Name
0x82E0
15:1
—
0
RXT_J1BFACCMPIM
Function
Reset
Default
Reserved.
—
J1 Buffer Access Complete Mask. Setting this bit to a 1
masks the interrupt from contributing to the RXT interrupt.
Setting this bit to a 0 and register 0x820F bit 0 (Table 363)
to a 0 allows the interrupt to contribute to the RXT
interrupt.
1
0 = Alarm is passed through.
1 = Alarm is masked.
436
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 393. RXT_PDI_ALMDBNMBSR, Path Overhead STS-1 Payload Defect Indicator Alarm Delta Status
Binning Masks Bytestream A—D (R/W)
Address
Bit
Name
0x82E9
15:4
—
3:0
RXT_PDI_
ALMDBNMBS[A—D]
Function
Reset
Default
Reserved.
—
Payload Defect Indicator Delta Binning Masks
Bytestream A—D.
1
0 = Payload defect indicator delta alarms in bytestream
A—D are passed through.
1 = Payload defect indicator delta alarms in bytestream
A—D are masked.
Table 394. RXT_TSPDI_ALMDMBSR[A—D], Path Overhead STS-1 Time Slots 1—12 Payload Defect
Indicator Alarm Delta Masks Bytestream A—D (R/W)
Address
Bit
0x82EA, 15:12
0x82EB, 11:0
0x82EC,
0x82ED
Name
—
RXT_TSPDI_ALMDMBS
[A—D][1—12]
Agere Systems Inc.
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Payload Defect Indicator
Delta Masks Bytestream A—D.
1
437
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Path Trace
Table 395. RXT_PTRBFR[1—32], Path Trace Buffer Registers 1—32 (R/W)
Address
Bit
Name
Function
Reset
Default
0x8300
—
0x831F
15:8
RXT_J1BYTE1[7:0]
J1 Byte 1, 3, 5, . . . , 63 Path Trace Buffer.
0
7:0
RXT_J1BYTE0[7:0]
J1 Byte 0, 2, 6, . . . , 62 Path Trace Buffer.
0
Table 396. RXT_PTRACCTLR1, Path Trace Access Control Register 1 (R/W)
Address
Bit
0x8330
15:2
1:0
Name
—
Function
Reset
Default
Reserved.
0
0
RXT_J1TS1_CHSEL[1:0] J1 Time Slots 1 Channel Select.
00 = Bytestream A.
01 = Bytestream B.
10 = Bytestream C.
11 = Bytestream D.
Table 397. RXT_PTRACCTLR2, Path Trace Access Control Register 2 (R/W)
Address
Bit
Name
0x8331
15:1
—
0
RXT_J1BF_MSGSEL
Function
Reset
Default
Reserved.
0
J1 Buffer Message Type Select (Compare/ Received
Message).
0
Table 398. RXT_PTRACCTLR3, Path Trace Access Control Register 3 (R/W)
Address
Bit
Name
0x8332
15:1
—
0
RXT_J1BF_ACTYP
Function
Reset
Default
Reserved.
0
J1 Buffer Access Type (Read/ Write). 0 = read, 1 =
write.
0
Table 399. RXT_PTRACBGR, Path Trace Access Begin (WO)
Address
Bit
Name
0x8333
15:1
—
0
RXT_J1_ACBG
438
Function
Reset
Default
Reserved.
0
J1 Access Begin. A J1 access complete interrupt,
through the RXT interrupt chain, will be generated from
823 ns to 8 ms after writing this bit to a 1. This bit will
return 0 after the access is complete.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 400. RXT_STS12PTRCTLR[1—6], STS-12 Channel Path Trace Control Registers 1—6 (R/W)
Address
Bit
Name
0x8338
15:4
—
3:0
RXT_J1MSG_MSEL
[A—D]
15:4
—
3:0
RXT_J1MSG_TYPSEL
[A—D]
0x8339
Function
Reset
Default
Reserved.
0
J1 Message Mode Select (Validated/Provisioned)
Bytestream A—D.
1
Reserved.
0
J1 Message Type Select (SDH/SONET) Bytestream
A—D.
0
0 = SONET.
1 = SDH.
0x833C,
0x833D,
0x833E,
0x833F
15:4
—
3:0
RXT_TSSEL_J1
[A—D][3:0]
Reserved.
0
Time Slots 1—12 Select for J1 Accumulation
Bytestream A—D.
0
1111 = Reserved.
1110 = Reserved.
1101 = Reserved.
1100 = STS-1 #12 time slot 12.
1011 = STS-1 #11 time slot 8.
1010 = STS-1 #10 time slot 4.
1001 = STS-1 #9 time slot 11.
1000 = STS-1 #8 time slot 7.
0111 = STS-1 #7 time slot 3.
0110 = STS-1 #6 time slot 10.
0101 = STS-1 #5 time slot 6.
0100 = STS-1 #4 time slot 2.
0011 = STS-1 #3 time slot 9.
0010 = STS-1 #2 time slot 5.
0001 = STS-1 #1 time slot 1.
0000 = Reserved.
Agere Systems Inc.
439
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Persistency
Table 401. RXT_TSRDI_ALMPSBSR[A—D], Time Slots 1—12 RDI Alarm Persistency Bytestream A—D (RO)
Address
Bit
0x8382, 15:12
0x8383, 11:0
0x8384,
0x8385
Name
—
RXT_TSRDI_ALMPSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 RDI Alarm Persistency Bytestream
A—D.
0
Table 402. RXT_TSPLM_ALMPSBSR[A—D], Time Slots 1—12 PLM Alarm Persistency Bytestream A—D
(RO)
Address
Bit
Name
Function
Reset
Default
—
Reserved.
0x838A, 15:12
0x838B, 11:0 RXT_TSPLM_ALMPSBS Time Slots 1—12 Payload Label Mismatch Alarm
0x838C,
[A—D][1—12]
Persistency Bytestream A—D.
0x838D
0
0
Table 403. RXT_TSPUNEQ_ALMPSBSR[A—D], Time Slots 1—12 Path Unequipped Alarm Persistency
Bytestream A—D (RO)
Address
Bit
0x8392, 15:12
0x8393, 11:0
0x8394,
0x8395
440
Name
—
RXT_TSPUNEQ_
ALMPSBS[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 Path Unequipped Alarm Persistency
Bytestream A—D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 404. RXT_TSAIS_ALMPSBSR[A—D], Time Slots 1—12 AIS Alarm Persistency Bytestream A—D (RO)
Address
Bit
Name
0x839A, 15:12
0x839B, 11:0
0x839C,
0x839D
—
RXT_TSAIS_ALMPSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 AIS Alarm Persistency Bytestream
A—D.
0
Table 405. RXT_TSLOP_ALMPSBSR[A—D], Time Slots 1—12 LOP Alarm Persistency Bytestream A—D
(RO)
Address
Bit
0x83A2, 15:12
0x83A3, 11:0
0x83A4,
0x83A5
Name
—
Function
Reserved.
Reset
Default
0
RXT_TSLOP_ALMPSBS Time Slots 1—12 LOP Alarm Persistency Bytestream
[A—D][1—12]
A—D.
0
Table 406. RXT_TSPDI_ALMPSBSR[A—D], Time Slots 1—12 PDI Alarm Persistency Bytestream A—D (RO)
Address
Bit
0x83AA, 15:12
0x83AB, 11:0
0x83AC,
0x83AD
Agere Systems Inc.
Name
—
RXT_TSPDI_ALMPSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 PDI Alarm Persistency Bytestream
A—D.
0
441
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
State
Table 407. RXT_TSRDI_STBSR[A—D], Time Slots 1—12 RDI State Bytestream A—D (RO)
Address
Bit
0x83C2, 15:12
0x83C3, 11:0
0x83C4,
0x83C5
Name
—
RXT_TSRDI_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 RDI State Bytestream A—D.
0
Table 408. RXT_TSPLM_STBSR[A—D], Time Slots 1—12 PLM State Bytestream A—D (RO)
Address
Bit
0x83CA, 15:12
0x83CB, 11:0
0x83CC,
0x83CD
Name
—
RXT_TSPLM_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 Payload Label Mismatch State
Bytestream A—D.
0
Table 409. RXT_TSPUNEQ_STBSR[A—D], Time Slots 1—12 Path Unequipped State Bytestream A—D (RO)
Address
Bit
0x83D2, 15:12
0x83D3, 11:0
0x83D4,
0x83D5
442
Name
—
RXT_TSRDI_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 Path Unequipped State Bytestream
A—D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 410. RXT_TSAIS_STBSR[A—D], Time Slots 1—12 AIS State Bytestream A—D (RO)
Address
Bit
0x83DA, 15:12
0x83DB, 11:0
0x83DC,
0x83DD
Name
—
RXT_TSAIS_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 AIS State Bytestream A—D.
0
Table 411. RXT_TSLOP_STBSR[A—D], Time Slots 1—12 LOP State Bytestream A—D (RO)
Address
Bit
0x83E2, 15:12
0x83E3, 11:0
0x83E4,
0x83E5
Name
—
RXT_TSLOP_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 LOP State Bytestream A—D.
0
Table 412. RXT_TSPDI_STBSR[A—D], Time Slots 1—12 PDI State Bytestream A—D (RO)
Address
Bit
0x83EA, 15:12
0x83EB, 11:0
0x83EC,
0x83ED
Agere Systems Inc.
Name
—
RXT_TSPDI_STBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slots 1—12 PDI State Bytestream A—D.
0
443
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Signal Fail
Table 413. RXT_SFWSZ_SELR[1—2], Signal Fail Window Size Select Registers 1—2 (R/W, Control)
Address
Bit
Name
0x8400
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
RXT_SFWSZ_SELSET
[0—7][1:0]
Window Size Select Set Threshold 0—7.
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
RXT_SFWSZ_SELCLR
[0—7][1:0]
Window Size Select Clear Threshold 0—7.
0x8401
444
Function
00 = Window size 0.
01 = Window size 1.
10 = Window size 2.
11 = Window size 3.
00 = Window size 0.
01 = Window size 1.
10 = Window size 2.
11 = Window size 3.
Reset
Default
0x1
0x2
0x1
0x2
0x1
0x2
0x1
0x2
0x2
0x3
0x2
0x3
0x2
0x3
0x2
0x3
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 414. RXT_SFDR[0—7], Signal Fail Detect Threshold Registers 0—7 (R/W, Control)
Address
Bit
Name
0x8410
15:9
—
8:0
RXT_SFD0[8:0]
Function
Reserved.
STS-1 Signal Fail Detect Threshold 0.
Reset
Default
0
0x0CF
Number of bit/block errors within detection window
required to trigger a signal fail.
0x8411
0x8412
0x8413
0x8414
0x8415
0x8416
0x8417
15:9
—
8:0
RXT_SFD1[8:0]
15:14
—
13:0
RXT_SFD2[13:0]
15:14
—
13:0
RXT_SFD3[13:0]
15:14
—
13:0
RXT_SFD4[13:0]
15:14
—
13:0
RXT_SFD5[13:0]
15:14
—
13:0
RXT_SFD6[13:0]
15:14
—
13:0
RXT_SFD7[13:0]
Agere Systems Inc.
Reserved.
STS-1 Signal Fail Detect Threshold 1.
Reserved.
STS-Nc Signal Fail Detect Threshold 2.
Reserved.
STS-Nc Signal Fail Detect Threshold 3.
Reserved.
STS-Nc Signal Fail Detect Threshold 4.
Reserved.
STS-Nc Signal Fail Detect Threshold 5.
Reserved.
STS-Nc Signal Fail Detect Threshold 6.
Reserved.
STS-Nc Signal Fail Detect Threshold 7.
0
0x0DE
0
0x0233
0
0x02B2
0
0x3A3
0
0x055E
0
0x51D
0
0x0A62
445
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 415. RXT_SFCLRR[0—7], Signal Fail Clear Threshold Registers 0—7 (R/W, Control)
Address
Bit
Name
0x8418
15:9
—
8:0
RXT_SFCLR0[8:0]
Function
Reset
Default
Reserved.
0
STS-1 Signal Fail Clear Threshold 0.
0x113
Number of bit/block errors within detection window
permitted when clearing a signal fail.
0x8419
15:9
—
8:0
RXT_SFCLR1[8:0]
0x841A 15:14
13:0
0x841B 15:14
13:0
0x841C 15:14
13:0
0x841D 15:14
13:0
0x841E 15:14
13:0
0x841F 15:14
13:0
446
—
RXT_SFCLR2[13:0]
—
RXT_SFCLR3[13:0]
—
RXT_SFCLR4[13:0]
—
RXT_SFCLR5[13:0]
—
RXT_SFCLR6[13:0]
—
RXT_SFCLR7[13:0]
Reserved.
STS-1 Signal Fail Clear Threshold 1.
Reserved.
STS-Nc Signal Fail Clear Threshold 2.
Reserved.
STS-Nc Signal Fail Clear Threshold 3.
Reserved.
STS-Nc Signal Fail Clear Threshold 4.
Reserved.
STS-Nc Signal Fail Clear Threshold 5.
Reserved.
STS-Nc Signal Fail Clear Threshold 6.
Reserved.
STS-Nc Signal Fail Clear Threshold 7.
0
0x115
0
0x030B
0
0x031B
0
0x5D8
0
0x0618
0
0x0B08
0
0x0BFC
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 416. RXT_SFWSZR[0—3], Signal Fail Window Size 0—3 Registers (R/W, Control)
Address
Bit
Name
Function
Reset
Default
0x8420
15:0
RXT_SFWSZ0[15:0]
Signal Fail Window Size 0 (in 0.5 ms Increments). A
setting of zero is the same as 1, will produce a 0.5 ms
window size.
0x000A
0x8430
15:0
RXT_SFWSZ1[15:0]
Signal Fail Window Size 1 (in 0.5 ms Increments). A
setting of zero is the same as 1, will produce a 0.5 ms
window size.
0x0064
0x8440
15:0
RXT_SFWSZ2[15:0]
Signal Fail Window Size 2 (in 0.5 ms Increments). A
setting of zero is the same as 1, will produce a 0.5 ms
window size.
0x03E8
0x8450
15:0
RXT_SFWSZ3[15:0]
Signal Fail Window Size 3 (in 0.5 ms Increments). A
setting of zero is the same as 1, will produce a 0.5 ms
window size.
0x2710
Signal Fail Window Size Registers: Above are the settings for the length of the four free-running windows that
are used in conjunction with the set and clear thresholds for the signal fail detection. This time unit depends on the
number of columns in a frame setting. The time unit is four times an STS-frame size, which is 0.5 ms for a system
setting of 90 columns.
After changing one of these window registers, it will take two time unit pules to occur before this new value is used,
i.e., the old window will come to a halt and the new one will begin from 0.5 ms to 1 ms (assuming 90 columns).
Agere Systems Inc.
447
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Concatenation
The expected concatenation map register is programmed via programmable registers (Table 417) on a per timeslot (STS-1) basis. The concatenation state of each time slot can be read from the received concatenation map
register (RXT_RCNCTM_TSBSR[A—D], Received Concatenation Map Time Slots 1—12 in Bytestream A—D
(RO), Table 419). Comparison of the expected and received concatenation state is enabled on a per time-slot basis
by software setting of the concatenation compare enable register (RXT_CNCTCPREN_TSBSR[A—D], Concatenation Compare Enable Time Slots 1—12 in Bytestream A—D (R/W, Control), Table 418). Alarms are binned on a per
bytestream (STS-12) basis in the concatenation map mismatch register (RXT_CNCTMM_ALMBNBSR, Channel
Path Concatenation Map Mismatch Alarm Status Binning Bytestream A—D (RO, COR/COW), Table 344), and
resulting interrupts can be masked by the concatenation map mismatch mask register (see
RXT_CNCTMM_ALMMBSR, Channel Path Concatenation Map Mismatch Alarm Status Masks Bytestream A—D
(R/W), Table 376); mismatches in the first time slot of a bytestream are special cases. When the expected state of
a bytestream is concatenation and the received state is normal, the mismatch status bit for the previous bytestream
will be set since the errored time slot is trying to concatenate to an STS-1 in the previous bytestream.
Table 417. RXT_ECNCTM_TSBSR[A—D], Expected Concatenation Map Time Slots 1—12 in Bytestream
A—D (R/W, Control)
Address
Bit
0x8502, 15:12
0x8503, 11:0
0x8504,
0x8505
Name
—
RXT_ECNCT_STTSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Expected Concatenation State for Time Slots 1—12 in
Bytestream A—D.
0
0 = Time slot not expected to be in concatenation.
1 = Time slot expected to be in concatenation.
Table 418. RXT_CNCTCPREN_TSBSR[A—D], Concatenation Compare Enable Time Slots 1—12 in
Bytestream A—D (R/W, Control)
Address
Bit
0x8507, 15:12
0x8508, 11:0
0x8509,
0x850A
Name
—
RXT_CNCTCPREN_
TSBS[A—D][1—12]
Function
Reset
Default
Reserved.
0
Concatenation Compare Enable Time Slots 1—12 in
Bytestream A—D.
0
0 = Inhibit comparison of received and expected
concatenation states.
1 = Compare received and expected concatenation
states.
Table 419. RXT_RCNCTM_TSBSR[A—D], Received Concatenation Map Time Slots 1—12 in Bytestream
A—D (RO)
Address
Bit
0x8512, 15:12
0x8513, 11:0
0x8514,
0x8515
Name
—
RXT_RCNCT_STTSBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Received Concatenation State for Time Slots 1—12 in
Bytestream A—D.
0
0 = Concatenation state not detected.
1 = Concatenation state detected.
448
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
AIS Insert Control
Table 420. RXT_SWAIS_ISRTR, Software AIS Insert (R/W, Control)
Address
Bit
Name
0x8542, 15:12
0x8543, 11:0
0x8544,
0x8545
Function
—
RXT_SWAIS_ISRT
[A—D][1—12]
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 STS AIS Insert Bytestream
A—D.
0
0 = No AIS insert.
1 = AIS insert.
AIS Insert on UNEQ Control
Table 421. RXT_AISONUNEQ_PR[A—D], Time Slot 1—Time Slot 12 AIS Insert on UNEQ-P Bytestream A—D
(R/W, Control)
Address
Bit
Name
0x8547,
0x8548,
0x8549,
0x854A
15:12
—
11:0
RXT_AISONUNEQ_P
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 AIS Insert on
UNEQ-P Bytestream A—D.
0
AIS Insert on PLM Control
Table 422. RXT_AISONPLM_PR[A—D], Time Slot 1—Time Slot 12 AIS Insert on PLM-P Bytestream A—D
(R/W, Control)
Address
Bit
Name
0x854C,
0x854D,
0x854E,
0x854F
15:12
—
11:0
RXT_AISONPLM_P
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 AIS Insert on PLMP Bytestream A—D.
0
AIS Insert on TIM Control
Table 423. RXT_AISONTIM_PR[A—D], Time Slot 1—Time Slot 12 Software AIS Insert on TIM-P Bytestream
A—D (R/W, Control)
Address
Bit
Name
0x8551,
0x8552,
0x8553,
0x8554
15:12
—
11:0
RXT_AISONTIM_P
[A—D][1—12]
Agere Systems Inc.
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 AIS Insert on TIM-P
Bytestream A—D.
0
449
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Pointer Processor Control
Table 424. RXT_STS12_PINCDECR, STS-12 Pointer Increment/Decrement (R/W, Control)
Address
Bit
Name
0x8580
15:4
—
3:0
RXT_PINCDEC[A—D]
Function
Reset
Default
Reserved.
—
Pointer Increment/Decrement Rules to Use (SONET/
SDH) Bytestream A—D.
1111
Table 425. RXT_TS_INCDECBNR[A—D], Time Slots 1—12 Increment/Decrement Binning Select
Bytestream A—D (R/W, Control)
Address
Bit
Name
0x8590,
0x8591,
0x8592,
0x8593
15:4
—
3:0
RXT_TS_INCDECBN
[A—D][3:0]
Function
Reset
Default
Reserved.
—
Time Slots 1—12 Increment/Decrement Binning
Select Bytestream A—D.
0000
(Disabled)
1111 = None selected counter disabled (see note below).
1110 = None selected counter disabled (see note below).
1101 = None selected counter disabled (see note below).
1100 = STS-1 #12 time slot 12.
1011 = STS-1 #11 time slot 8.
1010 = STS-1 #10 time slot 4.
1001 = STS-1 #9 time slot 11.
1000 = STS-1 #8 time slot 7.
0111 = STS-1 #7 time slot 3.
0110 = STS-1 #6 time slot 10.
0101 = STS-1 #5 time slot 6.
0100 = STS-1 #4 time slot 2.
0011 = STS-1 #3 time slot 9.
0010 = STS-1 #2 time slot 5.
0001 = STS-1 #1 time slot 1.
0000 = None selected counter disabled (see note below).
Note: Selecting 0, 13, 14, 15 will cause the increment/
decrement counter to remain at its last count until
the next PM 1-second pulse when it will clear and
remain at 0 thereafter.
450
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 426. RXT_TSPDIVLD_CTLBSR[A—D], Time Slot 1—Time Slot 12 PDI Validate Control Bytestream
A—D (R/W, Control)
Address
Bit
Name
Function
Reset
Default
Note: There are four PM increment/decrement counters, increment and decrement for both the interpreter and
generator, for each STS-12 group. For a concatenation spanning STS-12 blocks, the select should be set
to the head of the concatenation. It is suggested for clarity that counters not being used be disabled by
setting them to 0; for example, in an STS-48c, bytestream A increment/decrement binning select should be
set to STS-1 #1 and the selects for streams B, C, and D should be set to 0. The increments and decrements
for the entire concatenation should then be read from the stream A registers.
—
Reserved.
0x85A2, 15:12
0x85A3, 11:0 RXT_TSPDIVLD_CTLBS Time Slot 1—Time Slot 12 PDI Validate Control
0x85A4,
[A—D][1—12]
Bytestream A—D.
0x85A5
0 = Disables PDI codes.
1 = Enables PDI codes to affect path status byte.
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—
0
451
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Provisioning
Table 427. RXT_EXPC2_PVSNR[1—24], Expected C2 Byte Provisioning (R/W, Control)
Address
Bit
Name
Function
Reset
Default
0x8600
—
0x8617
15:8
RXT_EXPC2
[1, 3, 5, . . . , 47][7:0]
Time Slots 1, 3, 5, 7, 9, . . . , 47 Expected C2 Byte.
0
7:0
RXT_EXPC2
[2, 4, 6, . . . , 48][7:0]
Time Slots 2, 4, 6, 8, 10, . . . , 48 Expected C2 Byte.
0
Note: The expected C2 byte is only a programming mode and changing them does not affect the validation
counters.
Table 428. RXT_TSCBB_ERRBSR[A—D], Time Slot 1—Time Slot 12 Count Block/Bit Errors Bytestream
A—D
Address
Bit
0x8618, 15:12
0x8619,
11:0
0x861A,
0x861B
452
Name
—
RXT_TSCBB_ERRBS
[A—D][1—12]
Function
Reset
Default
Reserved.
—
Time Slot 1—Time Slot 12 Count Block/Bit Errors
Bytestream A—D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Maintenance
Table 429. RXT_TSMNTR[1—48], Time Slots 1—48 Maintenance (R/W, Control)
Address
Bit
Name
0x8690
—
0x86BF
15:3
—
2:0
RXT_TSSF_TH
[1—48][2:0]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 48 Signal Fail Threshold
Select. This value sets the signal fail threshold for the
respective time slot.
0
Interpreter Increment/Decrement PM
Table 430. RXT_PI_LSECINCR[A—D], Pointer Interpreter Last Second Increments Bytestream A—D (RO)
Address
Bit
0x8702, 15:11
0x8703, 10:0
0x8704,
0x8705
Name
—
RXT_PI_LSECINC
[A—D][10:0]
Function
Reset
Default
Reserved.
0
Last Second Increments in Pointer Interpreter
Bytestream A—D.
0
Table 431. RXT_PI_LSECDECR[A—D], Pointer Interpreter Last Second Decrements Bytestream A—D (RO)
Address
Bit
0x8712, 15:11
0x8713, 10:0
0x8714,
0x8715
Agere Systems Inc.
Name
—
RXT_PI_LSECDEC
[A—D][10:0]
Function
Reset
Default
Reserved.
0
Last Second Decrements in Pointer Interpreter
Bytestream A—D.
0
453
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Performance Monitoring
Table 432. RXT_POH_ALMPMR, Path Overhead Alarm Performance Monitoring (RO)
Address
Bit
Name
0x8780
15:7
—
6
RXT_1BRDI_DPM
Function
Reset
Default
Reserved.
0
One-Bit RDI Defect PM.
0
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
5
RXT_ERDI_PDPM
0
ERDI Payload Defect PM.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
4
RXT_ERDI_CDPM
0
ERDI Connectivity Defect PM.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
3
RXT_ERDI_SDPM
0
ERDI Server Defect PM.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
2
RXT_UNEQR_ALMPM
0
Unequipped Received Alarm PM.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
1
RXT_AIS_ALMPM
0
Alarm Indicator Signal Alarm PM.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
0
RXT_LOP_ALMPM
0
Loss of Pointer Alarm PM.
0 = Alarm has not been detected for any STS-1 in any
bytestream.
1 = Alarm has been detected for one or more STS-1s in
one or more bytestreams.
454
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 433. RXT_1BRDI_DPMBSR, Path Overhead One-Bit RDI Defect PM Bytestream A—D (RO)
Address
Bit
Name
0x8781
15:4
—
3:0
RXT_1BRDI_DPMBS
[A—D]
Function
Reset
Default
Reserved.
0
One-Bit RDI Defect PM Bytestream A—D.
0
0 = One-bit RDI defect PM has not been detected for any
STS-1s in bytestream A—D.
1 = One-bit RDI defect PM has been detected for one or
more STS-1s in bytestream A—D.
Table 434. RXT_TS1BRDI_DPMBSR[A—D], Path Overhead Time Slots 1—12 One-Bit RDI Defect PM
Bytestream A—D (RO)
Address
Bit
Name
0x8782, 15:12
0x8783, 11:0
0x8784,
0x8785
—
RXT_TS1BRDI_DPMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 One-Bit RDI Defect PM
Bytestream A—D.
0
Table 435. RXT_ERDI_PDPMBSR, Path Overhead ERDI Payload Defect PM Bytestream A—D (RO)
Address
Bit
Name
0x8791
15:4
—
3:0
RXT_ERDI_PDPMBS
[A—D]
Function
Reset
Default
Reserved.
0
ERDI Payload Defect PM Bytestream A—D.
0
0 = ERDI payload defect PM has not been detected for
any STS-1s in bytestream A—D.
1 = ERDI payload defect PM has been detected for one or
more STS-1s in bytestream A—D.
Table 436. RXT_TSERDI_PDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Payload Defect PM
Bytestream A—D (RO)
Address
Bit
0x8792, 15:12
0x8793, 11:0
0x8794,
0x8795
Name
—
RXT_TSERDI_PDPMBS
[A—D][1—12]
Agere Systems Inc.
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 ERDI Payload Defect PM
Bytestream A—D.
0
455
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 437. RXT_ERDI_CDPMBSR, Path Overhead ERDI Connectivity Defect PM Bytestream A—D (RO)
Address
Bit
Name
0x87A1
15:4
—
3:0
RXT_ERDI_CDPMBS
[A—D]
Function
Reset
Default
Reserved.
0
ERDI Connectivity Defect PM Bytestream A—D.
0
0 = ERDI connectivity defect PM has not been detected
for any STS-1s in bytestream A—D.
1 = ERDI connectivity defect PM has been detected for
one or more STS-1s in bytestream A—D.
Table 438. RXT_TSERDI_CDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Connectivity Defect PM
Bytestream A—D (RO)
Address
Bit
0x87A2, 15:12
0x87A3, 11:0
0x87A4,
0x87A5
Name
—
RXT_TSERDI_CDPMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 ERDI Connectivity Defect
PM Bytestream A—D.
0
Table 439. RXT_ERDI_SDPMBSR, Path Overhead ERDI Server Defect PM Bytestream A—D (RO)
Address
Bit
Name
0x87B1
15:4
—
3:0
RXT_ERDI_SDPMBS
[A—D]
Function
Reset
Default
Reserved.
0
ERDI Server Defect PM Bytestream A—D.
0
0 = ERDI server defect PM has not been detected for any
STS-1s in bytestream A—D.
1 = ERDI server defect PM has been detected for one or
more STS-1s in bytestream A—D.
Table 440. RXT_TSERDI_SDPMBSR[A—D], Path Overhead Time Slots 1—12 ERDI Server Defect PM
Bytestream A—D (RO)
Address
Bit
0x87B2, 15:12
0x87B3, 11:0
0x87B4,
0x87B5
456
Name
—
RXT_TSERDI_SDPMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 ERDI Server Defect PM
Bytestream A—D.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 441. RXT_UNEQR_PMBSR, Path Overhead Unequipped Received PM Bytestream A—D (RO)
Address
Bit
Name
0x87C1
15:4
—
3:0
RXT_UNEQR_PMBS
[A—D]
Function
Reset
Default
Reserved.
0
Unequipped Received PM Bytestream A—D.
0
0 = Unequipped received PM has not been detected for
any STS-1s in bytestream A—D.
1 = Unequipped received PM has been detected for one
or more STS-1s in bytestream A—D.
Table 442. RXT_TSUNEQR_PMBSR[A—D], Path Overhead Time Slots 1—12 Unequipped Received PM
Bytestream A—D (RO)
Address
Bit
0x87C2, 15:12
0x87C3, 11:0
0x87C4,
0x87C5
Name
—
RXT_TSUNEQR_PMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Unequipped Received PM
Bytestream A—D.
0
Table 443. RXT_AIS_PMBSR, Path Overhead Alarm Indicator Signal PM Bytestream A—D (RO)
Address
Bit
Name
0x87D1
15:4
—
3:0
RXT_AIS_PMBS[A—D]
Function
Reset
Default
Reserved.
0
Alarm Indicator Signal PM Bytestream A—D.
0
0 = Alarm indicator signal PM has not been detected for
any STS-1s in bytestream A—D.
1 = Alarm indicator signal PM has been detected for one
or more STS-1s in bytestream A—D.
Table 444. RXT_TSAIS_PMBSR[A—D], Path Overhead Time Slots 1—12 Alarm Indicator Signal PM
Bytestream A—D (RO)
Address
Bit
0x87D2, 15:12
0x87D3, 11:0
0x87D4,
0x87D5
Agere Systems Inc.
Name
—
RXT_TSAIS_PMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Alarm Indicator Signal PM
Bytestream A—D.
0
457
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
Table 445. RXT_LOP_PMBSR, Path Overhead Loss of Pointer PM Bytestream A—D (RO)
Address
Bit
Name
0x87E1
15:4
—
3:0
Function
Reset
Default
Reserved.
0
0
RXT_LOP_PMBSR[A—D] Loss of Pointer PM Bytestream A—D.
0 = Loss of pointer PM has not been detected for any
STS-1s in bytestream A—D.
1 = Loss of pointer PM has been detected for one or more
STS-1s in bytestream A—D.
Table 446. RXT_TSLOP_PMBSR[A—D], Path Overhead Time Slots 1—12 Loss of Pointer PM
Bytestream A—D (RO)
Address
Bit
0x87E2, 15:12
0x87E3, 11:0
0x87E4,
0x87E5
Name
—
RXT_TSLOP_PMBS
[A—D][1—12]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 12 Loss of Pointer PM
Bytestream A—D.
0
Table 447. RXT_LSECCVP_CPMR[1—48], Last Second CV-P Count Time Slot 1—Time Slot 48 PM (RO)
Address
Bit
Name
0x8800
—
0x882F
15:0
RXT_LSECCVP_CPM
[1—48][15:0]
Function
Time Slot 1—Time Slot 48 CV Count PM.
Reset
Default
0
Table 448. RXT_LSECREIP_CPMR[1—48], Last Second REI-P Count Time Slot 1—Time Slot 48 PM (RO)
Address
Bit
Name
0x8880
—
0x88AF
15:0
RXT_LSECREIP_CPM
[1—48][15:0]
458
Function
Time Slot 1—Time Slot 48 REI Count PM.
Reset
Default
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Descriptions (continued)
RDI, C2, and PDI Status
Table 449. RXT_TSRDIPR[1—48], Time Slots 1—48 Path RDI Status (RO)
Address
Bit
Name
0x8900
—
0x892F
15:3
—
2:0
RXT_TS_RRDI
[1—48][2:0]
Function
Reset
Default
Reserved.
0
Time Slot 1—Time Slot 48 Received RDI Code.
0
Table 450. RXT_TSC2R[1—24], Time Slots 1—48 Path C2 Status (RO)
Address
Bit
Name
Function
Reset
Default
0x8930
—
0x8947
15:8
RXT_TSRC2
[1, 3, . . . , 47][7:0]
Time Slots 1, 3, 5, 7, . . . , 47 Received C2 Byte.
0x13
7:0
RXT_TSRC2
[2, 4, . . . , 48][7:0]
Time Slots 2, 4, 6, 8, . . . , 48 Received C2 Byte.
0x13
Table 451. RXT_TSPDIR[1—24], Time Slots 1—48 Path PDI Status (RO)
Address
Bit
Name
0x8960
—
0x8977
15:8
RXT_TSRPDI
[1, 3, . . . , 47][7:0]
Time Slots 1, 3, 5, 7, . . . , 47 Received PDI Byte.
0
7:0
RXT_TSRPDI
[2, 4, . . . , 48][7:0]
Time Slots 2, 4, 6, 8, . . . , 48 Received PDI Byte.
0
Agere Systems Inc.
Function
Reset
Default
459
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map
Table 452. RXT Register Map
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Version Control (RO)
0x8000
RXT_IDR
0x8001
RXT_CORWR
0x8002
—
0x800E
—
0x800F
RXT_POH_ALMBNR1
0x8010
RXT_POH_ALMBNR2
0x8011
—
0x8030
—
0x8031
RXT_SF_ALMBNBSR
RXT_ID[15:0]
RXT_
CORW
Interrupts
RXT_PDI_ RXT_PDI_
ALMDBN
ALMBN
RXT_RDI_
ALMDBN
RXT_PLM
_ALMDBN
RXT_
UNEQR_
ALMDBN
RXT_AIS_
ALMDBN
RXT_LOP
_ALMDBN
RXT_
J1MM_
ALMBN
RXT_
J1VLD_
ALMBN
RXT_
USCNCT_
ALMBN
RXT_
CNCTMM
_ALMBN
RXT_SF_
ALMBN
RXT_RDI_
ALMBN
RXT_PLM
_ALMBN
RXT_
UNEQR_
ALMBN
RXT_AIS_
ALMBN
RXT_
J1ACCMP
_ALMBN
RXT_LOP
_ALMBN
Signal Fail Binning
RXT_SF_ALMBNBS[A—D]
0x8032
RXT_TSSF_ALMBSRA
Signal Fail Alarm per STS-1 Bytestream A
0x8033
RXT_TSSF_ALMBSRB
Signal Fail Alarm per STS-1 Bytestream B
0x8034
RXT_TSSF_ALMBSRC
Signal Fail Alarm per STS-1 Bytestream C
0x8035
RXT_TSSF_ALMBSRD
Signal Fail Alarm per STS-1 Bytestream D
0x8036
—
0x8040
—
0x8041
RXT_RDI_ALMBNBSR
0x8042
RXT_TSRDI_ALMBSRA
Remote Defect Indicator Alarm per STS-1 Bytestream A
0x8043
RXT_TSRDI_ALMBSRB
Remote Defect Indicator Alarm per STS-1 Bytestream B
0x8044
RXT_TSRDI_ALMBSRC
Remote Defect Indicator Alarm per STS-1 Bytestream C
0x8045
RXT_TSRDI_ALMBSRD
Remote Defect Indicator Alarm per STS-1 Bytestream D
0x8046
—
0x8050
—
RXT_TSSF_ALMBSA[1—12]
RXT_TSSF_ALMBSB[1—12]
RXT_TSSF_ALMBSC[1—12]
RXT_TSSF_ALMBSD[1—12]
Remote Defect Indicator Alarm Binning
RXT_RDI_ALMBNBS[A—D]
RXT_TSRDI_ALMBSA[1—12]
RXT_TSRDI_ALMBSB[1—12]
RXT_TSRDI_ALMBSC[1—12]
RXT_TSRDI_ALMBSD[1—12]
460
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x8051
RXT_PLM_ALMBNBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
0x8052
RXT_TSPLM_ALMBSRA
Payload Label Mismatch Alarm per STS-1 Bytestream A
0x8053
RXT_TSPLM_ALMBSRB
Payload Label Mismatch Alarm per STS-1 Bytestream B
0x8054
RXT_TSPLM_ALMBSRC
Payload Label Mismatch Alarm per STS-1 Bytestream C
0x8055
RXT_TSPLM_ALMBSRD
Payload Label Mismatch Alarm per STS-1 Bytestream D
0x8056
—
0x8060
—
0x8061
RXT_UNEQR_ALMBNBSR
0x8062
RXT_TSUNEQR_ALMBSRA
Unequipped Received Alarm per STS-1 Bytestream A
0x8063
RXT_TSUNEQR_ALMBSRB
Unequipped Received Alarm per STS-1 Bytestream B
0x8064
RXT_TSUNEQR_ALMBSRC
Unequipped Received Alarm per STS-1 Bytestream C
0x8065
RXT_TSUNEQR_ALMBSRD
Unequipped Received Alarm per STS-1 Bytestream D
0x8066
—
0x8070
—
0x8071
RXT_AIS_ALMBNBSR
0x8072
RXT_TSAIS_ALMBSRA
Alarm Indicator Signal Alarm per STS-1 Bytestream A
0x8073
RXT_TSAIS_ALMBSRB
Alarm Indicator Signal Alarm per STS-1 Bytestream B
0x8074
RXT_TSAIS_ALMBSRC
Alarm Indicator Signal Alarm per STS-1 Bytestream C
0x8075
RXT_TSAIS_ALMBSRD
Alarm Indicator Signal Alarm per STS-1 Bytestream D
0x8076
—
0x8080
—
Bit 3
Bit 2
Bit 1
Bit 0
Payload Label Mismatch Alarm Binning
RXT_PLM_ALMBNBS[A—D]
RXT_TSPLM_ALMBSA[1—12]
RXT_TSPLM_ALMBSB[1—12]
RXT_TSPLM_ALMBSC[1—12]
RXT_TSPLM_ALMBSD[1—12]
Unequipped Received Alarm Binning
RXT_UNEQR_ALMBNBS[A—D]
RXT_TSUNEQR_ALMBSA[1—12]
RXT_TSUNEQR_ALMBSB[1—12]
RXT_TSUNEQR_ALMBSC[1—12]
RXT_TSUNEQR_ALMBSD[1—12]
Alarm Indicator Signal Alarm Binning
RXT_AIS_ALMBNBS[A—D]
RXT_TSAIS_ALMBSA[1—12]
RXT_TSAIS_ALMBSB[1—12]
RXT_TSAIS_ALMBSC[1—12]
RXT_TSAIS_ALMBSD[1—12]
Agere Systems Inc.
461
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x8081
RXT_LOP_ALMBNBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
0x8082
RXT_TSLOP_ALMBSRA
Loss of Pointer Alarm per STS-1 Bytestream A
0x8083
RXT_TSLOP_ALMBSRB
Loss of Pointer Alarm per STS-1 Bytestream B
0x8084
RXT_TSLOP_ALMBSRC
Loss of Pointer Alarm per STS-1 Bytestream C
0x8085
RXT_TSLOP_ALMBSRD
Loss of Pointer Alarm per STS-1 Bytestream D
0x8086
—
0x8090
—
0x8091
RXT_CNCTMM_ALMBNBSR
0x8092
—
0x80A0
—
0x80A1
RXT_USCNCTM_ALMBNBSR
0x80A2
—
0x80C0
—
0x80C1
RXT_J1NVLDMSG_
ALMBNBSR
0x80C2
—
0x80D0
—
0x80D1
RXT_J1MSGMM_ALMBNBSR
0x80D2
—
0x8100
—
Bit 3
Bit 2
Bit 1
Bit 0
Loss of Pointer Alarm Binning
RXT_LOP_ALMBNBS[A—D]
RXT_TSLOP_ALMBSA[1—12]
RXT_TSLOP_ALMBSB[1—12]
RXT_TSLOP_ALMBSC[1—12]
RXT_TSLOP_ALMBSD[1—12]
Concatenation Map Mismatch Alarm Binning
RXT_CNCTMM_ALMBNBS[A—D]
Unsupported Concatenation Map Alarm Binning
RXT_USCNCTM_ALMBNBS[A—D]
J1 New Validated Message Alarm Binning
RXT_J1NVLDMSG_ALMBNBS[A—D]
J1 Message Mismatch Alarm Binning
RXT_J1MSGMM_ALMBNBS[A—D]
462
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x8101
RXT_PDI_ALMBNBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x8102
RXT_TSPDI_ALMBSRA
Payload Defect Indicator Alarm per STS-1 Bytestream A
0x8103
RXT_TSPDI_ALMBSRB
Payload Defect Indicator Alarm per STS-1 Bytestream B
0x8104
RXT_TSPDI_ALMBSRC
Payload Defect Indicator Alarm per STS-1 Bytestream C
0x8105
RXT_TSPDI_ALMBSRD
Payload Defect Indicator Alarm per STS-1 Bytestream D
0x8106
—
0x8110
—
0x8111
RXT_RDI_ALMDBNBSR
0x8112
RXT_TSRDI_ALMDBSRA
Remote Defect Indicator Alarm Delta per STS-1 Bytestream A
0x8113
RXT_TSRDI_ALMDBSRB
Remote Defect Indicator Alarm Delta per STS-1 Bytestream B
0x8114
RXT_TSRDI_ALMDBSRC
Remote Defect Indicator Alarm Delta per STS-1 Bytestream C
0x8115
RXT_TSRDI_ALMDBSRD
Remote Defect Indicator Alarm Delta per STS-1 Bytestream D
0x8116
—
0x8120
—
0x8121
RXT_PLM_ALMDBNBSR
0x8122
RXT_TSPLM_ALMDBSRA
Payload Label Mismatch Alarm Delta per STS-1 Bytestream A
0x8123
RXT_TSPLM_ALMDBSRB
Payload Label Mismatch Alarm Delta per STS-1 Bytestream B
0x8124
RXT_TSPLM_ALMDBSRC
Payload Label Mismatch Alarm Delta per STS-1 Bytestream C
0x8125
RXT_TSPLM_ALMDBSRD
Payload Label Mismatch Alarm Delta per STS-1 Bytestream D
0x8126
—
0x8130
—
Bit 2
Bit 1
Bit 0
Payload Defect Indicator Alarm Binning
RXT_PDI_ALMBNBS[A—D]
RXT_TSPDI_ALMBSA[1—12]
RXT_TSPDI_ALMBSB[1—12]
RXT_TSPDI_ALMBSC[1—12]
RXT_TSPDI_ALMBSD[1—12]
Remote Defect Indicator Alarm Delta Binning
RXT_RDI_ALMDBNBS[A—D]
RXT_TSRDI_ALMDBSA[1—12]
RXT_TSRDI_ALMDBSB[1—12]
RXT_TSRDI_ALMDBSC[1—12]
RXT_TSRDI_ALMDBSD[1—12]
Payload Label Mismatch Alarm Delta Binning
RXT_PLM_ALMDBNBS[A—D]
RXT_TSPLM_ALMDBSA[1—12]
RXT_TSPLM_ALMDBSB[1—12]
RXT_TSPLM_ALMDBSC[1—12]
RXT_TSPLM_ALMDBSD[1—12]
Agere Systems Inc.
463
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x8131
RXT_UNEQR_ALMDBNBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
0x8132
RXT_TSUNEQR_ALMDBSRA
Unequipped Received Alarm Delta per STS-1 Bytestream A
0x8133
RXT_TSUNEQR_ALMDBSRB
Unequipped Received Alarm Delta per STS-1 Bytestream B
0x8134
RXT_TSUNEQR_ALMDBSRC
Unequipped Received Alarm Delta per STS-1 Bytestream C
0x8135
RXT_TSUNEQR_ALMDBSRD
Unequipped Received Alarm Delta per STS-1 Bytestream D
0x8136
—
0x8140
—
0x8141
RXT_AIS_ALMDBNBSR
0x8142
RXT_TSAIS_ALMDBSRA
Alarm Indicator Signal Alarm Delta per STS-1 Bytestream A
0x8143
RXT_TSAIS_ALMDBSRB
Alarm Indicator Signal Alarm Delta per STS-1 Bytestream B
0x8144
RXT_TSAIS_ALMDBSRC
Alarm Indicator Signal Alarm Delta per STS-1 Bytestream C
0x8145
RXT_TSAIS_ALMDBSRD
Alarm Indicator Signal Alarm Delta per STS-1 Bytestream D
0x8146
—
0x8150
—
0x8151
RXT_LOP_ALMDBNBSR
0x8152
RXT_TSLOP_ALMDBSRA
Loss of Pointer Alarm Delta per STS-1 Bytestream A
0x8153
RXT_TSLOP_ALMDBSRB
Loss of Pointer Alarm Delta per STS-1 Bytestream B
0x8154
RXT_TSLOP_ALMDBSRC
Loss of Pointer Alarm Delta per STS-1 Bytestream C
0x8155
RXT_TSLOP_ALMDBSRD
Loss of Pointer Alarm Delta per STS-1 Bytestream D
0x8156
—
0x815F
—
Bit 3
Bit 2
Bit 1
Bit 0
Unequipped Received Alarm Delta Binning
RXT_UNEQR_ALMDBNBS[A—D]
RXT_TSUNEQR_ALMDBSA[1—12]
RXT_TSUNEQR_ALMDBSB[1—12]
RXT_TSUNEQR_ALMDBSC[1—12]
RXT_TSUNEQR_ALMDBSD[1—12]
Alarm Indicator Signal Alarm Delta Binning
RXT_AIS_ALMDBNBS[A—D]
RXT_TSAIS_ALMDBSA[1—12]
RXT_TSAIS_ALMDBSB[1—12]
RXT_TSAIS_ALMDBSC[1—12]
RXT_TSAIS_ALMDBSD[1—12]
Loss of Pointer Alarm Delta Binning
RXT_LOP_ALMDBNBS[A—D]
RXT_TSLOP_ALMDBSA[1—12]
RXT_TSLOP_ALMDBSB[1—12]
RXT_TSLOP_ALMDBSC[1—12]
RXT_TSLOP_ALMDBSD[1—12]
464
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x8160
RXT_PTRACCMPIR
0x8161
—
0x8170
—
0x8171
RXT_PDI_ALMDBNBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXT_J1BF
ACCMPI
PDI Alarm Delta Binning
RXT_PDI_ALMDBNBS[A—D]
0x8172
RXT_TSPDI_ALMDBSRA
PDI Alarm Delta per STS-1 Bytestream A
0x8173
RXT_TSPDI_ALMDBSRB
PDI Alarm Delta per STS-1 Bytestream B
0x8174
RXT_TSPDI_ALMDBSRC
PDI Alarm Delta per STS-1 Bytestream C
0x8175
RXT_TSPDI_ALMDBSRD
PDI Alarm Delta per STS-1 Bytestream D
0x8176
—
0x820E
—
RXT_TSPDI_ALMDBSA[1—12]
RXT_TSPDI_ALMDBSB[1—12]
RXT_TSPDI_ALMDBSC[1—12]
RXT_TSPDI_ALMDBSD[1—12]
Agere Systems Inc.
465
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Masks
0x820F
RXT_POH_ALMBNMR1
0x8210
RXT_POH_ALMBNMR2
0x8211
—
0x8220
—
0x8221
RXT_SF_ALMBNMBSR
0x8222
RXT_TSSF_ALMMBSRA
Signal Fail Alarm Mask per STS-1 Bytestream A
0x8223
RXT_TSSF_ALMMBSRB
Signal Fail Alarm Mask per STS-1 Bytestream B
0x8224
RXT_TSSF_ALMMBSRC
Signal Fail Alarm Mask per STS-1 Bytestream C
0x8225
RXT_TSSF_ALMMBSRD
Signal FAil Alarm Mask per STS-1 Bytestream D
0x8226
—
0x8230
—
0x8231
RXT_RDI_ALMBNMBSR
0x8232
RXT_TSRDI_ALMMBSRA
Remote Defect Indicator Alarm Mask per STS-1 Bytestream A
0x8233
RXT_TSRDI_ALMMBSRB
Remote Defect Indicator Alarm Mask per STS-1 Bytestream B
0x8234
RXT_TSRDI_ALMMBSRC
Remote Defect Indicator Alarm Mask per STS-1 Bytestream C
0x8235
RXT_TSRDI_ALMMBSRD
Remote Defect Indicator Alarm Mask per STS-1 Bytestream D
0x8236
—
0x8240
—
RXT_PDI_ RXT_PDI_
RXT_
ALMALMBNM J1ACCMP
DBNM
_ALMBNM
RXT_RDI_
ALMDBNM
RXT_PLM RXT_UNE RXT_AIS_
_ALMDBN QR_ALMD
ALMM
BNM
DBNM
RXT_LOP RXT_J1M RXT_J1VL
_ALMDBN M_ALMBN D_ALMBN
M
M
M
RXT_USC
NCT_ALM
BNM
RXT_CNC
TMM_ALM
BNM
RXT_SF_
ALMBNM
RXT_RDI_ RXT_PLM RXT_UNE
ALMBNM _ALMBNM QR_ALMB
NM
RXT_AIS_ RXT_LOP
ALMBNM _ALMBNM
Signal Fail Alarm Binning Mask
RXT_SF_ALMBNMBS[A—D]
RXT_TSSF_ALMMBSA[1—12]
RXT_TSSF_ALMMBSB[1—12]
RXT_TSSF_ALMMBSC[1—12]
RXT_TSSF_ALMMBSD[1—12]
Remote Defect Indicator Alarm Binning Mask
RXT_RDI_ALMBNMBS[A—D]
RXT_TSRDI_ALMMBSA[1—12]
RXT_TSRDI_ALMMBSB[1—12]
RXT_TSRDI_ALMMBSC[1—12]
RXT_TSRDI_ALMMBSD[1—12]
466
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x8241
RXT_PLM_ALMBNMBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x8242
RXT_TSPLM_ALMMBSRA
Payload Label Mismatch Alarm Mask per STS-1 Bytestream A
0x8243
RXT_TSPLM_ALMMBSRB
Payload Label Mismatch Alarm Mask per STS-1 Bytestream B
0x8244
RXT_TSPLM_ALMMBSRC
Payload Label Mismatch Alarm Mask per STS-1 Bytestream C
0x8245
RXT_TSPLM_ALMMBSRD
Payload Label Mismatch Alarm Mask per STS-1 Bytestream D
0x8246
—
0x8250
—
0x8251
RXT_UNEQR_ALMBNMBSR
0x8252
RXT_TSUNEQR_ALMMBSRA
Unequipped Received Alarm Mask per STS-1 Bytestream A
0x8253
RXT_TSUNEQR_ALMMBSB
Unequipped Received Alarm Mask per STS-1 Bytestream B
0x8254
RXT_TSUNEQR_ALMMBSC
Unequipped Received Alarm Mask per STS-1 Bytestream C
0x8255
RXT_TSUNEQR_ALMMBSD
Unequipped Received Alarm Mask per STS-1 Bytestream D
0x8256
—
0x8260
—
0x8261
RXT_AIS_ALMBNMBSR
0x8262
RXT_TSAIS_ALMMBSRA
Alarm Indicator Signal Alarm Mask per STS-1 Bytestream A
0x8263
RXT_TSAIS_ALMMBSRB
Alarm Indicator Signal Alarm Mask per STS-1 Bytestream B
0x8264
RXT_TSAIS_ALMMBSRC
Alarm Indicator Signal Alarm Mask per STS-1 Bytestream C
0x8265
RXT_TSAIS_ALMMBSRD
Alarm Indicator Signal Alarm Mask per STS-1 Bytestream D
0x8266
—
0x8270
—
Bit 2
Bit 1
Bit 0
Payload Label Mismatch Alarm Binning Mask
RXT_PLM_ALMBNMBS[A—D]
RXT_TSPLM_ALMMBSA[1—12]
RXT_TSPLM_ALMMBSB[1—12]
RXT_TSPLM_ALMMBSC[1—12]
RXT_TSPLM_ALMMBSD[1—12]
Unequipped Received Alarm Binning Mask
RXT_UNEQR_ALMBNMBS[A—D]
RXT_TSUNEQR_ALMMBSA[1—12]
RXT_TSUNEQR_ALMMBSB[1—12]
RXT_TSUNEQR_ALMMBSC[1—12]
RXT_TSUNEQR_ALMMBSD[1—12]
Alarm Indicator Signal Alarm Binning Mask
RXT_AIS_ALMBNMBS[A—D]
RXT_TSAIS_ALMMBSA[1—12]
RXT_TSAIS_ALMMBSB[1—12]
RXT_TSAIS_ALMMBSC[1—12]
RXT_TSAIS_ALMMBSD[1—12]
Agere Systems Inc.
467
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x8271
RXT_LOP_ALMBNMBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x8272
RXT_TSLOP_ALMMBSRA
Loss of Pointer Alarm Mask per STS-1 Bytestream A
0x8273
RXT_TSLOP_ALMMBSRB
Loss of Pointer Alarm Mask per STS-1 Bytestream B
0x8274
RXT_TSLOP_ALMMBSRC
Loss of Pointer Alarm Mask per STS-1 Bytestream C
0x8275
RXT_TSLOP_ALMMBSRD
Loss of Pointer Alarm Mask per STS-1 Bytestream D
0x8276
—
0x8277
RXT_CNCTMM_ALMMBSR
0x8278
—
0x8279
RXT_USCNCTM_ALMMBSR
0x827A
—
0x827B
RXT_J1NVLDMSG_ALMMBSR
0x827C
—
0x827D
RXT_J1MSGMM_ALMMBSR
0x827E
—
0x8280
—
0x8281
RXT_PDI_ALMBNMBSR
0x8282
RXT_TSPDI_ALMMBSRA
Payload Defect Indicator Alarm Mask per STS-1 Bytestream A
0x8283
RXT_TSPDI_ALMMBSRB
Payload Defect Indicator Alarm Mask per STS-1 Bytestream B
0x8284
RXT_TSPDI_ALMMBSRC
Payload Defect Indicator Alarm Mask per STS-1 Bytestream C
0x8285
RXT_TSPDI_ALMMBSRD
Payload Defect Indicator Alarm Mask per STS-1 Bytestream D
0x8286
—
0x8290
—
Bit 2
Bit 1
Bit 0
Loss of Pointer Alarm Binning Mask
RXT_LOP_ALMBNMBS[A—D]
RXT_TSLOP_ALMMBSA[1—12]
RXT_TSLOP_ALMMBSB[1—12]
RXT_TSLOP_ALMMBSC[1—12]
RXT_TSLOP_ALMMBSD[1—12]
Concatenation Map Mismatch Alarm Mask
RXT_CNCTMM_ALMMBS[A—D]
Unsupported Concatenation Map Alarm Mask
RXT_USCNCTM_ALMMBS[A—D]
J1 New Validated Message Alarm Mask
RXT_J1NVLDMSG_ALMMBS[A—D]
J1 Message Mismatch Alarm Mask
RXT_J1MSGMM_ALMMBS[A—D]
Payload Defect Indicator Alarm Binning Mask
RXT_PDI_ALMBNMBS[A—D]
RXT_TSPDI_ALMMBSA[1—12]
RXT_TSPDI_ALMMBSB[1—12]
RXT_TSPDI_ALMMBSC[1—12]
RXT_TSPDI_ALMMBSD[1—12]
468
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x8291
RXT_RDI_ALMDBNMBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0x8292
RXT_TSRDI_ALMDMBSRA
Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream A
0x8293
RXT_TSRDI_ALMDMBSRB
Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream B
0x8294
RXT_TSRDI_ALMDMBSRC
Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream C
0x8295
RXT_TSRDI_ALMDMBSRD
Remote Defect Indicator Alarm Delta Mask per STS-1 Bytestream D
0x8296
—
0x82A0
—
0x82A1
RXT_PLM_ALMDBNMBSR
0x82A2
RXT_TSPLM_ALMDMBSRA
Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream A
0x82A3
RXT_TSPLM_ALMDMBSRB
Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream B
0x82A4
RXT_TSPLM_ALMDMBSRC
Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream C
0x82A5
RXT_TSPLM_ALMDMBSRD
Payload Label Mismatch Alarm Delta Mask per STS-1 Bytestream D
0x82A6
—0x82B
—
0x82B1
RXT_UNEQR_ALMDBNMBSR
0x82B2
RXT_TSUNEQR_ALMDMBSRA
Unequipped Received Alarm Delta Mask per STS-1 Bytestream A
0x82B3
RXT_TSUNEQR_ALMDMBSRB
Unequipped Received Alarm Delta Mask per STS-1 Bytestream B
0x82B4
RXT_TSUNEQR_ALMDMBSRC
Unequipped Received Alarm Delta Mask per STS-1 Bytestream C
0x82B5
RXT_TSUNEQR_ALMDMBSRD
Unequipped Received Alarm Delta Mask per STS-1 Bytestream D
0x82B6
—
0x82C0
—
Bit 2
Bit 1
Bit 0
Remote Defect Indicator Alarm Delta Binning Mask
RXT_RDI_ALMBNDMBS[A—D]
RXT_TSRDI_ALMDMBSA[1—12]
RXT_TSRDI_ALMDMBSB[1—12]
RXT_TSRDI_ALMDMBSC[1—12]
RXT_TSRDI_ALMDMBSD[1—12]
Payload Label Mismatch Alarm Delta Binning Mask
RXT_PLM_ALMDBNMBS[A—D]
RXT_TSPLM_ALMDMBSA[1—12]
RXT_TSPLM_ALMDMBSB[1—12]
RXT_TSPLM_ALMDMBSC[1—12]
RXT_TSPLM_ALMDMBSD[1—12]
Unequipped Received Alarm Delta Binning Mask
RXT_UNEQR_ALMDBNMBS[A—D]
RXT_TSUNEQR_ALMDMBSA[1—12]
RXT_TSUNEQR_ALMDMBSB[1—12]
RXT_TSUNEQR_ALMDMBSC[1—12]
RXT_TSUNEQR_ALMDMBSD[1—12]
Agere Systems Inc.
469
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x82C1
RXT_AIS_ALMDBNMBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0x82C2
RXT_TSAIS_ALMDMBSRA
Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream A
0x82C3
RXT_TSAIS_ALMDMBSRB
Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream B
0x82C4
RXT_TSAIS_ALMDMBSRC
Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream C
0x82C5
RXT_TSAIS_ALMDMBSRD
Alarm Indicator Signal Alarm Delta Mask per STS-1 Bytestream D
0x82C6
—
0x82D0
—
0x82D1
RXT_LOP_ALMDBNMBSR
0x82D2
RXT_TSLOP_ALMDMBSRA
Loss of Pointer Alarm Delta Mask per STS-1 Bytestream A
0x82D3
RXT_TSLOP_ALMDMBSRB
Loss of Pointer Alarm Delta Mask per STS-1 Bytestream B
0x82D4
RXT_TSLOP_ALMDMBSRC
Loss of Pointer Alarm Delta Mask per STS-1 Bytestream C
0x82D5
RXT_TSLOP_ALMDMBSRD
Loss of Pointer Alarm Delta Mask per STS-1 Bytestream D
0x82D6
—
0x82DF
—
0x82E0
RXT_PTRACCMPIR
0x82E1
—
0x82E8
—
Bit 1
Bit 0
Alarm Indicator Signal Alarm Delta Binning Mask
RXT_AIS_ALMDBNMBS[A—D]
RXT_TSAIS_ALMDMBSA[1—12]
RXT_TSAIS_ALMDMBSB[1—12]
RXT_TSAIS_ALMDMBSC[1—12]
RXT_TSAIS_ALMDMBSD[1—12]
Loss of Pointer Alarm Delta Binning Mask
RXT_LOP_ALMDBNMBS[A—D]
RXT_TSLOP_ALMDMBSA[1—12]
RXT_TSLOP_ALMDMBSB[1—12]
RXT_TSLOP_ALMDMBSC[1—12]
RXT_TSLOP_ALMDMBSD[1—12]
470
RXT_J1BFACCMPIM
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x82E9
RXT_PDI_ALMDBNMBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
0x82EA
RXT_TSPDI_ALMDMBSRA
PDI Alarm Delta Mask per STS-1 Bytestream A
0x82EB
RXT_TSPDI_ALMDMBSRB
PDI Alarm Delta Mask per STS-1 Bytestream B
0x82EC
RXT_TSPDI_ALMDMBSRC
PDI Alarm Delta Mask per STS-1 Bytestream C
0x82ED
RXT_TSPDI_ALMDMBSRD
PDI Alarm Delta Mask per STS-1 Bytestream D
0x82EE
—
0x82FF
—
Bit 3
Bit 2
Bit 1
Bit 0
PDI Alarm Delta Binning Mask
RXT_PDI_ALMDBNMBS[A—D]
RXT_TSPDI_ALMDMBSA[1—12]
RXT_TSPDI_ALMDMBSB[1—12]
RXT_TSPDI_ALMDMBSC[1—12]
RXT_TSPDI_ALMDMBSD[1—12]
Agere Systems Inc.
471
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Path Trace
—
—
J1 Byte 1, 3, 5, . . . , 63 Path Trace Buffer
J1 Byte 0, 2, 4, . . . , 62 Path Trace Buffer
0x8300
—
0x831F
RXT_PTRBFR[1—32]
RXT_J1BYTE[1, 3, 5, . . . , 63][7:0]
RXT_J1BYTE[0, 2, 4, . . . , 62][7:0]
0x8330
RXT_PTRACCTLR1
RXT_J1TS1_CHSEL[1:0]
0x8331
RXT_PTRACCTLR2
RXT_J1BF
_MSGSEL
0x8332
RXT_PTRACCTLR3
RXT_J1BF
_ACTYP
0x8333
RXT_PTRACBGR
RXT_J1_A
CBG
0x8334
—
0x8337
—
0x8338
RXT_STS12PTRCTLR1
J1 Message Mode Select
RXT_J1MSG_MSEL[A—D]
0x8339
RXT_STS12PTRCTLR2
J1 Message Type Select
RXT_J1MSG_TYPSEL[A—D]
0x833A
—
0x833B
—
0x833C
RXT_STS12PTRCTLR3
0x833D
RXT_STS12PTRCTLR4
RXT_TSSEL_J1B[3:0]
0x833E
RXT_STS12PTRCTLR5
RXT_TSSEL_J1C[3:0]
0x833F
RXT_STS12PTRCTLR6
RXT_TSSEL_J1D[3:0]
0x8340
—
0x837F
—
472
Time Slots 1—12 Select for J1 Accumulation
RXT_TSSEL_J1A[3:0]
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Persistency
0x8380
—
0x8381
—
0x8382
RXT_TSRDI_ALMPSBSRA
RDI Alarm Persistency per STS-1 Bytestream A
0x8383
RXT_TSRDI_ALMPSBSRB
RDI Alarm Persistency per STS-1 Bytestream B
0x8384
RXT_TSRDI_ALMPSBSRC
RDI Alarm Persistency per STS-1 Bytestream C
0x8385
RXT_TSRDI_ALMPSBSRD
RDI Alarm Persistency per STS-1 Bytestream D
0x8386
—
0x8389
—
0x838A
RXT_TSPLM_ALMPSBSRA
Payload Label Mismatch Alarm Persistency per STS-1 Bytestream A
0x838B
RXT_TSPLM_ALMPSBSRB
Payload Label Mismatch Alarm Persistency per STS-1 Bytestream B
0x838C
RXT_TSPLM_ALMPSBSRC
Payload Label Mismatch Alarm Persistency per STS-1 Bytestream C
0x838D
RXT_TSPLM_ALMPSBSRD
Payload Label Mismatch Alarm Persistency per STS-1 Bytestream D
0x838E
—
0x8391
—
0x8392
RXT_TSPUNEQ_ALMPSBSRA
Path Unequipped Alarm Persistency per STS-1 Bytestream A
0x8393
RXT_TSPUNEQ_ALMPSBSRB
Path Unequipped Alarm Persistency per STS-1 Bytestream B
0x8394
RXT_TSPUNEQ_ALMPSBSR
C
Path Unequipped Alarm Persistency per STS-1 Bytestream C
0x8395
RXT_TSPUNEQ_ALMPSBSR
D
Path Unequipped Alarm Persistency per STS-1 Bytestream D
0x8396
—
0x8399
—
RXT_TSRDI_ALMPSBSA[1—12]
RXT_TSRDI_ALMPSBSB[1—12]
RXT_TSRDI_ALMPSBSC[1—12]
RXT_TSRDI_ALMPSBSD[1—12]
RXT_TSPLM_ALMPSBSA[1—12]
RXT_TSPLM_ALMPSBSB[1—12]
RXT_TSPLM_ALMPSBSC[1—12]
RXT_TSPLM_ALMPSBSD[1—12]
RXT_TSPUNEQ_ALMPSBSA[1—12]
RXT_TSPUNEQ_ALMPSBSB[1—12]
Agere Systems Inc.
RXT_TSPUNEQ_ALMPSBSC[1—12]
RXT_TSPUNEQ_ALMPSBSD[1—12]
473
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x839A
RXT_TSAIS_ALMPSBSRA
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
AIS Alarm Persistency per STS-1 Bytestream A
Bit 7
Bit 6
Bit 5
Bit 4
0x839B
RXT_TSAIS_ALMPSBSRB
AIS Alarm Persistency per STS-1 Bytestream B
0x839C
RXT_TSAIS_ALMPSBSRC
AIS Alarm Persistency per STS-1 Bytestream C
0x839D
RXT_TSAIS_ALMPSBSRD
AIS Alarm Persistency per STS-1 Bytestream D
0x839E
—
0x83A1
—
0x83A2
RXT_TSLOP_ALMPSBSRA
LOP Alarm Persistency per STS-1 Bytestream A
0x83A3
RXT_TSLOP_ALMPSBSRB
LOP Alarm Persistency per STS-1 Bytestream B
0x83A4
RXT_TSLOP_ALMPSBSRC
LOP Alarm Persistency per STS-1 Bytestream C
0x83A5
RXT_TSLOP_ALMPSBSRD
LOP Alarm Persistency per STS-1 Bytestream D
0x83A6
—
0x83A9
—
0x83AA
RXT_TSPDI_ALMPSBSRA
PDI Alarm Persistency per STS-1 Bytestream A
0x83AB
RXT_TSPDI_ALMPSBSRB
PDI Alarm Persistency per STS-1 Bytestream B
0x83AC
RXT_TSPDI_ALMPSBSRC
PDI Alarm Persistency per STS-1 Bytestream C
0x83AD
RXT_TSPDI_ALMPSBSRD
PDI Alarm Persistency per STS-1 Bytestream D
0x83AE
—
0x83BF
—
Bit 3
Bit 2
Bit 1
Bit 0
RXT_TSAIS_ALMPSBSA[1—12]
RXT_TSAIS_ALMPSBSB[1—12]
RXT_TSAIS_ALMPSBSC[1—12]
RXT_TSAIS_ALMPSBSD[1—12]
RXT_TSLOP_ALMPSBSA[1—12]
RXT_TSLOP_ALMPSBSB[1—12]
RXT_TSLOP_ALMPSBSC[1—12]
RXT_TSLOP_ALMPSBSD[1—12]
RXT_TSPDI_ALMPSBSA[1—12]
RXT_TSPDI_ALMPSBSB[1—12]
RXT_TSPDI_ALMPSBSC[1—12]
RXT_TSPDI_ALMPSBSD[1—12]
474
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State
0x83C0
—
0x83C1
—
0x83C2
RXT_TSRDI_STBSRA
RDI State per STS-1 Bytestream A
0x83C3
RXT_TSRDI_STBSRB
RDI State per STS-1 Bytestream B
0x83C4
RXT_TSRDI_STBSRC
RDI State per STS-1 Bytestream C
0x83C5
RXT_TSRDI_STBSRD
RDI State per STS-1 Bytestream D
0x83C6
—
0x83C9
—
0x83CA
RXT_TSPLM_STBSRA
Payload Label Mismatch State per STS-1 Bytestream A
0x83CB
RXT_TSPLM_STBSRB
Payload Label Mismatch State per STS-1 Bytestream B
0x83CC
RXT_TSPLM_STBSRC
Payload Label Mismatch State per STS-1 Bytestream C
0x83CD
RXT_TSPLM_STBSRD
Payload Label Mismatch State per STS-1 Bytestream D
0x83CE
—
0x83D1
—
0x83D2
RXT_TSPUNEQ_STBSRA
Path Unequipped State per STS-1 Bytestream A
0x83D3
RXT_TSPUNEQ_STBSRB
Path Unequipped State per STS-1 Bytestream B
0x83D4
RXT_TSPUNEQ_STBSRC
Path Unequipped State per STS-1 Bytestream C
0x83D5
RXT_TSPUNEQ_STBSRD
Path Unequipped State per STS-1 Bytestream D
0x83D6
—
0x83D9
—
RXT_TSRDI_STBSA[1—12]
RXT_TSRDI_STBSB[1—12]
RXT_TSRDI_STBSC[1—12]
RXT_TSRDI_STBSD[1—12]
RXT_TSPLM_STBSA[1—12]
RXT_TSPLM_STBSB[1—12]
RXT_TSPLM_STBSC[1—12]
RXT_TSPLM_STBSD[1—12]
RXT_TSPUNEQ_STBSA[1—12]
RXT_TSPUNEQ_STBSB[1—12]
RXT_TSPUNEQ_STBSC[1—12]
RXT_TSPUNEQ_STBSD[1—12]
Agere Systems Inc.
475
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x83DA
RXT_TSAIS_STBSRA
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
AIS State per STS-1 Bytestream A
Bit 6
Bit 5
Bit 4
0x83DB
RXT_TSAIS_STBSRB
AIS State per STS-1 Bytestream B
0x83DC
RXT_TSAIS_STBSRC
AIS State per STS-1 Bytestream C
0x83DD
RXT_TSAIS_STBSRD
AIS State per STS-1 Bytestream D
0x83DE
—
0x83E1
—
0x83E2
RXT_TSLOP_STBSRA
LOP State per STS-1 Bytestream A
0x83E3
RXT_TSLOP_STBSRB
LOP State per STS-1 Bytestream B
0x83E4
RXT_TSLOP_STBSRC
LOP State per STS-1 Bytestream C
0x83E5
RXT_TSLOP_STBSRD
LOP State per STS-1 Bytestream D
0x83E6
—
0x83E9
—
0x83EA
RXT_TSPDI_STBSRA
PDI State per STS-1 Bytestream A
0x83EB
RXT_TSPDI_STBSRB
PDI State per STS-1 Bytestream B
0x83EC
RXT_TSPDI_STBSRC
PDI State per STS-1 Bytestream C
0x83ED
RXT_TSPDI_STBSRD
LOP State per STS-1 Bytestream D
0x83EE
—
0x83FF
—
Bit 3
Bit 2
Bit 1
Bit 0
RXT_TSAIS_STBSA[1—12]
RXT_TSAIS_STBSB[1—12]
RXT_TSAIS_STBSC[1—12]
RXT_TSAIS_STBSD[1—12]
RXT_TSLOP_STBSA[1—12]
RXT_TSLOP_STBSB[1—12]
RXT_TSLOP_STBSC[1—12]
RXT_TSLOP_STBSD[1—12]
RXT_TSPDI_STBSA[1—12]
RXT_TSPDI_STBSB[1—12]
RXT_TSPDI_STBSC[1—12]
RXT_TSPDI_STBSD[1—12]
476
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Signal Fail
0x8400
RXT_SFWSZ_SELR1
RXT_SFWSZ_SELSET[0—7][1:0]
0x8401
RXT_SFWSZ_SELR2
RXT_SFWSZ_SELCLR[0—7][1:0]
0x8402
—
0x840F
—
0x8410
RXT_SFDR0
0x8411
RXT_SFDR1
RXT_SFD0[8:0]
0x8412
RXT_SFDR2
RXT_SFD2[13:0]
0x8413
RXT_SFDR3
RXT_SFD3[13:0]
0x8414
RXT_SFDR4
RXT_SFD4[13:0]
0x8415
RXT_SFDR5
RXT_SFD5[13:0]
0x8416
RXT_SFDR6
RXT_SFD6[13:0]
0x8417
RXT_SFDR7
RXT_SFD7[13:0]
0x8418
RXT_SFCLRR0
0x8419
RXT_SFCLRR1
0x841A
RXT_SFCLRR2
RXT_SFCLR2[13:0]
RXT_SFD1[8:0]
RXT_SFCLR0[8:0]
RXT_SFCLR1[8:0]
0x841B
RXT_SFCLRR3
RXT_SFCLR3[13:0]
0x841C
RXT_SFCLRR4
RXT_SFCLR4[13:0]
0x841D
RXT_SFCLRR5
RXT_SFCLR5[13:0]
0x841E
RXT_SFCLRR6
RXT_SFCLR6[13:0]
0x841F
RXT_SFCLRR7
0x8420
RXT_SFWSZR0
0x8421
—
0x842F
—
0x8430
RXT_SFWSZR1
0x8431
—
0x843F
—
0x8440
RXT_SFWSZR2
0x8441
—
0x844F
—
0x8450
RXT_SFWSZR3
0x8451
—
0x8501
—
Agere Systems Inc.
RXT_SFCLR7[13:0]
RXT_SFWSZ0[15:0]
RXT_SFWSZ1[15:0]
RXT_SFWSZ2[15:0]
RXT_SFWSZ3[15:0]
477
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Concatenation
0x8502
RXT_ECNCTM_TSBSRA
Expected Concatenation Map Bytestream A
0x8503
RXT_ECNCTM_TSBSRB
Expected Concatenation Map Bytestream B
0x8504
RXT_ECNCTM_TSBSRC
Expected Concatenation Map Bytestream C
0x8505
RXT_ECNCTM_TSBSRD
Expected Concatenation Map Bytestream D
0x8506
—
0x8507
RXT_CNCTCPREN_TSBSRA
Software Concatenation Compare Enable Bytestream A
0x8508
RXT_CNCTCPREN_TSBSRB
Software Concatenation Compare Enable Bytestream B
0x8509
RXT_CNCTCPREN_TSBSRC
Software Concatenation Compare Enable Bytestream C
0x850A
RXT_CNCTCPREN_TSBSRD
Software Concatenation Compare Enable Bytestream D
0x850B
—
0x8511
—
0x8512
RXT_RCNCTM_TSBSRA
Received Concatenation Map Bytestream A
0x8513
RXT_RCNCTM_TSBSRB
Received Concatenation Map Bytestream B
0x8514
RXT_RCNCTM_TSBSRC
Received Concatenation Map Bytestream C
0x8515
RXT_RCNCTM_TSBSRD
Received Concatenation Map Bytestream D
0x8516
—
0x8541
—
RXT_ECNCT_STTSBSA[1—12]
RXT_ECNCT_STTSBSB[1—12]
RXT_ECNCT_STTSBSC[1—12]
RXT_ECNCT_STTSBSD[1—12]
RXT_CNCTCPREN_TSBSA[1—12]
RXT_CNCTCPREN_TSBSB[1—12]
RXT_CNCTCPREN_TSBSC[1—12]
RXT_CNCTCPREN_TSBSD[1—12]
RXT_RCNCT_STTSBSA[1—12]
RXT_RCNCT_STTSBSB[1—12]
RXT_RCNCT_STTSBSC[1—12]
RXT_RCNCT_STTSBSD[1—12]
478
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AIS Insert Control
0x8542
RXT_SWAIS_ISRTRA
AIS Insert Bytestream A
RXT_SWAIS_ISRTA[1—12]
0x8543
RXT_SWAIS_ISRTRB
AIS Insert Bytestream B
RXT_SWAIS_ISRTB[1—12]
0x8544
RXT_SWAIS_ISRTRC
AIS Insert Bytestream C
RXT_SWAIS_ISRTC[1—12]
0x8545
RXT_SWAIS_ISRTRD
AIS Insert Bytestream D
RXT_SWAIS_ISRTD[1—12]
0x8546
—
0x8547
RXT_AISONUNEQ_PRA
AIS Insert on UNEQ Control Bytestream A
0x8548
RXT_AISONUNEQ_PRB
AIS Insert on UNEQ Control Bytestream B
0x8549
RXT_AISONUNEQ_PRC
AIS Insert on UNEQ Control Bytestream C
0x854A
RXT_AISONUNEQ_PRD
AIS Insert on UNEQ Control Bytestream D
0x854B
—
0x854C
RXT_AISONPLM_PRA
AIS Insert on PLM Control Bytestream A
0x854D
RXT_AISONPLM_PRB
AIS Insert on PLM Control Bytestream B
0x854E
RXT_AISONPLM_PRC
AIS Insert on PLM Control Bytestream C
0x854F
RXT_AISONPLM_PRD
AIS Insert on PLM Control Bytestream D
0x8550
—
0x8551
RXT_AISONTIM_PRA
AIS Insert on TIM Control Bytestream A
0x8552
RXT_AISONTIM_PRB
AIS Insert on TIM Control Bytestream B
0x8553
RXT_AISONTIM_PRC
AIS Insert on TIM Control Bytestream C
0x8554
RXT_AISONTIM_PRD
AIS Insert on TIM Control Bytestream D
0x8555
—
0x857F
—
RXT_AISONUNEQ_PA[1—12]
RXT_AISONUNEQ_PB[1—12]
RXT_AISONUNEQ_PC[1—12]
RXT_AISONUNEQ_PD[1—12]
RXT_AISONPLM_PA[1—12]
RXT_AISONPLM_PB{1—12]
RXT_AISONPLM_PC[1—12]
RXT_AISONPLM_PD[1—12]
RXT_AISONTIM_PA[1—12]
RXT_AISONTIM_PB[1—12]
RXT_AISONTIM_PC[1—12]
RXT_AISONTIM_PD[1—12]
Agere Systems Inc.
479
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pointer Processor Control
0x8580
RXT_STS12_PINCDECR
0x8581
—
0x858F
—
0x8590
RXT_TS_INCDECBNRA
STS-1 Inc/Dec Binning Select Bytestream A
RXT_TS_INCDECBNA[3:0]
0x8591
RXT_TS_INCDEBNCRB
STS-1 Inc/Dec Binning Select Bytestream B
RXT_TS_INCDECBNB[3:0]
0x8592
RXT_TS_INCDECBNRC
STS-1 Inc/Dec Binning Select Bytestream C
RXT_TS_INCDECBNC[3:0]
0x8593
RXT_TS_INCDECBNRD
STS-1 Inc/Dec Binning Select Bytestream D
RXT_TS_INCDECBND[3:0]
0x8594
—
0x85A1
—
0x85A2
RXT_TSPDIVLD_CTLBSRA
PDI Validate Control Bytestream A
0x85A3
RXT_TSPDIVLD_CTLBSRB
PDI Validate Control Bytestream B
0x85A4
RXT_TSPDIVLD_CTLBSRC
PDI Validate Control Bytestream C
0x85A5
RXT_TSPDIVLD_CTLBSRD
PDI Validate Control Bytestream D
0x85A6
—
0x85FF
—
SONET/SDH Pointer Inc/Dec Rules
RXT_PINCDEC[A—D]
RXT_TSPDIVLD_CTLBSA[1—12]
RXT_TSPDIVLD_CTLBSB[1—12]
RXT_TSPDIVLD_CTLBSC[1—12]
RXT_TSPDIVLD_CTLBSD[1—12]
480
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Provisioning
—
—
Time Slots 1, 3, 5, . . . , 47 Expected C2 Bytes
Time Slots 2, 4, 6, . . . , 48 Expected C2 Bytes
0x8600
—
0x8617
RXT_EXPC2_PVSNR[1—24]
RXT_EXPC2[1, 3, 5, . . . , 47][7:0]
RXT_EXPCP[2, 4, 6, . . . , 48][7:0]
0x8618
RXT_TSCBB_ERRBSRA
Count Bit/Block Errors Bytestream A
0x8619
RXT_TSCBB_ERRBSRB
Count Bit/Block Errors Bytestream B
0x861A
RXT_TSCBB_ERRBSRC
Count Bit/Block Errors Bytestream C
0x861B
RXT_TSCBB_ERRBSRD
Count Bit/Block Errors Bytestream D
0x861C
—
0x8681
—
RXT_TSCBB_ERRBSA[1—12]
RXT_TSCBB_ERRBSB[1—12]
RXT_TSCBB_ERRBSC[1—12]
RXT_TSCBB_ERRBSD[1—12]
Agere Systems Inc.
481
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Maintenance
0x8682
—
0x868F
—
0x8690
—
0x86BF
RXT_TSMNTR[1—48]
0x86C0
—
0x8701
—
0x8702
RXT_PI_LSECINCRA
0x8703
RXT_PI_LSECINCRB
RXT_PI_LSECINCB[10:0]
0x8704
RXT_PI_LSECINCRC
RXT_PI_LSECINCC[10:0]
0x8705
RXT_PI_LSECINCRD
RXT_PI_LSECINCD[10:0]
0x8706
—
0x8711
—
0x8712
RXT_PI_LSECDECRA
0x8713
RXT_PI_LSECDECRB
RXT_PI_LSECDECB[10:0]
0x8714
RXT_PI_LSECDECRC
RXT_PI_LSECDECC[10:0]
0x8715
RXT_PI_LSECDECRD
RXT_PI_LSECDECD[10:0]
0x8716
—
0x877F
—
RXT_TSSF_TH[1—48][2:0]
Interpreter Inc/Dec (PM)
482
RXT_PI_LSECINCA[10:0]
RXT_PI_LSECDECA[10:0]
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXT_AIS_
ALMPM
RXT_LOP
_ALMPM
Performance Monitoring
0x8780
RXT_POH_ALMPMR
0x8781
RXT_1BRDI_DPMBSR
RXT_1BR
DI_DPM
RXT_ERDI RXT_ERDI RXT_ERDI RXT_UNE
_PDPM
_CDPM
_SDPM
QR_ALMP
M
One-Bit RDI Alarm PM
RXT_1BRDI_DPMBS[A—D]
0x8782
RXT_TS1BRDI_DPMBSRA
One-Bit RDI Alarm PM per STS-1 Bytestream A
0x8783
RXT_TS1BRDI_DPMBSRB
One-Bit RDI Alarm PM per STS-1 Bytestream B
0x8784
RXT_TS1BRDI_DPMBSRC
One-Bit RDI Alarm PM per STS-1 Bytestream C
0x8785
RXT_TS1BRDI_DPMBSRD
One-Bit RDI Alarm PM per STS-1 Bytestream D
0x8786
—
0x8790
—
0x8791
RXT_ERDI_PDPMBSR
RXT_TS1BRDI_DPMBSA[1—12]
RXT_TS1BRDI_DPMBSB[1—12]
RXT_TS1BRDI_DPMBSC[1—12]
RXT_TS1BRDI_DPMBSD[1—12]
ERDI Payload Alarm PM
RXT_ERDI_PDPMBS[A—D]
0x8792
RXT_ERDI_PDPMBSRA
ERDI Payload Alarm PM per STS-1 Bytestream A
0x8793
RXT_ERDI_PDPMBSRB
ERDI Payload Alarm PM per STS-1 Bytestream B
0x8794
RXT_ERDI_PDPMBSRC
ERDI Payload Alarm PM per STS-1 Bytestream C
0x8795
RXT_ERDI_PDPMBSRD
ERDI Payload Alarm PM per STS-1 Bytestream D
0x8796
—
0x87A0
—
0x87A1
RXT_ERDI_CDPMBSR
0x87A2
RXT_TSERDI_CDPMBSRA
ERDI Connectivity Alarm PM per STS-1 Bytestream A
0x87A3
RXT_TSERDI_CDPMBSRB
ERDI Connectivity Alarm PM per STS-1 Bytestream B
0x87A4
RXT_TSERDI_CDPMBSRC
ERDI Connectivity Alarm PM per STS-1 Bytestream C
0x87A5
RXT_TSERDI_CDPMBSRD
ERDI Connectivity Alarm PM per STS-1 Bytestream D
0x87A6
—
0x87B0
—
RXT_TSERDI_PDPMBSA[1—12]
RXT_TSERDI_PDPMBSB[1—12]
RXT_TSERDI_PDPMBSC[1—12]
RXT_TSERDI_PDPMBSD[1—12]
ERDI Connectivity Alarm PM
RXT_ERDI_CDPMBS[A—D]
RXT_TSERDI_CDPMBSA[1—12]
RXT_TSERDI_CDPMBSB[1—12]
RXT_TSERDI_CDPMBSC[1—12]
RXT_TSERDI_CDPMBSD[1—12]
Agere Systems Inc.
483
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x87B1
RXT_ERDI_SDPMBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
0x87B2
RXT_TSERDI_SDPMBSRA
ERDI Server Alarm PM per STS-1 Bytestream A
0x87B3
RXT_TSERDI_SDPMBSRB
ERDI Server Alarm PM per STS-1 Bytestream B
0x87B4
RXT_TSERDI_SDPMBSRC
ERDI Server Alarm PM per STS-1 Bytestream C
0x87B5
RXT_TSERDI_SDPMBSRD
ERDI Server Alarm PM per STS-1 Bytestream D
0x87B6
—
0x87C0
—
0x87C1
RXT_UNEQR_PMBSR
0x87C2
RXT_TSUNEQR_PMBSRA
Unequipped Received Alarm PM per STS-1 Bytestream A
0x87C3
RXT_TSUNEQR_PMBSRB
Unequipped Received Alarm PM per STS-1 Bytestream B
0x87C4
RXT_TSUNEQR_PMBSRC
Unequipped Received Alarm PM per STS-1 Bytestream C
0x87C5
RXT_TSUNEQR_PMBSRD
Unequipped Received Alarm PM per STS-1 Bytestream D
0x87C6
—
0x87D0
—
0x87D1
RXT_AIS_PMBSR
0x87D2
RXT_TSAIS_PMBSRA
Alarm Indicator Signal Alarm PM per STS-1 Bytestream A
0x87D3
RXT_TSAIS_PMBSRB
Alarm Indicator Signal Alarm PM per STS-1 Bytestream B
0x87D4
RXT_TSAIS_PMBSRC
Alarm Indicator Signal Alarm PM per STS-1 Bytestream C
0x87D5
RXT_TSAIS_PMBSRD
Alarm Indicator Signal Alarm PM per STS-1 Bytestream D
0x87D6
—
0x87E0
—
Bit 3
Bit 2
Bit 1
Bit 0
ERDI Server Alarm PM
RXT_ERDI_SDPMBS[A—D]
RXT_TSERDI_SDPMBSA[1—12]
RXT_TSERDI_SDPMBSB[1—12]
RXT_TSERDI_SDPMBSC[1—12]
RXT_TSERDI_SDPMBSD[1—12]
Unequipped Received Alarm PM
RXT_UNEQR_PMBS[A—D]
RXT_TSUNEQR_PMBSA[1—12]
RXT_TSUNEQR_PMBSB[1—12]
RXT_TSUNEQR_PMBSC[1—12]
RXT_TSUNEQR_PMBSD[1—12]
Alarm Indicator Signal Alarm PM
RXT_AIS_PMBS[A—D]
RXT_TSAIS_PMBSA[1—12]
RXT_TSAIS_PMBSB[1—12]
RXT_TSAIS_PMBSC[1—12]
RXT_TSAIS_PMBSD[1—12]
484
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
STS Receive Terminator (RXT) Block (continued)
RXT Register Map (continued)
Table 452. RXT Register Map (continued)
Note: Shading denotes reserved bits.
Addr
Symbol
0x87E1
RXT_LOP_PMBSR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
0x87E2
RXT_TSLOP_PMBSRA
Loss of Pointer Alarm PM per STS-1 Bytestream A
0x87E3
RXT_TSLOP_PMBSRB
Loss of Pointer Alarm PM per STS-1 Bytestream B
0x87E4
RXT_TSLOP_PMBSRC
Loss of Pointer Alarm PM per STS-1 Bytestream C
0x87E5
RXT_TSLOP_PMBSRD
Loss of Pointer Alarm PM per STS-1 Bytestream D
0x87E6
—
0x87FF
—
0x8800
—
0x882F
RXT_LSECCVP_CPMR[1—48]
0x8830
—
0x887F
—
0x8880
—
0x88AF
RXT_LSECREIP_
CPMR[1—48]
0x88B0
—
0x88FF
—
0x8900
—
0x892F
RXT_TSRDIPR[1—48]
0x8930
—
0x8947
RXT_TSC2R[1—24]
0x8948
—
0x895F
—
0x8960
—
0x8977
RXT_TSPDIR[1—24]
0x8968
—
0x8FFF
—
Bit 3
Bit 2
Bit 1
Bit 0
Loss of Pointer Alarm PM
RXT_LOP_PMBS[A—D]
RXT_TSLOP_PMBSA[1—12]
RXT_TSLOP_PMBSB[1—12]
RXT_TSLOP_PMBSC[1—12]
RXT_TSLOP_PMBSD[1—12]
Time Slots 1, 2, 3, 4, . . . , 48 CV Count PM
RXT_LSECCVP_CPM[1—48][15:0]
Time Slots 1, 2, 3, 4, . . . , 48 REI Count PM
RXT_LSECREIP_CPM[1—48][15:0]
RDI, C2 Status
Time Slot 1—Time Slot 48 Received
RDI Code
RXT_TS_RRDI[1—48][2:0]
Time Slots 1, 3, 5, 7, . . . , 47 Received C2 Byte
RXT_TSRC2[1, 3, 5, . . . , 47][7:0]
Time Slots 2, 4, 6, 8, . . . , 48 Received C2 byte
RXT_TSRC2[2, 4, 6, . . . , 48][7:0]
PDI Status
Agere Systems Inc.
Time Slots 1, 3, 5, 7, . . . , 47 Received PDI Byte
RXT_TSRPDI[1, 3, 5, . . . , 47][7:0]
Time Slots 2, 4, 6, 8, . . . , 48 Received PDI Byte
RXT_TSRPDI[2, 4, 6, . . . , 48][7:0]
485
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block
DS3 Functional Description
DS3 Block Interface Diagram
The DS3 block consists of three major subblocks: DS3 Rx, DS3 Tx, and microprocessor interface. The DS3 block
interfaces with the pointer interpreter and SPE blocks on one side and the receive sequencer/data engine blocks
on the other side as shown in Figure 55.
DS3 BLOCK
POINTER
INTERPRETER
(PTR)
RECEIVE
SEQUENCER
(RXS)
DS3 RX
FEEDBACK
FEEDBACK
DS3 TX
SPE MAPPER
(SPE)
MICRO I/F
DATA ENGINE
(DE)
5-8326(F)r.5
Figure 55. DS3 Block Interface Diagram
DS3 Receive Subblock
The DS3 Rx block is responsible for extracting the i bits from an STS-1 frame, performing DS3 framing, and
extracting the d bits from the DS3 frame, and finally, extracting data (packets or ATM cells) from the d bits. The
ATM cells could be either direct mapped, or PLCP mapped, and packets are direct mapped.
Data arrives at the DS3 in the Rx direction grouped as four slices of 8 bits. The four slices are labeled A, B, C, and
D as shown in Figure 56. DS3 is only supported in slices A and B. The DS3 block is designed to accommodate up
to 24 channels, among the two slices. Thus, each slice could have up to 12 channels, and data for any given channel will always arrive at the same slice (that is, data for any one channel arriving on slice A, will never arrive on B,
C, or D).
Not all 16 channels need to be DS3 mapped. Any channels not DS3 mapped will be passed through the block
untouched. Additionally, the delay through each slice will be the same, if the data is not DS3 mapped, so that data
that is not DS3 mapped, belonging to a single channel, can be presented across the four slices at the same time, to
the next block, and the data will be transmitted out of the DS3 block aligned in time.
486
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Functional Description (continued)
24 DS3/PLCP—12 PER SLICE A AND B
A
B
DS3 I BITS EXTR.
DS3 I BITS EXTR.
DS3 FRM
DS3 FRM
FROM PT
SPE
MAPPER
(SPE
DS3)
PLCP FRM
PRBS MON
PLCP FRM
PRBS MON
A
B
TO RXS
C
SLICE C—DS3 NOT SUPPORTED
C
D
SLICE D—DS3 NOT SUPPORTED
D
DS3 INs
PLCP INs
FIFO
FROM DE
PRBS INSERT
PT BLOCK
16 LOGICAL CHANNELS
DS3 BLOCK
5-8715(F)r.1
Figure 56. DS3 Receive Subblock
The data entering the DS3 block passes through a mode look-up block, which is responsible for determining, from
the time slot, if the data for that channel is DS3 encoded. If data is DS3 encoded, then the mode look-up block is
responsible for indicating if DS3 data is PLCP encoded or clear channel as indicated by the following register bits
DS3_RDS3PLCP_[A—B][12—1][1:0] (Table 560, Table 561, Table 563, and Table 564): 00 = no mapping, 01 =
illegal (no mapping), 10 = DS3 clear channel, 11 = DS3/PLCP mapped signal.
The data is then passed through the DS3 I bits extract block, which is responsible for extracting the i bits from an
STS-1 frame. The format of DS3 i-bit mapping into an STS-1 frame is shown in Table 678. Data for any channels
not carrying DS3 traffic is sent through this block unmodified. In this block, path-level overhead bytes are ignored.
The r(reserved) and o(overhead communications channel) bits are ignored. The s bit is treated as a stuff bit
according to the majority vote of the c bits, as per GR253 R3-70 and GR253 R3-71 requirements. The DS3 I bits
extract block receives a J1 marker along with the data. All internal counters are resynchronized to the J1 marker,
on a per time-slot basis.
After the i bits are extracted, they are passed to the DS3 framer 8 bits at a time. This implies that data must be
packed in this and all blocks before being sent out for further processing. All reserved and fixed stuff bytes are
marked as invalid data, register bits DS3_RDS3PLCP_[A—B][12—1][1:0]. Setting a time slot into the no mapping
mode (00 or 01) resets all internal states for that time slot.
Once the i bits are extracted from an STS-1 frame, they are passed to the DS3 framer block, which is responsible
for performing framing onto the DS3 subframe alignment and multiframe alignment signals if the signal contains a
DS3 frame. The format of a DS3 multiframe is shown in Figure 61.
Agere Systems Inc.
487
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Functional Description (continued)
DS3 Framing Algorithm
Framing is done in two stages by first finding a bit position that matches the frame alignment pattern (F bits 1001),
and then locating the multiframe alignment signal (M bits 010). In F frame is declared once no errors are detected
in the F-bit sequence for 16 consecutive bits. After a matching F-bit sequence is found, in frame is declared
(DS3_OOF_[A—B][12—1] = 0 (Table 532 and Table 546)) when correct M bits are received for three M frames
(T1.231). The maximum average reframe time is 0.5 ms in the presence of a bit error rate of 10–3.
Once in frame, the received frame bits are monitored for out-of-frame. Out-of-frame is declared (DS3_OOF_[A—
B][12—1] = 1) if too many errors are received in either the F bits (three errors in 16 bits if DS3_OOF_FMODE_[A—
B] = 0 (Table 560 and Table 563), or at least one F-bit error in each of four consecutive M subframes if
DS3_OOF_FMODE_[A—B] = 1) or the M bits (at least one error in each of three consecutive M frames). For testing purposes, the user may also force the framer out-of-frame by setting the mapping bits.
The traditional algorithm for declaring out-of-frame (three errors in 16 F bits) results in false out-of-frame approximately every 30 seconds when the received bit error rate is 10–3. By waiting for four consecutive M subframes with
F-bit errors before declaring out-of-frame, the framer normally stays in frame for over an hour when the bit error
rate is 10–3.
After subframe and multiframe have been acquired, the DS3 channel is declared framed, and an alarm is raised.
DS3 Loss-of-Frame
The DS3_LOF_[A—B][12—1] bit (Table 533 and Table 547) is set if the associated DS3_OOF_[A—B][12—1] outof-frame bit is high continuously for 28 ± 1 frame periods (approximately 3 ms). Once set, the LOF state bit is not
cleared until the OOF state bit is continuously low for 28 ± 1 frame periods.
Register bits: DS3_LOF_[A—B][12—1], DS3_LOFD_[A—B][12—1] (Table 481 and Table 493), and
DS3_LOFM_[A—B][12—1] (Table 507 and Table 519).
Severely Errored Frame (SEF)
The received DS3 frames are checked for severely errored frames (SEF). A SEF defect is the occurrence of three
or more F-bit errors in 16 consecutive F bits and reported through register bits DS3_SEF_[A—B][12—1] (Table 534
and Table 548). A SEF defect is terminated when the signal is in-frame and there are less than three F-bit errors in
16 consecutive F bits. This error may cause the DS3 framer to transition to the out-of-frame state.
Register bits: DS3_SEF_[A—B][12—1], DS3_SEFD_[A—B][1—12] (Table 482 and Table 494), and
DS3_SEFM_[A—B][12—1] (Table 508 and Table 520).
AIS Detection/Removal
In each M-frame, the 4704 information bits are checked for the presence of the AIS (1010) pattern starting after
each overhead bit. In order to detect this pattern in the presence of a high error rate, AIS (DS3_AISPAT_DET_[A—
B][12—1] (Table 535 and Table 549)) pattern detection is declared if fewer than five pattern errors are received in
each of two consecutive frames. Once AIS is declared, it is not cleared until at least 16 pattern errors are received
in each of two consecutive M-frames (T1.231). In addition to detection of the pattern, the DS3 signal must be inframe and P-bit errors are binned during AIS detection.
Register bits: DS3_AISPAT_DET_[A—B][12—1], DS3_AISPAT_DETD_[A—B][12—1] (Table 483 and Table 495),
and DS3_AISPAT_DETM[A—B][12—1] (Table 509 and Table 521).
488
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Functional Description (continued)
Idle Detection/Removal
In each M-frame, the 4704 information bits are checked for the presence of the idle (1100) pattern starting after
each overhead bit. In order to detect this pattern in the presence of a high error rate, idle
(DS3_IDLEPAT_DET_[A—B][12—1] (Table 536 and Table 550)) pattern detection is declared if fewer than five
pattern errors are received in each of two consecutive frames. Once Idle is declared, it is not cleared until at least
16 pattern errors are received in each of two consecutive M-frames (T1.231). In addition to detection of the pattern,
the DS3 signal must be in-frame and P-bit errors are binned during Idle detection.
Register bits: DS3_IDLEPAT_DET_[A—B][12—1], DS3_IDLEPAT_DETD[A—B][12—1] (Table 484 and
Table 496), DS3_IDLEPAT_DETM_[A—B][12—1] (Table 510 and Table 522).
C-Bit Detection and X-Bit Detection
In addition to the fixed information bit patterns, AIS and Idle signals are transmitted with all C bits set to 0 and both
X-bits set to 1. These conditions are monitored and reported in DS3_CBZ_DET_[A—B][12—1] (Table 537 and
Table 551) and DS3_RAI_DET_[A—B][12—1] (Table 538 and Table 552) bits.
If every C bit in three consecutive DS3 frame is 0, set DS3_CBZ_DET_[A—B][12—1] = 1. If the three C bits in a
single M subframe are 1, clear the associated DS3_CBZ_DET_[A—B][12—1] bit.
If both X bits (RAI or yellow signal) in two consecutive M frames are received as 0 (error-free), the device sets
DS3_RAI_DET_[A—B][12—1] = 1. Once this bit is set, it is not cleared until both X bits in two consecutive Mframes are received as 1.
The user may wish to declare AIS or idle based on a combination of some of the DS3_CBZ_DET, DS3_RAI_DET,
and DS3_AISPAT_DET or DS3_IDLEPAT_DET bits.
Register bits: DS3_CBZ_DET_[A—B][12—1], DS3_CBZ_DETD_[A—B][12—1] (Table 485 and Table 497),
DS3_CBZ_DETM_[A—B][12—1] (Table 511 and Table 523), DS3_RAI_DET_[A—B][12—1],
DS3_RAI_DETD_[A—B][12—1] (Table 486 and Table 498), DS3_RAI_DETM_[A—B][12—1]
(Table 512 and Table 524).
Near-End Path Failure Event and Count
Near-end path failure event and count are detected via a host microprocessor.
Agere Systems Inc.
489
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Functional Description (continued)
DS3 OH Bits Processor
All overhead bits defined in a 44.736 kbit/s multiframe structure are defined in the table below. Bold bits are processed by the OH processor block, while all other bits are ignored.
Table 453. Overhead Bits Defined in a 44.736 Mbits/s Multiframe Structure
Note: F1, F2, F3, F4 = 1001, M1, M2, M3 = 010, X1 = X2, P1 = P2, C31 = C32 = C33.
The 56 overhead bits sequential positions as follows:
X1
F1
C11
F2
C12
F3
C13
F4
X2
F1
C21
F2
C22
F3
C23
F4
P1
F1
C31
F2
C32
F3
C33
F4
P2
F1
C41
F2
C42
F3
C43
F4
M1
F1
C51
F2
C52
F3
C53
F4
M2
F1
C61
F2
C62
F3
C63
F4
M3
F1
C71
F2
C72
F3
C73
F4
X-Bit Detection
The X bits are used to indicate received errored multiframes to the remote-end (remote-alarm indication RAI or yellow signal); these bits are set to binary 1 (i.e., X1 = X2 =1) during error-free conditions, and to binary 0 (i.e., X1 =
X2 = 0) if OOF or AIS are detected in the incoming signal. See C-Bit Detection and X-Bit Detection section on page
489 for monitoring information.
490
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Functional Description (continued)
P Bits (P1, P2)
For each channel that is DS3 mapped, parity is calculated over the 4704 data bits (84 info bits * 8 blocks/subframe
* 7 subframes/multiframe) following the X1 bit.
Parity errors are accumulated in a read-only saturating counter. The coding violation parameter count (CVP-P)
counter increments if at least one of the P bits disagree with the parity of the previous frame. This counter is
cleared on a 0-to-1 transition of the PMRST (pin D7, Table 10, Pin Descriptions—Microprocessor Interface Signals
on page 117) input signal.
Register bits: DS3_PERR_CNT_[A—B][1—12][13:0] (Table 567 and Table 573).
C31, C32, and C33 CP Bits
CP bits are used to carry path (end-to-end facility) parity information. The network terminating equipment (NTE)
that originates the DS3 signal must set these bits (C31 = C32 = C33) to the same value as the P bits.
The CP-bit coding violation parameter count (CVCP-P) counts frames with at least two of the three C-bit parity bits
indicating an error.
Register bit: DS3_CPERR_CNT_[A—B][1—12][13:0] (Table 568 and Table 574).
C41, C42, and C4 FEBE Bits
FEBE bits are used to carry far-end block error information. All three FEBE bits are set to 1 (C41 = C42 = C43 = 1)
if no errors are detected in the M bits, or F bits, or indicated by the CP bits. If any error condition is detected within
the M frame, the FEBE bits must be set to any combination of 1s or 0s (except 111).
The CVCP-PFE counter accumulates FEBE error indications (one error indication for each M-frame with at least
one FEBE bit equal to zero).
Register bit: DS3_FEBE_CNT_[A—B][1—12][13:0] (Table 569 and Table 575).
C13 FEAC (Far-End Alarm and Control)
FEAC is used to receive alarm and status information from the far-end terminal and to initiate or terminate line
loopbacks (not supported) at the request of the far-end terminal. The FEAC signal consists of a 16-bit code word of
format 0iiiiii011111111 with the right-most bit transmitted first (1); i = information bit. When no code words are transmitted, the FEAC channel is set to all 1s. After validation (four consecutive times), the code word is stored in register (DS3_RFEAC_CODE_[A—B][12—1][5:0] (Table 544 and Table 558)). If the validated codeword equals one of
the codewords listed in Table 454, the RAI state bit is set. Otherwise, the RAI state bit is zero
(DS3_RFEAC_RAI_[A—B][12—1] (Table 539 and Table 553), DS3_RFEAC_RAID_[A—B][12—1] (Table 487 and
Table 499), DS3_RFEAC_RAIM_[A—B][12—1] (Table 513 and Table 525)). If the validated code word is not listed
in Table 454, the DS3_RFEAC_CTL_[A—B][12—1] (Table 540 and Table 554) state bit is set; otherwise, this state
bit is 0 (DS3_RFEAC_CTLD_[A—B][12—1] (Table 488 and Table 500), DS3_RFEAC_CTLM_[A—B][12—1]
(Table 514 and Table 526)).
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Data Sheet
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DS3/E3 Block (continued)
DS3 Functional Description (continued)
Table 454. RAI Code Words
Value
(LSB) 011001 (MSB)
Description
DS3 Equipment Failure Service Affecting
001110
DS3 Loss of Signal
000000
DS3 Out of Frame
010110
DS3 AIS Received
C5X Processing
The C51, C52, and C53 bits are used for a 28.2 kbits/s terminal-to-terminal path maintenance data link. The implementation of this data link is optional and therefore is not monitored in this block.
All Other C-Bit Processing
C11, C12, C2X, C6X, and C7X should be set to all 1s. These bits are ignored.
PRBS Detector
The test-pattern detector contains a self-synchronizing detector using the identical QRSS sequence as found in the
test-pattern generator (220 – 1 and 215 – 1). When the detector is out of sync, the device continually monitors the
input data signal for matches to the expected data signal. When the device detects 32 matches in a row, it declares
itself in sync and the error detector is enabled. If the device detects eight consecutive mismatches, the test-pattern
detector declares itself out of sync and starts searching again.
When in sync, the device counts the number of times the input data differs from the expected data in an 8-bit
counter that holds its count when it reaches the maximum value of 255. This counter is reset when read by the
microprocessor and is not affected by the PMRST (pin D7) input signal.
This function is enabled on two time slots at a time, and the data must be DS3 or PLCP frame encoded. Two PRBS
detectors are implemented per slice. Setting the DS3_RPRBS_TSSEL_[A—B][2—1][3:0] (Table 562 and
Table 565) value to 0xF will disable the PRBS algorithm and reset all counters and state machine values to their
reset default states.
Register bits: DS3_RPRBS_TSSEL_[A—B][2—1][3:0],
DS3_RPRBS_INV_[A—B][1:0] (Table 561 and Table 564),
DS3_RPRBS_SYNC_ERR_[A—B][1:0] (Table 543 and Table 557),
DS3_RPRBS_SYNC_ERRD_[A—B][1:0] (Table 491 and Table 503),
DS3_RPRBS_SYNC_ERRM_[A—B][1:0] (Table 517 and Table 529),
DS3_RPRBS_DS3_PLCP_[A—B][1:0] (Table 562 and Table 565),
DS3_RPRBS_15or20_[A—B][1:0] (Table 562 and Table 565),
DS3_RPRBS_ERRCNT_[A—B][1—2][7:0] (Table 545 and Table 559).
492
Agere Systems Inc.
Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Functional Description (continued)
DS3 PLCP (Physical Layer Convergence Protocol) Framer
Once the data is extracted by the DS3 framer, if that data is PLCP mapped, PLCP framing must be performed.
Otherwise, the data is sent through this block unmodified. If the data is PLCP encoded, framing is performed by
checking for the A1A2 pattern.
Framing: In-frame is declared after two consecutive A1A2 and two consecutive path overhead indicator (POI) patterns are detected in a row. Out of frame is declared after five consecutive A1A2 mismatches or five consecutive
POI values are received in error.
An alarm is issued on a per time-slot basis each time the framer changes state. Until the in-frame state is declared,
all data is marked as invalid leaving this block for the associated time slot.
Register bits: DS3_PLCP_OOF_[A—B][12—1] (Table 541 and Table 555), DS3_PLCP_OOFD_[A—B][12—1]
(Table 489 and Table 501), DS3_PLCP_OOFM_[A—B][1—12] (Table 515 and Table 527).
B1 Monitoring
The BIP-8 is computed over the 12 x 54 octet structure consisting of the POH fields and the associated ATM cells
of the previous PLCP frame and compared to the received BIP-8 value, and the errors are accumulated in a 16-bit
saturating counter. This counter is cleared by the PMRST signal, and the error value per frame is sent to the transmit direction for insertion into the G1[7:4] bits.
Register bits: DS3_PLCP_B1ERRCNT_[A—B][1—12][15:0] (Table 570 and Table 576).
G1 Monitoring
The G1[7:4] FEBE error value is binned in a 16-bit saturating counter that is cleared by the PMRST signal. Valid
values are 0 to 8. Any value outside this range is considered 0 errors (DS3_PLCP_G1_FEBE_ERRCNT_[A—
B][1—12][15:0] (Table 571 and Table 577)).
The G1[3] RAI value is monitored for a change in state. Each time a validated change of state is detected
(DS3_PLCP_CNTD_G1_RAI_[A—B][3:0] (Table 562 and Table 565)), a delta bit is set (DS3_PLCP_G1_RAI_[A—
B][12—1] (Table 542 and Table 556), DS3_PLCP_G1_RAID_[A—B][12—1] (Table 490 and Table 502), and
DS3_PLCP_G1_RAIM_[A—B][12—1] (Table 516 and Table 528)).
All other bits are ignored.
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155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Transmit Direction
The DS3 transmit block consists of three functional blocks. They are the FIFO block used to buffer packets from
the data engine, the PLCP frame insert block used to pack ATM cells into a PLCP frame and insert the byte overhead associated with this format, and the DS3 frame insert block that inserts the valid data from the FIFO block in
to a DS3 frame. The PLCP and DS3 frame insert blocks can be bypassed for pass-through traffic (virtual concatenation, etc.). Channel ID to slice/time-slot number mapping is provided for bidirectional alarm insertion in the DS3
(X1, X2) and PLCP (G1) frames.
Register bits: DS3_TDS3PLCP[1—16][1:0] (Table 578); 00 = no mapping, 01 = DS3 locked mode, 10 = DS3 clear
channel, 11 = DS3/PLCP mapped signal, DS3_TXCHID_TO_TSMAPPING[1—16][1:0][3:0]
(Table 578) = channel ID to slice/time-slot mapping [A—B][0—11]; A = 3, B = 2; illegal values default
to all selected signals are inactive (0).
The DS3 locked mode allows the insertion of DS3 overhead bytes into a received packed of length (84 * 7 bytes).
The DS3 frame insert mechanism will synchronize to the EOP marker. Each time the EOP marker changes position, an event indication is set (DS3_TXEOPERRE[16—1] (Table 505), DS3_TXEOPERRM[16—1] (Table 531)).
The EOP marker indicates when the next MSByte contains the start of the packet.
The DS3_TXEOPERRE[16—1] indicates when the EOP marker changes position in the PLCP mapping mode or
DS3 locked mode.
FIFO Block
The FIFO block accepts data from the data engine input 32 bits at a time. Each 32 bits is associated with a channel
ID, a data valid indicator and a data marker for the entire bus, and an EOP marker per byte to indicate the end of a
packet (ATM, HDLC, etc). All valid data (valid indicator and data marker = 1) is written into the associated FIFO
location (16 active channels x 32 locations x 36 bits = 18,432 bits (~ 36,864 gates) for the selected channel ID.
Data is not read out of the FIFO until data has accumulated above the lower threshold (DS3_TFIFO_MIN[5:0]
(Table 582)), and blank requests are sent if the FIFO reaches the upper threshold (DS3_TFIFO_MAX[5:0]
(Table 582)).
Writes to the FIFO always occur for valid data even if the FIFO will overflow. In this case, the FIFO is considered
empty and reads are disabled until the lower threshold is reached.
Reads from the FIFO are designed as a pull mechanism. The receiving block allows data for a particular channel
ID or sends a blank request for that channel ID to the DS3 framer block. A blank request guarantees no valid data
is sent to the PT block. The DS3 block requests or inhibits data from the PLCP block by asserting its data valid signal. This same mechanism exists between the PLCP framer and FIFO. The PLCP block can inhibit reads from the
FIFO if it does not need data. The FIFO will issue blank requests upstream once the high-buffer threshold is
exceeded. This is the only mechanism that will cause blank requests to be issued for a selected channel ID.
Register bits: DS3_TFIFO_MIN[5:0], DS3_TFIFO_MAX[5:0], DS3_TFIFO_OVR_UNFLE_[16—1] (Table 504), and
DS3_TFIFO_OVR_UNFLM_[16—1] (Table 530).
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 PLCP Frame/Data Insert
Frame Format Insert
This block is responsible for creating the PLCP frame if the associated channel is PLCP encoded; otherwise, the
data is sent through unchanged. The channel being processed is controlled incoming channel ID. The PLCP block
will request 32 bits from the FIFO when needed. The PLCP frame floats within the DS3 frame.
ATM cell header locations are determined by the location of the EOP marker. If an EOP marker abruptly changes
location, the remaining PLCP ATM location will be filled with 0s. This ensures the receive framer will stay in PLCP
frame.
Frame Alignment (A1, A2)
The A1 (0xF6) and A2 (0x28) framing bytes are the same as SONET and SDH A1 and A2 bytes, respectively. The
A2 byte can be inverted through (DS3_TPLCP_A2INV[1—16] (Table 578)).
Path Overhead Identifier (P00—P11)
The path overhead identifier (POI) indexes the adjacent path overhead (POH) octet of the PLCP. Table 455 provides the coding for each of the P00—P11 octets. The most significant bit can be inverted through
(DS3_TPLCP_POIB7INV[1—16] (Table 578)).
Table 455. POI Values
POI
POI Code
POH
P11
0010_1100
Z6
P10
0010_1001
Z5
P09
0010_0101
Z4
P08
0010_0000
Z3
P07
0001_1100
Z2
P06
0001_1001
Z1
P05
0001_0101
X
P04
0001_0000
B1
P03
0000_1101
G1
P02
0000_1000
X
P01
0000_0100
X
P00
0000_0001
C1
Growth Octets (Z1—Z6 and X Bytes)
The growth octets are reserved for future use. These octets are set to 0.
PLCP Path Error Monitoring (B1)
The BIP-8 field is calculated over a 12 x 54 octet structure consisting of the POH field and the associated ATM
cells (648 octets) of the previous PLCP frame. The B1 byte can be inverted on a per-channel basis by setting
(DS3_TPLCP_B1INV[1—16] (Table 578)).
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Data Sheet
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DS3/E3 Block (continued)
DS3 PLCP Frame/Data Insert (continued)
PLCP Path Status (G1)
The PLCP path status is allocated to convey the received PLCP status and performance to the transmitting farend. Table 456 illustrates the G1 octet subfields: a 4-bit far-end block error (FEBE), a 1-bit remote alarm indication
(RAI), and 3 X bits (X bits are set to all 1s).
The FEBE is the number of B1 errors detected in the previous received PLCP frame. Valid values are 0—8. The
outgoing FEBE value can be forced to a programmable value through (DS3_TPLCP_FEBE_SWENB[1—16]
(Table 578), DS3_TPLCP_FEBE_DINS[3:0] (Table 581)). The same data value is used for all channels while the
enable signals are per channel.
The RAI bit is set to a logic 1 when the associated PLCP framer is in the out-of-frame state. This value can be overwritten through DS3_TPLCP_RAI_SWENB[1—16] (Table 578) and DS3_TPLCP_RAI_DINS[1—16] (Table 578).
Table 456. G1 Byte Definition
Far-End Block Error (FEBE)
RAI
X-X-X
4 bits (MSB)
1 bit
3 bits (LSB), Set to 111
Cycle/Stuff Counter (C1)
The cycle/stuff counter provides a nibble stuffing opportunity cycle and length indicator for the PLCP frame. A stuffing opportunity occurs every third frame of a three-frame (375 µs) stuffing cycle. The value of the C1 code is used
as an indication of the phase of the 375 µs stuffing opportunity cycle.
Table 457 shows that a trailer containing 13 nibbles is used in the first frame of the 375 µs stuffing opportunity
cycle. A trailer of 14 nibbles is used in the second frame. The third frame provides a nibble stuffing opportunity. The
contents of each of the 13/14 trailer nibbles will be 1100.
Table 457. Trailer Length
C1 Code
Frame Phase of Cycle
Trailer Length
1111_1111 (0xFF)
1
13
0000_0000 (0x00)
2
14
0110_0110 (0x66)
3 (no stuff)
13
1001_1001 (0x99)
3 (stuff)
14
The algorithm for generating the stuff bytes is summarized in Table 458. Sequence number 1 is repeated 28 times,
and then sequence 2 is created. This sequence repeats after 255 PLCP frames.
Table 458. PLCP Nibble Stuff Sequence
Sequence Number
Sequence
Repeat Sequence N Times
1
13 - 14 - 14
28
13 - 14 - 13
13 - 14 - 14
2
496
13 - 14 - 13
1
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Frame Generate/OH Bit Inserter
F Bits and M Bits Insert
The DS3 frame generator is responsible for generating the M-frame as shown in Figure 61. It generates and
inserts the subframe framing bits F1, F2, F3, F4 = 1001, respectively, and the framing bits M1, M2, M3 = 010,
respectively. These bits can be corrupted by setting DS3_TDS3_FINV[1—16] (Table 579) to 1. This causes the F
bits to be set to 1000. To corrupt the M bits, set the DS3_TDS3_MINV[1—16] (Table 579) to 1. This causes the M
bits to be set to 011.
X Bits Insert
This block is responsible for setting the X bits. These bits are set to a binary 1 during an error-free condition or to a
binary 0 if DS3_LOF, DS3_OOF, DS3_AISPAT_DET are detected in the associated received signal. The X bits
must persist for 1 second after change of state. This means 0 to 1 or 1 to 0. The X-bit value is provisioned through
(DS3_TDS3_XDINS[1—16] (Table 579)).
P Bits (P1, P2)
This block is responsible for computing parity over the previous M-frame data bits (4704). If the digital sum is 1,
P1 = P2 = 1; otherwise, P1 = P2 = 0. If the DS3_TDS3_PINV[1—16] (Table 579) is set to a logic 1, the P bits are
inverted.
C Bits Insert
Allocation of C bits for C-bit parity applications is summarized in Table 459.
Table 459. C-Bit Insert
C Bit
C11, C12
C13
Description
Set to binary 1.
FEAC is a 16-bit code word of the form
0x5x4x3_x2x1x00_1111_1111 with the right-most bit
sent first.
Settings
—
When DS3_TDS3_TFEAC_INS[1—
16] (Table 579) bit is a 0 the C13-bit is
set to a logic 1. When the control bit is
set to a 1, the C13 bit is sent as a 16-bit
repeating code word.
DS3_TDS3_TFEAC_CODE[1—
16][5:0] (Table 579) is sent as shown
(bit 5 = x5). The 16-bit codeword must
be repeated at least 10 times, or while
the condition exists, whichever is
longer.
C21, C22, C23
Not used; set to binary 1.
C31, C32, C33
C31 = C32 = C33 = computed P-bit value.
Setting the DS3_TDS3_CPINV[1—16]
(Table 579) = 1 inverts all CP bits.
C41. C42, C43
C41 = C42 = C43 = 1 if no errors are detected in the
received M or F bits or indicated by the received CP
bits. If any errors are detected in the previous received
DS3 frame, the FEBE bits are set to 000.
An override bit
(DS3_TDS3_FEBEINS[1—16]
(Table 579) = 1, set the FEBE bits to
000.
C51, C52, C53
Nominal carries the LAPD message. This feature is
optional and is not supported (C51 = C52 = C53 = 1).
—
C61, C62, C63
Not used; must be set to binary 1.
—
C71, C72, C73
Not used, must be set to binary 1.
—
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Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Frame Generate/OH Bit Inserter (continued)
Data Bits
There are four types of data that can be inserted in to the d bits. They are idle. AIS, pseudorandom data, or data
engine data. This is programmable through DS3_TDS3_AIS[1—16] (Table 579), DS3_TDS3_IDLE[1—16]
(Table 579); 00 or 11 = data engine data, 01 = idle, 10 = AIS.
AIS Insert
When AIS is forced, the pattern 1010 . . . is sent in the data bits with a 1 starting after each overhead bit. Additionally, the X1 = X2 = 1 and all C bits are set to 0.
Idle Insert
When idle is forced, the pattern 1100 . . . is sent in the data bits with a 1 starting after each overhead bit. Additionally, the X1 = X2 = 1 and C bits are generated normally.
PRBS Sequence
When a pseudorandom sequence is inserted, a (215 – 1) or ((220 – 1) (x20 + x17 + 1 = 0 with a 14 zero limit)
sequence is inserted into the data bits with the pattern starting after each overhead bit. Additionally, all overhead
bits function normally. This pattern can be inserted in to the PLCP ATM cell payload bytes or the DS3 i bits.
Register bits: DS3_TPRBS_CHID_INS[1—2][5:0], DS3_TPRBS15or20[1—2], DS3_TPRBS_DS3orPLCP[1—2],
DS3_TPRBS_INV[1—2], DS3_TPRBS_1BERRINS[1—2] all (Table 580).
Transparent Payload Mode (Used in Conjunction with DS3 Mapping)
Transparent payload mode is used in conjunction with DS3 mapping. In this mode, full frames of DS3 payload
bytes are treated as fixed-length packets. The packets are 588 bytes long; each M subframe contains 84 data
bytes (eight blocks of 84D bits), and there are seven M subframes in a DS3 multiframe, giving 7 x 84 = 588 data
payload bytes per DS3 multiframe. The DS3 frame structure is shown for reference in Figure 61.
The fixed-length packet format allows a user to map data into consistent locations in a DS3 frame so that they can
implement any desired sub-DS3-rate mapping (standard or nonstandard). To use this mode, configure the DS3
block to be active, and configure the DE in transparent payload mode.
Configure the corresponding UT channel/interface for packets and ensure that there is enough bandwidth to avoid
starvation. Other blocks are configured as usual. It is then possible to post/preprocess data from this fixed
588-byte format to any other format that may be needed.
Payload data is mapped between the 588-byte packet format and the DS3 payload format in time order of transmission. The MSB of the first byte of the 588-byte packet is mapped to the first DS3 payload data bit. The first ten
and a half bytes of the 588-byte packet format go into the first 84D block of the DS3 multiframe. This mapping continues from left to right, top to bottom through the entire DS3 frame.
It is also possible to use this mode for monitoring the contents of an SPE (i.e., to observe the number of 7E bytes
between packets or to verify the operation of the HDLC byte escaper), but in this case, there is no indication of the
beginning of the SPE (i.e., first byte following J1).
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Functional Description
The DS3/E3 block is an enhancement of the DS3 block of the (TADM042G5 (TADMV1B)) device. The E3 subblock
was implemented in MARS2G5 P-Pro for E3 mapping into the VC-3, AU-3, and AUG path as shown in Figure 57.
The E3 (34.368 Mbits/s) signal is mapped into a VC-3 and then to an AU-3 as shown in Figure 58. The final step is
multiplexing the AU-3 map into an AUG.
SONET DS3 MAPPING
STS-1
SPE
DS3
SDH DS3/E3 MAPPING
xN
x1
AUG
AU-4
VC-4
x3
x1
TUG-3
TU-3
VC-3
x3
AU-3
C-3
VC-3
DS3(44.736)
OR
E3 (34.368)
THIS PATH IS EQUIVALENT TO SONET STS-1 ↔ DS3 SPE MAPPING
2318(F)
Note: Shaded mappings are supported. AU-3 and STS-1 are equivalent.
Figure 57. DS3/E3 Mappings
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Data Sheet
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DS3/E3 Block (continued)
E3 Functional Description (continued)
1
J1
B3
C2
G1
F2
H4
F3
K3
N1
29 30 31
C-3
58 59 60
C-3
87
VC-3 PLUS
2 COLUMNS OF
FIXED STUFF
C-3
(84 DATA COLUMNS)
FLOATING
PHASE
VC-3 POH
H1 H2 H3
AU-3
2319(F)
Figure 58. VC-3 Into an AU-3
A 34.368 Mbits/s signal can be mapped into a VC-3 as shown in Figure 59. In addition to the VC-3 POH, the VC-3
consists of a payload of 9 x 84 bytes every 125 µs. This payload is divided in three subframes, each subframe consisting of:
1431 data bits (D);
two sets of five justification control bits (C1, C2);
two justification opportunity bits (S1, S2);
573 fixed stuff bits (R);
Two sets of five justification control bits C1 and C2 are used to control the two justification opportunity bits S1 and
S2, respectively.
C1C2C3C4C5 = 00000 indicates that the S1 is a data bit while C1C2C3C4C5 = 11111 indicates that S1 is a justification bit. C2 bits control S2 in the same way. Majority vote should be used to make the justification decision in the
desynchronizer for protection against single and double bit errors in the C bits.
The value contained in S1 and S2, when they are justification bits, is not defined. To maintain the E3 rate in the
transmit direction, the S1 bit should be a fixed stuff bit while the S2 bit is a data bit.
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Functional Description (continued)
J1
B3
C2
G1
F2
H4
F3
K3
N1
T1
T2
T3
1
84 bytes
VC-3 POH
3
3
3
3
3
3
3
3
3
C 3
3
3
3
3
3
3
3
3
3
C 3
3
3
3
3
3
3
3
3
3
C 3
3
3
3
3
3
3
3
3
3
C 3
3
3
3
3
3
3
3
3
3
C3
3
3
3
3
3
3
3
3
3
A B 1
= RRRRRRRR (FIXED STUFF)
C = RRRRRRC1C2
A = RRRRRRRS1
3 = THREE DATA bytes (DDDDDDDD)
B = S2DDDDDDD
1 = ONE DATA byte (DDDDDDDD)
2320(F)
Figure 59. Asynchronous Mapping of 34,368 kbits/s Tributary Into VC-3
E3 Frame Format Requirements from ITU-T G.832 (10/98)
The basic G.832 E3 frame structure at 34,368 kbits/s comprises 7 octets of overhead and 530 octets of payload
capacity per 125 µs as shown in Table 463.
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Data Sheet
August 18, 2004
DS3/E3 Block (continued)
E3 Functional Description (continued)
59 COLUMNS
FA1 FA2
EM
TR
MA
9
ROWS
530 OCTET PAYLOAD
NR
GC
2321(F)
Figure 60. G.832 E3 Frame Structure at 34,368 kbits/s
E3 Overhead Octets
The values and allocation of the overhead octets are shown in Table 460 and described below.
Table 460. Overhead Allocation at 34,368 kbits/s
FA1
1
1
1
1
0
1
1
EM
BIP-8
TR
Trail Trace—16-Byte Sequence
MA
RDI REI
Payload Type
MFI
NR
Network Operator Byte
GC
GP Communication Channel
502
0
0
0
1
0
1
0
0
0
FA2
SSM
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Functional Description (continued)
Frame Synchronization Bytes (Frame Alignment: FA1/FA2)
Frame alignment signal values 0xF6/0x28 (11110110 00101000). This pattern is inserted at the transmitter at the
beginning of each 125 µs frame interval. The receiver identifies the pattern to establish frame alignment so that all
other bytes can be properly located and interpreted.
Performance Byte (Error Monitoring: EM)
One byte is allocated for error monitoring. This function will be a BIP-8 code using even parity. The BIP-8 is calculated over all bits, including the overhead bits, of the previous 125 µs frame. The receiver compares this received
parity value with the parity computed by receiver. The result of this comparison indicates the error performance of
the connection between the transmitter and the receiver.
Trail Trace Byte (TR)
This byte is used to repetitively transmit a trail access point identifier so that a trail receiving terminal can verify its
continued connection to the intended transmitter.
A 16-byte frame is defined for the transmission of the access point identifier. The most significant bit (MSB) of the
message is a logic 1 value while all other MSBs are 0.
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Data Sheet
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DS3/E3 Block (continued)
E3 Functional Description (continued)
MA—Maintenance and Adaptation Byte
Each bit in the MA byte is defined in the table below.
Table 461. MA Byte Description
Bit 7
RDI
Set when the associated receive E3 signal is in an alarm
state. This bit is controlled under software control only.
Bit 6
REI
This bit is set to 1 if one or more errors were detected by
the BIP-8, otherwise set to 0.
Bits[5:3]
Payload Type
Bits[2:0]
Multiframe
Indicator/
SSM*
Code
Signal
000
Unequipped
001
Equipped, Nonspecific
010
ATM
011
SDH TU-12s
Others
Undefined
Bit 2
Bit 1
Bit 0
0
0
SSM Bit 3 (MSB)
0
1
SSM Bit 2
1
0
SSM Bit 1
1
1
SSM Bit 0 (LSB)
* Bit 0 is used in a four-frame multiframe. The phase of the multiframe is determined by the value of MA bits 2 and 1. The 4 bits of the multiframe are allocated to the synchronization status message (SSM).
When interworking with old equipment that used bit 0 as a timing marker (nonmultiframe), the new equipment
implementing the above requirement should be capable of being configured to transmit the old requirement as
given below.
Bit 0, timing marker. This bit is set to 0 to indicate that the timing source is traceable to a primary reference clock,
and is otherwise set to 1.
NR—Network Operator Byte
This byte is allocated for maintenance purposes specific to individual network operators. Its transparency from trail
termination to trail termination is not guaranteed. For tandem connection maintenance, the byte is used in accordance with Annex D/G.707. Tandem connection maintenance is not supported by this block. This byte is not
supported.
GC
General purpose communication channel (e.g., to provide data/voice channel connection for maintenance purposes). This byte is not supported.
504
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Functional Description (continued)
Mapping of ATM Cells into 34,368 kbits/s—ITU-T G.804 (02/98)
The ATM cells are mapped into the 530 payload octets of the 34,368 kbit/s frame with the octet structure of the cell
aligned with the octet structure of the frame. The ATM cell payload (48 bytes) shall be scrambled before mapping
into the 34,368 kbit/s signal.
E3-PLCP Frame Format
The E3-PLCP format consists of 57 bytes x 9 rows with a programmable trailer of 17 to 21 octets in length. The
G.751 E3 framing bytes are defined to be (1111010000 A N 1100) as shown in the G.751 E3 frame in Table 462.
The overhead bits are defined as an alarm indication bit (A or RAI) and a national use bit (N). The least significant
nibble is set to a fixed pattern of 1100.
Table 462. G.751 E3 Frame Format
1
1
1
1
0
1
0
0
0
0
RAI NA
1
1
C11 C21 C31 C41
380 Payload Bits
C12 C22 C32 C42
380 Payload Bits
C13 C23 C33 C43
J1
J2
J3
J4
0
0
368 Payload Bits
376 Payload Bits
Note: Framing occurs on 10-bit pattern 1111010000. When ATM cells are either directly mapped or with a PLCP frame, all C and J bits are
used as data bits.
Table 463. E3-PLCP Mapping of ATM Cells
Framing (3 octets)
POH
53 octets
A1
A2
P8
Z3
ATM Cell
A1
A2
P7
Z2
ATM Cell
A1
A2
P6
Z1
ATM Cell
A1
A2
P5
F1
ATM Cell
A1
A2
P4
B1
ATM Cell
A1
A2
P3
G1
ATM Cell
A1
A2
P2
M2
ATM Cell
A1
A2
P1
M1
ATM Cell
A1
A2
P0
C1
ATM Cell
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Trailer (17—21)
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Data Sheet
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DS3/E3 Block (continued)
E3 Functional Description (continued)
E3-PLCP Field Definitions
The PLCP frame has framing, path overhead (POH), data, and trailer bytes.
Framing Octets (A1, A2). The first two columns (A1, A2) are used for frame delineation (A1 = 0xF6, A2 = 0x28).
Path Overhead Identifier (P0—P8). The third column identifies the PLCP overhead octets contained in the fourth
column of Table 463. The left most 6 bits of these octets provide numbering of the 9 rows. The 7th bit is reserved,
and the right-most bit (LSB) is parity bit. The reserved bit is set to 0. The parity bit provides odd parity over this
field. A code is considered invalid if it does not match a value in Table 464 or its parity bit is invalid and will not be
used to transition the in-PLCP-frame state.
Table 464. Path Overhead Identifier Codes (POI)
POI
Row Count Value
Reserved Odd Parity
P8
001
000
0
0
P7
000
111
0
0
P6
000
110
0
1
P5
000
101
0
1
P4
000
100
0
0
P3
000
011
0
1
P2
000
010
0
0
P1
000
001
0
0
P0
000
000
0
1
PLCP Path User Channel (F1). The F1 octet is the user channel, which is allocated for user communication purposes between adjacent PLCPs. The default code for this octet is 00000000.
Bit Interleaved Parity-8 (B1). One octet is allocated for PLCP path error monitoring. This function is a bit interleaved parity-8 (BIP-8) code using even parity. The PLCP path BIP-8 is calculated over the 9 x 54 octet structure
(columns 4 to 57, numbering from 1) of the previous PLCP frame and inserted into the B1 of the current frame.
506
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155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Functional Description (continued)
PLCP Path Status (G1). The G1 octet is allocated to convey the received PLCP status and performance back to
the transmitting PLCP. The G1 octet consists of:
■
4 bits for far-end block error (FEBE—G1[7:4]) code.
— FEBE code may be used to convey the count of the interleaved-bit blocks that have been detected to be in
error by the BIP-8 code in the preceding frame. If implemented, this count has nine legal values, namely zero
(0000) to eight (1000) errors. If not implemented, the code is 1111. All other codes are interpreted as zero errors.
■
1 bit for the alarm signal (AS).
— The AS bit is set to a logic 1 when a received failure is detected. This bit is set under software control only.
■
3 bits for a link status signal (LSS).
— The remaining 3 bits are used for the LSS as described in IEEE Standard 802.6 Section 11.3.2. The LSS is
used to communicate information about the status of the transmission link between two adjacent PLCP entities.
The function is not supported and the bits are set to 111.
The G1 fields are illustrated in Table 465.
Table 465. PLCP G1 byte
7
6
5
4
FEBE
3
AS
2
1
0
LSS
DQDB Layer Management Information Octets (M1, M2). The octets M1 and M2 carry the DQDB layer management information octets that are described in IEEE Standard 802.6, Section 10.1. These bytes are not supported
and set to 0.
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Data Sheet
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DS3/E3 Block (continued)
E3 Functional Description (continued)
Stuffing (C1). The C1 octet indicates the PLCP frame in which an octet stuffing will occur and contains the number
of trailer octets transmitted (17 to 21). The allowed C1 codes are as per Table 466.
Table 466. C1 Values and Transmit Insert Sequence
Trailer
Byte
Value
Numbering
7
6
Protection Code
5
4
3
2
Not
Used
1
Hex
0
17
001
1101
1
0x3B
18
010
0111
1
0x4F
19
011
1010
1
0x75
20
100
1110
1
0x9D
21
101
0011
1
0xA7
Transmit C1 Insert Sequence
Sequence
Type
Sequence
A
18
19
B
18
19
18
Repeat N times
19
18
6
1
The C1 codes above provide error correction capability for one bit error and two adjacent bit errors, and error
detection capability for three random bit errors using the Abramson code (x3 + x + 1)(x + 1).
Growth Octets (Z1—Z3). These octets are reserved for future use. These octets are encoded to the default code
of 00000000.
508
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
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DS3/E3 Block (continued)
E3 Functional Description (continued)
Register Description Control Bits for G.751 E3 Frame, E3 PLCP Frame, and G.832 Frame
This section describes the monitoring and insert capabilities for G.751 E3 frame, E3 PLCP frame, and G.832 E3
frame.
Rx/Tx Mode Control Definition. Three bits are used in the receive/transmit directions to determine the mapping/
demapping mode. See Table 467 and Table 468.
Table 467. Receive Mode Control Signals
Control Bit
Mode
Reset Default Mode
X/ No Mapping
000,
No Mapping
RDS3orE3
RDS3PLCP[1:0]
0
00
0
01
0
10
DS3/Clear Channel
Mapping
0
11
DS3/PLCP Mapping
1
00
X/No Mapping
1
01
E3/G.832 Frame
1
10
E3/G.751 Frame
1
11
E3/G.751 PLCP Mapping
Table 468. Transmit Mode Control Signals
Control Bit
Mode
Reset Default Mode
000,
No Mapping
TDS3orE3
TDS3PLCP[1:0]
0
00
No Mapping
0
01
DS3 Locked Mode
0
10
DS3 Clear Channel
0
11
DS3/PLCP Mapping
1
00
X/No Mapping
1
01
E3/G.832 Frame
1
10
E3/G751 Frame
1
11
E3/G751 PLCP Mapping
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Data Sheet
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DS3/E3 Block (continued)
E3 Functional Description (continued)
G.751 E3 Frame. This block implements only direct or PLCP mapping into the G.751 E3 frame. ATM cells are octet
aligned with the 16 overhead bits at the start of each frame.
See Table 462 for the G.751 E3 frame format.
Table 469. G.751 E3 Frame Transmit Overhead Operation
Control Bit
Transmit Direction
Frame Alignment Signal
Register Bits
Insert value 10b‘1111010000.
TE3_FA_INV[16—1]
RAI: Remote Alarm Indication (A)
NA: National Use Bit
Insert the RAI value under software control only.
TE3_RAI_DINS[16—1]
Set the NA bit to 0.
No Control Bit
Cjk: Justification Service Bits
Included as part of payload.
No Control Bit
Jk: Tributary Justification Bits
Included as part of payload.
No Control Bit
Table 470. G.751 E3 Frame Receive Overhead Operation
Control Bit
Receive Direction
Register Bits
Frame Alignment Signal
Out of frame = 0, when the pattern (10 or 14
bits) has been detected for three consecutive
frames.
E3_OOF[A—B][12—1],
E3_OOF[A—B][12—1]D/M,
Out of frame = 1, when four consecutive
frames are detected with errors.
E3_G751_10or14bit_FRMPAT
Loss of frame = 1, when the associated OOF
bit is high continuously for a programmable
number of frame periods (range 0 to 4 ms in
125 µs steps).
E3_LOF[A—B][12—10],
E3_LOF[A—B][12—1]D/M
Loss of frame = 0, when the associated OOF
bit is low continuously for a programmable
number of frame periods.
E3_LOF_SETCNT[4:0],
E3_LOF_CLRCNT[4:0]
RAI: Remote Alarm
Indication
Monitor with a programmable continuous N
times detect (CNTD), 0 to 15.
NA: National Use Bit
Not monitored.
No Control Bit
Process as part of payload.
No Control Bit
Jk: Tributary Justification Process as part of payload.
Bits
No Control Bit
Cjk: Justification Service
Bits
510
E3_G751_RAI_DET_CNTD[3:0],
E3_G751_RAI_DET[A—B][12—1],
E3_G751_RAI_DET[A—B][12—1]D/M
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Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Functional Description (continued)
AIS Insertion and Detection.
Insertion. Under software control, an all 1s pattern can be generated to replace the G.751 E3 frame and payload
bytes (TE3_AISINS[16—1]).
Detection. E3_AISPAT_DET = 1, when less than a programmable number of 0s are detected during one complete
frame period while the framer is in the out-of-frame mode (E3_OOF = 1).
E3_AISPAT_DET = 0, when greater than or equal to a programmable number of 0s are detected during one complete frame period, or the framer is in frame (E3_OOF = 0).
Register bits: E3_G751_AIS_0CNT[3:0] (Default Value = 5), E3_AISPAT_DET[A—B][12—1],
E3_AISPAT_DET[A—B][12—1]D/M.
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Data Sheet
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DS3/E3 Block (continued)
E3 Functional Description (continued)
G.751 E3 PLCP Frame. The PLCP frame is octet aligned to the 16 overhead bits. There is no relationship between
the start of the PLCP frame and the start of the E3 frame.
Table 471. G.751 E3-PLCP Transmit Overhead Operation
Control Bit
A1, A2: Frame
P0—P8: Path Overhead
Identifier
Z1—Z3: Growth
F1: User Channel
Transmit Direction
Insert A1, A2 values (0xF6, 0x28),
respectively.
Register Bits
TE3_PLCP_A2_INV[16—1]
Insert per Table 464.
TE3_PLCP_POIB7_INV[16—1]
Insert a programmable value into the
selected time slot from the associated
software register; otherwise, insert a fixed
value of all zeros.
TE3_PLCP_ZF_CHID[5:0],
TE3_PLCP_Z1_DINS[7:0],TE3_
PLCP_Z2_DINS[7:0],
TE3_PLCP_Z3_DINS[7:0],
TE3_PLCP_F1_DINS[7:0],
B1: Bit Interleaved Parity
A calculated BIP-8 value over the previous
frame (Col. 4 to 57) is inserted into this byte.
TE3_PLCP_B1_INV
[16—1]
G1: Path Status
G1[7:4] = FEBE indicates the number of B1
errors detected in the receive direction. The
FEBE field has nine legal values (4b‘0000 to
4b‘1000). Its value can be inserted under
software control (used for testing).
TE3_PLCP_FEBE_SWEN
[16—1],
TE3_PLCP_FEBE_DINS
[3:0],
G1[3] = AS, This bit is programmable
through the microprocessor interface.
TE3_PLCP_G1_AS_DINS
[16—1]
G[2:0] = LSS, This function is not supported
and fixed to (3b‘111).
M1 and M2: Control Information This function is not supported. Set both
octets to (00000000).
C1: Stuff Counter
512
Table 466 defines the sequence used for the
C1 byte to yield a nominal PLCP frame rate
of 125 µs. The C1 value can only change by
±1 at any value change.
No control bits
No control bits
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155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Functional Description (continued)
Table 472. G.751 E3-PLCP Receive Overhead Operation
Control Bit
A1, A2: Frame
Receive Direction
Register Bits
E3_PLCP_OOF[A—B][12—1],
Out-of-frame = 0, when the pattern has been
detected for two consecutive rows, along with two E3_PLCP_OOF[A—B][12—1]D/M
valid POI octets.
Out-of-frame = 1, when errors are detected in
both octets in a single row, or when errors are
detected in two consecutive POI octets.
Loss-of-frame = 1, when the associated OOF bit
is high continuously for a programmable number
of frame periods (range 0 to 4 ms in 125 µs
steps).
P0—P8: Path Overhead
Identifier
Z1—Z3: Growth
F1: User Channel
Loss-of-frame = 0, when the associated OOF bit
is low continuously for a programmable number of
frame periods.
Used in PLCP framing.
These bytes are independently monitored for a
CNTD value change.
B1: Bit Interleaved Parity The received BIP-8 value is checked against the
calculated value. Any differences are
accumulated in a saturating counter. This counter
can count bit or block errors; this is a per block
control bit.
G1: Path Status
G1[7:4] = FEBE, All legal values are accumulated
in a saturating counter. This counter can
accumulate bit or block errors; this is a per block
control bit.
G1[3] = AS, This bit is monitored for a CNTD
value change. This is a per block control bit.
M1 and M2: Control
Information
C1: Stuff Counter
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G[2:0] = LSS, This function is not supported and
ignored.
These octets are ignored.
The stuff counter is decoded and error correction
is performed to determine the number of trailer
bytes (see Stuffing (C1). The C1 octet indicates
the PLCP frame in which an octet stuffing will
occur and contains the number of trailer octets
transmitted (17 to 21). The allowed C1 codes are
as per Table 466. on page 508).
E3_PLCP_LOF[A—B][12—1],
E3_PLCP_LOF[A—B][12—1]D/M
E3_PLCP_LOF_SETCNT[4:0],
E3_PLCP_LOF_CLRCNT[4:0]
No status bits
E3_PLCP_ZF_CNTD[3:0],
E3_PLCP_ZF_TSSEL[A-D][3:0],
E3_PLCP_ZF_DMON
[A—B]D/M
E3_PLCP_Z1_DMON[A—B][7:0],
E3_PLCP_Z2_DMON[A—B][7:0],
E3_PLCP_Z3_DMON[A—B][7:0],
E3_PLCP_F1_DMON[A—B][7:0]
E3_PLCP_B1ERRCNT
[A—B][12—1][15:0],
E3_PLCP_B1_BITBLK
E3_PLCP_G1_FEBE_BITBLK,
E3_PLCP_G1_FEBE_ERRCNT
[A—B][12—1][15:0],
E3_PLCP_G1_AS[A—B][12—1],
E3_PLCP_G1_AS[A—B][12—
1]D/M,
E3_PLCP_G1_AS_CNTD[3:0]
No status bits
No status bits
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Data Sheet
August 18, 2004
DS3/E3 Block (continued)
E3 Functional Description (continued)
G.832 E3 Frame Overhead Operation. The G.832 E3 frame format allows direct byte mapping of ATM cells. ATM
cells are octet aligned with the G.832 E3 frame. This block does not support E3 PLCP mapped ATM cells in the
G.832 E3 frame.
Table 473. G.832 E3 Transmit Frame Overhead Operation
Control Bit
Transmit Direction
Register Bits
A1, A2: Frame
Insert FA1, FA2 as 0xF6, 0x28, respectively. The
framing pattern can be inverted under software
control.
TE3_FA_INV[16—1]
Inserts even parity (BIP-8) calculated over the
entire frame including the overhead bits.
TE3_B1_INV[16—1]
EM: Error Monitor BIP-8
TR: Trail Trace
MA: Maintenance and
Adaptation Byte
Inserts the 16-byte identifier from provisionable
TE3_TR_INS[16—1],
registers when enabled; otherwise, set TR byte to TE3_TR_DINS[16—1][15—0][7:0]
00000000.
MA[7] = RDI, This bit is software provisionable
only.
MA[6] = REI, Set to 1 if one or more BIP-8 errors
were detected in the associated E3 signal. If the
error insert bit is zero, follow the hardware value;
otherwise, force the bit to 1 continuously.
MA[5:3] = Payload type. Insert value under software control.
MA[2:0] = Multiframe indicator and SSM pattern.
Bits[2:1] are a multiframe pattern counting from 0
to 3. A multiframe count of 0 = MSB of SSM four
bit pattern. To support old equipment, set all SSM
values to 0 or 1.
NR: Network Operator
Byte
TE3_MA_RDI_DINS[16—1],
TE3_MA_REI_ERRINS[16—1],
TE3_MA_PTYPE_DINS[16—
1][2:0],
TE3_MA_SSM[16—1][3:0].
Inserts a fixed value (00000000) for this byte.
Software insert is not supported.
No control bits
GC: General-Purpose
Inserts a fixed value (00000000) for this byte.
Communication Channel Software insert is not supported.
No control bits
514
Agere Systems Inc.
Data Sheet
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MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Functional Description (continued)
Table 474. G.832 E3 Receive Frame Overhead Operation
Control Bit
Receive Direction
Register Bits
A1, A2: Frame
Out of frame = 0, when the pattern has
been detected for two consecutive frames.
Out of frame = 1, when four consecutive
frame are detected with errors.
E3_OOF[A—B][12—1],
E3_OOF[A—B][12—1]D/M
Loss of frame = 1, when the associated
OOF bit is high continuously for a
programmable number of frame periods
(range 0 to 4 ms in 125 µs steps).
Loss of frame = 0, when the associated
OOF bit is low continuously for a
programmable number of frame periods.
E3_LOF[A—B][12—1],
E3_LOF[A—B][12—1]D/M
E3_LOF_SETCNT[4:0],
E3_LOF_CLRCNT[4:0]
Computes the incoming BIP-8 and
compares that value to the incoming value.
Errors are accumulated in a 14-bit
saturating counter. Bit or block errors can
be accumulated (block control bit).
E3_B1_ERRCNT
[A—B][12—1][13:0],
TR: Trail Trace
Compares the TR 16-byte pattern with an
expected value. (See description in G.832
E3 Frame TR-Byte Processing on page
516.)
E3_TR_MODE[A—B][12—1][1:0],
E3_TR_MISMATCH
[A—B][12—1]D/M,
E3_TR_MISMATCH[A—B][12—1],
E3_TR_EXP[A—B][12—1][15—0][7:0],
E3_TR_CAP[A—B][12—1][15—0][7:0]
MA: Maintenance and
Adaptation Byte
MA[7] = RDI, this bit is monitored using a
CNTD monitor.
E3_G832_MA_RDI_CNTD[3:0],
E3_G832_MA_RDI_DET
[A—B][12—1]D/M,
E3_G832_MA_RDI_DET
[A—B][12—1],
EM: Error Monitor BIP-8
MA[6] = REI, A saturating counter accumulates the REI values.
MA[5:3] = Payload type (PT). A CNTD
monitor is used on this field. A stable value
is accessible through the µP interface.
MA[2:0] = In nonmultiframe alignment
mode, bit 0 is monitored for a CNTD value.
In multiframe alignment mode, a CNTD
detection is performed on the 4-bit SSM
message.
E3_B1_BITBLK
E3_MA_REI_ERRCNT
[A—B][12—1][13:0],
E3_MA_PT_CNTD[3:0],
E3_MA_PT[A—B][12—1]D/M,
E3_MA_PT_CODE
[A—B][12—1][2:0],
E3_MA_MF_ENABLE[A—B][12—1],
E3_MA_SSM_CNTD[3:0],
E3_MA_SSM[A—B][12—1]D/M,
E3_MA_SSM_CODE
[A—B][12—1][3:0]
NR: Network Operator
Byte
Byte not monitored.
No status bits
GC: General Purpose
Byte not monitored.
Communication Channel
No status bits
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Data Sheet
August 18, 2004
DS3/E3 Block (continued)
E3 Functional Description (continued)
AIS Insertion and Detection.
Insertion. Under software control an all 1s pattern can be generated to replace the G.751 E3 frame and payload
bytes (TE3_AISINS[16—1]).
Detection (Default = 8 Matches/Mismatches). E3_AISPAT_DET = 1, when less than a programmable number of
0s are detected during one complete frame period (E3 G.751 frame (192 bytes)), while the framer is in the out-offrame mode (E3_OOF = 1).
E3_AISPAT_DET = 0, when greater than or equal to a programmable number of 0s are detected during one complete frame period, or the framer is in frame (E3_OOF = 0).
Register bits: E3_G832_AIS_0CNT[3:0], E3_AISPAT_DET[A—B][11—0], E3_AISPAT_DET[A—B][11—0]D/M.
G.832 E3 Frame TR-Byte Processing
The TR byte carries a repeating 16-byte message. The block extracts the message from all E3 channels and
stores the message in an internal register bank. Three types of monitoring are allowed:
1. Mode = 00, disable function.
2. Mode = 01, monitor for a mismatch between the incoming value and an expected value.
— A mismatch is declared if the received message differs from the expected message for ten consecutive messages. A mismatch clears when 4-out-of-5 received messages match the expected message.
— In this mode, the device frames on the most significant bit (MSB) of the first byte in the message being set to 1.
3. Mode = 10, monitor for a sustained change in the message.
— A sustained change is detected when the received message differs from the last stable message for ten consecutive messages. The new message then becomes the stable message and the device starts checking for
a sustained change from this new stable message.
— In this mode, no framing on the MSB occurs.
4. Mode = 11, capture incoming data.
516
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Functional Description (continued)
Transmit Channel ID to Time-Slot Alarm Mapping
The control bits to provide this function are TxChidtoTSMapping[16—1][1:0][3:0], where [16—1] = channel ID number, [1:0] = slice (A = 00, B, C, or D = 11, respectively), and [3:0] = time slots 0 to 11. The following signals are
transferred from the receive in each mode.
1. G.832 E3 framing mode.
— MA byte, REI—One bit signal that toggles for each error detected in the received EM byte.
2. G.751 E3 framing mode.
— No status bits transferred.
3. G.751 E3 PLCP framing mode.
— G1 byte, FEBE, 4-bit field, and single toggles for each error.
PRBS Insert and Monitor
A 223 – 1 PRBS pattern can be generated and placed in either E3 frame or the E3 PLCP frame under software
control. See Table 475 and Table 476 for the control bit summary for the receive and transmit directions, respectively. These bits, along with the other PRBS insert/monitor bits already defined (see DS3 requirements), control
the PRBS functions.
Table 475. PRBS Receive (Monitor) Pattern Control Signals
Control Bit
Mode
RPRBS23
RPRBS_15or20
0
0
215 – 1
0
1
220 – 1
1
X
223 – 1
1
Table 476. PRBS Transmit Pattern Control Signals
Control Bit
Mode
TPRBS23
TPRBS15or20
0
0
215 – 1
0
1
220 – 1
1
X
223 – 1
1
Agere Systems Inc.
517
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions
DS3 Global Registers
Table 477. DS3E3_VERR, Version Control (RO)
Address
Bit
Name
0x5000
15:8
—
7:0
DS3E3_VER[7:0]
Function
Reset
Default
Reserved.
0x00
Block Version. Indicates version number of this block.
0x00
Table 478. DS3_SCRATCHR, Scratch Register (R/W)
Address
Bit
Name
0x5001
15:0
DS3_SCRATCH
[15:0]
Function
Reset
Default
Read/write register with no other internal DS3 connections. 0x0000
Table 479. DS3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for
Delta/Event Registers (R/W)
Address
Bit
Name
Function
Reset
Default
0x5002
15
DS3_COR_COWN
Control bit, when set (0) all delta and event registers
function in the clear-on-write (COW) mode; otherwise, they
function in the clear-on-read (COR) mode.
0
14:12
—
Reserved.
—
11
SEQ_RX
518
Monitor receive output signals (active-high)
DS3_TM_DATA
<=
("00000000000000",
DS3_RXSYNC,
DS3_RXPM_A,
DS3_RXEOP_A,
DS3_RXPM_B,
DS3_RXEOP_B,
DS3_RXPM_C,
DS3_RXEOP_C,
DS3_RXPM_D,
DS3_RXEOP_D,
DS3_RXDATA_A,
DS3_RXDATA_B,
DS3_RXDATA_C,
DS3_RXDATA_D);
0x0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 479. DS3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for
Delta/Event Registers (R/W) (continued)
Address
Bit
Name
0x5002
10
TM_RX
Control inputs into the receive direction (active-high)
if (TM_RX = ’1’) the
PT_RXSYNC_i <= TM_DATA(40);
PT_RXJ1_A_i <= TM_DATA(39);
PT_RXPM_A_i <= TM_DATA(38);
PT_RXJ1_B_i <= TM_DATA(37);
PT_RXPM_B_i <= TM_DATA(36);
PT_RXJ1_C_i <= TM_DATA(35);
PT_RXPM_C_i <= TM_DATA(34);
PT_RXJ1_D_i <= TM_DATA(33);
PT_RXPM_D_i <= TM_DATA(32);
PT_RXDATA_A_i <= TM_DATA(31:24);
PT_RXDATA_B_i <= TM_DATA(23:16);
PT_RXDATA_C_i <= TM_DATA(15:8);
PT_RXDATA_D_i <= TM_DATA(7:0);
else
PT_RXSYNC_i <= PT_RXSYNC;
PT_RXJ1_A_i <= PT_RXJ1_A;
PT_RXPM_A_i <= PT_RXPM_A;
PT_RXDATA_A_i <= PT_RXDATA_A;
PT_RXJ1_B_i <= PT_RXJ1_B;
PT_RXPM_B_i <= PT_RXPM_B;
PT_RXDATA_B_i <= PT_RXDATA_B;
PT_RXJ1_C_i <= PT_RXJ1_C;
PT_RXPM_C_i <= PT_RXPM_C;
PT_RXDATA_C_i <= PT_RXDATA_C;
PT_RXJ1_D_i <= PT_RXJ1_D;
PT_RXPM_D_i <= PT_RXPM_D;
PT_RXDATA_D_i <= PT_RXDATA_D;
end if;
0x0
9
PT_TX
Monitor transmit output signals (active-high)
DS3_TM_DATA <= ("00",
PT_TXBR,
PT_TXBR_CID,
DS3_TXBR,
DS3_TXBR_CID,
DS3_TXPM,
DS3_TXCID,
DS3_TXDATA);
0x0
Agere Systems Inc.
Function
Reset
Default
519
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 479. DS3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for
Delta/Event Registers (R/W) (continued)
Address
Bit
Name
0x5002
8
TM_TX
7:6
—
5:0
GPOSEL[5:0]
520
Function
Reset
Default
Control inputs into the transmit direction (active-high)
DS3_TM_DATA
<=
("00000000000000000",
"00000000000000000",
"00000000000000",
DS3_TXBR_CID,
DS3_TXBR);
if (TM_TX = ’1’) then
DE_TXDATA_i <= TM_DATA(31 0);
DE_TXPM_i
<= TM_DATA(32);
DE_TXDVLD_i <= TM_DATA(33);
DE_TXEOP_i <= TM_DATA(37:34);
DE_TXCID_i <= TM_DATA(43: 38);
else
DE_TXDATA_i <= DE_TXDATA;
DE_TXPM_i
<= DE_TXPM;
DE_TXDVLD_i <= DE_TXDVLD;
DE_TXEOP_i <= DE_TXEOP;
DE_TXCID_i <= DE_TXCID;
end if;
Reserved.
0x0
—
GPO_ADDRESS can be 0x00 to 0x2b. Configure the
GPO_ADDRESS to this register, and this address is
passed to DS3_GPO_MUX block to select one of GPO
outputs when it is selected to read.
000000
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Interface A Delta/Event Registers
Table 480. DS3FRMD_A, DS3 Out-of-Frame Delta (COR/COW)
Address
Bit
Name
0x5003
15:12
—
11:0
DS3_OOFD_
A[12—1]
Function
Reserved.
Reset
Default
0x0
Each time the DS3_OOF_A[12—1] state bit changes state
(0 to 1 or 1 to 0), the delta bit is set.
0x0FFF
Table 481. DS3LOFD_A, DS3 Loss-of-Frame Delta (COR/COW)
Address
Bit
Name
0x5004
15:12
—
11:0
DS3_LOFD_
A[12—1]
Agere Systems Inc.
Function
Reserved.
Each time the DS3_LOF_A[12—1] state bit changes state
(0 to 1 or 1 to 0), the delta bit is set.
Reset
Default
0x0
0x0FFF
521
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 482. DS3SEFD_A, DS3 Severely Errored Frame (SEF) Delta (COR/COW)
Address
Bit
Name
0x5005
15:12
—
11:0
DS3_SEFD_
A[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the DS3_SEF_A[12—1] state bit changes state
(0 to 1 or 1 to 0), the delta bit is set.
0x0FFF
Table 483. DS3AISD_A, DS3 AIS Detection Delta (COR/COW)
Address
Bit
Name
0x5006
15:12
—
11:0
DS3_AISPAT_
DETD_A[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the DS3_AISPAT_DET_A[12—1] state bit
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Table 484. DS3IDLED_A, DS3 Idle Detection Delta (COR/COW)
Address
Bit
Name
0x5007
15:12
—
11:0
DS3_IDLEPAT_
DETD_A[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the DS3_IDLEPAT_DET_A[12—1] state bit
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Table 485. DS3CBD_A, DS3 C-Bit Detect Delta (COR/COW)
Address
Bit
Name
0x5008
15:12
—
11:0
DS3_CBZ_DETD_
A[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the DS3_CBZ_DET_A[12—1] state bit changes
state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Table 486. DS3RAID_A, DS3 X-Bit Detect Delta (COR/COW)
Address
Bit
Name
0x5009
15:12
—
11:0
DS3_RAI_DETD_
A[12—1]
522
Function
Reset
Default
Reserved.
0x0
Each time the DS3_RAI_DET_A[12—1] state bit changes
state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 487. DS3FEACALMD_A, DS3 Far-End Alarm and Control (FEAC) RAI Delta (COR/COW)
Address
Bit
Name
0x500A
15:12
—
11:0
Function
Reserved.
Reset
Default
0x0
DS3_RFEAC_RAID_ Each time the DS3_RFEAC_RAI_A[12—1] state bit
A[12—1]
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Table 488. DS3FEACCTLD_A, DS3 Far-End Alarm and Control (FEAC) Control Delta (COR/COW)
Address
Bit
Name
0x500B
15:12
—
11:0
DS3_RFEAC_
CTLD_A[12—1]
Function
Reserved.
Reset
Default
0x0
Each time the DS3_RFEAC_CTL_A[12—1] state bit
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x0FFF
Table 489. DS3_PLCPOOFD_A, PLCP Out-of-Frame Monitor Delta (COR/COW)
Address
Bit
Name
0x500C
15:12
—
11:0
Function
Reserved.
Reset
Default
0x0
DS3_PLCP_OOFD_ Each time the DS3_PLCP_OOF_A[12—1] state bit
A[12—1]
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x0FFF
Table 490. DS3_PLCPRAID_A, PLCP RAI (G1[3]) Monitoring Delta (COR/COW)
Address
Bit
Name
0x500D
15:12
—
11:0
DS3_PLCP_G1_
RAID_A[12—1]
Function
Reserved.
Reset
Default
0x0
Each time the DS3_PLCP_G1_RAI_A[12—1] state bit
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Table 491. DS3_RXPRBS_SYNCD_A, PRBS Detector Sync Delta (COR/COW)
Address
Bit
Name
0x500E
15:2
—
1:0
Agere Systems Inc.
Function
Reserved.
DS3_RPRBS_
Each time the DS3_RPRBS_SYNC_ERR_A[12—1] state
SYNC_ERRD_A[1:0] bit changes state (0 to 1 or 1 to 0), the delta bit is set.
Reset
Default
0x000
11
523
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Interface B Delta/Event Registers
Table 492. DS3FRMD_B, DS3 Out-of-Frame Delta (COR/COW)
Address
Bit
Name
0x500F
15:12
—
11:0
DS3_OOFD_
B[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the DS3_OOF_B[12—1] state bit changes state
(0 to 1 or 1 to 0), the delta bit is set.
0x0FFF
Table 493. DS3LOFD_B, DS3 Loss-of-Frame Delta (COR/COW)
Address
Bit
Name
0x5010
15:12
—
11:0
DS3_LOFD_
B[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the DS3_LOF_B[12—1] state bit changes state
(0 to 1 or 1 to 0), the delta bit is set.
0x0FFF
Table 494. DS3SEFD_B, DS3 Severely Errored Frame (SEF) Delta (COR/COW)
Address
Bit
Name
0x5011
15:12
—
11:0
DS3_SEFD_
B[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the DS3_SEF_B[12—1] state bit changes state
(0 to 1 or 1 to 0), the delta bit is set.
0x0FFF
Table 495. DS3AISD_B, DS3 AIS Detection Delta (COR/COW)
Address
Bit
Name
0x5012
15:12
—
11:0
DS3_AISPAT_
DETD_B[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the DS3_AISPAT_DET_B[12—1] state bit
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Table 496. DS3IDLED_B, DS3 Idle Detection Delta (COR/COW)
Address
Bit
Name
0x5013
15:12
—
11:0
DS3_IDLEPAT_
DETD_B[12—1]
524
Function
Reset
Default
Reserved.
0x0
Each time the DS3_IDLEPAT_DET_B[12—1] state bit
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 497. DS3CBD_B, DS3 C-Bit Detect Delta (COR/COW)
Address
Bit
Name
0x5014
15:12
—
11:0
DS3_CBZ_DETD_
B[12—1]
Function
Reserved.
Reset
Default
0x0
Each time the DS3_CBZ_DET_B[12—1] state bit changes
state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Table 498. DS3RAID_B, DS3 X-Bit Detect Delta (COR/COW)
Address
Bit
Name
0x5015
15:12
—
11:0
DS3_RAI_DETD_
B[12—1]
Function
Reserved.
Reset
Default
0x0
Each time the DS3_RAI_DET_B[12—1] state bit changes
state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Table 499. DS3FEACALMD_B, DS3 Far-End Alarm and Control (FEAC) RAI Delta (COR/COW)
Address
Bit
Name
0x5016
15:12
—
11:0
Function
Reserved.
Reset
Default
0x0
DS3_RFEAC_RAID_ Each time the DS3_RFEAC_RAI_B[12—1] state bit
B[12—1]
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Table 500. DS3FEACCTLD_B, DS3 Far-End Alarm and Control (FEAC) Control Delta (COR/COW)
Address
Bit
Name
0x5017
15:12
—
11:0
DS3_RFEAC_
CTLD_B[12—1]
Function
Reserved.
Reset
Default
0x0
Each time the DS3_RFEAC_CTL_B[12—1] state bit
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x0FFF
Table 501. DS3_PLCPOOFD_B, PLCP Out-of-Frame Monitor Delta (COR/COW)
Address
Bit
Name
0x5018
15:12
—
11:0
Agere Systems Inc.
Function
Reserved.
DS3_PLCP_OOFD_ Each time the DS3_PLCP_OOF_B[12—1] state bit
B[12—1]
changes state (0 to 1 or 1 to 0), the delta bit is set.
Reset
Default
0x0
0x0FFF
525
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 502. DS3_PLCPRAID_B, PLCP RAI (G1[3]) Monitoring Delta (COR/COW)
Address
Bit
Name
0x5019
15:12
—
11:0
DS3_PLCP_G1_
RAID_B[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the DS3_PLCP_G1_RAI_B[12—1] state bit
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Table 503. DS3_RXPRBS_SYNCD_B, PRBS Detector Sync Delta (COR/COW)
Address
Bit
Name
0x501A
15:2
—
1:0
Function
Reset
Default
Reserved.
0x000
DS3_RPRBS_
Each time the DS3_RPRBS_SYNC_ERR_B[2:1] state bit
SYNC_ERRD_B[1:0] changes state (0 to 1 or 1 to 0), the delta bit is set.
11
Transmit Direction FIFO Overflow/Underflow Event
Table 504. DS3_TXFIFOERRE, FIFO Overflow Indicator Event (COR/COW)
Address
Bit
Name
0x5033
15:0
DS3_TFIFO_OVR_
UNFLE[16—1]
Function
Reset
Default
Transmit FIFO overflow or underflow event indication
(active-high).
0x0000
Transmit Direction EOP Marker Error Event
Table 505. DS3_TXEOPERRER, EOP Marker Error Event (COR/COW)
Address
Bit
Name
0x5036
15:0
DS3_TXEOPERRE
[16—1]
526
Function
Reset
Default
EOP marker in PLCP or DS3 locked mode changed
position.
0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Interface A Mask Registers
Table 506. DS3FRMM_A, DS3 Out-of-Frame Mask (R/W)
Address
Bit
Name
0x5039
15:12
—
11:0
DS3_OOFM_
A[12—1]
Function
Reserved.
Reset
Default
0x0
DS3 Out-of-Frame Mask. When set high, the delta will not
contribute to the interrupt signal.
0xFFF
Table 507. DS3LOFM_A, DS3 Loss-of-Frame Mask (R/W)
Address
Bit
Name
0x503A
15:12
—
11:0
DS3_LOFM_
A[12—1]
Function
Reserved.
Reset
Default
0x0
DS3 Loss-of-Frame Mask. When set high, the delta will
not contribute to the interrupt signal.
0xFFF
Table 508. DS3SEFM_A, DS3 Severely Errored Frame (SEF) Mask (R/W)
Address
Bit
Name
0x503B
15:12
—
11:0
DS3_SEFM_
A[12—1]
Function
Reserved.
Reset
Default
0x0
DS3 Severely Errored Frame (SEF) Mask. When set
high, the delta will not contribute to the interrupt signal.
0xFFF
Table 509. DS3AISM_A, DS3 AIS Detection Mask (R/W)
Address
Bit
Name
0x503C
15:12
—
11:0
DS3_AISPAT_
DETM_A[12—1]
Function
Reserved.
Reset
Default
0x0
DS3 AIS Detection Mask. When set high, the delta will not
contribute to the interrupt signal.
0xFFF
Table 510. DS3IDLEM_A, DS3 Idle Detection Mask (R/W)
Address
Bit
Name
0x503D
15:12
—
11:0
DS3_IDLEPAT_
DETM_A[12—1]
Agere Systems Inc.
Function
Reserved.
DS3 Idle Detection Mask. When set high, the delta will not
contribute to the interrupt signal.
Reset
Default
0x0
0xFFF
527
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 511. DS3CBM_A, DS3 C-Bit Detect Mask (R/W)
Address
Bit
Name
0x503E
15:12
—
11:0
DS3_CBZ_DETM_
A[12—1]
Function
Reset
Default
Reserved.
0x0
DS3 C-Bit Detect Mask. When set high, the delta will not
contribute to the interrupt signal.
0xFFF
Table 512. DS3RAIM_A, DS3 X-Bit Detect Mask (R/W)
Address
Bit
Name
0x503F
15:12
—
11:0
DS3_RAI_DETM_
A[12—1]
Function
Reset
Default
Reserved.
0x0
DS3 X-Bit Detect Mask. When set high, the delta will not
contribute to the interrupt signal.
0xFFF
Table 513. DS3FEACALMM_A, DS3 Far-End Alarm and Control (FEAC) Alarm Mask (R/W)
Address
Bit
Name
0x5040
15:12
—
11:0
Function
Reset
Default
Reserved.
0x0
DS3_RFEAC_RAIM_ DS3 Far-End Alarm and Control (FEAC) Alarm Mask.
A[12—1]
When set high, the delta will not contribute to the interrupt
signal.
0xFFF
Table 514. DS3FEACCTLM_A, DS3 Far-End Alarm and Control (FEAC) Control Mask (R/W)
Address
Bit
Name
0x5041
15:12
—
11:0
DS3_RFEAC_
CTLM_A[12—1]
Function
Reset
Default
Reserved.
0x0
DS3 Far-End Alarm and Control (FEAC) Control Mask.
When set high, the delta will not contribute to the interrupt
signal.
0xFFF
Table 515. DS3_PLCPOOFM_A, PLCP Out-of-Frame Monitor Mask (R/W)
Address
Bit
Name
0x5042
15:12
—
11:0
528
Function
Reset
Default
Reserved.
0x0
DS3_PLCP_OOFM_ PLCP Out-of-Frame Monitor Mask. When set high, the
A[12—1]
delta will not contribute to the interrupt signal.
0xFFF
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 516. DS3_PLCPRAIM_A, PLCP RAI (G1[3]) Monitoring Mask (R/W)
Address
Bit
Name
0x5043
15:12
—
11:0
DS3_PLCP_G1_
RAIM_A[12—1]
Function
Reserved.
Reset
Default
0x0
PLCP RAI (G1[3]) Monitoring Mask. When set high, the
delta will not contribute to the interrupt signal.
0xFFF
Table 517. DS3_RXPRBS_SYNCM_A, PRBS Detector Sync Mask (R/W)
Address
Bit
Name
0x5044
15:2
—
1:0
Function
Reserved.
Reset
Default
0x000
DS3_RPRBS_
PRBS Detector Sync Mask. When set high, the delta will
SYNC_ERRM_A[1:0] not contribute to the interrupt signal.
11
Interface B Mask Registers
Table 518. DS3_DS3FRMM_B, DS3 Out-of-Frame Mask (R/W)
Address
Bit
Name
0x5045
15:12
—
11:0
DS3_DS3_OOFM_
B[12—1]
Function
Reserved.
Reset
Default
0x0
DS3 Out-of-Frame Mask. When set high, the delta will not
contribute to the interrupt signal.
0xFFF
Table 519. DS3LOFM_B, DS3 Loss-of-Frame Mask (R/W)
Address
Bit
Name
0x5046
15:12
—
11:0
DS3_LOFM_
B[12—1]
Function
Reserved.
Reset
Default
0x0
DS3 Loss-of-Frame Mask. When set high, the delta will
not contribute to the interrupt signal.
0xFFF
Table 520. DS3SEFM_B, DS3 Severely Errored Frame (SEF) Mask (R/W)
Address
Bit
Name
0x5047
15:12
—
11:0
DS3_SEFM_
B[12—1]
Agere Systems Inc.
Function
Reserved.
DS3 Severely Errored Frame (SEF) Mask. When set
high, the delta will not contribute to the interrupt signal.
Reset
Default
0x0
0xFFF
529
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 521. DS3AISM_B, DS3 AIS Detection Mask (R/W)
Address
Bit
Name
0x5048
15:12
—
11:0
DS3_AISPAT_
DETM_B[12—1]
Function
Reset
Default
Reserved.
0x0
DS3 AIS Detection Mask. When set high, the delta will not
contribute to the interrupt signal.
0xFFF
Table 522. DS3IDLEM_B, DS3 Idle Detection Mask (R/W)
Address
Bit
Name
0x5049
15:12
—
11:0
DS3_IDLEPAT_
DETM_B[12—1]
Function
Reset
Default
Reserved.
0x0
DS3 Idle Detection Mask. When set high, the delta will not
contribute to the interrupt signal.
0xFFF
Table 523. DS3CBM_B, DS3 C-Bit Detect Mask (R/W)
Address
Bit
Name
0x504A
15:12
—
11:0
DS3_CBZ_DETM_
B[12—1]
Function
Reset
Default
Reserved.
0x0
DS3 C-Bit Detect Mask. When set high, the delta will not
contribute to the interrupt signal.
0xFFF
Table 524. DS3RAIM_B, DS3 X-Bit Detect Mask (R/W)
Address
Bit
Name
0x504B
15:12
—
11:0
DS3_RAI_DETM_
B[12—1]
Function
Reset
Default
Reserved.
0x0
DS3 X-Bit Detect Mask. When set high, the delta will not
contribute to the interrupt signal.
0xFFF
Table 525. DS3FEACALMM_B, DS3 Far-End Alarm and Control (FEAC) Alarm Mask (R/W)
Address
Bit
Name
0x504C
15:12
—
11:0
530
Function
Reset
Default
Reserved.
0x0
DS3_RFEAC_RAIM_ DS3 Far-End Alarm and Control (FEAC) Alarm Mask.
B[12—1]
When set high, the delta will not contribute to the interrupt
signal.
0xFFF
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 526. DS3FEACCTLM_B, DS3 Far-End Alarm and Control (FEAC) Control Mask (R/W)
Address
Bit
Name
0x504D
15:12
—
11:0
DS3_RFEAC_
CTLM_B[12—1]
Function
Reserved.
Reset
Default
0x0
DS3 Far-End Alarm and Control (FEAC) Control Mask.
When set high, the delta will not contribute to the interrupt
signal.
0xFFF
Table 527. DS3_PLCPOOFM_B, PLCP Out-of-Frame Monitor Mask (R/W)
Address
Bit
Name
0x504E
15:12
—
11:0
Function
Reserved.
Reset
Default
0x0
DS3_PLCP_OOFM_ PLCP Out-of-Frame Monitor Mask. When set high, the
B[12—1]
delta will not contribute to the interrupt signal.
0xFFF
Table 528. DS3_PLCPRAIM_B, PLCP RAI (G1[3]) Monitoring Mask (R/W)
Address
Bit
Name
0x504F
15:12
—
11:0
DS3_PLCP_G1_
RAIM_B[12—1]
Function
Reserved.
Reset
Default
0x0
PLCP RAI (G1[3]) Monitoring Mask. When set high, the
delta will not contribute to the interrupt signal.
0xFFF
Table 529. DS3_RXPRBS_SYNCM_B, PRBS Detector Sync Mask (R/W)
Address
Bit
Name
0x5050
15:2
—
1:0
Agere Systems Inc.
Function
Reserved.
DS3_RPRBS_
PRBS Detector Sync Mask. When set high, the delta will
SYNC_ERRM_B[1:0] not contribute to the interrupt signal.
Reset
Default
0x000
11
531
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Transmit Direction FIFO Overflow/Underflow Mask
Table 530. DS3_TXFIFOERRM, FIFO Overflow Indicator Mask (R/W)
Address
Bit
Name
0x5069
15:0
DS3_TFIFO_OVR_
UNFLM[16—1]
Function
Reset
Default
FIFO Overflow Indicator Mask. Transmit FIFO overflow or 0xFFFF
underflow event indication (active-high).
Transmit Direction EOP Marker Error Mask
Table 531. DS3_TXEOPERRM, EOP Marker Error Mask (R/W)
Address
Bit
Name
0x506C
15:0
DS3_TXEOPERRM
[16—1]
532
Function
Reset
Default
EOP Marker Error Mask. EOP marker in PLCP or DS3
locked mode changed position.
0xFFFF
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Interface A State Registers
Table 532. DS3FRM_A, DS3 Out-of-Frame State (RO)
Address
Bit
Name
0x506F
15:12
—
11:0
Function
Reserved.
Reset
Default
0x0
DS3_OOF_A[12—1] DS3 Out-of-Frame State. State bit indicating on a per slice
and time-slot basis if the DS3 framer is in frame. 0 = in
frame, 1 = out of frame.
0xFFF
Table 533. DS3LOF_A, DS3 Loss-of-Frame State (RO)
Address
Bit
Name
0x5070
15:12
—
11:0
DS3_LOF_A[12—1]
Function
Reserved.
Reset
Default
0x0
DS3 Loss-of-Frame State. State bit is set (1) when the
DS3 framer is in the out-of-frame state for 28 continuous
frame periods (approximately 3 ms).
0xFFF
Table 534. DS3SEF_A, DS3 Severely Errored Frame (SEF) (RO)
Address
Bit
Name
0x5071
15:12
—
11:0
DS3_SEF_A[12—1]
Function
Reserved.
Reset
Default
0x0
A SEF defect is the occurrence of three or more F-bit errors
in 16 consecutive F bits. A SEF is cleared when the signal
is in-frame and there are less than 3 F-bit errors in 16
consecutive F bits.
0xFFF
Table 535. DS3AIS_A, DS3 AIS Detection (RO)
Address
Bit
Name
0x5072
15:12
—
11:0
Agere Systems Inc.
Function
Reserved.
DS3_AISPAT_DET_ AIS is declared if fewer than five pattern errors (1010) are
A[12—1]
received in each of two consecutive M-frames. AIS is
cleared when at least 16 pattern errors are received in each
of two consecutive M-frames.
Reset
Default
0x0
0x000
533
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 536. DS3IDLE_A, DS3 Idle Detection (RO)
Address
Bit
Name
0x5073
15:12
—
11:0
DS3_IDLEPAT_
DET_A[12—1]
Function
Reset
Default
Reserved.
0x0
Idle is declared if fewer than five pattern errors (1100) are
received in each of two consecutive M-frames. Idle is
cleared when at least 16 pattern errors are received in each
of two consecutive M-frames.
0x000
Table 537. DS3CB_A, DS3 C-Bit Detect (RO)
Address
Bit
Name
0x5074
15:12
—
11:0
DS3_CBZ_DET_
A[12—1]
Function
Reset
Default
Reserved.
0x0
Set if every C bit in three consecutive M frames are set to
0; clear if the three C bits in a M subframe are 1.
0x000
Table 538. DS3RAI_A, DS3 X-Bit Detect (RO)
Address
Bit
Name
0x5075
15:12
—
11:0
DS3_RAI_DET_
A[12—1]
Function
Reset
Default
Reserved.
0x0
Set if both X bits in two consecutive M frames are received
as 0; clear when both X bits in two consecutive M frames
are received as 1.
0x000
Table 539. DS3FEACALM_A, DS3 Far-End Alarm and Control (FEAC) (RO)
Address
Bit
Name
0x5076
15:12
—
11:0
DS3_RFEAC_RAI_
A[12—1]
534
Function
Reset
Default
Reserved.
0x0
If the validated code equals (011001, 001110, 000000, or
010110), then the RAI state bit is set. When the validated
code word does not equal one of the patterns above, the
RAI state bit is 0.
0x000
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 540. DS3FEACCTL_A, DS3 Far-End Alarm and Control (FEAC) (RO)
Address
Bit
Name
0x5077
15:12
—
11:0
DS3_RFEAC_CTL_
A[12—1]
Function
Reserved.
Reset
Default
0x0
If the validated code does not equal (011001, 001110,
000000, or 010110), then the CTL state bit is set. When the
validated code word equals one of the patterns above, the
CTL state bit is 0.
0xFFF
Table 541. DS3_PLCPOOF_A, PLCP Out-of-Frame Monitor (RO)
Address
Bit
Name
0x5078
15:12
—
11:0
DS3_PLCP_OOF_
A[12—1]
Function
Reserved.
Reset
Default
0x0
When the A1A2 pattern is detected in two consecutive
rows, the PLCP framer is considered in-frame. The PLCP
framer will transition to the OOF state when five
consecutive A1A2 mismatches are detected or five
consecutive POI mismatches occur.
0xFFF
Table 542. DS3_PLCPRAI_A, PLCP RAI (G1[3]) Monitoring (RO)
Address
Bit
Name
0x5079
15:12
—
11:0
DS3_PLCP_G1_
RAI_A[12—1]
Function
Reserved.
Reset
Default
0x0
While the PLCP framer is in the in-frame state, the RAI bit
is validated for changes and the validated value is placed in
this state register.
0x000
Table 543. DS3_RXPRBS_SYNC_A, PRBS Detector Sync State (RO)
Address
Bit
Name
0x507A
15:2
—
1:0
DS3_RPRBS_
SYNC_ERR_A[1:0]
Agere Systems Inc.
Function
Reserved.
When the device detects 32 matches in a row, it declares
itself in-sync (DS3_RPRBS_SYNC_ERR[A—B][1:0] is
cleared to 0) and the error detector is enabled. If the device
detects eight consecutive mismatches, the test-pattern
detector declares itself out-of-sync and starts searching
again.
Reset
Default
0x000
11
535
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 544. DS3FEACCODE_A[1—6], DS3 Far-End Alarm and Control (FEAC) (RO)
Address
Bit
Name
0x507B
—
0x5080
15:12
—
11:0
Function
Reset
Default
Reserved.
0x0
DS3_RFEAC_
This register is updated each time a validated code word is
CODE_A[12—1][5:0] accepted (same code word four consecutive times) serially
through the C13 bit. (Bit 5 = MSB of code word, LSB = Bit
0.)
0xFFF
Table 545. DS3_RXPRBSERRCNT_A, PRBS Error Counter (RO)
Address
Bit
Name
Function
Reset
Default
0x5081
15:0
DS3_RPRBS_
ERRCNT_
A[2—1][7:0]
The device counts the number of times the input data
differs from the expected value in an 8-bit counter that
holds its count when it reaches the maximum value of 255.
This counter is reset when read by the microprocessor and
is not affected by the PMRST signal.
0x0000
Interface B State Registers
Table 546. DS3FRM_B, DS3 Out-of-Frame State (RO)
Address
Bit
Name
0x5082
15:12
—
11:0
Function
Reset
Default
Reserved.
0x0
DS3_OOF_B[12—1] DS3 Out-of-Frame State. State bit indicating on a per slice
and time-slot basis if the DS3 framer is in frame. 0 = in
frame, 1 = out of frame.
0xFFF
Table 547. DS3LOF_B, DS3 Loss-of-Frame State (RO)
Address
Bit
Name
0x5083
15:12
—
11:0
DS3_LOF_B[12—1]
536
Function
Reset
Default
Reserved.
0x0
DS3 Loss-of-Frame State. State bit is set (1) when the
DS3 framer is in the out-of-frame state for 28 continuous
frame periods (approximately 3 ms).
0xFFF
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 548. DS3SEF_B, DS3 Severely Errored Frame (SEF) (RO)
Address
Bit
Name
0x5084
15:12
—
11:0
DS3_SEF_B[12—1]
Function
Reserved.
Reset
Default
0x0
A SEF defect is the occurrence of three or more F-bit errors
in 16 consecutive F bits. A SEF is cleared when the signal
is in-frame and there are less than 3 F-bit errors in 16
consecutive F bits.
0xFFF
Table 549. DS3AIS_B, DS3 AIS Detection (RO)
Address
Bit
Name
0x5085
15:12
—
11:0
Function
Reserved.
Reset
Default
0x0
DS3_AISPAT_DET_ AIS is declared if fewer than five pattern errors (1010) are
B[12—1]
received in each of two consecutive M frames. AIS is
cleared when at least 16 pattern errors are received in each
of two consecutive M frames.
0x000
Table 550. DS3IDLE_B, DS3 Idle Detection (RO)
Address
Bit
Name
0x5086
15:12
—
11:0
DS3_IDLEPAT_
DET_B[12—1]
Function
Reserved.
Reset
Default
0x0
Idle is declared if fewer than five pattern errors (1100) are
received in each of two consecutive M frames. Idle is
cleared when at least 16 pattern errors are received in each
of two consecutive M frames.
0x000
Table 551. DS3CB_B, DS3 C-Bit Detect (RO)
Address
Bit
Name
0x5087
15:12
—
11:0
DS3_CBZ_DET_
B[12—1]
Agere Systems Inc.
Function
Reserved.
Set if every C bit in three consecutive M frames are set to
0; clear if the three C bits in a M subframe are 1.
Reset
Default
0x0
0x000
537
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 552. DS3RAI_B, DS3 X-Bit Detect (RO)
Address
Bit
Name
0x5088
15:12
—
11:0
DS3_RAI_DET_
B[12—1]
Function
Reset
Default
Reserved.
0x0
Set if both X bits in two consecutive M frames are received
as 0; clear when both X bits in two consecutive M frames
are received as 1.
0x000
Table 553. DS3FEACALM_B, DS3 Far-End Alarm and Control (FEAC) (RO)
Address
Bit
Name
0x5089
15:12
—
11:0
DS3_RFEAC_RAI_
B[12—1]
Function
Reset
Default
Reserved.
0x0
If the validated code equals (011001, 001110, 000000, or
010110), then the RAI state bit is set. When the validated
code word does not equal one of the patterns above, the
RAI state bit is 0.
0x000
Table 554. DS3FEACCTL_B, DS3 Far-End Alarm and Control (FEAC) (RO)
Address
Bit
Name
0x508A
15:12
—
11:0
DS3_RFEAC_CTL_
B[12—1]
Function
Reset
Default
Reserved.
0x0
If the validated code does not equal (011001, 001110,
000000, or 010110), then the CTL state bit is set. When the
validated code word equals one of the patterns above, the
CTL state bit is 0.
0xFFF
Table 555. DS3_PLCPOOF_B, PLCP Out-of-Frame Monitor (RO)
Address
Bit
Name
0x508B
15:12
—
11:0
DS3_PLCP_OOF_
B[12—1]
538
Function
Reset
Default
Reserved.
0x0
When the A1A2 pattern is detected in two consecutive
rows, the PLCP framer is considered in frame. The PLCP
framer will transition to the OOF state when five
consecutive A1A2 mismatches are detected or five
consecutive POI mismatches occur.
0xFFF
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 556. DS3_PLCPRAI_B, PLCP RAI (G1[3]) Monitoring (RO)
Address
Bit
Name
0x508C
15:12
—
11:0
DS3_PLCP_G1_
RAI_B[12—1]
Function
Reserved.
Reset
Default
0x0
While the PLCP framer is in the in-frame state, the RAI bit
is validated for changes and the validated value is placed in
this state register.
0x000
Table 557. DS3_RXPRBS_SYNC_B, PRBS Detector Sync State (RO)
Address
Bit
Name
0x508D
15:2
—
1:0
DS3_RPRBS_
SYNC_ERR_B[1:0]
Function
Reserved.
Reset
Default
0x000
When the device detects 32 matches in a row, it declares
itself in-sync (DS3_RPRBS_SYNC_ERR[A—B][1:0] is
cleared to 0) and the error detector is enabled. If the device
detects eight consecutive mismatches, the test-pattern
detector declares itself out-of-sync and starts searching
again.
11
Table 558. DS3FEACCODE_B[1—6], DS3 Far-End Alarm and Control (FEAC) (RO)
Address
Bit
Name
0x508E
—
0x5093
15:12
—
11:0
Function
Reserved.
Reset
Default
0x0
DS3_RFEAC_
This register is updated each time a validated code word is
CODE_B[12—1][5:0 accepted (same code word four consecutive times) serially
through the C13 bit. (Bit 5 = MSB of code word, LSB = Bit
0.)
0xFFF
Table 559. DS3_RXPRBSERRCNT_B, PRBS Error Counter (RO)
Address
Bit
Name
Function
Reset
Default
0x5094
15:0
DS3_RPRBS_
ERRCNT_
B[2—1][7:0]
The device counts the number of times the input data
differs from the expected value in an 8-bit counter that
holds its count when it reaches the maximum value of 255.
This counter is reset when read by the microprocessor, and
is not affected by the PMRST signal.
0x0000
Agere Systems Inc.
539
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Receive Interface A Control Registers
Table 560. DS3_RXMODE_A_1, Receive Interface A Control Register 1 (R/W)
Address
Bit
0x50BB
15
Name
Function
Reset
Default
DS3_OOF_FMODE_ DS3 Framer F-Bit Error Control. (0 = 3 or more errors in
A
16 F bits) or (1 = 1 or more F-bit error in each of four
consecutive M-subframes) declare the DS3 out of frame.
14:12
—
11:0
DS3_RDS3PLCP_
A[6—1][1:0]
Reserved.
0
0x0
Receive Mode Control. 00 or 01 = no mapping, 10 = DS3
clear channel mapping, 11 = DS3/PLCP mapped signal.
See Table 560, DS3_RXMODE_A_1, Receive Interface A
Control Register 1 (R/W) on page 540 and Table 565,
DS3_RXPRBS_B, Receive PRBS (R/W) on page 542.
0x000
Table 561. DS3_RXMODE_A_2, Receive Interface A Control Register 2 (R/W)
Address
Bit
Name
0x50BC
15:14
DS3_RPRBS_INV_
A[1:0]
Control bit, when set, inverts the incoming pattern before
synchronization occurs.
00
13:12
DS3_RPRBS23_
A[1:0]
Control bit, when set, generates a (223 – 1) PRBS pattern;
otherwise, follow the RPRBS_15or20 control bit.
00
11:0
DS3_RDS3PLCP_
A[12—7][1:0]
Receive Mode Control. 00 or 01 = no mapping, 10 = DS3
clear channel mapping, 11 = DS3/PLCP mapped signal.
See Table 560, DS3_RXMODE_A_1, Receive Interface A
Control Register 1 (R/W) on page 540 and Table 565,
DS3_RXPRBS_B, Receive PRBS (R/W) on page 542.
0x000
540
Function
Reset
Default
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 562. DS3_RXPRBS_A, Receive PRBS (R/W)
Address
Bit
0x50BD
15:8
DS3_RPRBS_
PRBS Detector Time-Slot Detect. This register selects
TSSEL_A[2—1][3:0] which time slot the PRBS detector will monitor. Valid values
are 0 to 11, all illegal values disable the monitor. See
DS3_RPRBS_DS3_PLCP_A[1:0] bits 7:6 of this table and
DS3_PLCP_CNTD_G1_RAI_A[3:0] bits 3:0 of this table.
0xFF
7:6
DS3_RPRBS_DS3_ PRBS Detector Control. Control bit, when cleared, inserts
PLCP_A[1:0]
the PRBS sequence into a DS3 frame structure; otherwise,
it causes the PRBS sequence insertion to occur in the
PLCP ATM cell locations.
00
Control bit, when set, generates a (220 – 1) QRSS pattern;
otherwise, it generates a (215 – 1) PRBS pattern.
00
5:4
3:0
Name
DS3_RPRBS_
15or20_A[1:0]
Function
DS3_PLCP_CNTD_ (PLCPRAI[x][y]) PLCP RAI (G1[3]) Monitoring. The RAI
G1_RAI_A[3:0]
is validated using a continuous N times detect (CNTD)
mechanism, where the value must be the same for N times
in a row. This value can be programmed from 0 to 7. A
value of 0 or 1 causes the RAI value to be accepted each
time it changes state.
Reset
Default
0xB
Receive Interface B Control Registers
Table 563. DS3_RXMODE_B_1, Receive Interface B Control Register 1 (R/W)
Address
Bit
0x50BF
15
Name
DS3_OOF_FMODE_ DS3 Framer F-Bit Error Control. (0 = 3 or more errors in
B
16 F bits) or (1 = 1 or more F-bit error in each of four
consecutive M-subframes) declare the DS3 out of frame.
14:12
—
11:0
DS3_RDS3PLCP_
B[6—1][1:0]
Agere Systems Inc.
Function
Reserved.
Receive Mode Control. 00 or 01 = no mapping, 10 = DS3
clear channel mapping, 11 = DS3/PLCP mapped signal.
See Table 560, DS3_RXMODE_A_1, Receive Interface A
Control Register 1 (R/W) on page 540 and Table 565,
DS3_RXPRBS_B, Receive PRBS (R/W) on page 542.
Reset
Default
0
0x0
0x000
541
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 564. DS3_RXMODE_B_2, Receive Interface B Control Register 2 (R/W)
Address
Bit
Name
Function
Reset
Default
0x50C0
15:14
DS3_RPRBS_INV_
B[1:0]
Control bit, when set, inverts the incoming pattern before
synchronization occurs.
00
13:12
DS3_RPRBS23_
B[1:0]
Control bit, when set, generates a (223 – 1) PRBS pattern;
otherwise, follow the RPRBS_15or20 control bit.
00
11:0
DS3_RDS3PLCP_
B[12—7][1:0]
Receive Mode Control. 00 or 01 = no mapping, 10 = DS3
clear channel mapping, 11 = DS3/PLCP mapped signal.
See Table 560, DS3_RXMODE_A_1, Receive Interface A
Control Register 1 (R/W) on page 540 and Table 565,
DS3_RXPRBS_B, Receive PRBS (R/W) on page 542.
0x000
Table 565. DS3_RXPRBS_B, Receive PRBS (R/W)
Address
Bit
0x50C1
15:8
DS3_RPRBS_
PRBS Detector Time-Slot Detect. This register selects
TSSEL_B[2—1][3:0] which time slot the PRBS detector will monitor. Valid values
are 0 to 11; all illegal values disable the monitor. See
DS3_RPRBS_DS3_PLCP_B[1:0] bits 7:6 of this table and
DS3_PLCP_CNTD_G1_RAI_B[3:0] bit 3:0 of this table.
0xFF
7:6
DS3_RPRBS_DS3_ PRBS Detector Control. Control bit, when cleared, inserts
PLCP_B[1:0]
the PRBS sequence into a DS3 frame structure; otherwise,
it causes the PRBS sequence insertion to occur in the
PLCP ATM cell locations.
00
Control bit, when set, generates a (220 – 1) QRSS pattern;
otherwise, it generates a (215 – 1) PRBS pattern.
00
DS3_PLCP_CNTD_ (PLCPRAI[x][y]) PLCP RAI (G1[3]) Monitoring. The RAI
G1_RAI_B[3:0]
is validated using a continuous N times detect (CNTD)
mechanism, where the value must be the same for N times
in a row. This value can be programmed from 0 to 7. A
value of 0 or 1 causes the RAI value to be accepted each
time it changes state.
0xB
5:4
3:0
542
Name
DS3_RPRBS_
15or20_B[1:0]
Function
Reset
Default
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Receive Interface A Counters
Table 566. DS3_RXDS3FBIT_A[1—12], DS3 F-Bit and M-Bit Error Count (RO)
Address
Bit
Name
0x5100—
0x510B
15:14
—
13:0
DS3_FERR_CNT_
A[1—12][13:0]
Function
Reserved.
Reset
Default
00
This counter increments each time an error is detected in
either an F bit or M bit while the DS3 framer is in frame.
This counter is disabled while DS3_OOF = 1.
0x0000
Table 567. DS3_RXDS3_CVP_P_A[1—12], DS3 P-Bit CVP-P Error Counter (CVP-P) (RO)
Address
Bit
Name
0x510C—
0x5117
15:14
—
13:0
DS3_PERR_CNT_
A[1—12][13:0]
Function
Reserved.
Reset
Default
00
This counter increments if at least one of the P bits
disagree with the parity of the previous frame. This counter
saturates at its maximum value and is cleared by PMRST.
0x0000
Table 568. DS3_RXDS3_CVCP_P_A[1—12], DS3 CP-Bit Error Counter (CVCP-P) (RO)
Address
Bit
Name
0x5118—
0x5123
15:14
—
13:0
Agere Systems Inc.
Function
Reserved.
DS3_CPERR_CNT_ This counter increments if at least two of the three CP bits
A[1—12][13:0]
disagree with the parity of the previous frame. This counter
saturates at its maximum value and is cleared by PMRST.
Reset
Default
00
0x0000
543
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 569. DS3_RXDS3FEBE_A[1—12], DS3 FEBE Error Counter (CVCP-PFE) (RO)
Address
Bit
Name
0x5124—
0x512F
15:14
—
13:0
DS3_FEBE_CNT_
A[1—12][13:0]
Function
Reset
Default
Reserved.
00
The counter increments whenever 1 of the FEBE bits (C41,
C42, and C43) is set to zero in one M frame. This counter
saturates at its maximum value and is cleared by PMRST.
0x0000
Table 570. DS3_RXPLCPB1ECNT_A[1—12], PLCP B1 Error Count (RO)
Address
Bit
Name
Function
Reset
Default
0x5160—
0x516B
15:0
DS3_PLCP_
B1ERRCNT_
A[1—12][15:0]
While the PLCP framer is in the in-frame state, the number
of bit errors between the incoming BIP-8 and the calculated
BIP-8 value is accumulated in a 16-bit saturating counter.
This counter is cleared by the PMRST signal.
0x0000
Table 571. DS3_PLCPFEBECNT_A[1—12], PLCP FEBE (G1[7:4]) Error Count (RO)
Address
Bit
Name
Function
Reset
Default
0x516C—
0x5177
15:0
DS3_PLCP_G1_
FEBE_ERRCNT_
A[1—12][15:0]
While the PLCP framer is in the in-frame state, the number
of FEBE errors received (0—8) is accumulated in a 16-bit
saturating counter. Values greater than eight are ignored.
This counter is cleared by the PMRST signal.
0x0000
544
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Receive Interface B Counters
Table 572. DS3_RXDS3FBIT_B[1—12], DS3 F-Bit and M-Bit Error Count (RO)
Address
Bit
Name
0x5180—
0x518B
15:14
—
13:0
DS3_FERR_CNT_
B[1—12][13:0]
Function
Reserved.
Reset
Default
00
This counter increments each time an error is detected in
either an F bit or M bit while the DS3 framer is in-frame.
This counter is disabled while DS3_OOF = 1.
0x0000
Table 573. DS3_RDS3_CVP_P_B[1—12], DS3 P-Bit CVP-P Error Counter (CVP-P)
Address
Bit
Name
0x518C—
0x5197
15:14
—
13:0
DS3_PERR_CNT_
B[1—12][13:0]
Function
Reserved.
Reset
Default
00
This counter increments if at least one of the P bits
disagree with the parity of the previous frame. This counter
saturates at its maximum value and is cleared by PMRST.
0x0000
Table 574. DS3_RXDS3_CVCP_P_B[1—12], DS3 CP-Bit Error Counter (CVCP-P) (RO)
Address
Bit
Name
0x5198—
0x51A3
15:14
—
13:0
Agere Systems Inc.
Function
Reserved.
DS3_CPERR_CNT_ This counter increments if at least two of the three CP bits
B[1—12][13:0]
disagree with the parity of the previous frame. This counter
saturates at its maximum value and is cleared by PMRST.
Reset
Default
00
0x0000
545
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 575. DS3_RXDS3FEBE_B[1—12], DS3 FEBE Error Counter (CVCP-PFE) (RO)
Address
Bit
Name
0x51A4—
0x51AF
15:14
—
13:0
DS3_FEBE_CNT_
B[1—12][13:0]
Function
Reset
Default
Reserved.
00
The counter increments whenever 1 of the FEBE bits (C41,
C42, and C43) is set to 0 in one M frame. This counter
saturates at its maximum value and is cleared by PMRST.
0x0000
Table 576. DS3_RXPLCPB1ECNT_B[1—12], PLCP B1 Error Count (RO)
Address
Bit
Name
Function
Reset
Default
0x51C0—
0x51CB
15:0
DS3_PLCP_
B1ERRCNT_
B[1—12][15:0]
While the PLCP framer is in the in-frame state, the number
of bit errors between the incoming BIP-8 and the calculated
BIP-8 value is accumulated in a 16-bit saturating counter.
This counter is cleared by the PMRST signal.
0x0000
Table 577. DS3_PLCPFEBECNT_B[1—12], PLCP FEBE (G1[7:4]) Error Count (RO)
Address
Bit
Name
Function
Reset
Default
0x51CC—
0x51D7
15:0
DS3_PLCP_G1_
FEBE_ERRCNT_
B[1—12][15:0]
While the PLCP framer is in the in-frame state, the number
of FEBE errors received (0—8) is accumulated in a 16-bit
saturating counter. Values greater than eight are ignored.
This counter is cleared by the PMRST (pin D7) signal.
0x0000
546
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Transmit Control Signals (Channel Based 1—16)
Table 578. DS3_TDS3PLCPCTL1_CHD[1—16], Transmit PLCP (R/W)
Address
Bit
Name
0x5300—
0x530F
15:14
DS3_TDS3PLCP
[1—16][1:0]
13
12
11
Function
Transmit Mode Control Per Channel.
Reset
Default
00
00 = No mapping.
01 = DS3 locked mode.
10 = DS3 clear channel.
11 = DS3/PLCP mapped signal.
DS3_TPLCP_A2INV Transmit PLCP A2 Byte Invert Control.
[1—16]
1 = Invert all A2 bytes (0xD7) of a PLCP frame.
0 = Send valid A2 byte values (0x28).
DS3_TPLCP_
POIB7INV[1—16]
Transmit PLCP POI Bit 7 Invert Control.
DS3_TPLCP_
B1INV[1—16]
Transmit PLCP B1 Byte Invert Control.
0
0
1 = Invert bit 7 of all POI bytes of a PLCP frame.
0 = Send valid POI B7 bits.
0
1 = Invert B1 byte of a PLCP frame.
0 = Send valid B1 values.
10
DS3_TPLCP_RAI_
SWENB[1—16]
Transmit PLCP RAI Insert. Control bit, when set, forces
the DS3_PLCP_RAI_DINS value to be inserted into the
outgoing G1[3] bit; otherwise, sends the hardware value.
0
9
DS3_TPLCP_RAI_
DINS[1—16]
Transmit PLCP RAI Insert Data Value for All Channels.
This bit when enabled will be inserted into the G1[3] bit.
0
DS3_TPLCP_FEBE_ Transmit PLCP FEBE Insert. Control bit, when set, forces
SWENB[1—16]
the DS3_TLCP_FEBE_DINS[3:0] (Table 581) value to be
inserted into the outgoing G1[7:4] nibble; otherwise, sends
the hardware value.
0
8
7:6
—
5:0
DS3_TXCHID_TO_
TSMAPPING
[1—16][1:0][3:0]
Agere Systems Inc.
Reserved.
This parameter maps time-slot-based received alarms to
channel-based transmit far-end alarms. Valid DS3 block
slice values are [A—B] selected through bits [5:4], where
11 = A and 10 = B; valid time-slot values are 0 to 11 and are
selected through bits [3:0]. Invalid values disable the
mapping and force all error conditions to their inactive
state.
00
0x00
547
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Table 579. DS3_TDS3CTL_CHD[1—16], Transmit DS3 (R/W)
Address
Bit
Name
0x53C0—
0x53CF
15:14
DS3_TDS3_
AIS[1—16],
DS3_TDS3_
IDLE[1—16]
Transmit DS3 Data Type.
13
DS3_TDS3_
FINV[1—16]
Transmit DS3 F-Bit Invert. Control bit, when set, forces an
error in the F-bit sequence (1000); otherwise, insert a valid
sequence (1001) into the F1—F4 framing bits, respectively.
0
12
DS3_TDS3_
MINV[1—16]
Transmit DS3 M-Bit Invert. Control bit, when set, forces
an error in the M-bit sequence (011); otherwise, insert a
valid sequence (010) into the M1—M3 bits, respectively.
0
11
DS3_TDS3_
PINV[1—16]
Transmit DS3 P1-Bit, P2-Bit Control. This bit, when set,
inverts the P1 and P2 bits in the associated DS3 frame.
10
DS3_TDS3_
CPINV[1—16]
Transmit DS3 CP-Bit Control. Control bit, when set, the
computed CP-bit value is inverted (C31 = C32 = C33);
otherwise, insert a valid CP-bit value.
0
9
DS3_TDS3_
FEBEINS[1—16]
Transmit DS3 FEBE Error Insert. Control bit, when set,
forces the FEBE bits (C41 = C42 = C43) to 000
respectively (error condition); otherwise, insert FEBE bits
under hardware control. C41 = C42 = C43 = 1, if no errors
are detected in the received M or F bits or indicated by the
received CP bits; otherwise, set the FEBE bits to 000.
0
8
—
Reserved.
0
7
DS3_TDS3_
XDINS[1—16]
Transmit DS3 X-Bit Control. X-bit value (1 = error-free,
0 = error condition).
0
6
DS3_TDS3_TFEAC_ Transmit DS3 C-Bit Control. Control bit, when set to 0,
INS[1—16]
the C13-bit is set to 1; otherwise, set the C13 bits as a
16-bit repeating sequence in the form of
0x5x4x3_x2x1x00_1111_1111 with the right-most bit sent
first. Bits x5 to x0 are programmable from register
DS3_TFEAC_CODE.
0
5:0
DS3_TDS3_TFEAC_ Value for FEAC Programmable Bits. Bit 5 is transmitted
CODE[1—16][5:0] first.
0
548
Function
Reset
Default
0
00 or 11 = Data engine data.
01 = Idle.
10 = AIS.
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
DS3 Register Descriptions (continued)
Transmit PRBS Control Signals
Table 580. DS3_TXPRBSCTL_[1—2], Transmit PRBS Control (R/W)
Address
Bit
Name
0x53F0—
0x53F1
15:10
—
9
DS3_TPRBS_
1BERRINS[1—2]
8
7
Function
Reserved.
0x00
Error Insert Bit. When a 0-to-1 transition is detected, one
error is injected into the PRBS sequence.
DS3_TPRBS_15or20 Control bit, when set, inserts 220 – 1 QRSS pattern;
[1—2]
otherwise, insert 215 – 1 PRBS pattern.
DS3_TPRBS_INV
[1—2]
Reset
Default
Control bit, when set, inverts the PRBS pattern before
insertion into the DS3 or PLCP frames.
0
0
0
6
DS3_TPRBS_DS3or Control bit, when set, inserts into the PLCP ATM cell
PLCP[1—2]
payload bytes; otherwise, it causes the PRBS pattern to be
inserted into the DS3 frame.
0
5:0
DS3_TPRBS_CHID_ PRBS Channel ID Insert Control Function. Valid values
INS[1—2][5:0]
are 0 to 15; invalid values disable the PRBS insert function.
0x3F
Transmit FEBE Insert Value
Table 581. DS3_TXFEBEDINS, Transmit Blank Request Counter Reset (R/W)
Address
Bit
0x53F2
15
Name
DS3_TBRCNT_RST Control bit, when set, resets internal blank request counter.
14:4
3:0
Function
—
Reserved.
Reset
Default
0
0x000
DS3_TPLCP_FEBE_ Transmit PLCP FEBE Insert Data Value for All
DINS[3:0]
Channels.
0x0
Transmit FIFO Control
Table 582. DS3_TXFIFO, Transmit FIFO Min/Max Thresholds (R/W)
Address
Bit
Name
0x53F3
15
—
Selects TFIFO_OVF_UNFL_SEL alarm.
0
14
—
Reserved.
0
13:8
DS3_TFIFO_MIN
[5:0]
7:6
—
5:0
DS3_TFIFO_MAX
[5:0]
Agere Systems Inc.
Function
Data is not read out of the FIFO until data has accumulated
to at least the lower threshold.
Reserved.
Blank requests are generated for the associated channel
when the FIFO fill has reached or exceeded the max value.
Reset
Default
0x03
00
0x2A
549
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
E3 Register Descriptions
Global Registers
Table 583. DS3E3_VERR, Version Control (RO)
Address
Bit
Name
0x5000
15:8
—
7:0
DS3E3_VER[7:0]
Function
Reset
Default
Reserved.
0x00
Block Version. Indicates version number of this block.
0x00
Table 584. E3_SCRATCHR, Scratch Register (R/W)
Address
Bit
Name
0x5001
15:0
E3_SCRATCH
[15:0]
Function
Reset
Default
Read/write register with no other internal E3 connections.
0x0000
Table 585. E3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for
Delta/Event Registers (R/W)
Address
Bit
Name
Function
Reset
Default
0x5002
15
E3_COR_COWN
Control bit, when set (0) all delta and event registers
function in the clear-on-write (COW) mode; otherwise, they
function in the clear-on-read (COR) mode.
0
14:12
—
11
SEQ_RX
550
Reserved.
Monitor receive output signals (active-high)
E3_TM_DATA
<=
("00000000000000",
E3_RXSYNC,
E3_RXPM_A,
E3_RXEOP_A,
E3_RXPM_B,
E3_RXEOP_B,
E3_RXPM_C,
E3_RXEOP_C,
E3_RXPM_D,
E3_RXEOP_D,
E3_RXDATA_A,
E3_RXDATA_B,
E3_RXDATA_C,
E3_RXDATA_D);
0x0
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Register Descriptions (continued)
Table 585. E3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/
Event Registers (R/W) (continued)
Address
Bit
Name
0x5002
10
TM_RX
Control inputs into the receive direction (active-high)
if (TM_RX = 1) the
PT_RXSYNC_i <= TM_DATA(40);
PT_RXJ1_A_i <= TM_DATA(39);
PT_RXPM_A_i <= TM_DATA(38);
PT_RXJ1_B_i <= TM_DATA(37);
PT_RXPM_B_i <= TM_DATA(36);
PT_RXJ1_C_i <= TM_DATA(35);
PT_RXPM_C_i <= TM_DATA(34);
PT_RXJ1_D_i <= TM_DATA(33);
PT_RXPM_D_i <= TM_DATA(32);
PT_RXDATA_A_i <= TM_DATA(31:24);
PT_RXDATA_B_i <= TM_DATA(23:16);
PT_RXDATA_C_i <= TM_DATA(15:8);
PT_RXDATA_D_i <= TM_DATA(7:0);
else
PT_RXSYNC_i <= PT_RXSYNC;
PT_RXJ1_A_i <= PT_RXJ1_A;
PT_RXPM_A_i <= PT_RXPM_A;
PT_RXDATA_A_i <= PT_RXDATA_A;
PT_RXJ1_B_i <= PT_RXJ1_B;
PT_RXPM_B_i <= PT_RXPM_B;
PT_RXDATA_B_i <= PT_RXDATA_B;
PT_RXJ1_C_i <= PT_RXJ1_C;
PT_RXPM_C_i <= PT_RXPM_C;
PT_RXDATA_C_i <= PT_RXDATA_C;
PT_RXJ1_D_i <= PT_RXJ1_D;
PT_RXPM_D_i <= PT_RXPM_D;
PT_RXDATA_D_i <= PT_RXDATA_D;
end if;
0x0
9
PT_TX
Monitor transmit output signals (active-high)
E3_TM_DATA <= (00,
PT_TXBR,
PT_TXBR_CID,
E3_TXBR,
E3_TXBR_CID,
E3_TXPM,
E3_TXCID,
E3_TXDATA);
0x0
Agere Systems Inc.
Function
Reset
Default
551
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
E3 Register Descriptions (continued)
Table 585. E3_CORW_GPOSEL, Clear-on-Read/Clear-on-Write Global Select for Delta/
Event Registers (R/W) (continued)
Address
Bit
Name
0x5002
8
TM_TX
7:6
—
5:0
GPOSEL[5:0]
552
Function
Reset
Default
Control inputs into the transmit direction (active-high)
E3_TM_DATA
<=
("00000000000000000",
"00000000000000000",
"00000000000000",
E3_TXBR_CID,
E3_TXBR);
if (TM_TX = ’1’) then
DE_TXDATA_i <= TM_DATA(31 0);
DE_TXPM_i
<= TM_DATA(32);
DE_TXDVLD_i <= TM_DATA(33);
DE_TXEOP_i <= TM_DATA(37:34);
DE_TXCID_i <= TM_DATA(43: 38);
else
DE_TXDATA_i <= DE_TXDATA;
DE_TXPM_i
<= DE_TXPM;
DE_TXDVLD_i <= DE_TXDVLD;
DE_TXEOP_i <= DE_TXEOP;
DE_TXCID_i <= DE_TXCID;
end if;
0x0
Reserved.
GPO_ADDRESS can be 0x00 to 0x2B. Configure the
GPO_ADDRESS to this register and this address is passed
to E3_GPO_MUX block to select one of GPO outputs when
it is selected to read.
000000
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Register Descriptions (continued)
Interface A Delta/Event Registers
Table 586. E3FRMD_A, E3 Out-of-Frame Delta (COR/COW)
Address
Bit
Name
0x5003
15:12
—
11:0
E3_OOFD_
A[12—1]
Function
Reserved.
Reset
Default
0x0
Each time the E3_OOFD_A[12—1] state bit changes state
(0 to 1 or 1 to 0), the delta bit is set.
0xFFF
Table 587. E3LOFD_A, E3 Loss-of-Frame Delta (COR/COW)
Address
Bit
Name
0x5004
15:12
—
11:0
E3_LOFD_
A[12—1]
Function
Reserved.
Reset
Default
0x0
Each time the E3_LOFD_A[12—1] state bit changes state
(0 to 1 or 1 to 0), the delta bit is set.
0xFFF
Table 588. E3_TR_MISMATCHD_A, E3 Delta (COR/COW)
Address
Bit
Name
0x5005
15:12
—
11:0
Function
Reserved.
Reset
Default
0x0
E3_TR_MISMATCHD Each time the state bit changes state (0 to 1 or 1 to 0), the
_A[12—1]
delta bit is set.
0xFFF
Table 589. E3AISD_A, E3 AIS Detection Delta (COR/COW)
Address
Bit
Name
0x5006
15:12
—
11:0
E3_AISPAT_
DETD_A[12—1]
Agere Systems Inc.
Function
Reserved.
Each time the E3_AISPAT_DETD_A[12—1] state bit
changes state (0 to 1 or 1 to 0), the delta bit is set.
Reset
Default
0x0
0x000
553
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
E3 Register Descriptions (continued)
Table 590. E3_D_A, E3 Delta (COR/COW)
Address
Bit
Name
0x5007
15:4
—
3:0
E3_PLCP_ZF_
DMON[x]D
Function
Reset
Default
Reserved.
0x0
Each time an associated state value changes, the
composite delta bit is set.
Table 591. E3_MA_SSMD_A, E3 Delta (COR/COW)
Address
Bit
Name
0x5008
15:12
—
11:0
E3_MA_SSMD_
A[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the E3_MA_SSMD_A[12—1] state bit changes
state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Table 592. E3_D_A, E3 Delta (COR/COW)
Address
Bit
Name
0x5009
15:12
—
11:0
E3_G751_RAI_
DETD_A[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the state bit changes state (0 to 1 or 1 to 0), the
delta bit is set.
0x000
E3_G832_MA_RDI_
DETD_A[12—1]
Table 593. E3_MA_PTD_A, E3 Delta (COR/COW)
Address
Bit
Name
0x500A
15:12
—
11:0
E3_MA_PTD_
A[12—1]
554
Function
Reset
Default
Reserved.
0x0
Each time the E3_MA_PTD_A[12—1] state bit changes
state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Register Descriptions (continued)
Table 594. E3_PLCP_LOFD_A, E3 Delta (COR/COW)
Address
Bit
Name
0x500B
15:12
—
11:0
E3_PLCP_LOFD_
A[12—1]
Function
Reserved.
Reset
Default
0x0
Each time the E3_PLCP_LOFD_A[12—1] state bit changes
state (0 to 1 or 1 to 0), the delta bit is set.
0xFFF
Table 595. E3_PLCPOOFD_A, PLCP Out-of-Frame Monitor Delta (COR/COW)
Address
Bit
Name
0x500C
15:12
—
11:0
E3_PLCP_OOFD_
A[12—1]
Function
Reserved.
Reset
Default
0x0
Each time the E3_PLCP_OOFD_A[12—1] state bit
changes state (0 to 1 or 1 to 0), the delta bit is set.
0xFFF
Table 596. E3_PLCPASD_A, PLCP (G1[3]) Monitoring Delta (COR/COW)
Address
Bit
Name
0x500D
15:12
—
11:0
Agere Systems Inc.
Function
Reserved.
E3_PLCP_G1_ASD_ Each time the E3_PLCP_G1_ASD_A[12—1] state bit
A[12—1]
changes state (0 to 1 or 1 to 0), the delta bit is set.
Reset
Default
0x0
0x000
555
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
Data Sheet
August 18, 2004
DS3/E3 Block (continued)
E3 Register Descriptions (continued)
Interface B Delta/Event Registers
Table 597. E3FRMD_B, E3 Out-of-Frame Delta (COR/COW)
Address
Bit
Name
0x500F
15:12
—
11:0
E3_OOFD_
B[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the E3_OOFD_B[12—1] state bit changes state
(0 to 1 or 1 to 0), the delta bit is set.
0xFFF
Table 598. E3LOFD_B, E3 Loss-of-Frame Delta (COR/COW)
Address
Bit
Name
0x5010
15:12
—
11:0
E3_LOFD_
B[12—1]
Function
Reset
Default
Reserved.
0x0
Each time the E3_LOFD_B[12—1] state bit changes state
(0 to 1 or 1 to 0), the delta bit is set.
0xFFF
Table 599. E3_TR_MISMATCHD_B, E3 Delta (COR/COW)
Address
Bit
Name
0x5011
15:12
—
11:0
Function
Reset
Default
Reserved.
0x0
E3_TR_MISMATCHD Each time the state bit changes state (0 to 1 or 1 to 0), the
_B[12—1]
delta bit is set.
0xFFF
Table 600. E3AISD_B, E3 AIS Detection Delta (COR/COW)
Address
Bit
Name
0x5012
15:12
—
11:0
E3_AISPAT_
DETD_B[12—1]
556
Function
Reset
Default
Reserved.
0x0
Each time the E3_AISPAT_DETD_B[12—1] state bit
changes state (0 to 1 or 1 to 0), the delta bit is set.
0x000
Agere Systems Inc.
Data Sheet
August 18, 2004
MARS2G5 P-Pro (TDAT162G52) SONET/SDH
155/622/2488 Mbits/s Data Interface
DS3/E3 Block (continued)
E3 Register Descriptions (continued)
Table 601. E3_D_B, E3 Delta (COR/COW)
Address
Bit
Name
0x5013
15:4
—
3:0
E3_PLCP_ZF_
DMOND[A—B]
Function
Reserved.
Reset
Default
0x000
Each time an associated state value changes, the
composite delta bit is set.
Table 602. E3_MA_SSMD_B, E3 Delta (COR/COW)
Address
Bit
Name
0x5014