TEA6422 BUS-CONTROLLED AUDIO MATRIX ■ ■ ■ ■ ■ ■ ■ ■ ■ 6 Stereo Inputs 3 Stereo Ouputs Gain Control 0 dB/Mute for each Output Cascadable (2 different addresses) Serial Bus Controlled Very Low Noise Very Low Distorsion Fully ESD Protected Wide Audio Dynamic Range ( 3 VRMS) SHRINK DIP24 (Shrink Plastic Package) ORDER CODE: TEA6422 DESCRIPTION The TEA6422 switches 6 stereo audio inputs on 3 stereo outputs. All the switching possibilities are changed through the I2C BUS. SO28 (Plastic Monopackage) ORDER CODE: TEA6422D Figure 1. PIN CONNECTIONS SO28 SDIP24 GND 1 28 SDA GND 1 24 SDA CAPACITANCE 2 27 SCL CAPACITANCE 2 23 SCL VS 3 26 ADDR VS 3 22 ADDR L1 4 25 R1 L1 4 21 R1 L2 5 24 R2 L2 5 20 R2 L3 6 23 R3 L3 6 19 R3 NC 7 22 NC L4 7 18 R4 NC 8 21 NC L5 8 17 R5 L4 9 20 R4 L6 9 16 R6 L5 10 19 R5 LOUT1 10 15 ROUT3 L6 11 18 R6 ROUT1 11 14 LOUT3 LOUT1 12 17 ROUT3 LOUT2 12 13 ROUT2 ROUT1 13 16 LOUT3 LOUT2 14 15 ROUT2 September 2003 1/10 1 TEA6422 BLOCK DIAGRAM RIGHT INPUTS GAIN = 0 dB RIGHT OUTPUTS VS SDA BUS DECODER SUPPLY C SCL GND ADDR LEFT OUTPUTS GAIN = 0 dB LEFT INPUTS ABSOLUTE MAXIMUM RATINGS Symbol VCC Toper Tstg Parameter Value 12 0, + 70 - 20, + 150 Parameter Value 75 75 Supply Voltage Operating Temperature Storage Temperature Unit V oC oC THERMAL DATA Symbol Rth(j-a) 2/10 1 Junction - ambient Thermal Resistance SDIP24 SO28 Unit C/W oC/W o TEA6422 ELECTRICAL CHARACTERISTICS TA = 25 oC, VS = 9 V, RL = 10 kΩ, RG = 600 Ω, f = 1 kHz (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. 8 10 11 3 8 Unit SUPPLY VS Supply Voltage IS Supply Current SVR Ripple Rejection VIN = 500mVRMS, f = 1kHz 70 80 V mA dB MATRIX VIN Input DC Level RI Input Resistance CS Channel Separation VCC/2 VIN = 2VRMS, f = 1kHz 30 50 80 90 V 100 kΩ dB OUTPUT BUFFER VOUT Output DC Level ROUT Output Resistance VCC/2 50 V 100 Ω eNI Input Noise BW = 20 - 20kHz, flat 3 µV S/N Signal to Noise Ratio VIN = VOUT = 1VRMS 110 dB G Gain d Distortion VIN = VOUT = 1VRMS -1 VCL Clipping Level d = 0.3 %, VS = 10 V RL Output Load Resistance 2.8 2 0 +1 dB 0.01 0.05 % 3 VRMS kΩ 3/10 1 TEA6422 I2C BUS CHARACTERISTICS Symbol Test Conditions Parameter Min. Max. Unit - 0.3 3.0 - 10 0 + 1.5 VCC + 0.5 + 10 100 1000 300 10 V V µA kHz ns ns pF - 0.3 3.0 - 10 + 1.5 VCC + 0.5 + 10 10 1000 300 0.4 250 400 V V µA pF ns ns V ns pF 340 µs µs ns ns µs µs µs SCL VIL VIH ILI fSCL tR tF CI Low Level Input Voltage High Level Input Voltage Input Leakage Current Clock Frequency Input Rise Time Input Fall Time Input Capacitance VI = 0 to VCC 1.5V to 3V 3V to 1.5V SDA VIL VIH ILI CI tR tF VOL tF CL TIMING tLOW tHIGH tSU, DAT tHD, DAT tSU, STO tBUF tHD, STA tSU, STA Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Capacitance Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time Load Capacitance VI = 0 to VCC 1.5V to 3V 3V to 1.5V IOL = 3mA 3V to 1.5V Clock Low Period Clock High Period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low-to High Transition 4.7 4.0 250 0 4.0 4.7 4.0 4.7 µs Figure 2. I²C Bus Timing SDA t BUF t LOW tf SCL t HD,STA tr t HD,DAT t HIGH t SU,DAT SDA (start, stop) 4/10 1 t SU,STA t SU,STO TEA6422 POWER ON RESET After power-on reset all outputs are in mute mode Symbol Parameter Start of Reset Conditions Incr. VCC Decr. VCC Incr. VCC Reset End of Reset Min. Typ. Max. 2.5 4.2 4.5 Unit V V V SOFTWARE SPECIFICATION 1. Chip address Address HEX 98 9A 1001 1000 1001 1010 ADDR 0 1 2. Data bytes Output select X 0 0 1 0 1 0 X X I2 I1 I0 Output 1 Output 2 Output 3 X 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Mute Input select X Q1 Q0 X X = don’t care - MSB is transmitted first Example : 010XX100 connects output 3 with input 5. 5/10 1 TEA6422 Figure 3. Distorsion Level versus Input Voltage dis (%) 3.5 0.1 0.08 Figure 5. Clipping Level versus Supply Voltage V S = 10 V f = 1 kHz T amb = 25 °C 3.3 3.1 Vclipp ( VRMS ) dis = 0.3% f = 1 kHz Tamb = 25 °C 2.9 0.06 2.7 0.04 2.5 2.3 VIN (V RMS ) 0.02 0 2.4 2.5 2.6 2.7 2.8 2.9 3.0 Figure 4. Supply Voltage Rejection versus Frequency ( VIN = 500 mVRMS) SVR (dB) 98 V S = 10 V 95 92 89 86 83 80 77 74 0.05 6/10 1 freq (kHz) 0.5 5 20 2.1 7.5 VS (V) 8 8.5 9 9.5 10 10.5 11 TEA6422 PIN CONFIGURATIONS (SDIP24 Package) Figure 6. Audio IN Figure 8. Audio OUT VCC VC C Pins 10- 11-12 13-14-15 50kΩ Pins 4-5-6-7-8-9 16-17-18-19-20- 21 L (R) x in x = 1, 2, 3, 4, 5, 6 V C C /2 L (R) x out x = 1, 2, 3 Matrix Point Figure 9. Bus Inputs (SDA, SCL) Figure 7. ADDR VCC VCC 50kΩ ESD PROT. 22 Pins 23 - 24 to CMOS VREF to CMOS X4 ACKN For SDA only Figure 10. TYPICAL APPLICATION (SDIP24 Package) 22 µ F 1 24 SDA 2 23 SCL 3 22 Bus Inputs +10V 100nF C1 C2 C3 Left C4 Inputs C5 C11 C H 1 Output L R C H 2 Output L C12 C13 C14 SW T 4 5 6 7 E A 6 4 8 21 20 19 18 17 2 9 10 16 2 15 11 14 12 13 C6 C7 C8 Right C9 Inputs C10 C18 C17 R C16 C15 C H 3 Output L R C H 2 Output 7/10 TEA6422 PACKAGE MECHANICAL DATA 24 PINS - PLASTIC SHRINK Figure 11. 24-Pin Shrink Plastic Dual In Line Package Dim. E E1 mm Min inches Typ Max B1 A2 A2 3.05 3.30 4.57 0.120 0.130 0.180 B 0.36 0.46 0.56 e1 B1 0.76 1.02 1.14 0.030 0.040 0.045 e2 C 0.23 0.25 0.38 D 22.61 22.86 23.11 0.890 0.90 0.910 E 7.62 E1 6.10 c D E 13 .015 F 24 0,38 Gage Plane 1 12 e3 SDIP24 8.64 0.014 0.018 0.022 2 1 0 0.009 0.009 0.015 0 8 0 0.30 0.340 6.40 6.86 0.240 0.252 0.270 e 1.778 e1 7.62 0.070 0.30 e2 10.92 0.430 e3 1.52 0.060 Number of Pins e2 N 8/10 0.20 0.020 A e Max 0.51 Stand-off B Typ 5.08 A1 L A1 A Min 24 TEA6422 PACKAGE MECHANICAL DATA 28 PINS - PLASTIC MICROPACKAGE Figure 12. 28-Pin Plastic Small Outline Package, 300-mil Width Dim. mm Min Typ inches Max Min Typ Max A 2.35 2.65 0.0926 0.1043 A1 0.10 0.30 0.0040 0.0118 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.0091 0.0125 D 17.70 18.10 0.6969 0.7125 E 7.40 7.60 0.2914 e 1.27 0.2992 0.0500 H 10.01 10.64 0.394 0.419 h 0.25 0.74 0.010 0.029 K L G SO28 0° 0.41 8° 1.27 0.016 0.050 0.10 0.004 Number of Pins N 28 9/10 TEA6422 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. 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