STMICROELECTRONICS TDA7311

TDA7311

SERIAL BUS CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
– TWO STEREO DIFFERENTIAL INPUTS
– TWO STEREO SINGLE ENDED INPUTS
– ONE MONO DIFFERENTIAL INPUT
INPUT AND OUTPUT FOR EXTERNAL
EQUALIZER OR NOISE REDUCTION SYSTEM
VOLUME CONTROL IN 1.25dB STEPS
TREBLE AND BASS CONTROL
FOUR SPEAKER ATTENUATORS:
– 4 INDEPENDENT SPEAKERS CONTROL
IN 1.25dB STEPS FOR BALANCE AND
FADER FACILITIES
– INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SPI
COMPATIBLE SERIAL BUS
DESCRIPTION
The TDA7311 is a volume, tone (bass and treble)
and fader (front/rear) processor for high quality
audio applications in car radio and Hi-Fi systems.
DIP40
ORDERING NUMBER: TDA7311
Control is accomplished by serial bus microprocessor interface.
The AC signal setting is obtained by resistor networks and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS technology,
low distortion, low noise and DC stepping are obtained.
PINS CONNECTION (Top view)
July 1999
1/11
TDA7311
TEST CIRCUIT
THERMAL DATA
Symbol
R th j-pins
Description
Thermal Resistance Junction-pins
DIP40
Unit
85
°C/W
max
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VS
Operating Supply Voltage
Top
Operating Temperature Range
Tstg
Storage Temperature Range
Value
Unit
11.2
V
-40 to 85
°C
-55 to +150
°C
QUICK REFERENCE DATA
Symbol
Parameter
VS
Supply Voltage
VCL
Max. input signal handling
Min.
Typ.
Max.
8
10
11
2.3
Unit
V
Vrms
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
%
S/N
Signal to Noise Ratio
106
dB
SC
Channel Separation f = 1KHz
Volume Control
Treble Control
BR SS
1.25dB step
2dB step
Bass Control 2dB step
Fader and Balance Control
Mute Attenuation
2/11
1.25dB step
95
dB
-78.75
+11.25
dB
-14
+14
dB
–20
+20
dB
-38.75
0
92
dB
dB
RIGHT
INPUTS
LEFT
INPUTS
IN4
IN3
DIFF
STEREO 1
DIFF
STEREO 2
DIFF MONO
DIFF
STEREO 2
DIFF
STEREO 1
IN3
IN4
D94AU178
32
33
36
37
35
34
3
38
6
7
5
4
8
9
SECMUTE
SECMUTE
31
10
30
11
VOL
VOL
29
12
TREBLE
14
BASS
28
27
TREBLE
1
VCC
SPI BUS DECODER + LATCHES
BASS
13
AN-GND
40
SUPPLY
MUTE
SPKR
ATT
2
CREF
MUTE
SPKR
ATT
MUTE
SPKR
ATT
MUTE
SPKR
ATT
25
26
21
18
19
20
16
15
OUT
RIGHT REAR
OUT
RIGHT FRONT
DIG GND
CE
DA
CL
OUT
LEFT REAR
OUT
LEFT FRONT
TDA7311
BLOCK DIAGRAM
3/11
TDA7311
ELECTRICAL CHARACTERISTICS (Tamb = 25°C, VCC = 10V, RL = 10KΩ, RG = 600Ω, GV=0dB,
f = 1KHz unless otherwise specified) (refer to the test circuit)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
VS
Supply Voltage
IS
Supply Current
SVR
8
Ripple Rejection
55
10
11
V
15
20
mA
80
dB
INPUT SELECTORS
R II
V CL
CMRR
Input Resistance
Clipping Level
Common Mode Rejection
Single Ended inputs
30
50
Differential Inputs
10
20
KΩ
Single Ended Inputs
2.3
2.8
Vrms
Differential Inputs
4.6
5.6
Vrms
65
dB
Differential Inputs
INS
Input Separation (2)
70
RL
Output Load resistance
2
CL
Output Load capacitance
RO
Output Impedance
GIN
Input Gain
70
90
KΩ
dB
KΩ
1
nF
15
50
Ω
Single Ended Inputs
-1
0
1
dB
differential Inputs
-7
-6
-5
dB
15
30
VOLUME CONTROL
R IN
Input Resistance
GR
Control Range
Max. Attenuation
Max. Gain
ASTEP
Step Resolution
EA
Attenuation Set Error
ET
Tracking Error
VDC
DC Steps
Vimax.
kΩ
– 75
dB
+11.25
dB
1.25
AV = +11.25 to -20dB
AV = -20 to -60dB
-1.25
-3
adjacent attenuation steps
From 0dB to AVmax
Max. Input Voltage
2.3
dB
0
1.25
2
dB
dB
2
dB
0
1
3.0
10.0
mV
mV
2.8
Vrms
Control Range
37.5
dB
Step Resolution
1.25
SPEAKER ATTENUATORS
AR
Astep
EA
Attenuation set error
VDC
DC Steps
dB
1.5
adjacent att. steps
from 0 to mute
dB
0
1
mV
mV
+20
dB
BASS CONTROL (1)
Control Range
Step Resolution
Attenuation / Gain set error
2
–2.0
dB
2.0
dB
TREBLE CONTROL (1)
Control Range
+14
dB
Step Resolution
2.0
dB
Attenuation / Gain set error
4/11
–1.0
0
1.0
dB
TDA7311
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
2.3
2.8
Max.
Unit
AUDIO OUTPUTS
Output Voltage
d = 0.3%
Output Load Resistance
Vrms
2
KΩ
Output Load Capacitance
10
nF
25
75
Ω
5.0
5.4
V
BW = 20-20KHz, flat
output muted
all gains = 0dB Single Ended
all gains = 0dB Diff. Inputs
4
5
10
15
30
µV
µV
µV
all gains = 0dB; VO = 1Vrms
Single Ended
Differential Inputs
106
100
dB
dB
VIN = 1Vrms
0.01
%
Output resistance
DC Voltage Level
4.6
GENERAL
e NO
S/N
d
Sc
Output Noise
Signal to Noise Ratio
Distortion
Channel Separation left/right
70
Total Tracking error
AV = 0 to -20dB
AV = -20 to -60 dB
AV = 0dB to 11.25dB
Output Attenuation
Mute Condition (3)
95
0
0
0
80
dB
1
2
1
90
dB
dB
dB
dB
BUS INPUTS
V IL
Input Low Voltage
VIH
Input High Voltage
1
3
V
V
Notes:
(1) Bass and Treble response see attached diagram (fig.17). The center frequency and quality of the resonance behaviour can be choosen by
the external circuitry. A standard first order bass response can be realized by a standard feedback network
(2) The selected input is grounded thru the 2.2µF capacitor.
(3) Condition obtained programming: mute on speaker attenuators (1X111111) followed by selection of SECMUTE (1XXXX111).
5/11
TDA7311
APPLICATION INFORMATION
SERIAL BUS INTERFACE
The serial bus interface is compatible to SPI bus
systems.
During the LOW state of the chip enable signal
(CE) the data on pin DA are clocked into the shift
register at the LOW to HIGH transition of the
clock signal CL.
At the LOW to HIGH transition of the CE signal
the content of the internal shift register is stored
into the addressed latches.
The transmission is separated into bytes with 8 bit
according to the data specification of the audioprocessor. After every byte a positive slope of the
CE signal has to be generated in order to store
the data byte.
A special clock counter enables the latch of the
data byte only, if exactly 8 clocks were present
during the LOW state of the CE signal. This results in a high immunity against spikes on the
clock line and avoids a storage of wrong databytes.
Figure 1: BUS Timing
Nr.
Parameter
Min.
Clock Frequency
6/11
Max.
Units
250
KHz
1
CE Lead time
4
µs
2
Clock High Time
2
µs
3
Clock Low Time
2
µs
4
Data Hold Time
1.8
µs
5
Data Setup Time
1.8
µs
µs
6
Clock Setup Time
0
7
CE lagtime
0
µs
8
Clock Hold Time
6
µs
9
CE High TIme
6
µs
TDA7311
STATUS AFTER POWER-ON RESET
Volume
–78.75dB
Speaker
Mute
Audio Switch
Mute
Bass
–20dB
Treble
–14dB
SOFTWARE SPECIFICATION
Data Bytes
FIRST BYTE
MSB
LSB
Function
0
0
0
0
X
X
X
X
VOL ATTENUATION
0
1
0
0
X
X
X
X
VOL GAIN
0
0
1
0
X
X
X
X
BASS
0
1
1
0
X
X
X
X
TREBLE
0
0
0
1
X
X
X
X
ATT RF (speaker)
0
1
0
1
X
X
X
X
ATT RR (speaker)
0
0
1
1
X
X
X
X
ATT LF (speaker)
0
1
1
1
0
X
X
X
ATT LR (speaker)
0
1
1
1
1
X
X
X
AUDIO SWITCH
SECOND BYTE
VOLUME ATTENUATION
MSB
1
1
X
X
LSB
B2
B1
B0
B2
B1
B0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Volume 1.25dB Steps
0
-1.25
-2.5
-3.75
-5.00
-6.25
-7.50
-8.75
Volume 10dB Steps
0
-10
-20
-30
-40
-50
-60
-70
7/11
TDA7311
SOFTWARE SPECIFICATION (continued)
VOLUME GAIN
MSB
LSB
1.25dB STEPS
1
X
X
X
0
0
0
0
0.00
1
X
X
X
0
0
0
1
1.25
1
X
X
X
0
0
1
0
2.50
1
X
X
X
0
0
1
1
3.75
1
X
X
X
0
1
0
0
5.00
1
X
X
X
0
1
0
1
6.25
1
X
X
X
0
1
1
0
7.50
1
X
X
X
0
1
1
1
8.75
1
X
X
X
1
0
0
0
10.00
1
X
X
X
1
0
0
1
11.25
LSB
1.25dB STEPS
1
0
0
0
0
1
0
0
1
-1.25
1
0
1
0
-2.50
1
0
1
1
-3.75
1
1
0
0
-5.00
1
1
0
1
-6.25
1
1
1
0
-7.50
1
1
1
1
-8.75
SPEAKER ATTENUATION
MSB
10dB STEPS
1
X
0
0
0
0
1
X
0
0
1
-10
1
X
0
1
0
-20
1
X
0
1
1
1
X
1
1
1
-30
1
1
1
MUTE
AUDIO SWITCH
MSB
8/11
LSB
INPUT
1
X
X
X
X
0
0
0
MONO
1
X
X
X
X
0
0
1
DIFF1
1
X
X
X
X
0
1
0
DIFF2
1
X
X
X
X
0
1
1
IN3
1
X
X
X
X
1
0
0
IN4
1
X
X
X
X
1
1
1
SECMUTE
TDA7311
SOFTWARE SPECIFICATION (continued)
TREBLE
MSB
LSB
2dB STEPS
1
X
X
X
0
1
1
1
14
1
X
X
X
0
1
1
0
12
1
X
X
X
0
1
0
1
10
1
X
X
X
0
1
0
0
8
1
X
X
X
0
0
1
1
6
1
X
X
X
0
0
1
0
4
1
X
X
X
0
0
0
1
2
1
X
X
X
0
0
0
0
0
1
X
X
X
1
0
0
0
-0
1
X
X
X
1
0
0
1
-2
1
X
X
X
1
0
1
0
-4
1
X
X
X
1
0
1
1
-6
1
X
X
X
1
1
0
0
-8
1
X
X
X
1
1
0
1
-10
1
X
X
X
1
1
1
0
-12
1
X
X
X
1
1
1
1
-14
LSB
2dB STEPS
1
X
X
1
1
1
1
1
-20
1
X
X
1
1
0
0
1
-18
1
X
X
1
1
0
0
0
-16
1
X
X
1
0
1
1
1
-14
1
X
X
1
0
1
1
0
-12
1
X
X
1
0
1
0
1
-10
1
X
X
1
0
1
0
0
-8
1
X
X
1
0
0
1
1
-6
1
X
X
1
0
0
1
0
-4
1
X
X
1
0
0
0
1
-2
1
X
X
1
0
0
0
0
0
1
X
X
0
0
0
0
0
0
1
X
X
0
0
0
0
1
2
1
X
X
0
0
0
1
0
4
1
X
X
0
0
0
1
1
6
1
X
X
0
0
1
0
0
8
1
X
X
0
0
1
0
1
10
1
X
X
0
0
1
1
0
12
1
X
X
0
0
1
1
1
14
1
X
X
0
1
0
0
0
16
1
X
X
0
1
0
0
1
18
1
X
X
0
1
1
1
1
20
BASS
MSB
9/11
TDA7311
mm
DIM.
MIN
TYP
inch
MAX
MIN
TYP
a1
0.63
0.025
b
0.45
0.018
b1
0.23
b2
0.31
1.27
D
E
0.009
0.012
0.050
52.58
15.2
16.68
2.070
0.598
0.657
e
2.54
0.100
e3
48.26
1.900
F
MAX
OUTLINE AND
MECHANICAL DATA
14.1
0.555
I
4.445
0.175
L
3.3
0.130
DIP40
10/11
TDA7311
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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11/11