THine THC63LVD104A Rev.1.0 THC63LVD104A 90MHz 30Bits COLOR LVDS Receiver General Description Features The THC63LVD104A receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to WXGA resolutions. The THC63LVD104A converts the LVDS data streams back into 35bits of CMOS/TTL data with rising edge or falling edge clock for convenient with a variety of LCD panel controllers.At a transmit clock frequency of 90MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC,VSYNC,DE,CNTL1,CNTL2) are transmitted at an effective rate of 630Mbps per LVDS channel.Using a 90MHz clock, the data throughput is 394Mbytes per second. • Wide dot clock range: 8-90MHz suited for NTSC, VGA, SVGA, XGA, and WXGA • • • • • • • PLL requires no external components 50% output clock duty cycle TTL clock edge programmable Power down mode Low power single 3.3V CMOS design 64pin TQFP Backward compatible with THC63LVDF64x (18bits) / F84x(24bits) Block Diagram LVDS INPUT CMOS/TTL OUTPUT RB+/RC+/RD+/- SERIAL TO PARALLEL RA+/- RE+/RCLK+/- PLL 7 RA6-RA0 7 RB6-RB0 7 RC6-RC0 7 RD6-RD0 7 RE6-RE0 CLKOUT (8 to90MHz) CMOS/TTL INPUT TEST PD OE R/F Copyright 2003 THine Electronics, Inc. All rights reserved 1 THine Electronics, Inc. THine THC63LVD104A Rev.1.0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC RA0 RA1 RA2 GND RA3 RA4 RA5 RA6 RB0 RB1 VCC RB2 RB3 RB4 RB5 Pin Out 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RB6 CLKOUT GND RC0 RC1 RC2 RC3 RC4 RC5 VCC RC6 RD0 RD1 RD2 RD3 RD4 GND TEST PD OE R/F RE6 RE5 RE4 VCC RE3 RE2 RE1 RE0 RD6 RD5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RARA+ RBRB+ LVCC RCRC+ RCLKRCLK+ LGND RDRD+ RERE+ PGND PVCC Copyright 2003 THine Electronics, Inc. All rights reserved 2 THine Electronics, Inc. THine THC63LVD104A Rev.1.0 Pin Description Pin Name Pin # Type Description RA+, RA- 50, 49 LVDS IN RB+, RB- 52, 51 LVDS IN RC+, RC- 55, 54 LVDS IN RD+, RD- 60, 59 LVDS IN RE+,RE- 62, 61 LVDS IN RCLK+, RCLK- 57, 56 LVDS IN RA6 ~ RA0 40,41,42,43,45,46,47 OUT RB6 ~ RB0 32,33,34,35,36,38,39 OUT RC6 ~ RC0 22,24,25,26,27,28,29 OUT RD6 ~ RD0 14,15,17,18,19,20,21 OUT RE6 ~ RE0 6,7,8,10,11,12,13 OUT TEST 2 IN PD 3 IN OE 4 IN R/F 5 IN VCC 9,23,37,48 Power CLKOUT 31 OUT LVDS Data In. LVDS Clock In. CMOS/TTL Data Outputs. Test pin, must be “L” for normal operation. H: Normal operation, L: Power down (all outputs are “L”) H:Output enable (Normal operation). L:Output disable(all outputs are Hi-Z) Output Clock Triggering Edge Select. H: Rising edge, L: Falling edge Power Supply Pins for TTL outputs and digital circuitry. Clock out. GND 1,16,30,44 Ground Ground Pins for TTL outputs and digital circuitry. LVCC 53 Power Power Supply Pin for LVDS inputs. LGND 58 Ground Ground Pin for LVDS inputs. PVCC 64 Power Power Supply Pin for PLL circuitry. PGND 63 Ground Ground Pin for PLL circuitry. Data Outputs CLKOUT PD R/F OE 0 0 0 Hi-Z Hi-Z 0 0 1 All 0 Fixed Low 0 1 0 Hi-Z Hi-Z 0 1 1 All 0 Fixed Low 1 0 0 Hi-Z Hi-Z 1 0 1 Data Out It latches output data on falling edge. 1 1 0 Hi-Z Hi-Z 1 1 1 Data Out It latches output data on rising edge. (Rxn) ** Rxn x = A,B,C,D,E n = 0,1,2,3,4,5,6 Copyright 2003 THine Electronics, Inc. All rights reserved 3 THine Electronics, Inc. THine THC63LVD104A Rev.1.0 Absolute Maximum Ratings 1 Supply Voltage (VCC) -0.3V ~ +4.0V CMOS/TTL Input Voltage -0.3V ~ (V CC + 0.3V) CMOS/TTL Output Voltage -0.3V ~ (V CC + 0.3V) LVDS Receiver Input Voltage -0.3V ~ (V CC + 0.3V) Output Current -30mA ~ 30mA Junction Temperature +125 °C Storage Temperature Range -55 °C ~ +125 °C Resistance to soldering heat +260 °C /10sec Maximum Power Dissipation @+25 °C 1.0W Electrical Characteristics CMOS/TTL DC Specifications VCC = 3.0V ~ 3.6V, Ta = 0 °C ~ +70 °C Symbol Parameter Conditions Min. Typ. Max. Units VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VOH High Level Output Voltage VOL Low Level Output Voltage IINC Input Current IOH= -4mA (data) IOH= -8mA (clock) 2.4 V IOL= 4mA (data) IOL= 8mA (clock) 0V ≤ V IN ≤ V CC 0.4 V ± 10 µA LVDS Receiver DC Specifications VCC = 3.0V ~ 3.6V, Ta = 0 °C ~ +70 °C Symbol Parameter Conditions VTH Differential Input High Threshold VOC= 1.2V VTL Differential Input Low Threshold VOC= 1.2V IINL Input Current VIN= 2.4V / 0V VCC= 3.6V Min. Typ. Max. 100 -100 Units mV mV ± 20 µA 1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Copyright 2003 THine Electronics, Inc. All rights reserved 4 THine Electronics, Inc. THine THC63LVD104A Rev.1.0 Supply Current VCC = 3.0V ~ 3.6V, Ta = 0 °C ~ +70 °C Symbol Parameter Conditions Receiver Supply IRCCG Current fCLKOUT = 90MHz (Gray Scale Pattern) Receiver Supply IRCCW Current fCLKOUT = 90MHz (Checker Pattern) IRCCS Receiver Power Down Supply Current PD = L Copyright 2003 THine Electronics, Inc. All rights reserved CL=8pF, Vcc=3.3V CL=8pF, Vcc=3.3V Typ. Max. 70 mA 112 mA 10 5 Units µA THine Electronics, Inc. THine THC63LVD104A Rev.1.0 Incremental Pattern(Gray Scale) CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 x=A,B,C,D,E Toggle Pattern(Checker) CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 x=A,B,C,D,E Copyright 2003 THine Electronics, Inc. All rights reserved 6 THine Electronics, Inc. THine THC63LVD104A Rev.1.0 Switching Characteristics VCC = 3.0V ~ 3.6V, Ta = 0 °C ~ +70 °C Symbol Parameter Min. Typ. Max. T Units tRCP CLKOUT Period tRCH CLKOUT High Time T–1 -----------2 ns tRCL CLKOUT Low Time T–1 -----------2 ns tRS TTL Data Setup to CLKOUT tRH TTL Data Hold from CLKOUT tTLH TTL Low to High Transition Time 1.0 2.0 ns tTHL TTL High to Low Transition Time 1.0 2.0 ns tRIP1 Input Data Position0 -0.25 0.0 +0.25 ns tRIP0 Input Data Position1 t RCIP ------------ – 0.25 7 t RCIP ------------7 tRCIP ------------ + 0.25 7 ns tRIP6 Input Data Position2 t RCIP 2 ------------ – 0.25 7 t RCIP 2 -----------7 t RCIP 2 ------------ + 0.25 7 ns tRIP5 Input Data Position3 t RCIP 3 ------------ – 0.25 7 t RCIP 3 -----------7 t RCIP 3 ------------ + 0.25 7 ns tRIP4 Input Data Position4 t RCIP 4 ------------ – 0.25 7 t RCIP 4 -----------7 t RCIP 4 ------------ + 0.25 7 ns tRIP3 Input Data Position5 t RCIP - – 0.25 5 -----------7 t RCIP 5 -----------7 t RCIP 5 ------------ + 0.25 7 ns tRIP2 Input Data Position6 t RCIP 6 ------------ – 0.25 7 t RCIP 6 -----------7 t RCIP 6 ------------ + 0.25 7 ns tRPLL Phase Lock Loop Set 10.0 ms tRCIP CLKIN Period 125.0 ns 11.1 125.0 tRCP - 7.0 ns ns 1.0 ns 11.1 AC Timing Diagrams TTL Outputs TTL Output 80% 80% CL=8pF 20% 20% TTL Output Load tTLH Copyright 2003 THine Electronics, Inc. All rights reserved 7 tTHL THine Electronics, Inc. THine THC63LVD104A Rev.1.0 AC Timing Diagrams TTL Outputs tRCH tRCL R/F = L CLKOUT 2.0V 2.0V 2.0V 0.8V 0.8V R/F = H tRCP tRS Rxn tRH 2.0V 2.0V 0.8V 0.8V x = A,B,C,D,E n = 0,1,2,3,4,5,6 Phase Lock Loop Set Time VCC 3.0V RCLK+/- 2.0V PD tRPLL 2.0V CLKOUT Copyright 2003 THine Electronics, Inc. All rights reserved 8 THine Electronics, Inc. THine THC63LVD104A Rev.1.0 Power Up Sequence Power Up Sequence must be Sequence1 or Sequence2. 1)Sequence1 VCC PVCC LVCC VCC/2 Min 100usec PD VCC/2 Recommended PD Pin Circuit VCC 100kohm PD Pin 0.1uF 2)Sequence2 VCC PVCC LVCC VCC 3.0V GND VCC PD GND GND PD pin must be High after VCC voltage is 3.0V. Copyright 2003 THine Electronics, Inc. All rights reserved 9 THine Electronics, Inc. THine THC63LVD104A Rev.1.0 AC Timing Diagrams LVDS Inputs tRIP2 tRIP3 tRIP4 tRIP5 tRIP6 tRIP0 tRIP1 Rx+/- Rx6 Rx5 Rx4 Rx3 RCLK+ Rx2 Rx1 Rx6 Rx5 Vdiff = 0V Rx4 Rx3 Rx2 Rx1 Vdiff = 0V tRCIP x = A,B,C,D,E Copyright 2003 THine Electronics, Inc. All rights reserved Rx0 10 THine Electronics, Inc. THine THC63LVD104A Rev.1.0 AC Timing Diagrams LVDS Inputs Vdiff = 0V Vdiff = 0V RCLK+ (Differential) RA+/- RA3’ RA2’ RA1’ RA0’ RA6 RA5 RA4 RA3 RA2 RA1 RA0 RA6’’ RB+/- RB3’ RB2’ RB1’ RB0’ RB6 RB5 RB4 RB3 RB2 RB1 RB0 RB6’’ RC+/- RC3’ RC2’ RC1’ RC0’ RC6 RC5 RC4 RC3 RC2 RC1 RC0 RC6’’ RD+/- RD3’ RD2’ RD1’ RD0’ RD6 RD5 RD4 RD3 RD2 RD1 RD0 RD6’’ RE+/- RE3’ RE6 RE5 RE4 RE3 RE2 RE1 RE0 RE2’ RE1’ RE0’ Previous Cycle Current Cycle RE6’’ Next Cycle tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 Copyright 2003 THine Electronics, Inc. All rights reserved 11 THine Electronics, Inc. THine THC63LVD104A Rev.1.0 Package INDEX ∆ 64 49 PIN No.1 33 16 32 1.2MAX 17 1.00TYP 12.0TYP 0.22 10.0TYP 0.5TYP 48 UNITS: mm Copyright 2003 THine Electronics, Inc. All rights reserved 12 THine Electronics, Inc. THine THC63LVD104A Rev.1.0 Notes to Users: 1. The contents of this data sheet are subject to change without prior notice. 2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention when designing circuits. EVEN IF THERE ARE INCORRECT DESCRIPTIONS, THINE IS NOT RESPOSIBLE FOR ANY PROBLEM DUE TO THEM. Please note that incorrect descriptions sometimes cannot be corrected immediately if found. 3. THine’s copyright, know-how and other intellectual property rights are included in this data sheet. Duplication of the data sheet and disclosure to other persons are strictly prohibited without THine’s prior written permission. 4. THINE IS NOT RESPONSIBLE FOR ANY PROBLEMS OF INTELLECTUAL PROPERTY RIGHTS OCCURRING DURING THC63LVD104A USE, EXCEPT FOR DAMAGES RESULTING FROM INFRINGEMENT CAUSED ONLY BY THC63LVD104A WITHOUT ANY ITEM NOT SOLD BY THINE AND/OR ANY USERS’ ACTION. THINE IS NOT RESPONSIBLE FOR PROBLEMS CAUSED BY SPECIFICATIONS SUPPLIED BY USERS. THC63LVD104A is designed on the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people’s lives, etc.). In addition, when using THC63LVD104A for traffic signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures should be taken. 5. THINE IS MAKING THE UTMOST EFFORT TO IMPROVE THE QUALITY AND RELIABILITY OF THINE’S PRODUCTS. HOWEVER, THERE IS A VERY SLIGHT POSSIBILITY OF FAILURE IN SEMICONDUCTOR DEVICES. To avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 6. No radiation-hardened design is incorporated in THC63LVD104A. 7. Judgment on whether THC63LVD104A comes under strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law is the user’s responsibility. 8. This technical document was provisionally created during development of THC63LVD104A, so there is a possibility of differences between it and the product’s final specifications. When designing circuits using THC63LVD104A, be sure to refer to the final technical documents. THine Electronics, Inc. Wakamatsu Bldg, 6F 3-3-6, Nihombashi-Honcho, Chuo-ku, Tokyo, 103-0023 Japan Tel: 81-3-3270-0666 Fax: 81-3-3270-0688 Copyright 2003 THine Electronics, Inc. All rights reserved 13 THine Electronics, Inc.