SLIS101A − MAY 2001 D 5-V DC Fan Motor PWM Drive for Speed D D D D D Control With No External Power Drive Stage Required High Efficiency H-Bridge Topology With Integrated Low RDSON MOS Output Drivers to Drive Single Winding, Bipolar Wound, Two-Phase BLMs Digital PWM Input to Control Output PWM Frequency and Duty Cycle—Suited for Cooling Fan Applications Requiring Variable RPM Control to Reduce Noise/Increase MTBF Single Wire RPM Control, Tachometer Feedback Signal, and Locked Rotor Detect Feedback Signal Low Current Sleep State Tachometer Signal Valid Over Entire RPM Range D Noise Immune Signal Conditioning to Allow D D D Use of Low Cost Hall Effect Position Sensor Locked Rotor Protection With Auto Retry Thermal Shutdown Protection 8-Pin MSOP PowerPad Package Suited for Small Fan Circuit Board and Rotor Housing DGN Package (TOP VIEW) VPWR OUTA OUTB GND 1 8 2 7 3 6 4 5 PWM H− H+ TACH description The THMC45 is a dc brushless motor (BLM) driver and control device designed for use with low-voltage (5 V or 3.3 V) dc cooling fans having two-phase motors with a single-winding stator. The device includes a high-efficiency H-bridge pulse width modulation (PWM) drive topology with integrated MOS high-side and low-side drivers, plus a PWM control input stage to provide the industry’s first efficient speed control solution inside low-voltage dc cooling fans. This solution eliminates the need for any power drive components on the main system board, reducing printed-circuit board (PCB) component count, PCB space, and assembly time. The device also offers two advantages over the other commonly used fan speed control methods, adjustable external dc supply voltage and adjustable external PWM drive duty cycle. Unlike the external linear voltage regulation method, the THMC45 high-efficiency PWM drive method adjusts the level of motor winding power while all other circuitry inside the fan obtains a fixed dc voltage from the fan supply. This eliminates problems with loss of headroom to internal control circuitry at low fan supply voltage and the resulting limitation of low-speed operation of 40% that is typically associated with external dc voltage regulation. The high-efficiency PWM drive method employed by the THMC45 reduces fan supply power consumption and maximizes full-scale RPM speed over the external linear voltage regulation method, which has V × I power loss due to the voltage drop across the regulator. The THMC45 includes a Hall sensor amplifier and signal conditioning, global thermal shutdown, and locked rotor protection with automatic restart after a locked rotor condition. The device provides a sleep state to eliminate the need for an external power component to disconnect the fan from the supply during a system sleep state. The device also has internal reverse blocking capability to prevent excessive reverse leakage current due to reversal of power line. The THMC45 is primarily designed for 5-V dc notebook PC cooling fan applications that require single-wire RPM speed control and tachometer feedback. However, with an open-drain tachometer output, the device is also suitable for applications that require two wires for RPM speed control and tachometer signal. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. Copyright 2001, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"& *%$"# $ " #'&$$!"# '& "+& "&# &,!# #"%&"# #"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*& "&#"/ !)) '!!&"&# POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLIS101A − MAY 2001 functional block diagram VPWR Sleep State Detection SLEEP OSC Oscillator 70 kΩ PWM 8 SLEEP OSC Locked Rotor Detection and Auto-Restart +5 V OSC 1 VPWR C1 1 µF OSC ITACH/RD Signaling H-Bridge Drive and Control 2 OUTA ITACH 700 µA S N N S +5 V Hall Sensor H− 7 H+ 6 TACH 5 − + OUTB 4 GND Signal Conditioning Hall Sensor Amplifier TACH TACH 2 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLIS101A − MAY 2001 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION GND 4 I Ground H+ 6 I Hall sensor positive input H− 7 I Hall sensor negative input OUTA 2 O Motor winding drive output A OUTB 3 O Motor winding drive output B PWM 8 I/O PWM duty cycle control input and tachometer/locked rotor detect current sink output TACH 5 O Open drain tachometer output signal VPWR 1 I 5-V Supply voltage input absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage input, VPWR (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Open-drain tachometer output voltage, VTACH (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V H-bridge output voltage, VOUTA, VOUTB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Hall sensor amplifier input voltage, VH+, VH− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Speed control voltage input and tachometer/locked rotor feedback, VPWM (see Note 1) . . . . . . . . . . . . . . 6 V Continuous H-bridge output current source/sink, IOUTA, IOUTB (see Note 2) . . . . . . . . . . . . . . . . . . . . 350 mA Continuous H-bridge output current source/sink, IOUTA, IOUTB (see Note 3) . . . . . . . . . . . . . . . . . . . . 260 mA Continuous power dissipation, PD (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 W Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30°C to 80°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (soldering, 10 sec), TLEAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Assumed package plus PCB system thermal impedance = 170°C/W, TA = 25°C. 3. Assumed package plus PCB system thermal impedance = 170°C/W, TA = 80°C. 4. In free air at TA = 25°C, assumed 58.4°C/W and TJ = 150°C. recommended operating conditions Supply voltage, VPWR PWM high-level input voltage, VIH MIN MAX 2.5 5 2 PWM low-level input voltage, VIL PWM input frequency, fPWM Operating case temperature, TC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 0.8 V 18 50 kHz −30 80 °C 3 SLIS101A − MAY 2001 dc electrical characteristics, VPWR = 5V, TA = −30°C to 80°C (unless otherwise noted) supply current PARAMETER TEST CONDITIONS MIN TYP MAX 5 5.5 Supply voltage normal operation 4.5 VPWR Supply voltage functional with derated performance 2.4 VPOR Power-on reset voltage threshold Increase VPWR until logic active 1.5 IVPWR VPWR supply current IL = 0 A Idle condition, in locked rotor detect 0.5 1.5 0.5 1.5 IREV Reverse leakage ISLEEP Sleep-state current VPWR = −5 V at TA = 25°C VPWM = 0 V for >2 ms 4.5 UNIT V V 5 mA mA 75 300 µA TYP MAX UNIT Hall sensor signal conditioning PARAMETER IIB(HL) VICR(HL) TEST CONDITIONS Input bias current See Note 5 MIN −1 ICR(HL) common mode input voltage range VIO Hall amplifier input offset voltage NOTE 5: Design target only. Not tested in production. 1 1 µA 3.5 V −20 0 20 mV MIN TYP MAX OUTA, OUTB phase winding driver outputs PARAMETER TEST CONDITIONS ILEAK OUTA, OUTB output leakage current VPWM = 0 V for >2 ms, VOUTx = 5 V RDSON(Low) OUTA, OUTB low-side output ON resistance IOUTx = 200 mA, TA = 25°C RDSON(High) OUTA, OUTB high-side output ON resistance IOUTx = −200 mA, TA = 25°C OUTA, OUTB low-side output ON resistance IOUTx = 100 mA, TA = 25°C, IOUTx = −100 mA, TA = 25°C, RDSON OUTA, OUTB high-side output ON resistance sleep state, UNIT 1 µA 1.6 2.5 Ω 1.9 2.5 Ω VPWR = 2.4 V 3 6 Ω VPWR = 2.4 V 3.5 6 Ω TYP MAX −1 PWM input/TACH pulse output PARAMETER TEST CONDITIONS VIH VIL PWM high-level input voltage IIH IIL PWM high-level input current PWM low-level input current VPWM = 5 V VPWM = 0 V VOL PWM input tachometer pulse output low voltage IPWM = 2 mA MIN 2 UNIT V PWM low-level input voltage −1 75 0.8 V 1 µA 200 µA 0.4 V TACH open-drain output PARAMETER IIH VOL 4 TEST CONDITIONS VTACH = VPWR ITACH = 5 mA TACH output high leakage TACH output low voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN −1 TYP MAX UNIT 1 µA 400 mV SLIS101A − MAY 2001 ac electrical characteristics, VPWR = 5 V, TA = −30°C to 80°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 18 30 50 UNIT fPWM PWM input frequency t(SLEEP) Time to enter sleep state after no transitions on PWM terminal See Figure 5 2 ms t(PW) td Tachometer signal pulse width See Figure 4 1 µs Delay after rising edge of PWM input for TACH signal See Figure 4 1 µs tRD tRETRY Locked rotor detect delay time See Figure 6 1 s Auto-restart delay time See Figure 6 8 s t(de-glitch) Hall transition valid time for commutation to occur See Figures 1 and 4 25 µs t(PWM_de-glitch) De-glitch time for PWM input to prevent TACH current pulses from falsely triggering PWM See Figure 5 25 µs OUTA, OUTB output fall time See Note 5 200 ns OUTA, OUTB output rise time See Note 5 200 ns TEST CONDITIONS MIN tf(OUT) tr(OUT) kHz NOTE 5: Design target only. Not tested in production. thermal resistance PARAMETER RθJ(SYS) Thermal resistance, in system 2 oz. copper traces, JEDEC low K board, 0 LFPM airflow RθJC Thermal resistance, junction-to-case Exposed back-side die mount MAX UNIT 58.4 °C/W 4.7 °C/W PRINCIPLES OF OPERATION general overview The THMC45 is a dc BLM driver and control device designed for use with low-voltage (5 V or 3.3 V) dc cooling fans having two-phase motors with a single winding, bipolar-wound stator. The device is intended primarily for low-voltage cooling fan applications requiring speed control with a tachometer feedback signal to ensure normal fan operation. The output drive PWM duty cycle and frequency are dependent on the input signal on the PWM terminal. The device has an internal Hall sensor amplifier and signal conditioning with drive commutation logic, a low power sleep-state mode, and locked rotor protection with automatic restart after a locked rotor condition. The PWM terminal is used to input PWM frequency and duty cycle, to output a tachometer current pulse feedback signal, and to provide a means for entering sleep and run states. The THMC45 provides a more effective drive solution to fan RPM control than either external linear voltage regulation or external PWM drive. The device is offered in an MSOP-8 miniature surface-mount package to meet the critical space constraints of PCB designs of small low-voltage fans typically found in notebook PCs. supply voltage input (VPWR) The VPWR terminal serves as the voltage supply input to the THMC45. A 0.1-µF bypass capacitor should be placed as close to this terminal as layout permits. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLIS101A − MAY 2001 PRINCIPLES OF OPERATION Hall sensor amplifier inputs (H+, H−) The THMC45 has an internal Hall sensor amplifier with signal conditioning to allow the use of low-cost Hall sensors requiring no external components for noise filtering. The Hall signal conditioning block receives a low-level differential voltage from the Hall position sensor and implements a zero differential voltage crossing detection with a de-glitch time of 25 µs (typical), t(de-glitch), to reject noise on the Hall signal inputs. Refer to Figure 1, the OUTA output changes from sourcing current to sinking current after the 25-µs de-glitch time. Likewise, the OUTB output changes from sinking current to sourcing current after the 25-µs de-glitch time. The Hall amplifier circuit has an input offset voltage, VIO, not greater than ±13 mV when VPWR is between 4.5 V and 5.5 V. The common mode input voltage range is 1 V to 3.5 V when VPWR is between 4.5 V and 5.5 V. Differential Hall Signal (H+ − H−) t(de-glitch) t(de-glitch) t(de-glitch) Conditioned Hall Amplifier Output (Internal) PWM Input OUTA OUTB Figure 1. Hall Sensor Signal Conditioning Waveform and OUTA/OUTB Commutation Illustrated in truth table format, Table 1 shows OUTA and OUTB commutation and PWM. Table 1. OUTA and OUTB Low-Side Drive Commutation H+ H− OUTA OUTB H L H PWM L H PWM H H-bridge motor drive outputs (OUTA, OUTB) Using an H-bridge to drive a bipolar wound, two-phase BLM provides several advantages for dc fans over the unipolar-wound motor commonly driven by two commutated low-side switches. A bipolar-wound motor has only two connections; hence, the H-bridge drive topology requires only two output terminals and two traces are needed on the fan PCB. A bipolar-wound stator has a single-wire winding which is simpler to manufacture, and thus increases reliability and reduces manufacturing time. All factors combine to allow a smaller diameter fan center hub, and thus higher blade area for increased airflow on a given fan frame size. Generally, an H-bridge drive method with bipolar-wound stator increases fan motor torque density over a typical unipolar drive method. The H-bridge drive method also eliminates the need for snubbing inductive energy at commutation transitions and allows for recirculation of winding current to maintain energy in the motor while PWM switching occurs. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLIS101A − MAY 2001 PRINCIPLES OF OPERATION H-bridge motor drive outputs (OUTA, OUTB) (continued) Figures 2a and 2b show THMC45 H-bridge motor drive states with stator winding current being driven from OUTA to OUTB and from OUTB to OUTA, respectively, based on the Hall sensor commutation state. As shown during tON, PWM signal is high and the drive current is from VPWR through the activated switches and motor to GND. PWM occurs on the low side, and the stator winding inductive current recirculates on the high side during tOFF and PWM signal is low (see Figure 3 for motor current waveform). Recirculation of inductive current through the high-side switches during tOFF, known as synchronous rectification, improves power conversion efficiency by maintaining energy in the stator winding and results in a continuous dc current level. VPWR ON M1 PWM tON OUTA VPWR PWM M2 ON M1 I(RECIRCULATE) M2 OUTB Motor Motor OUTA OFF M3 PWM I(DRIVE) PWM M4 OFF OUTB M3 GND PWM tOFF M4 PWM GND H+ H− OUTA OUTB H L H PWM a) A to B Current Direction VPWR PWM M1 PWM tON OUTA VPWR M2 ON PWM M1 I(RECIRCULATE) M2 OUTB Motor Motor OUTA PWM M3 ON I(DRIVE) OFF M4 PWM M3 GND OUTB PWM tOFF M4 OFF GND H+ H− OUTA OUTB L H PWM H b) B to A Current Direction Figure 2. H-Bridge PWM Drive With Synchronous Rectification POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLIS101A − MAY 2001 PRINCIPLES OF OPERATION PWM input (PWM) The PWM input provides several functions: D Input for controlling H-bridge PWM drive frequency and duty cycle D Output for a tachometer current sink pulse on the first rising edge of the PWM input signal after a commutation D Initiating a low-current sleep state when the voltage maintained a logic low level for 2 ms (typical) or longer, and allowing the THMC45 to return to a normal run state on the next rising edge of the PWM input signal The THMC45 requires a TTL level PWM input signal from another device, such as a Super I/O device. This signal, along with the Hall sensor input, is used to PWM the OUTA and OUTB outputs according to truth table, Table 1. It is recommended that the frequency of the PWM input signal be between 18 kHz and 60 kHz. A PWM frequency of 18 kHz or higher, being above the audible range, ensures quiet fan operation. Frequencies above 18 kHz also promote efficient fan speed control by keeping the PWM period below the electrical L/R time constant of the motor. This allows continuous current in the fan windings (see Figure 3). Keeping the PWM frequency below 60 kHz minimizes switching losses. Switching losses, typically observed at higher frequencies, decreases overall efficiency. The speed of the cooling fan can be varied by adjusting the duty cycle of the PWM input signal. The higher the duty cycle of the PWM input signal, the higher the current in the fan windings, and thus results in faster fan speed. I(DRIVE) I(MOTOR) I(RECIRCULATE) PWM Period tOFF tON PWM Figure 3. Motor Current Waveform 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLIS101A − MAY 2001 PRINCIPLES OF OPERATION tachometer signaling on PWM input (PWM) The PWM terminal of the THMC45 provides a 1-µs (typical) current sink pulse, t(PW), following the next rising edge of the PWM input signal after the Hall sensor amplifier changes states (see Figure 4). Note that the THMC45 incorporates a blanking circuit that disregards transitions on the PWM terminal during the TACH current pulses. This ensures that the TACH pulses do not corrupt the output PWM signal. This current signal can be detected with external circuitry and can be sent to the TACH input of the hardware monitor portion of a Super I/O device. Differential Hall Signal (H+ − H−) t(de-glitch) t(de-glitch) t(de-glitch) Conditioned Hall Amplifier Output (Internal) PWM Input td t(PW) TACH Current Sink Pulses TACH Figure 4. Tachometer Current Pulse Timing on PWM Input Pin sleep/run states using PWM input (PWM) The THMC45 enters a low-current sleep state when the PWM input maintains a logic low level for more than 2 ms (typical), t(SLEEP). In sleep state, the OUTA and OUTB outputs are in a high-impedance state. The THMC45 transitions from sleep state to run state on the first rising edge on the PWM input. Figure 5 shows the timing relationships between the PWM signal and sleep/run state. PWM Input t(SLEEP) t(PWM_de-glitch) OUTA, OUTB Enable Signal Figure 5. PWM Input Signal, Sleep State, and Run State Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLIS101A − MAY 2001 PRINCIPLES OF OPERATION locked rotor protection An internal digital timer is used to monitor the output of the Hall sensor amplifier. When change in commutation state is not observed via the Hall amplifier inputs within 1 second (typical), t(RD), the OUTA and OUTB outputs are disabled for 8 seconds (typical), t(RETRY). After this period, the THMC45 re-enables the OUTA and OUTB outputs to automatically restart the motor after a locked rotor condition. When the locked rotor condition continues to exist, the above process repeats itself until the locked condition is removed or the THMC45 is powered down (see Figure 6). Conditioned Hall Amplifier Output (Internal) t(RD) t(RD) t(RETRY) t(RETRY) OUTA, OUTB Enable Figure 6. Typical Locked Rotor Protection Timing Waveforms open-drain tachometer output (TACH) The TACH output is an open-drain output that is activated by the output of the Hall sensor comparator output. When the output of the Hall sensor comparator is high, the TACH output floats high. When the output of the Hall sensor amplifier is low, the TACH output is pulled low. The resulting output signal has two pulses per revolution on a four-pole motor. The TACH output can be used to monitor and measure actual fan speed. It may also be used as part of a closed-loop speed control system. thermal shutdown The THMC45 provides protection against excessive device temperature with a thermal sensor to monitor the die temperature. In the event that operating or abnormal condition causes the die temperature to exceed t(SD), the thermal shutdown threshold (175°C typical), all output drivers are turned off. When t(SD) has been exceeded, the die temperature must fall below a hystersis temperature, t(SD_HYS) (15°C typical) before the output drivers are re-enabled. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLIS101A − MAY 2001 THERMAL INFORMATION POWER DISSIPATION vs AMBIENT TEMPERATURE 1.3 P D − Power Dissipation − W 1.2 1.1 RθJ(SYS) = 100°C/W 1.0 RθJ(SYS) = 125°C/W 0.9 0.8 RθJ(SYS) = 170°C/W 0.7 0.6 RθJ(SYS) = 225°C/W 0.5 0.4 0.3 0.2 RθJ(SYS) = 285°C/W 0.1 0.0 20 30 40 50 60 70 80 90 100 110 120 130 140 150 t − Ambient Temperature − °C Note: RθJ(SYS) refers to composite thermal impedance provided by the IC package, PCB, and fan housing. Figure 7 CONTINUOUS CURRENT vs AMBIENT TEMPERATURE I VPWR − Continuous Current − A 0.5 RθJ(SYS) = 100°C/W 0.4 0.3 RθJ(SYS) = 125°C/W 0.2 RθJ(SYS) = 170°C/W RθJ(SYS) = 225°C/W 0.1 RθJ(SYS) = 285°C/W 0.0 20 30 40 50 60 70 80 90 100 110 120 130 140 150 t − Ambient Temperature − °C Note: RθJ(SYS) refers to composite thermal impedance provided by the IC package, PCB, and fan housing. Analysis assumes combined high and low-side RDSon = 5.5 Ω. Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLIS101A − MAY 2001 APPLICATION INFORMATION GND PWM INPUT + 5V TACH R1 1.3 kΩ 1 C1 1 µF 10 V 2 + 3 4 VPWR PWM H− OUTA THMC45 H+ OUTB TACH GND 8 7 6 5 Bipolar Wound Motor NOTES: A. Traces in bold are high current traces. B. C1 should be placed as close as possible to terminals 1 and 4. Figure 9. Application Schematic 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 A D Hall Sensor C B SLIS101A − MAY 2001 MECHANICAL DATA DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 Thermal Pad (See Note D) 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°−ā 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073271/A 04/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusions. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-187 PowerPAD is a trademark of Texas Instruments. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 8-Apr-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty THMC45DGN OBSOLETE MSOPPower PAD DGN 8 TBD Call TI Call TI THMC45DGNR OBSOLETE MSOPPower PAD DGN 8 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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