TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 BUCK/BOOST SWITCH-MODE REGULATOR FEATURES 1 • Qualified for Automotive Applications • Switch-Mode Regulator – 5 V ±2%, Normal Mode – 5 V ±3%, Low-Power or Crossover Mode • Switching Frequency, 440 kHz (typical) • Input Operating Range, 1.5 V to 40 V, (Vdriver) – 500-mA Load-Current Capability – 200-mA Load-Current Capability Down to 2-V Input (Vdriver) – 120-mA Load-Current Capability Down to 1.5-V Input (Vdriver) • Enable Function • Low-Power Operation Mode 23 • • • • • Switched 5-V Regulated Output on 5Vg With Current Limit Programmable Slew Rate and Frequency Modulation for EMI Consideration Reset Function With Deglitch Timer and Programmable Delay Alarm Function for Undervoltage Detection and Indication Thermally Enhanced Package for Efficient Heat Management APPLICATIONS • Automotive Electronic Controller Power Supply PWP HTSSOP PACKAGE (TOP VIEW) SCR1 Cboot2 Cboot1 Vdriver L1 PGND L2 VOUT 5Vg AIN 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SCR0 5Vg_ENABLE ENABLE Vlogic GND Rmod REST AOUT RESET CLP P0021-02 DESCRIPTION The TPS55065 is a switch-mode regulator with integrated switches for voltage-mode control. With the aid of external components (LC combination), the device regulates the output to 5 V ±3% for a wide input-voltage range. The TPS55065 offers a reset function to detect and indicate when the 5-V output rail is outside of the specified tolerance. This reset delay is programmable using an external timing capacitor on the REST terminal. Additionally, an alarm (AOUT) feature is activated when the input supply rail Vdriver is below a prescaled specified value (set by the AIN terminal). The TPS55065 has a frequency-modulation scheme to minimize EMI. The clock modulator permits a modulation of the switching frequency to reduce interference energy in the frequency band. The 5Vg output is a switched 5-V regulated output with internal current limiting to prevent RESET from being asserted when powering a capacitive load on the supply line. This function is controlled by the 5Vg_ENABLE terminal. If there is a short to ground on this output (5Vg output), the output self-protects by operating in a chopping mode. This does, however, increase the output ripple voltage on VOUT during this fault condition. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 125°C (1) (2) HTSSOP – PWP ORDERABLE PART NUMBER Reel of 2000 TPS55065QPWPRQ1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Cboot1 Q1 Vdriver L Vreg Vbattery Charge Pump Osc L1 External Schottky Diode Required, Max. 0.4 V 4.7 nF @1A @ 125ºC Q2 22 mH– 100 mH C L2 ENABLE Switch-Mode Controller With Dead Time Vlogic R2 470 nF Cboot2 Bandgap Ref Q4 AIN Rmod R1 4.7 nF Q3 - Clock Modulator 12 kW + + 5Vg_ENABLE VOUT PGND Vref Inrush Current Limit 5Vg - Low-Power Mode Digital Signal CLP Low-Power Mode Control GND Shutdown Regulator Bandgap Ref 5Vg_Supply 1 µF–100 µF SCR0 SCR1 22 µF–470 µF Charge Pump + Slew Rate Control 5 V Supply AOUT Temp Monitor POR With Delay Timer 5 kW 5 kW RESET REST 2.2 nF–150 nF B0130-01 NOTE: All component values are typical. 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 Table 1. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION SCR1 1 I Programmable slew-rate control Cboot2 2 I External bootstrap capacitor Cboot1 3 I External bootstrap capacitor Vdriver 4 I Input voltage source L1 5 I Inductor input (an external Schottky diode (1) to GND must be connected to L1) PGND 6 I Power ground L2 7 I Inductor output VOUT 8 O 5-V regulated output 5Vg 9 O Switched 5-V supply Programmable alarm setting AIN 10 I CLP 11 I/O Low-power operation mode (digital input) RESET 12 O Reset function (open drain) AOUT 13 O Alarm output (open drain) REST 14 O Programmable reset timer delay Rmod 15 I Main switching frequency modulation setting to minimize EMI GND 16 I Ground Vlogic 17 O Supply decoupling output (may be used as a 5-V supply for logic-level inputs) ENABLE 18 I Switch-mode regulator enable/disable 5Vg_ENABLE 19 I Switched 5-V voltage regulator output enable/disable SCR0 20 I Programmable slew-rate control Exposed thermal pad of the package should be connected to GND or left floating. (1) Maximum 0.4 V at 1 A at 125°C Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS over recommended operating free-air temperature range (unless otherwise noted) (1) Unregulated input voltage, V(driver) (2) –0.5 V to 40 V Unregulated inputs, V(AIN), V(ENABLE) (2) –0.5 V to 40 V Bootstrap voltages V(Cboot1) 52 V V(Cboot2) Switch mode voltages 14 V V(L1) –1 V to 40 V V(L2) –1 V to 7 V Logic input voltages, V(Rmod),V(SCR0),V(SCR1),V(CLP), and V(5Vg_ENABLE) (2) –0.5 V to 7 V Low output voltages, V(RESET),V(AOUT),V(logic), and V(REST) (2) Electrostatic-discharge susceptibility –0.5 V to 7 V V(HBMESD) (3), pin 7 (L2), pin 8 (VOUT), pin 9 (5Vg) V(HBMESD) 800 V (3) , pins 1–6 and 10–20 2 kV Thermal impedance, junction-to-case, RθJC (4) Thermal impedance, junction-to-ambient 2°C/W RθJA (4) 32°C/W RθJA (5) 40°C/W Continuous power dissipation, PD See Dissipation Rating Table Operating virtual junction temperature range, TJ –40°C to 150°C Operating ambient temperature range, TA –40°C to 125°C Storage temperature range, Tstg –65°C to 125°C Lead temperature (soldering, 10 s), T(LEAD) (1) (2) (3) (4) (5) 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to ground. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each terminal. The thermal data is based on using 2-oz. copper trace with at least four square inches of copper footprint for heat dissipation. The copper pad is soldered to the thermal land pattern. Correct attachment procedure must be incorporated. The thermal data is based on using 1-oz. copper trace with at least four square inches of copper footprint for heat dissipation. The copper pad is soldered to the thermal land pattern. Correct attachment procedure must be incorporated. DISSIPATION RATING TABLE POWER RATING TA ≤ 25°C DERATING FACTOR ABOVE TA = 25°C 32°C/W 3.9 W 40°C/W 3.125 W RθJA POWER RATING TA = 85°C POWER RATING TA = 125°C 31.25 mW/°C 2.03 W 0.781 W 25 mW/°C 1.625 W 0.625 W RECOMMENDED OPERATING CONDITIONS MIN MAX Unregulated input voltage, V(driver) 6 24 V Unregulated input voltages, V(AIN) and V(ENABLE) 0 24 V V(L1) –1 17 V(L2) 5 5.5 Switch-mode terminals Bootstrap voltages V(Cboot1) V(driver) + 10 V(Cboot2) 8 Logic levels (I/O), V(Rmod), V(logic),V(SCR0),V(SCR1),V(5Vg_ENABLE),V(RESET), V(AOUT), V(CLP), and V(REST) Operating ambient temperature range, TA Logic levels (I/O), V(SCR0), V(SCR1), V(CLP) directly connected to V(logic) 4 Submit Documentation Feedback 0 UNIT V V 5.25 V –40 125 °C V(logic) V(logic) V Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 ELECTRICAL CHARACTERISTICS V(driver) = 6 V to 17 V, TA = -40°C to 125°C, unless otherwise noted Parameters TEST CONDITIONS MIN TYP Unregulated input voltage V(driver) Start-up condition voltage CO = 36 µF (min) to 220 µF (max) 4 20 SOM Soft-start ramp CO = 220 µF (min) to 470 µF (max), see Note (1) 2 20 I(standby) Standby current ENABLE = low Iq Quiescent current CLP = 0 V, V(driver) = 11 V, IO = 0 mA VO Output voltage DC VO Output-voltage tolerance IO Output current 1.5 MAX V(driver) IO = 500 mA V 5 V 10 20 µA 160 µA V Normal mode 2 Boost/buck crossover or low-power mode 3 V(driver) ≥ 7 V 0.5 (2) 200 IO(Boost) Output current, boost mode IPPn Internal peak current limit (normal mode) (1) 1.75 2.5 IPPl Internal peak current limit (low-power mode) (1) 0.75 1.25 IP Peak current V(driver) = 16 V, IO = 500 mA, L = 33 µH V(driver) Boost/buck crossover voltage window See Note Tot Thermal shutdown V(driver)= 1.5 V, see Note (3) (4) (2) 120 1.5 5 160 V/ms 100 5 V(driver) = 2 V, see Note UNIT 40 % A mA A A 5.9 V 180 200 °C 135 225 mΩ 400 mA VO V 5Vg Output and ENABLE rDS(on) On-state resistance IO Output current VI 5Vg_ENABLE input-voltage range VIH 5Vg_ENABLE threshold high voltage V(5Vg) = 5 V 2.5 3 3.5 V VIL 5Vg_ENABLE threshold low voltage V(5Vg) = 0 V 1.5 2 2.5 V V(hys) Hysteresis voltage 0.5 1 r(pd) Internal pulldown resistor 300 500 850 kΩ 40 V –0.5 V ENABLE VI ENABLE input-voltage range VIH ENABLE threshold high voltage VIL ENABLE threshold low voltage V(hys) (1) (2) (3) (4) Hysteresis voltage –0.5 8 V ≤ V(driver) ≤ 17 V 2.5 3 3.5 6 V ≤ V(driver) < 8 V 1.9 3 3.5 VO = 5 V 1.5 2 2.5 8 V ≤ V(driver) ≤ 17 V 0.5 1 6 V ≤ V(driver) < 8 V 0.1 V V V Ensured by characterization. Tested with inductor having following characteristics: L = 33 µH, Rmax = 0.1 Ω, IR = 1.8 A. Output current must be verified in application when inductor Rmax (ESR) is increased. Ensured by characterization. For further details, see the Buck/Boost Transitioning section. Ensured by characterization; hysteresis 15°C (typical) Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) V(driver) = 6 V to 17 V, TA = -40°C to 125°C, unless otherwise noted Parameters TEST CONDITIONS MIN TYP MAX UNIT 4.51 4.65 4.79 V 8 10 12 80 100 120 RESET V(th) RESET threshold voltage V(RESET) RESET tolerance t(RESET) RESET time VOL RESET output low voltage t(deglitch) RESET deglitch time 3% C(REST) = 10 nF C(REST)= 100 nF, see Note (5) Isink = 5 mA 450 Isink = 1 mA 84 See Note (5) 8 ms mV 10 12.5 µs Alarm VI Alarm input-voltage range 40 V VIL Alarm threshold low voltage 2.2 2.3 2.35 V VIH Alarm threshold high voltage 2.43 2.5 2.58 V V(hys) Hysteresis voltage VOL Alarm output low voltage –0.5 200 mV Isink = 5 mA 450 Isink = 1 mA 84 mV Low-Power Mode (Pulse Mode) PFM IO(LPM) Load current in low-power mode V(driver) < 7 V II(avg) Average input current V(driver) = 11 V, IO = 5 mA, CLP = low VO Output-voltage tolerance VO = 5 V 2.4 50 mA 3.55 mA 3 % Digital Low-Power Mode (CLP) VIH High-level CLP input threshold voltage Normal mode VIL Low-level CLP input threshold voltage 2.6 V Low-power mode 1.15 V Switching Parameters f(sw) Switching frequency V(Rmod) = 0 V, modulator OFF 440 kHz f(sw) = 440 kHz 18 f(sw) = 440 kHz 20 f(sw)ac Operating-frequency accuracy f(sw)min Modulation minimum frequency 270 330 445 kHz f(sw)max Modulation maximum frequency 450 550 680 kHz f(mod)span Modulation span f(mod) Modulation frequency f(mod)ac Modulation-frequency accuracy (5) 6 220 Rmod = 12 kΩ ±1% % kHz 28 kHz 12 % Ensured by characterization. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 PRINCIPLES OF OPERATION Functional Principle The TPS55065 is a buck/boost switch-mode regulator that operates in a power-supply concept to ensure a stable output voltage with input voltage excursions and specified load range. The device provides an alarm indicator and reset output to interface with systems that require supervisory function. The switching regulator offers a clock modulator and a current-mode slew-rate control for the internal switching transistor (Q1) to minimize EMI. An internal low-rDS(on) switch has a current-limit feature to prevent inadvertent reset when turning on the 5Vg output. Description of the Functional Terminals Switch-Mode Input/Output Terminals (L1, L2) The external inductor for the switch-mode regulator is connected between terminals L1 and L2. This inductor is placed close to the terminals to minimize parasitic effects. For stability, an inductor with 20 µH to 100 µH should be used. Supply Terminal (Vdriver) The input voltage of the device is connected to the Vdriver terminal. This input line requires a filter capacitor to minimize noise. A low-ESR aluminum or tantalum input capacitor is recommended. The relevant parameters for the input capacitor are the voltage rating and RMS current rating. The voltage rating should be approximately 1.5 times the maximum applied voltage for an aluminum capacitor and 2 times for a tantalum capacitor. In buck ǸD * D2 mode, the RMS current is I OUT , where D is the duty cycle and its maximum RMS current value is reached when D = 50% with IRMS = IOUT/2. In boost mode, the RMS current is 0.3 × ΔI, where ΔI is the peak-to-peak ripple current in the inductor. To achieve this, ESR ceramic capacitors are used in parallel with the aluminum or tantalum capacitors. Internal Supply Decoupling Terminal (Vlogic) The Vlogic terminal is used to decouple the internal power-supply noise by use of a 470-nF capacitor. This terminal can also be used as an output supply for the logic-level inputs for this device (SCR0, SCR1, ENABLE, CLP, and 5Vg_ENABLE). Input Voltage Monitoring Terminal (AIN) The AIN terminal is used to program the threshold voltage for monitoring and detecting undervoltage conditions on the input supply. A maximum of 40 V may be applied to this terminal and the voltage at this terminal may exceed the V(driver) input voltage without effecting the device operation. The resistor divider network is programmed to set the undervoltage detection threshold on this terminal (see the application schematic). The input has a typical hysteresis of 200 mV with a typical upper limit threshold of 2.5 V and a typical lower limit threshold of 2.3 V. When V(AIN) falls below 2.3 V, V(AOUT) is asserted low; when V(AIN) exceeds 2.5 V, V(AOUT) is in the high-impedance state. The equations to set the upper and lower thresholds of V(AIN) are: . Upper: V(driver) = 2.5 V × Lower: V(driver) = 2.3 V × R1 + R2 R1 R1 + R2 R1 Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7 TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com Input Undervoltage Alarm Terminal (AOUT) The AOUT terminal is an open-drain output that asserts low when the input voltage falls below the set threshold on the AIN input. Reset Delay Timer Terminal (REST) The REST terminal sets the desired delay time to assert the RESET terminal low after the 5-V supply has exceeded 4.65 V (typical). The delay can be programmed in the range of 2.2 ms to 150 ms using capacitors in the range of 2.2 nF to 150 nF. The delay time is calculated using the following equation: RESET delay = C(REST)× 1 ms, where C(REST) has nF units Reset Terminal (RESET) The RESET terminal is an open-drain output. The power-on reset output is asserted low until the output voltage exceeds the 4.65-V threshold and the reset delay timer has expired. Additionally, whenever the ENABLE terminal is low, RESET is immediately asserted low regardless of the output voltage. Main Regulator Output Terminal (VOUT) The VOUT terminal is the output of the switch-mode regulated supply. This terminal requires a filter capacitor with low-ESR characteristics to minimize output ripple voltage. For stability, a capacitor with 22 µF to 470 µF should be used. The total capacitance at pin VOUT and pin 5Vg must be less than or equal to 470 µF. Low-Power-Mode Terminal (CLP) The CLP terminal controls the low-power mode of the device. An external low digital signal switches the device to low-power mode or normal mode when the input is high. Switch-Output Terminal (5Vg) The 5Vg terminal switches the 5-V regulated output. The output voltage of the regulator can be enabled or disabled using this low-rDS(on) internal switch. This switch has a current-limiting function to prevent generation of a reset signal at turnon caused by the capacitive load on the output or overload condition. When the switch is enabled, the regulated output may deviate and drop momentarily to a tolerance of 7% until the 5Vg capacitor is fully charged. This deviation depends on the characteristics of the capacitors on VOUT and 5Vg. 5Vg-Enable Terminal (5Vg_ENABLE) The 5Vg_ENABLE is a logic-level input for enabling the switch output on 5Vg. For the functional terminal, 5Vg_ENABLE results in the following table: 8 5Vg_ENABLE Function 0 5Vg is off Open (internal pulldown = 500 kΩ) 5Vg is off 1 5Vg is on Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 Vdriver Q1 Peak Current Limit Switch Control Slew Rate Control L1 Buck/Boost 33 µH L2 Q4 VOUT Gate Driver Q3 47 µF Q2 Gate Driver VOUT 5Vg 5Vg Charge Pump typ ~VOUT – 100 mV 100 µF VOUT RESET typ 4.65 V RESET Deglitch RESET 5Vg_ENABLE S0174-01 Figure 1. Current-Limit Switched Output 5Vg Slew-Rate Control Terminals (SCR0, SCR1) The slew rate of the switching transistor Q1 is set using the SCR0 and SCR1 terminals. The following table shows the values of the slew rate (SR): SCR1 SCR0 SRQ1 0 0 Slow 0 1 Medium-slow 1 0 Medium-fast 1 1 Fast Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9 TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com See the converter efficiency plots in the Typical Characteristics section to determine power dissipation. Modulator Frequency Setting (Terminal Rmod) The Rmod terminal adjusts the clock modulator frequency. A resistor of Rmod = 12 kΩ generates a modulation frequency of 28 kHz. The modulator function may be disabled by connecting Rmod to GND and the device operates with the nominal frequency. The modulator function cannot be activated during IC operation, only at IC start-up. Ground Terminal (PGND) The PGND terminal is the power ground for the device. Enable Terminal (ENABLE) The ENABLE terminal allows the enabling and disabling of the switch mode regulator. A maximum of 40 V may be applied to this terminal to enable the device and increasing it above the V(driver) input voltage does not affect the device operation. The functionality of the ENABLE terminal is described in the following table: ENABLE Function 0 Vreg is off. Open Undefined 1 Vreg is on. Bootstrap Terminals (Cboot1 and Cboot2) An external bootstrap capacitor is required for driving the internal high-side MOSFET switch. A 4.7-nF ceramic capacitor is typically required. Functional Modes Clock Modulator To minimize EMI issues associated with the switch-mode regulator, the device offers an integrated clock modulator. The function of the clock modulator is to modulate the switching frequency and to distribute the energy over the wave band. The average switching frequency is 440 kHz (typical) and varies between 330 kHz and 550 kHz at a rate set by the Rmod resistor. A typical value of 12 kΩ on the Rmod terminal relates to a 28-kHz modulation frequency. The clock modulator function can only be activated during IC start-up, not during IC operation. The equation for the modulation frequency is as follows: f(mod) (Hz) = (–2.2 × Rmod) + 54.5 kHz, when Rmod = 8 kΩ to 16 kΩ Buck/Boost Transitioning The operation mode switches automatically between buck and boost modes depending on the input voltage of V(driver) and output load conditions. During start up, when V(driver) is less than 5.8 V (typical), the device starts in boost mode and continues to run in boost mode until V(driver) exceeds 5.8 V; at which time, the device switches over to buck mode. In buck mode, the device continues to run in buck mode until it is required to switch back to boost to hold regulation. This crossover window to switch to boost mode is when V(driver) is between 5.8 V and 5 V and depends on the loading conditions. When Vdriver drops below 5.8 V but the device is holding regulation (~2%), the device remains in buck mode. However, when V(driver) is within the 5.8-V to 5-V window and VOUT drops to 4.9 V, the device crosses over to boost mode to hold regulation. In boost mode, the device remains in boost mode until V(driver) exceeds 5.8 V; at which time, the device enters the buck mode. When the device is operating in boost mode and V(driver) is in the crossover window of 5.8 V to 5 V, the output regulation may contain a higher than normal ripple and only maintain a 3% tolerance. This ripple and tolerance depends on the loading and improves with a higher loading condition. When the device is operated with low-power mode active (CLP = low) and high output currents (>50 mA), the buck/boost transitioning can cause a reset signal at the RESET pin. 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 Buck SMPS In buck mode, the duty cycle of transistor Q1 sets the voltage VOUT. The duty cycle of transistor Q1 varies 10% to 99% depending on the input voltage, V(driver). If the peak inductor current (measured by Q1) exceeds 450 mA (typical), Q2 is turned on for this cycle (synchronized rectification). Otherwise, the current recirculates through Q2 as a free-wheeling diode. The detection for synchronous or asynchronous mode is done cycle-by-cycle. To avoid a cross-conduction current between Q1 and Q2, an inherent delay is incorporated when switching Q1 off and Q2 on and vice versa. In buck mode, transistor Q3 is not required and is switched off. Transistor Q4 is switched on to reduce power dissipation. The switch timings for transistors Q3 and Q4 are not considered. In buck mode, the logical control of the transistors does not change. Vdriver Input Voltage SMPS Q1 Current Control L1 Q2 33 µH Switch Control L2 Q4 VOUT Q3 22 µF–470 µF FB S0182-01 Figure 2. Buck/Boost Switch Mode Configuration Boost SMPS In boost mode, the duty cycle of transistor Q3 controls the output voltage VOUT. The duty cycle is internally adjusted 5% to 85% depending on the internally sensed voltage of the output. Synchronized rectification occurs when V(driver) is below 5 V. To avoid a discharging of the buffer capacitor, a simultaneous switching on of Q3 and Q4 is not allowed. An inherent delay is incorporated between Q3 switching off and Q4 switching on and vice versa. In boost mode, transistor Q2 is not required and remains off. Transistor Q1 is switched on for the duration of the boost-mode operation (serves as a supply line). The switch timings of transistors Q1 and Q2 are not considered. In boost mode, the logical control of the transistors does not change. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11 TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com Extension of the Input Voltage Range on V(driver) To ensure a stable 5-V output voltage with the output load in the specified range, the V(driver) supply must be greater than or equal to 5 V for greater than 1 ms (typical). After a period of 1 ms (typical), the logic may be supplied by the VOUT regulator and the V(driver) supply may be capable of operating down to 1.5 V. The switch-mode regulator does not start at V(driver) less than 5 V. Low-Power Mode To reduce quiescent current and to provide efficient operation, the regulator enters a pulsed mode. The device enters this mode by a logic-level low on this terminal. Automatic low-power mode is not available. The low-power-mode function is not available in boost mode. The device leaves low-power mode during boost mode regardless of the logic level on the CLP terminal. Temperature and Short-Circuit Protection To prevent thermal destruction, the device offers overtemperature protection to disable the IC. Also, short-circuit protection is included for added protection on VOUT and 5Vg. Switch Output Terminal (5Vg) Current Limitation A charge pump drives the internal FET, which switches the primary output voltage VOUT to the 5Vg pin. Protection is implemented to prevent the output voltage from dropping below its specified value while enabling the secondary output voltage. An explanation of the block diagram (see Figure 1) is given by the following example: • Device is enabled, output voltage VOUT is up and stable. • 5Vg is enabled (pin 5Vg_ENABLE set to high) with load resistance connected to 5Vg pin. • If output voltage VOUT drops below typical ( VOUT – 100 mV), the charge pump of the 5Vg FET is switched off and the FET remains on for a while as the gate voltage drops slowly. • If VOUT drops below the RESET threshold of 4.65 V (typical), the FET of the secondary output voltage 5Vg is switched off (gate drawn to ground level). • A deglitch time ensures that a device reset does not occur if VOUT drops to the reset level during the 5Vg turnon phase. • If VOUT rises above typical (VOUT – 100 mV), the charge pump of the 5Vg FET is switched on and drives the gate of the 5Vg FET on. Soft Start On power up, the device offers a soft-start feature which ramps the output of the regulator at a slew of 10 V/ms. When a reset occurs, the soft start is reenabled. Additionally, if the output capacitor is greater than 220 µF (typical), the slew rate decreases to a value set by the internal current limit. In boost mode, the soft-start feature is not active. 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 TYPICAL CHARACTERISTICS 6 V(driver) = 11 V II − Input Current − mA 5 4 Maximum 3 TA = 125° TA = 25° 2 1 0 0 1 2 3 4 5 6 7 8 9 IO − Output Current − mA 10 G001 NOTE: Maximum characteristic specified by design. Figure 3. Low-Power Mode Current, IO = 0 mA–10 mA 1.0 V(driver) = 11 V 0.9 II - Input Current - mA 0.8 0.7 0.6 Maximum 0.5 TA = 125° 0.4 TA = 25° 0.3 0.2 0.1 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 IO - Output Current - mA 0.9 1.0 G002 NOTE: Maximum characteristic specified by design. Figure 4. Low-Power-Mode Current, IO = 0 mA–1 mA Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13 TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) 85 SCR: 10, V (driver) = 11 V SCR: 11, V (driver) = 11 V 80 Efficiency - % 75 70 65 SCR: 10, V (driver) = 17 V 60 SCR: 01, V (driver) = 17 V SCR: 01, V (driver) = 11 V SCR: 00, V (driver) = 11 V 55 50 100 SCR: 00, V (driver) = 17 V SCR: 11, V (driver) = 17 V 150 200 250 300 350 400 450 500 IO - Output Current - mA NOTE: The average converter efficiency with four different slew rate controls (SCRx) on the Q1 switching FET with input voltage V(driver) = 11 V and 17 V, TA = 125°C. Figure 5. Converter Efficiency V(L1) Input Current (200 mA/div) G005 Figure 6. Input Current With Slope Control, SCR0 = 0, SCR1 = 0, Input-Current Slew Rate = 2.8 A/µs, IL = 500 mA, V(driver) = 15 V 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 TYPICAL CHARACTERISTICS (continued) G010 Figure 7. Input Current With Slope Control, SCR1 = 0, SCR0 = 1, Input-Current Slew Rate = 6.25 A/µs, IL = 500 mA, V(driver) = 15 V G011 Figure 8. Input Current With Slope Control, SCR1 = 1, SCR0 = 0, Input-Current Slew Rate = 9.4 A/µs, IL = 500 mA, V(driver) = 15 V Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15 TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) G008 Figure 9. Input Current With Slope Control, SCR0 = 1, SCR1 = 1, Input-Current Slew Rate = 18.8 A/µs, IL = 500 mA, V(driver) = 15 V G009 Figure 10. Low-Power-Mode Operation, IL = 15 mA, CO = 47 µF 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 TYPICAL CHARACTERISTICS (continued) G012 Figure 11. Nominal Switching Frequency of Q1 Switch (446 kHz) With Modulation Function Disabled, IL = 200 mA (Reference L1 Terminal, see Figure 12 through Figure 14) G013 Figure 12. Minimum Switching Frequency (333 kHz) With Modulation Enabled, Rmod = 12 kΩ, IL = 200 mA Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17 TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) (Reference L1 Terminal, see Figure 12 through Figure 14) G006 Figure 13. Maximum Switching Frequency (555 kHz) With Modulation Enabled, Rmod = 12 kΩ, IL = 200 mA G007 Figure 14. Modulation Frequency (Full Span) of 28 kHz 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 TYPICAL CHARACTERISTICS (continued) (Reference L1 Terminal, see Figure 12 through Figure 14) VO 11 V, IL = 500 mA V(driver) 5 V, IL = 500 mA 2 V, IL = 225 mA Figure 15. Input Voltage Excursions (Similar to Low-Crank Conditions) G015 Figure 16. Switch-Mode Regulator Transition From Buck Mode to Boost Mode, IL = 400 mA Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 19 TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) (Reference L1 Terminal, see Figure 12 through Figure 14) G016 Figure 17. Switch-Mode Regulator Transition From Boost Mode to Buck Mode, IL = 400 mA Modulation Off LO G 10 dB /div Modulation = 28 kHz G017 NOTE: These values represent conducted EMI results of a test board for display purposes only. Actual results may vary greatly depending on board layout and external components and must be verified in actual application. Figure 18. Conducted Emissions on Test Board Showing Effects of Switching-Frequency Modulation 20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 TYPICAL CHARACTERISTICS (continued) LO G 10 dB /div (Reference L1 Terminal, see Figure 12 through Figure 14) Slew Rate = 11 Slew Rate = 00 G018 NOTE: These values represent conducted EMI results of a test board for display purposes only. Actual results may vary greatly depending on board layout and external components and must be verified in actual application. Figure 19. Conducted Emissions on Test Board Showing Effects of Minimum and Maximum Slew Rate Settings Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 21 TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com APPLICATION INFORMATION To maximize the efficiency of this package for application on a single-layer or multilayer PCB, certain guidelines must be followed when laying out this device on the PCB. The following information is to be used as a guideline only. For further information see the PowerPAD Thermally Enhanced Package technical brief (SLMA002). The following are guidelines for mounting the PowerPAD™ IC on a multilayer PCB with a ground plane. Solder Pad (Land Pattern) Package Thermal Pad Thermal Vias Package Outline M0026-01 Figure 20. Package and PCB Land Configuration for a Multilayer PCB Power Pad Package Solder Pad Component Traces 1,5038-mm–1,5748-mm Component Trace (2-oz. Cu) 2 Plane 4 Plane Thermal Via 1,5748 mm Thermal Isolation Power Plane Only 1,0142-mm–1,0502-mm Ground Plane (1-oz. Cu) 0,5246-mm–0,5606-mm Power Plane (1-oz. Cu) 0-mm–0,071-mm Board Base and Bottom Pad Package Solder Pad (Bottom Trace) M0027-01 Figure 21. Multilayer Board (Side View) In a multilayer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane. The efficiency of this method depends on several factors (die area, number of thermal vias, thickness of copper, etc.). See the PowerPAD Thermally Enhanced Package technical brief (SLMA002). 22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 Use as Much Copper Area as Possible for Heat Spread Package Thermal Pad Package Outline M0028-01 Figure 22. Land Configuration for Single-Layer PCB Layout recommendation is to use as much copper area for the power-management section of a single-layer board as possible. In a single-layer board application, the thermal pad is attached to a heat spreader (copper areas) by using a low-thermal-impedance attachment method (solder paste or thermal-conductive epoxy). In both of these cases, it is advisable to use as much copper and as many traces as possible to dissipate the heat. IMPORTANT When this attachment method is not implemented correctly, this product may operate inefficiently. Power dissipation capability may be adversely affected when the device is incorrectly mounted onto the circuit board. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 23 TPS55065-Q1 SLIS132 – OCTOBER 2008 ............................................................................................................................................................................................... www.ti.com 22 µH–100 µH 4.7 nF 4.7 nF L1 L2 Cboot1 VOUT 5V 22 µF–470 µF Cboot2 L Vbattery Vdriver C 5Vg R2 5V AIN 1 µF–100 µF R1 TPS55065 5V ENABLE 5 kW Vlogic 470 nF Optional Connection RESET 5 kW 5Vg_ENABLE REST 2.2 nF–150 nF CLP AOUT SCR1 SCR0 Rmod 12 kW GND PGND S0183-01 A. To minimize voltage ripple on the output due to transients, it is recommended to use a low-ESR capacitor on the VOUT line. B. The L and C component values are system application dependent for EMI consideration. Figure 23. Application Schematic Layout Guidelines for Switch-Mode Power Supply The following guidelines are recommended for PCB layout of the TPS55065 device. Inductor Use a low-EMI inductor with a ferrite-type closed core. Other types of inductors may be used; however, they must have low-EMI characteristics and be located away from the low-power traces and components in the circuit. Filter Capacitors Input ceramic filter capacitors should be located in the close proximity of the Vdriver terminal. Surface-mount capacitors are recommended to minimize lead length and reduce noise coupling. Traces and Ground Plane All power (high-current) traces should be thick and as short as possible. The inductor and output capacitors should be as close to each other as possible. This reduces EMI radiated by the power traces due to high switching currents. 24 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated TPS55065-Q1 www.ti.com ............................................................................................................................................................................................... SLIS132 – OCTOBER 2008 In a two-sided PCB, it is recommended to have ground planes on both sides of the PCB to help reduce noise and ground-loop errors. The ground connection for the input and output capacitors and IC ground should be connected to this ground plane. In a multilayer PCB, the ground plane is used to separate the power plane (where high switching currents and components are placed) from the signal plane (where the feedback trace and components are) for improved performance. Also, arrange the components such that the switching-current loops curl in the same direction. Place the high-current components such that during conduction, the current path is in the same direction. This prevents magnetic field reversal caused by the traces between the two half-cycles, helping to reduce radiated EMI. Buck Mode • Select inductor ripple current DIL: for example ΔIL = 0.2 × IOUT • Calculate inductor L: ǒV IN * V OUTǓ V OUT L+ f SW DI L V IN • • (1) where fSW is the regulator switching frequency. Inductor peak current: DI I L,max + I OUT ) L 2 Output voltage ripple: DV OUT + DI L ǒESR ) 8 (2) Ǔ 1 f SW COUT (3) Usually, the first term is dominant. I pk(t on ) t off) C OUT + 8 Vripple (4) Boost Mode • Select inductor ripple current ΔIL: for example ΔIL = 0.2 × IIN • Calculate inductor L: ǒV OUT * V INǓ V IN L+ f SW DI L V OUT • • (5) where fSW is the regulator switching frequency. Inductor peak current: DI I p + I L,max + I IN ) L 2 Output voltage ripple: I OUT DV OUT + I p ESR ) ǒ1 * f SW Copyright © 2008, Texas Instruments Incorporated V IN V (6) Ǔ OUT COUT (7) Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 12-Nov-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPS55065QPWPRQ1 ACTIVE HTSSOP PWP Pins Package Eco Plan (2) Qty 20 2000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page www.ti.com/video e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated