TI THS4500IDGK

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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
FEATURES
D Fully Differential Architecture
D Bandwidth: 370 MHz
D Slew Rate: 2800 V/µs
D IMD3: −90 dBc at 30 MHz
D OIP3: 49 dBm at 30 MHz
D Output Common-Mode Control
D Wide Power Supply Voltage Range: 5 V, ±5 V,
APPLICATIONS
D High Linearity Analog-to-Digital Converter
Preamplifier
Wireless Communication Receiver Chains
Single-Ended to Differential Conversion
D
D
D Differential Line Driver
D Active Filtering of Differential Signals
VIN−
1
8
VIN+
VOCM
2
7
PD
VS+
3
6
VS−
VOUT+
4
5
VOUT−
12 V, 15 V
D Input Common-Mode Range Shifted to
Include the Negative Power Supply Rail
D Power-Down Capability (THS4500)
D Evaluation Module Available
RELATED DEVICES
DESCRIPTION
DEVICE(1)
The THS4500 and THS4501 are high-performance fully
differential amplifiers from Texas Instruments. The
THS4500, featuring power-down capability, and the
THS4501, without power-down capability, set new
performance standards for fully differential amplifiers
with unsurpassed linearity, supporting 14-bit operation
through 40 MHz. Package options include the 8-pin
SOIC and the 8-pin MSOP with PowerPAD for a
smaller footprint, enhanced ac performance, and
improved thermal dissipation capability.
370 MHz, 2800 V/µs, VICR Includes VS−
THS4502/3
370 MHz, 2800 V/µs, Centered VICR
THS4120/1
3.3 V, 100 MHz, 43 V/µs, 3.7 nV√Hz
THS4130/1
±15 V, 150 MHz, 51 V/µs, 1.3 nV√Hz
THS4140/1
±15 V, 160 MHz, 450 V/µs, 6.5 nV√Hz
THS4150/1
±15 V, 150 MHz, 650 V/µs, 7.6 nV√Hz
(1) Even numbered devices feature power-down capability
5V
VS
0.1 µF
374 Ω
+
56.2 Ω
5V
10 µF
24.9 Ω
−
ADC
12 Bit/80 MSps
IN
VOCM
1 µF
−
IN
+
24.9 Ω
402 Ω
392 Ω
10 pF
Vref
THIRD-ORDER INTERMODULATION
DISTORTION
−62
10
VS = 5 V
−68
VS = ±5 V
−74
12
Bits
392 Ω
IMD 3 − Third-Order Intermodulation Distortion − dBc
10 pF
APPLICATION CIRCUIT DIAGRAM
50 Ω
DESCRIPTION
THS4500/1
−80
392 Ω
50 Ω
−86
374 Ω
2.5 V
56.2 Ω
VS
−92
402 Ω
VS+
VOUT
+−
−+
VS−
392 Ω
−98
10
20
30
40
50
60
14
800 Ω
VOCM
70
80
90
16
100
f − Frequency − MHz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
! "#$%&'( $#()(! * (+#,&)#( $%,,'( )! #+ -%./$)#( ")'0 ,#"%$! $#(+#,& # !-'$+$)#(! -',
' ',&! #+ '1)! (!,%&'(! !)(")," 2),,)(30 ,#"%$#( -,#$'!!(4 "#'!
(# ('$'!!),/3 ($/%"' '!(4 #+ )// -),)&'',!0
Copyright  2002−2004, Texas Instruments Incorporated
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
16.5 V
Supply voltage, VS
±VS
Input voltage, VI
Output current, IO (2)
150 mA
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
4V
Differential input voltage, VID
Continuous power dissipation
See Dissipation Rating Table
Maximum junction temperature, TJ (3)
150°C
Maximum junction temperature, continuous
operation, long term reliability TJ (4)
125°C
Operating free-air temperature
range, TA
PACKAGE DISSIPATION RATINGS
PACKAGE
θJC
(°C/W)
θJA(1)
(°C/W)
D (8 pin)
38.3
97.5
POWER RATING(2)
TA ≤ 25°C
1.02 W
TA = 85°C
410 mW
685 mW
C suffix
0°C to 70°C
DGN (8 pin)
4.7
58.4
1.71 W
I suffix
−40°C to 85°C
DGK (8 pin)
54.2
260
385 mW
Storage temperature range, Tstg
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
ESD ratings:
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
−65°C to 150°C
300°C
HBM
4000 V
CDM
2000 V
MM
100 V
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2) The THS4500/1 may incorporate a PowerPAD on the underside
of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical briefs SLMA002 and SLMA004 for more information
about utilizing the PowerPAD thermally enhanced package.
(3) The absolute maximum temperature under any condition is
limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is
limited by package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device.
154 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C.
This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the
junction temperature at or below 125°C for best performance and
long term reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Dual supply
Supply voltage
Operating freeair temperature,
TA
NOM
MAX
±5
±7.5
5
15
Single supply
4.5
C suffix
0
70
I suffix
−40
85
UNIT
V
°C
PACKAGE/ORDERING INFORMATION
ORDERABLE PACKAGE AND NUMBER
TEMPERATURE
0°C to 70°C
−40°C to 85°C
PLASTIC MSOP(1)
PowerPad
PLASTIC
SMALL OUTLINE
(D)
(DGN)
THS4500CD
THS4501CD
THS4500ID
PLASTIC MSOP(1)
SYMBOL
(DGK)
SYMBOL
THS4500CDGN
BFB
THS4500CDGK
ATV
THS4501CDGN
BFD
THS4501CDGK
ATW
THS4500IDGN
BFC
THS4500IDGK
ASV
THS4501ID
THS4501IDGN
BFE
THS4501IDGK
ASW
(1) All packages are available taped and reeled. The R suffix standard quantity is 2500. The T suffix standard quantity is 250 (e.g., THS4501DT).
2
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
PIN ASSIGNMENTS
D, DGN, DGK
THS4500
(TOP VIEW)
V IN−
D, DGN, DGK
THS4501
(TOP VIEW)
1
8
V IN+
V IN−
2
7
PD
V OCM
V S+
3
6
V S−
V OUT+
4
5
V OUT−
V OCM
1
8
V IN+
2
7
NC
V S+
3
6
V S−
V OUT+
4
5
V OUT−
ELECTRICAL CHARACTERISTICS VS = ±5 V
Rf = Rg = 392 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted.
THS4500 AND THS4501
PARAMETER
TEST CONDITIONS
TYP
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
−40°C to
85°C
UNITS
MIN/
TYP/
MAX
AC PERFORMANCE
G = +1, PIN= −20 dBm, Rf = 392 Ω
370
MHz
Typ
G = +2, PIN= −30 dBm, Rf = 1 kΩ
175
MHz
Typ
G = +5, PIN= −30 dBm, Rf = 2.4 kΩ
70
MHz
Typ
G = +10, PIN = −30 dBm, Rf = 5.1 kΩ
30
MHz
Typ
G > +10
300
MHz
Typ
PIN = −20 dBm
VP = 2 V
150
MHz
Typ
220
MHz
Typ
Slew rate
4 VPP Step
2800
V/µs
Typ
Rise time
2 VPP Step
0.4
ns
Typ
Fall time
2 VPP Step
0.5
ns
Typ
Settling time to 0.01%
VO = 4 VPP
VO = 4 VPP
8.3
ns
Typ
6.3
ns
Typ
f = 8 MHz
−82
dBc
Typ
f = 30 MHz
−71
dBc
Typ
f = 8 MHz
−97
dBc
Typ
f = 30 MHz
−74
dBc
Typ
VO = 2 VPP, fc = 30 MHz,
Rf = 392 Ω, 200 kHz tone spacing
−90
dBc
Typ
fc = 30 MHz, Rf = 392 Ω,
Referenced to 50 Ω
49
dBm
Typ
Small-signal bandwidth
Gain-bandwidth product
Bandwidth for 0.1dB flatness
Large-signal bandwidth
0.1%
Harmonic distortion
2nd harmonic
3rd harmonic
Third-order intermodulation
distortion
Third-order output intercept point
G = +1, VO = 2 VPP
Typ
Input voltage noise
f > 1 MHz
7
nV/√Hz
Typ
Input current noise
f > 100 kHz
1.7
pA/√Hz
Typ
Overdrive = 5.5 V
60
ns
Typ
Overdrive recovery time
3
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS VS = ±5 V
Rf = Rg = 392 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted (continued).
THS4500 AND THS4501
PARAMETER
TEST CONDITIONS
TYP
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
−40°C to
85°C
UNITS
MIN/
TYP/
MAX
DC PERFORMANCE
Open-loop voltage gain
55
52
50
50
dB
Min
Input offset voltage
−4
−7 / −1
−8 / 0
−9 / +1
mV
Max
±10
±10
µV/°C
Typ
4
4.6
5
5.2
µA
Max
±10
±10
nA/°C
Typ
0.5
1
2
2
µA
Max
±40
±40
nA/°C
Typ
−5.4 / 2.3
−5.1 / 2
−5.1 / 2
V
Min
80
107 || 1
74
70
70
Average offset voltage drift
Input bias current
Average bias current drift
Input offset current
Average offset current drift
INPUT
−5.7/2.
6
Common-mode input range
Common-mode rejection ratio
Input impedance
dB
Min
Ω || pF
Typ
OUTPUT
RL = 1 kΩ
RL = 20 Ω
±8
±7.6
±7.4
±7.4
V
Min
120
110
100
100
mA
Min
PIN = −20 dBm, f = 100 kHz
−58
dB
Typ
f = 1 MHz
0.1
Ω
Typ
RL = 400 Ω
2 VPP step
180
MHz
Typ
92
V/µs
Typ
Differential output voltage swing
Differential output current drive
Output balance error
Closed-loop output impedance
(single-ended)
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
Slew rate
Minimum gain
1
0.98
0.98
0.98
V/V
Min
Maximum gain
1
1.02
1.02
1.02
V/V
Max
−0.4
−4.6/+3.8
−6.6/+5.8
−7.6/+6.8
mV
Max
100
150
170
170
µA
Max
±4
±3.7
±3.4
±3.4
V
Min
kΩ || pF
Typ
0
0.05
0.10
0.10
V
Max
0
−0.05
−0.10
−0.10
V
Min
Specified operating voltage
±5
7.5
7.5
7.5
V
Max
Maximum quiescent current
23
28
32
34
mA
Max
Minimum quiescent current
23
18
14
12
mA
Min
Power supply rejection (±PSRR)
80
76
73
70
dB
Min
Common-mode offset voltage
Input bias current
VOCM = 2.5 V
Input voltage range
Input impedance
Maximum default voltage
Minimum default voltage
25 || 1
VOCM left floating
VOCM left floating
POWER SUPPLY
POWER DOWN (THS4500 ONLY)
Enable voltage threshold
Device enabled ON above –2.9 V
−2.9
V
Min
Disable voltage threshold
Device disabled OFF below –4.3 V
−4.3
V
Max
µA
Max
Power-down quiescent current
800
1000
1200
1200
Input bias current
200
240
260
260
µA
Max
Input impedance
50 || 1
kΩ || pF
Typ
Turnon time delay
1000
ns
Typ
Turnoff time delay
800
ns
Typ
4
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS VS = 5 V
Rf = Rg = 392 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted.
THS4500 AND THS4501
PARAMETER
TEST CONDITIONS
TYP
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
−40°C to
85°C
UNITS
MIN/
TYP/
MAX
AC PERFORMANCE
G = +1, PIN = −20 dBm, Rf = 392 Ω
320
MHz
Typ
G = +2, PIN = −30 dBm, Rf = 1 kΩ
G = +5, PIN = −30 dBm, Rf = 2.4 kΩ
160
MHz
Typ
60
MHz
Typ
G = +10, PIN = −30 dBm, Rf = 5.1 kΩ
30
MHz
Typ
G > +10
300
MHz
Typ
PIN = −20 dBm
VP = 1 V
180
MHz
Typ
200
MHz
Typ
Slew rate
2 VPP Step
1300
V/µs
Typ
Rise time
2 VPP Step
0.5
ns
Typ
Fall time
2 VPP Step
0.6
ns
Typ
VO = 2 V Step
VO = 2 V Step
13.1
ns
Typ
8.3
ns
Typ
f = 8 MHz,
−80
dBc
Typ
f = 30 MHz
−55
dBc
Typ
f = 8 MHz
−76
dBc
Typ
Small-signal bandwidth
Gain-bandwidth product
Bandwidth for 0.1 dB flatness
Large-signal bandwidth
Settling time to 0.01%
0.1%
Harmonic distortion
2nd harmonic
3rd harmonic
G = +1, VO = 2 VPP
Typ
f = 30 MHz
−60
dBc
Typ
Input voltage noise
f > 1 MHz
7
nV/√Hz
Typ
Input current noise
f > 100 kHz
1.7
pA/√Hz
Typ
Overdrive = 5.5 V
60
ns
Typ
Overdrive recovery time
DC PERFORMANCE
Open-loop voltage gain
54
51
49
49
dB
Min
Input offset voltage
−4
−7 / −1
−8 / 0
−9 / +1
mV
Max
±10
±10
µV/°C
Typ
4
4.6
5
5.2
µA
Max
±10
±10
nA/°C
Typ
0.5
0.7
1.2
1.2
µA
Max
±20
±20
nA/°C
Typ
−0.4 / 2.3
−0.1 / 2
−0.1 / 2
V
Min
80
107 || 1
74
70
70
Average offset voltage drift
Input bias current
Average bias current drift
Input offset current
Average offset current drift
INPUT
−0.7/2.
6
Common-mode input range
Common-mode rejection ratio
Input Impedance
dB
Min
Ω || pF
Typ
OUTPUT
RL = 1 kΩ, Referenced to 2.5 V
RL = 20 Ω
±3.3
±3
±2.8
±2.8
V
Min
Output current drive
100
90
80
80
mA
Min
Output balance error
PIN = −20 dBm, f = 100 kHz
−58
dB
Typ
f = 1 MHz
0.1
Ω
Typ
Differential output voltage swing
Closed-loop output impedance
(single-ended)
5
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS VS = 5 V
Rf = Rg = 392 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted (continued).
THS4500 AND THS4501
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
0°C to
70°C
−40°C
to 85°C
UNITS
MIN/
MAX
180
MHz
Typ
80
V/µs
Typ
25°C
25°C
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
Slew rate
RL = 400 Ω
2 VPP Step
Minimum gain
1
0.98
0.98
0.98
V/V
Min
Maximum gain
1
1.02
1.02
1.02
V/V
Max
0.4
−2.6/3.4
−4.2/5.4
−5.6/6.4
mV
Max
1
2
3
3
µA
Max
1/4
1.2 / 3.8
1.3 / 3.7
1.3 / 3.7
V
Min
kΩ || pF
Typ
2.5
2.55
2.6
2.6
V
Max
2.5
2.45
2.4
2.4
V
Min
Specified operating voltage
5
15
15
15
V
Max
Maximum quiescent current
20
25
29
31
mA
Max
Minimum quiescent current
20
16
12
10
mA
Min
Power supply rejection (+PSRR)
75
72
69
66
dB
Min
Common-mode offset voltage
Input bias current
VOCM = 2.5 V
Input voltage range
Input impedance
Maximum default voltage
Minimum default voltage
25 || 1
VOCM left floating
VOCM left floating
POWER SUPPLY
POWER DOWN (THS4500 ONLY)
Enable voltage threshold
Device enabled ON above 2.1 V
2.1
V
Min
Disable voltage threshold
Device disabled OFF below 0.7 V
0.7
V
Max
Power-down quiescent current
600
800
1200
1200
µA
Max
Input bias current
100
125
140
140
µA
Max
Input impedance
50 || 1
kΩ || pF
Typ
Turnon time delay
1000
ns
Typ
Turnoff time delay
800
ns
Typ
6
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
Small signal unity gain frequency response
1
Small signal frequency response
2
0.1 dB gain flatness frequency response
3
Large signal frequency response
Harmonic distortion (single-ended input to differential output) vs Frequency
4
5, 7, 13, 15
Harmonic distortion (differential input to differential output) vs Frequency
6, 8, 14, 16
Harmonic distortion (single-ended input to differential output) vs Output voltage swing
9, 11, 17, 19
Harmonic distortion (differential input to differential output) vs Output voltage swing
10, 12, 18, 20
Harmonic distortion (single-ended input to differential output) vs Load resistance
21
Harmonic distortion (differential input to differential output) vs Load resistance
22
Third order intermodulation distortion (single-ended input to differential output) vs Frequency
23
Third order output intercept point vs Frequency
24
Slew rate vs Differential output voltage step
25
Settling time
Large signal transient response
Small signal transient response
Overdrive recovery
26, 27
28
29
30, 31
Voltage and current noise vs Frequency
32
Rejection ratios vs Frequency
33
Rejection ratios vs Case temperature
34
Output balance error vs Frequency
35
Open-loop gain and phase vs Frequency
36
Open-loop gain vs Case temperature
37
Input bias offset current vs Case temperature
38
Quiescent current vs Supply voltage
39
Input offset voltage vs Case temperature
40
Common-mode rejection ratio vs Input common-mode range
41
Output drive vs Case temperature
42
Harmonic distortion (single-ended and differential input to differential output) vs Output common-mode voltage
43
Small signal frequency response at VOCM
44
Output offset voltage at VOCM vs Output common-mode voltage
45
Quiescent current vs Power-down voltage
46
Turnon and turnoff delay times
47
Single-ended output impedance in power down vs Frequency
48
Power-down quiescent current vs Case temperature
49
Power-down quiescent current vs Supply voltage
50
7
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs (5 V)
FIGURE
Small signal unity gain frequency response
51
Small signal frequency response
52
0.1 dB gain flatness frequency response
53
Large signal frequency response
54
Harmonic distortion (single-ended input to differential output) vs Frequency
55, 57, 63, 65
Harmonic distortion (differential input to differential output) vs Frequency
56, 58, 64, 66
Harmonic distortion (single-ended input to differential output) vs Output voltage swing
59, 61, 67, 69
Harmonic distortion (differential input to differential output) vs Output voltage swing
60, 62, 68, 70
Harmonic distortion (single-ended input to differential output) vs Load resistance
71
Harmonic distortion (differential input to differential output) vs Load resistance
72
Third-order intermodulation distortion vs Frequency
73
Third-order intercept point vs Frequency
74
Slew rate vs Differential output voltage step
75
Large-signal transient response
76
Small-signal transient response
77
Voltage and current noise vs Frequency
78
Rejection ratios vs Frequency
79
Rejection ratios vs Case temperature
80
Output balance error vs Frequency
81
Open-loop gain and phase vs Frequency
82
Open-loop gain vs Case temperature
83
Input bias offset current vs Case temperature
84
Quiescent current vs Supply voltage
85
Input offset voltage vs Case temperature
86
Common-mode rejection ratio vs Input common-mode range
87
Output drive vs Case temperature
88
Harmonic distortion (single-ended and differential input) vs Output common-mode voltage
89
Small signal frequency response at VOCM
90
Output offset voltage vs Output common-mode voltage
91
Quiescent current vs Power-down voltage
92
Turnon and turnoff delay times
93
Single-ended output impedance in power down vs Frequency
94
Power-down quiescent current vs Case temperature
95
Power-down quiescent current vs Supply voltage
96
8
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (±5 V Graphs)
1
22
0.5
20
−0.5
−1
−1.5
−2
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −20 dBm
VS = ±5 V
−2.5
−3
0.1
1
16
14
Gain = 5, Rf = 2.4 kΩ
12
10
8
Gain = 2, Rf = 1 kΩ
6
4
2
10
100
0
−2
0.1
1000
f − Frequency − MHz
RL = 800 Ω
PIN = −30 dBm
VS = ±5 V
1
−0.3
10
100
1000
−1
−2
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = 10 dBm
VS = ±5 V
−20
−30
−40
−50
100
1000
100
−70
HD2
−80
HD3
1
HD2
HD3
−90
1
10
f − Frequency − MHz
−20
−30
−40
−50
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = ±5 V
−70
HD2
−80
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 8 MHz
VS = ±5 V
−10
−90
100
100
Figure 6
−60
−100
0.1
10
f − Frequency − MHz
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−70
Figure 7
−60
−100
0.1
0
−10
−60
−100
0.1
−50
HARMONIC DISTORTION
vs
FREQUENCY
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = ±5 V
−80
−40
Figure 5
0
−50
−30
f − Frequency − MHz
HARMONIC DISTORTION
vs
FREQUENCY
−40
10
−20
−90
HD3
1
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = ±5 V
−10
HD2
−80
Figure 4
−30
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = ±5 V
−70
f − Frequency − MHz
1000
HARMONIC DISTORTION
vs
FREQUENCY
−60
−100
0.1
100
f − Frequency − MHz
Figure 3
−90
−4
−20
10
1
Harmonic Distortion − dBc
Harmonic Distortion − dBc
0
−10
Rf = 392 Ω
−0.1
−0.2
0
−10
10
0
HARMONIC DISTORTION
vs
FREQUENCY
1
1
Rf = 499 Ω
Figure 2
LARGE SIGNAL FREQUENCY RESPONSE
0.1
0.1
f − Frequency − MHz
Figure 1
−3
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = ±5 V
0.2
0.1 dB Gain Flatness − dB
0
−4
Large Signal Gain − dB
0.3
Gain = 10, Rf = 5.1 kΩ
18
−3.5
Harmonic Distortion − dBc
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
Small Signal Gain − dB
Small Signal Unity Gain − dB
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
−20
−30
−40
−50
−60
−70
HD2
−80
−90
HD3
HD3
−100
1
10
f − Frequency − MHz
Figure 8
100
0
0.5
1
1.5 2
2.5
3
3.5 4
4.5
5
VO − Output Voltage Swing − V
Figure 9
9
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (±5 V Graphs)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
−20
−30
−40
−50
−60
−70
HD2
−80
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
−10
Harmonic Distortion − dBc
−90
−20
−30
−40
−50
−60
HD2
−70
−80
HD3
−90
HD3
−100
0.5
1
1.5 2
2.5
3
3.5 4
4.5
5
0
0.5
VO − Output Voltage Swing − V
1
−60
−70
HD2
−80
3
3.5 4
4.5
−100
0.1
1
10
f − Frequency − MHz
−20
−30
−40
0
HD3
−80
−70
−80
HD3
1
10
f − Frequency − MHz
Figure 16
100
3.5 4
4.5
5
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = ±5 V
−20
−30
−40
−50
−60
HD2
−70
−80
HD3
−100
100
0.1
1
10
f − Frequency − MHz
100
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 8 MHz
VS = ±5 V
−20
−30
−40
−50
−60
−70
HD2
−80
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 8 MHz
VS = ±5 V
−10
−20
−30
−40
−50
−60
−70
−80
HD2
−90
HD3
−100
1
10
f − Frequency − MHz
3
Figure 15
−90
−90
2.5
−90
0
HD2
1.5 2
0
HD2
−70
−10
−50
−100
0.1
1
HARMONIC DISTORTION
vs
FREQUENCY
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = ±5 V
−60
0.5
Figure 14
Harmonic Distortion − dBc
−40
HD3
−10
−60
−100
0.1
100
0
−30
−80
Figure 12
−50
HARMONIC DISTORTION
vs
FREQUENCY
−20
HD2
−70
VO − Output Voltage Swing − V
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = ±5 V
Figure 13
−10
−60
−100
5
−90
HD3
Harmonic Distortion − dBc
2.5
Harmonic Distortion − dBc
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−50
−10
−90
10
1.5 2
0
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = ±5 V
−40
−50
HARMONIC DISTORTION
vs
FREQUENCY
0
−30
−40
Figure 11
HARMONIC DISTORTION
vs
FREQUENCY
−20
−30
VO − Output Voltage Swing − V
Figure 10
−10
−20
−90
−100
0
Differentia Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
−10
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−10
Harmonic Distortion − dBc
0
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HD3
−100
0
0.5
1
1.5 2
2.5
3
3.5 4
VO − Output Voltage Swing − V
Figure 17
4.5
5
0
0.5
1
1.5 2
2.5
3
3.5 4
VO − Output Voltage Swing − V
Figure 18
4.5
5
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (±5 V Graphs)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−20
−30
−40
−50
HD2
−60
Differentia Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 8 MHz
VS = ±5 V
−10
Harmonic Distortion − dBc
−70
−80
HD3
−90
−20
−30
−40
−50
−60
HD2
−70
−80
HD3
−90
−100
1
1.5 2
2.5
3
3.5 4
4.5
5
VO − Output Voltage Swing − V
Harmonic Distortion − dBc
Third-Order Intermodulation Distortion − dBc
Differential Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
−40
−50
−60
HD2
−70
−80
HD3
−90
−100
0
400
800
0.5
1
1.5 2
3
3.5 4
4.5
1200
1600
0
400
800
1200
1600
Figure 21
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
−60
−70
−80
−90
−100
10
100
Gain = 1
Rf = 392 Ω
VO = 2 VPP
VS = ± 5 V
50
45
40
35
30
0
20
40
60
80
100
120
f − Frequency − MHz
Figure 23
Figure 24
SETTLING TIME
SETTLING TIME
0.8
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VS = ±5 V
1.5
Rising Edge
Rising Edge
0.6
VO − Output Voltage − V
1
2000
1500
1000
0.4
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = ±5 V
0.2
0
−0.2
−0.4
Falling Edge
500
2.5
3 3.5
4
4.5
VO − Differential Output Voltage Step − V
Figure 25
5
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = ±5 V
0.5
0
−0.5
Falling Edge
−1
−0.6
1.5 2
HD3
f − Frequency − MHz
3000
0.5 1
−80
55
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE STEP
0
HD2
−70
RL − Load Resistance − Ω
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = ±5 V
Figure 22
0
−60
5
−50
RL − Load Resistance − Ω
2500
2.5
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
0
−30
−50
Figure 20
HARMONIC DISTORTION
vs
LOAD RESISTANCE
−20
−40
VO − Output Voltage Swing − V
Figure 19
−10
−30
−100
0
Third-Order Output Intersept Point − dBm
0.5
−20
−90
−100
0
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 30 MHz
VS = ±5 V
−10
VO − Output Voltage − V
Harmonic Distortion − dBc
0
0
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 30 MHz
VS = ±5 V
Harmonic Distortion − dBc
0
−10
SR − Slew Rate − V/ µ s
HARMONIC DISTORTION
vs
LOAD RESISTANCE
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
−0.8
0
5
10
t − Time − ns
Figure 26
15
20
−1.5
0
20
40
60
80
100
120
140
t − Time − ns
Figure 27
11
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (±5 V Graphs)
SMALL-SIGNAL TRANSIENT RESPONSE
1.5
0.3
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
0
−0.5
−1
0.2
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
0.1
0
−0.1
−0.2
−0.3
−1.5
−2
−100
0
100
200
300
400
−0.4
−100
500
0
100
Figure 28
−0.5
−2
−1
−3
−1.5
−4
−2
−2.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−1
−1
−2
−3
−2
−4
REJECTION RATIOS
vs
FREQUENCY
90
Hz
0
0
Figure 30
I n − Current Noise − pA/
1
Vn
10
PSRR+
80
70
60
50
CMMR
PSRR−
40
30
20
In
10
RL = 800 Ω
VS = ±5 V
0
1
0.01
−3
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t − Time − µs
0.1
1
10
100
1000
−10
10 k
0.1
Figure 31
Figure 32
REJECTION RATIOS
vs
CASE TEMPERATURE
OPEN-LOOP GAIN AND FHASE
vs
FREQUENCY
60
0
CMMR
80
60
40
20
RL = 800 Ω
VS = ±5 V
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 34
−20
30
Gain
PIN = 10 dBm
RL = 800 Ω
Rf = 392 Ω
VS = ±5 V
−10
Output Balance Error − dB
PSRR+
100
Figure 33
OUTPUT BALANCE ERROR
vs
FREQUENCY
120
100
1
10
f − Frequency − MHz
f − Frequency − kHz
PIN = −30 dBm
RL = 800 Ω
VS = ±5 V
50
Open-Loop Gain − dB
0
Rejection Ratios − dB
−1
t − Time − µs
Hz
1
−5
−6
12
0
−5
500
Vn − Voltage Noise − nV/
2
VI − Input Voltage − V
Single-Ended Output Voltage − V
3
1
0
100
2
1.5
0.5
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
3
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 5.5 V
VS = ±5 V
4
400
2
1
Figure 29
OVERDRIVE RECOVERY
5
300
2
t − Time − ns
t − Time − ns
6
200
3
Rejection Ratios − dB
0.5
2.5
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 4.5 V
VS = ±5 V
4
−30
−40
−50
−60
40
0
−30
−60
30
Phase
Phase − °
1
OVERDRIVE RECOVERY
5
VI − Input Voltage − V
0.4
Single-Ended Output Voltage − V
2
VO − Output Voltage − V
VO − Output Voltage − V
LARGE-SIGNAL TRANSIENT RESPONSE
20
−90
10
−120
−70
−80
0.1
1
10
f − Frequency − MHz
Figure 35
100
0
0.01
0.1
1
10
f − Frequency − MHz
Figure 36
100
−150
1000
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (±5 V Graphs)
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
I IB − Input Bias Current − µ A
3.3
55
54
53
52
51
−0.02
3.2
IIB+
3.1
−0.03
3
−0.04
2.9
−0.05
2.8
−0.06
IOS
−0.07
50
2.6
−0.08
49
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−0.09
2.5
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 37
5
4
3
2
1
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
HD2-SE
−70
HD3-SE
HD3-Diff
−80
−90
−100
−3.5
−2.5 −1.5 −0.5
0.5
1.5
2.5
3.5
VOC − Output Common-Mode Voltage − V
Figure 43
0 0.5
1
1.5
3
3.5
4 4.5
5
200
VS = ±5 V
VS = ±5 V
Source
150
80
70
60
50
40
30
100
50
0
−50
20
10
Sink
−100
0
−10
−6 −5 −4 −3 −2 −1 0
1
2
3
4
5
−150
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
6
Case Temperature − °C
Figure 42
OUTPUT OFFSET VOLTAGE at VOCM
vs
OUTPUT COMMON-MODE VOLTAGE
600
3
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN= −20 dBm
VS = ±5 V
1
2.5
OUTPUT DRIVE
vs
CASE TEMPERATURE
90
2
2
VS − Supply Voltage − ±V
SMALL SIGNAL FREQUENCY RESPONSE
at VOCM
Small Signal Frequency Response at VOCM − dB
−40
HD2
-Diff
0
Figure 41
Single-Ended and Differential
Input to Differential Output
Gain = 1, VO = 2 VPP
f= 8 MHz, Rf = 392 Ω
VS = ±5 V
−60
5
Input Common-Mode Voltage Range − V
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE VOLTAGE
−50
10
110
Figure 40
−30
15
Figure 39
100
Case Temperature − °C
−20
TA = −40°C
20
Output Drive − mA
6
CMRR − Common-Mode Rejection Ratio − dB
VS = ±5 V
0
TA = 25°C
25
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
7
−10
TA = 85°C
30
Figure 38
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
VOS − Input Offset Voltage − mV
−0.01
2.7
Case Temperature − °C
Harmonic Distortion − dBc
IIB−
VOS − Output Offset Voltage − mV
Open-Loop Gain − dB
56
35
0
VS = ±5 V
Quiescent Current − mA
3.4
RL = 800 Ω
VS = ±5 V
I OS − Input Offset Current − µ A
58
57
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
0
−1
400
200
0
−200
−2
−400
−3
1
10
100
f − Frequency − MHz
Figure 44
1000
−600
−5 −4 −3 −2 −1
0
1
2
3
4
5
VOC − Output Common-Mode Voltage − V
Figure 45
13
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (±5 V Graphs)
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
TURNON AND TURNOFF DELAY TIME
0.03
20
15
10
5
0
ZO− Single-Ended Output Impedance
in Powerdown − Ω
Quiescent Current − mA
25
800
0.02
0.01
Current
0
0
−1
−2
−3
Quiescent Current − mA
Powerdown Voltage Signal − V
30
−4
−5
−5
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0
Power-Down Voltage − V
−6
0 0.5 1 1.5 2 2.5 3 100.5 101
t − Time − ms
102
700
600
500
400
300
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −1 dBm
VS = ±5 V
200
100
0
0.1
103
1
10
Figure 47
Figure 48
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERATURE
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
1000
1000
900
RL = 800 Ω
VS = ±5 V
800
700
600
500
400
300
200
100
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 49
100
f − Frequency − MHz
Power-Down Quiescent Current − µ A
Power-Down Quiescent Current − µ A
Figure 46
14
SINGLE-ENDED OUTPUT IMPEDANCE
IN POWER DOWN
vs
FREQUENCY
RL = 800 Ω
900
800
700
600
500
400
300
200
100
0
0
0.5 1
1.5 2
2.5 3
3.5 4
VS − Supply Voltage − ±V
Figure 50
4.5 5
1000
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
22
1
−2
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −20 dBm
VS = 5 V
−3
1
Gain = 5, Rf = 2.4 kΩ
14
12
10
8
Gain = 2, Rf = 1 kΩ
6
4
2
0
−2
0.1
−4
0.1
16
10
100
1000
0.1 dB Gain Flatness − dB
Small Signal Gain − dB
−1
0.1
f − Frequency − MHz
RL = 800 Ω
PIN = −30 dBm
VS = 5 V
1
10
100
−1
−2
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = 10 dBm
VS = 5 V
−30
−40
−50
−60
10
100
−70
−80
0.1
0
Harmonic Distortion − dBc
−10
−60
HD3
HD2
−80
−90
1
10
f − Frequency − MHz
−60
HD2
−70
−80
HD3
−100
0.1
100
1
10
f − Frequency − MHz
−20
−30
−40
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
10
f − Frequency − MHz
100
−60
HD3
HD2
−80
−100
0.1
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 8 MHz
VS = 5 V
−10
−50
−70
100
Figure 56
−20
−30
−40
−50
−60
HD3
−70
−80
HD2
−90
Figure 57
−50
HARMONIC DISTORTION
vs
FREQUENCY
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 2 VPP
VS = 5 V
1
−40
Figure 55
0
−100
0.1
−30
−90
HARMONIC DISTORTION
vs
FREQUENCY
−70
−20
HD3
Figure 54
−50
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = 5 V
−10
HD2
f − Frequency − MHz
−40
0
−100
1000
1000
HARMONIC DISTORTION
vs
FREQUENCY
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VO = 1 VPP
VS = 5 V
−20
100
f − Frequency − MHz
Figure 53
−90
−4
−30
10
1
Harmonic Distortion − dBc
Harmonic Distortion − dBc
0
−20
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = 5 V
−0.5
1000
0
−10
−10
−0.3
HARMONIC DISTORTION
vs
FREQUENCY
1
1
−0.2
Figure 52
LARGE SIGNAL FREQUENCY RESPONSE
0.1
Rf = 392 Ω
−0.1
f − Frequency − MHz
Figure 51
−3
0
−0.4
Harmonic Distortion − dBc
Small Signal Unity Gain − dB
Rf = 499 Ω
18
0
Large Signal Gain − dB
0.2
Gain = 10, Rf = 5.1 kΩ
20
Harmonic Distortion − dBc
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
−90
−100
1
10
f − Frequency − MHz
Figure 58
100
0
0.5
1
1.5
2
2.5
3
VO − Output Voltage Swing − V
Figure 59
15
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
Differentia Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 8 MHz
VS = 5 V
−20
−30
−40
−50
−60
HD3
−70
−80
−20
−30
−40
0.5
1
1.5
2
2.5
HD2
−70
−80
−40
0
0.5
1
1.5
2
2.5
−70
−80
3
0
VO − Output Voltage Swing − V
HD3
−60
−70
HD2
−80
−90
−20
−30
−40
−50
HD2
−60
−70
−80
HD3
1
10
−100
0.1
100
1
10
f − Frequency − MHz
f − Frequency − MHz
Figure 63
−40
−50
HD3
HD2
−80
−90
−100
0.1
1
10
f − Frequency − MHz
Figure 66
−60
HD3
−70
−80
HD2
1
10
f − Frequency − MHz
100
−20
−30
−40
0
HD3
−70
−80
HD2
−20
−30
−40
−50
−60
−80
−90
−100
−100
0.5
1
1.5
2
2.5
VO − Output Voltage Swing − V
Figure 67
3
HD3
−70
−90
0
Differentia Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 8 MHz
VS = 5 V
−10
−50
−60
100
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f = 8 MHz
VS = 5 V
−10
−60
−70
−50
Figure 65
0
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = 5 V
Harmonic Distortion − dBc
−30
−40
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
−20
−30
Figure 64
HARMONIC DISTORTION
vs
FREQUENCY
−10
−20
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 2 VPP
VS = 5 V
−100
0.1
100
Harmonic Distortion − dBc
0.1
3
−90
−90
−100
2.5
0
−10
Harmonic Distortion − dBc
−50
2
HARMONIC DISTORTION
vs
FREQUENCY
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = 5 V
−10
Harmonic Distortion − dBc
−40
1.5
Figure 62
0
−30
1
VO − Output Voltage Swing − V
HARMONIC DISTORTION
vs
FREQUENCY
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
VO = 1 VPP
VS = 5 V
−20
0.5
Figure 61
0
−10
HD2
−60
−90
3
HD3
−50
−100
HARMONIC DISTORTION
vs
FREQUENCY
Harmonic Distortion − dBc
−30
−100
Figure 60
Harmonic Distortion − dBc
−20
−90
VO − Output Voltage Swing − V
16
HD3
−60
−100
Differentia Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f= 30 MHz
VS = 5 V
−10
−50
HD2
−90
0
0
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 392 Ω
f = 30 MHz
VS = 5 V
−10
Harmonic Distortion − dBc
Harmonic Distortion − dBc
−10
Harmonic Distortion − dBc
0
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HD2
0
0.5
1
1.5
2
2.5
VO − Output Voltage Swing − V
Figure 68
3
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
0
−30
−40
−50
HD2
−60
HD3
−70
−20
−80
−30
−40
−60
HD3
−70
−80
−40
−60
−80
−90
−100
1.5
2
2.5
3
0
0.5
−40
−50
HD2
−60
HD3
−70
−80
−90
−100
0
400
800
1200
1600
Third-Order Intermodulation Distortion − dBc
Differentia Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 30 MHz
VS = 5 V
−30
−60
−70
800
600
400
200
−80
−90
−100
10
1
1.5
2
2.5
VO − Differential Output Voltage Step − V
Figure 75
3
1600
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
Gain = 1
VO = 2 VPP
Rf = 392 Ω
RL = 800 Ω
VS = 5 V
50
45
40
35
30
0
100
20
0.4
0.3
1
Gain = 1
RL = 800 Ω
Rf = 392 Ω
tr/tf = 300 ps
VS = 5 V
−0.5
80
100
120
SMALL-SIGNAL TRANSIENT RESPONSE
1.5
0
60
Figure 74
2
0.5
40
f − Frequency − MHz
−1
0.2
Gain = 1
RL = 800 Ω
Rf = 392 Ω
tr/tf = 300 ps
VS = 5 V
0.1
0
−0.1
−0.2
−0.3
−1.5
0
1200
55
LARGE-SIGNAL TRANSIENT RESPONSE
VO − Output Voltage − V
Gain = 1
RL = 800 Ω
Rf = 392 Ω
VS = 5 V
800
Figure 71
Figure 73
1400
0.5
400
RL − Load Resistance − Ω
f − Frequency − MHz
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE STEP
0
0
3
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
RL = 800 Ω
VS = 5 V
Figure 72
1000
2.5
−50
RL − Load Resistance − Ω
1200
2
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
0
−20
1.5
Figure 70
HARMONIC DISTORTION
vs
LOAD RESISTANCE
−10
1
VO − Output Voltage Swing − V
Third-Order Output Intersept Point − dBm
1
HD3
−70
−100
0.5
HD2
−50
−100
Figure 69
Harmonic Distortion − dBc
−30
−90
VO − Output Voltage Swing − V
SR − Slew Rate − V/ µ s
HD2
−50
−20
−90
0
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 30 MHz
VS = 5 V
−10
VO − Output Voltage − V
Harmonic Distortion − dBc
−20
0
Differentia Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f= 30 MHz
VS = 5 V
−10
Harmonic Distortion − dBc
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1 kΩ
f = 30 MHz
VS = 5 V
−10
Harmonic Distortion − dBc
0
HARMONIC DISTORTION
vs
LOAD RESISTANCE
−2
−100
0
100
200
300
t − Time − ns
Figure 76
400
500
−0.4
−100
0
100
200
300
400
500
t − Time − ns
Figure 77
17
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
120
90
In
60
50
CMMR
PSRR−
40
30
20
10
1
10
100
1000
0.1
20
1
10
f − Frequency − MHz
Figure 78
RL = 800 Ω
VS = 5 V
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
100
Case Temperature − °C
Figure 79
OUTPUT BALANCE ERROR
vs
FREQUENCY
Figure 80
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
60
30
Gain
PIN = −20 dBm
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
PIN = −30 dBm
RL = 800 Ω
VS = 5 V
Open-Loop Gain − dB
50
−30
−40
−50
−60
57
RL = 800 Ω
VS = 5 V
56
0
40
55
−30
Phase − °
0
−20
40
−10
10 k
f − Frequency − kHz
−10
PSRR+
60
−60
30
Phase
20
−90
10
−120
Open-Loop Gain − dB
0.1
PSRR−
80
RL = 800 Ω
VS = 5 V
0
1
0.01
CMMR
100
70
Rejection Ratios − dB
Hz
I n − Current Noise − pA/
Vn
10
PSRR+
80
Rejection Ratios − dB
Hz
Vn − Voltage Noise − nV/
100
Output Balance Error − dB
REJECTION RATIOS
vs
CASE TEMPERATURE
REJECTION RATIOS
vs
FREQUENCY
54
53
52
51
50
49
48
47
1
10
f − Frequency − MHz
100
1
10
100
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
2.75
−0.03
−0.04
2.5
2.25
−0.05
IOS
−0.06
2
−0.07
1.75
−0.08
−0.09
1.5
−0.1
1.25
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 84
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
4
30
TA = 25°C
−0.02
Quiescent Current − mA
IIB−
I OS − Input Offset Current − µ A
3
Figure 83
TA = 85°C
−0.01
IIB+
−40−30−20−100 10 20 30 40 50 60 70 80 90
35
0
VS = 5 V
46
Case Temperature − °C
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
3.5
−150
1000
f − Frequency − MHz
Figure 82
3.25
18
0.1
Figure 81
3.75
I IB − Input Bias Current − µ A
0
0.01
VOS − Input Offset Voltage − mV
−70
0.1
25
TA = −40°C
20
15
10
5
0
0 0.5
1
1.5
2
2.5
3
3.5
VS − Supply Voltage − ±V
Figure 85
4 4.5
5
3.5
VS = 5 V
3
2.5
2
1.5
1
0.5
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 86
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
OUTPUT DRIVE
vs
CASE TEMPERATURE
110
90
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE VOLTAGE
0
150
VS = 5 V
VS = 5 V
100
Source
Harmonic Distortion − dBc
100
Output Drive − mA
70
60
50
40
30
50
0
−50
20
−100
10
0
−10
−1
0
1
2
3
4
Sink
5
−50
HD3-SE
and Diff
−60
−70
−80
HD2-SE
VOCM − Output Common-Mode Voltage − V
Figure 89
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
25
800
1
0
VS = 5 V
600
Quiescent Current − mA
VOS − Output Offset Voltage − mV
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN= −20 dBm
VS = 5 V
400
200
0
−200
−1
HD2-Diff
1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
OUTPUT OFFSET VOLTAGE
vs
OUTPUT COMMON-MODE VOLTAGE
4
2
−40
Figure 88
SMALL SIGNAL FREQUENCY RESPONSE
at VOCM
3
−30
−90
Case Temperature − °C
Figure 87
−20
−100
−150
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Input Common-Mode Range − V
Single-Ended and
Differential Input
Gain = 1
VO = 2 VPP
Rf = 392 Ω
f= 8 MHz, VS = 5 V
−10
80
−400
20
15
10
5
−600
−2
−800
−3
1
10
100
0
0 0.5
1000
1
1.5
2
2.5
3
3.5
4
4.5
5
VOC − Output Common-Mode Voltage − V
f − Frequency − MHz
Figure 90
Figure 91
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Power-down Voltage − V
Figure 92
TURNON AND TURNOFF DELAY TIME
0.03
0.02
0.01
Current
0
0
−1
−2
−3
Quiescent Current − mA
0.1
Power-Down Voltage Signal − V
Small Signal Frequency Response at VOCM − dB
CMRR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
−4
−5
−6
0 0.5 1 1.5 2 2.5 3 100.5 101
t − Time − ms
102
103
Figure 93
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
SINGLE-ENDED OUTPUT IMPEDANCE
IN POWER DOWN
vs
FREQUENCY
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERATURE
800
ZO− Single-Ended Output Impedance
in Power Down − Ω
900
800
700
600
500
400
300
200
100
0
0.1
Gain = 1
RL = 400 Ω
Rf = 499 Ω
PIN = −1 dBm
VS = 5 V
1
10
100
f − Frequency − MHz
Figure 94
20
1000
700
1000
RL = 800 Ω
VS = 5 V
600
500
400
300
200
100
0
−40 −30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Figure 95
Power-Down Quiescent Current − µ A
Power-Down Quiescent Current − µ A
1100
1000
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
900
800
700
600
500
400
300
200
100
0
0
0.5 1
1.5 2
2.5 3
3.5 4
VS − Supply Voltage − V
Figure 96
4.5 5
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIERS
Differential signaling offers a number of performance
advantages in high-speed analog signal processing
systems, including immunity to external common-mode
noise, suppression of even-order nonlinearities, and
increased dynamic range. Fully differential amplifiers not
only serve as the primary means of providing gain to a
differential signal chain, but also provide a monolithic
solution for converting single-ended signals into
differential signals for easier, higher performance
processing. The THS4500 family of amplifiers contains
products in Texas Instruments’ expanding line of
high-performance fully differential amplifiers. Information
on fully differential amplifier fundamentals, as well as
implementation specific information, is presented in the
applications section of this data sheet to provide a better
understanding of the operation of the THS4500 family of
devices, and to simplify the design process for designs
using these amplifiers.
Applications Section
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Fully Differential Amplifier Terminal Functions
Input Common-Mode Voltage Range and the
THS4500 Family
Choosing the Proper Value for the Feedback and
Gain Resistors
Application Circuits Using Fully Differential
Amplifiers
Key Design Considerations for Interfacing to an
Analog-to-Digital Converter
Setting the Output Common-Mode Voltage With the
VOCM Input
Saving Power with Power-Down Functionality
Linearity: Definitions, Terminology, Circuit
Techniques, and Design Tradeoffs
An Abbreviated Analysis of Noise in Fully
Differential Amplifiers
Printed-Circuit Board Layout Techniques for Optimal
Performance
Power Dissipation and Thermal Considerations
Power Supply Decoupling Techniques and
Recommendations
Evaluation Fixtures, Spice Models, and Applications
Support
Additional Reference Material
FULLY DIFFERENTIAL AMPLIFIER
TERMINAL FUNCTIONS
Fully differential amplifiers are typically packaged in
eight-pin packages as shown in the diagram. The device
pins include two inputs (VIN+, VIN−), two outputs (VOUT−,
VOUT+), two power supplies (VS+, VS−), an output
common-mode control pin (VOCM), and an optional
power-down pin (PD).
VIN− 1
8 VIN+
VOCM 2
7 PD
VS+ 3
6 VS−
VOUT+ 4
5 VOUT−
Fully Differential Amplifier Pin Diagram
A standard configuration for the device is shown in the
figure. The functionality of a fully differential amplifier can
be imagined as two inverting amplifiers that share a
common noninverting terminal (though the voltage is not
necessarily fixed). For more information on the basic
theory of operation for fully differential amplifiers, refer to
the Texas Instruments application note titled Fully
Differential Amplifiers, literature number SLOA054.
INPUT COMMON-MODE VOLTAGE RANGE
AND THE THS4500 FAMILY
The key difference between the THS4500/1 and the
THS4502/3 is the input common-mode range for the two
devices. The THS4502 and THS4503 have an input
common-mode range that is centered around midrail, and
the THS4500 and THS4501 have an input common-mode
range that is shifted to include the negative power supply
rail. Selection of one or the other is determined by the
nature of the application. Specifically, the THS4500 and
THS4501 are designed for use in single-supply
applications where the input signal is ground-referenced,
as depicted in Figure 97. The THS4502 and THS4503 are
designed for use in single-supply or split-supply
applications where the input signal is centered between
the power supply voltages, as depicted in Figure 98.
RS
VS
Rg1
Rf1
+VS
RT
VOCM
Rg2
+ −
− +
Rf2
Application Circuit for the THS4500 and THS4501,
Featuring Single-Supply Operation With a
Ground-Referenced Input Signal
Figure 97
21
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
Rg1
RS
Rg
Rf1
Rf
VIN+
VS
+VS
RT
VOCM
Vp
+ −
− +
VOCM
VOUT−
+ −
− +
VOUT+
Vn
−VS
Rg2
VIN−
Rg
Rf2
Rf
Diagram For Input Common-Mode Range Equations
Application Circuit for the THS4500 and THS4501,
Featuring Split-Supply Operation With an Input
Signal Referenced at the Midrail
Figure 99
Figure 98
Equations 1−5 allow for calculation of the required input
common-mode range for a given set of input conditions.
The equations allow calculation of the input commonmode range requirements given information about the
input signal, the output voltage swing, the gain, and the
output common-mode voltage. Calculating the maximum
and minimum voltage required for VN and VP (the
amplifier’s input nodes) determines whether or not the
input common-mode range is violated or not. Four
equations are required. Two calculate the output voltages
and two calculate the node voltages at VN and VP (note
that only one of these needs calculation, as the amplifier
forces a virtual short between the two nodes).
V (1–β)–V IN–(1–β) ) 2V OCMβ
(1)
V OUT) + IN)
2β
–V IN)(1–β) ) V IN–(1–β) ) 2V OCMβ
V OUT– +
2β
V N + V IN–(1–β) ) V OUT)β
Where:
RG
β+
RF ) RG
(2)
(3)
(4)
V P + V IN)(1–β) ) V OUT–β
NOTE:
The equations denote the device inputs as VN and
VP, and the circuit inputs as VIN+ and VIN−.
(5)
The two tables below depict the input common-mode
range requirements for two different input scenarios, an
input referenced around the negative rail and an input
referenced around midrail. The tables highlight the
differing requirements on input common-mode range, and
illustrate reasoning for choosing either the THS4500/1 or
the THS4502/3. For signals referenced around the
negative power supply, the THS4500/1 should be chosen
since its input common-mode range includes the negative
supply rail. For all other situations, the THS4502/3 offers
slightly improved distortion and noise performance for
applications with input signals centered between the
power supply rails.
Table 1. Negative-Rail Referenced
Gain
(V/V)
VIN+ (V)
VIN−
(V)
VIN
(VPP)
VOCM
(V)
VOD
(VPP)
VNMIN
(V)
VNMAX
(V)
1
−2.0 to
2.0
0
4
2.5
4
0.75
1.75
2
−1.0 to
1.0
0
2
2.5
4
0.5
1.167
4
−0.5 to
0.5
0
1
2.5
4
0.3
0.7
8
−0.25 to
0.25
0
0.5
2.5
4
0.167
0.389
NOTE: This table assumes a negative-rail referenced, single-ended
input signal on a single 5-V supply as shown in Figure 97.
VNMIN = VPMIN and VNMAX = VPMAX.
Table 2. Midrail Referenced
Gain
(V/V)
VIN+ (V)
VIN−
(V)
VIN
(VPP)
VOCM
(V)
VOD
(VPP)
VNMIN
(V)
VNMAX
(V)
1
0.5 to
4.5
2.5
4
2.5
4
2
3
2
1.5 to
3.5
2.5
2
2.5
4
2.16
2.83
4
2.0 to
3.0
2.5
1
2.5
4
2.3
2.7
8
2.25 to
2.75
2.5
0.5
2.5
4
2.389
2.61
NOTE: This table assumes a midrail referenced, single-ended input
signal on a single 5-V supply.
VNMIN = VPMIN and VNMAX = VPMAX.
22
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
CHOOSING THE PROPER VALUE FOR THE
FEEDBACK AND GAIN RESISTORS
Table 3. Resistor Values for Balanced Operation
in Various Gain Configurations
The selection of feedback and gain resistors impacts
circuit performance in a number of ways. The values in this
section provide the optimum high frequency performance
(lowest distortion, flat frequency response). Since the
THS4500 family of amplifiers is developed with a voltage
feedback architecture, the choice of resistor values does
not have a dominant effect on bandwidth, unlike a current
feedback amplifier. However, resistor choices do have
second-order effects. For optimal performance, the
following feedback resistor values are recommended. In
higher gain configurations (gain greater than two), the
feedback resistor values have much less effect on the high
frequency performance. Example feedback and gain
resistor values are given in the section on basic design
considerations (Table 3).
Gain
Amplifier loading, noise, and the flatness of the frequency
response are three design parameters that should be
considered when selecting feedback resistors. Larger
resistor values contribute more noise and can induce
peaking in the ac response in low gain configurations, and
smaller resistor values can load the amplifier more heavily,
resulting in a reduction in distortion performance. In
addition, feedback resistor values, coupled with gain
requirements, determine the value of the gain resistors,
directly impacting the input impedance of the entire circuit.
While there are no strict rules about resistor selection,
these trends can provide qualitative design guidance.
APPLICATION CIRCUITS USING FULLY
DIFFERENTIAL AMPLIFIERS
Fully differential amplifiers provide designers with a great
deal of flexibility in a wide variety of applications. This
section provides an overview of some common circuit
configurations and gives some design guidelines.
Designing the interface to an ADC, driving lines
differentially, and filtering with fully differential amplifiers
are a few of the circuits that are covered.
BASIC DESIGN CONSIDERATIONS
The circuits in Figures 100 through 104 are used to
highlight basic design considerations for fully differential
amplifier circuit designs.
ǒ Ǔ
VOD
VIN
R2 & R4 (Ω)
R1 (Ω)
R3 (Ω)
RT (Ω)
1
392
412
383
54.9
1
499
523
487
53.6
2
392
215
187
60.4
2
1.3k
665
634
52.3
5
1.3k
274
249
56.2
5
3.32k
681
649
52.3
10
1.3k
147
118
64.9
10
6.81k
698
681
52.3
NOTE: Values in the table above assume a 50 Ω source impedance.
R1
R2
Vn
RS
Vout+
−
+
+ −
R3
Vout−
VP
VOCM
RT
VS
R4
Figure 100
Equations for calculating fully differential amplifier resistor
values in order to obtain balanced operation in the
presence of a 50-Ω source impedance are given in
equations 6 through 9.
RT +
β1 +
1
K + R2
R1
1– K
1 – 2(1)K)
RS
R3
R2 + R4
(6)
R3 + R1 * ǒRs || R TǓ
R3 ) RT || R S
R1
β2 +
R1 ) R2
R3 ) RT || R S ) R4
(7)
ǒ
Ǔ ǒR R) R Ǔ
(8)
ǒ
Ǔ
(9)
V OD
1–β 2
+2
β1 ) β 2
VS
V OD
1–β 2
+2
β1 ) β 2
V IN
T
T
S
For more detailed information about balance in fully
differential amplifiers, see Fully Differential Amplifiers,
referenced at the end of this data sheet.
23
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
INTERFACING TO AN ANALOG-TO-DIGITAL
CONVERTER
The THS4500 family of amplifiers are designed
specifically to interface to today’s highest-performance
analog-to-digital converters. This section highlights the
key concerns when interfacing to an ADC and provides
example ADC/fully differential amplifier interface circuits.
Key design concerns when
analog-to-digital converter:
interfacing
to
Terminate the input source properly. In high-frequency
receiver chains, the source feeding the fully
differential amplifier requires a specific load
impedance (e.g., 50 Ω).
D
Design a symmetric printed-circuit board layout.
Even-order distortion products are heavily influenced
by layout, and careful attention to a symmetric layout
will minimize these distortion products.
D
Minimize inductance in power supply decoupling
traces and components. Poor power supply
decoupling can have a dramatic effect on circuit
performance. Since the outputs are differential,
differential currents exist in the power supply pins.
Thus, decoupling capacitors should be placed in a
manner that minimizes the impedance of the current
loop.
Use separate analog and digital power supplies and
grounds. Noise (bounce) in the power supplies
(created by digital switching currents) can couple
directly into the signal path, and power supply noise
can create higher distortion products as well.
D
Use care when filtering. While an RC low-pass filter
may be desirable on the output of the amplifier to filter
broadband noise, the excess loading can negatively
impact the amplifier linearity. Filtering in the feedback
path does not have this effect.
D
AC-coupling allows easier circuit design. If
dc-coupling is required, be aware of the excess power
dissipation that can occur due to level-shifting the
output through the output common-mode voltage
control.
D
D
24
D
D
an
D
D
the required amount of current to move VOCM to the
desired value. A buffer may be needed.
Decouple the VOCM pin to eliminate the antenna
effect. VOCM is a high-impedance node that can act as
an antenna. A large decoupling capacitor on this node
eliminates this problem.
Be cognizant of the input common-mode range. If the
input signal is referenced around the negative power
supply rail (e.g., around ground on a single 5 V
supply), then the THS4500/1 accommodates the
input signal. If the input signal is referenced around
midrail, choose the THS4502/3 for the best operation.
Packaging makes a difference at higher frequencies.
If possible, choose the smaller, thermally enhanced
MSOP package for the best performance. As a rule,
lower junction temperatures provide better
performance. If possible, use a thermally enhanced
package, even if the power dissipation is relatively
small compared to the maximum power dissipation
rating to achieve the best results.
Comprehend the effect of the load impedance seen by
the fully differential amplifier when performing
system-level intercept point calculations. Lighter
loads (such as those presented by an ADC) allow
smaller intercept points to support the same level of
intermodulation distortion performance.
Do not terminate the output unless required. Many
open-loop, class-A amplifiers require 50-Ω
termination for proper operation, but closed-loop fully
differential amplifiers drive a specific output voltage
regardless of the load impedance present.
Terminating the output of a fully differential amplifier
with a heavy load adversely effects the amplifier’s
linearity.
Comprehend the VOCM input drive requirements.
Determine if the ADC’s voltage reference can provide
D
D
EXAMPLE ANALOG-TO-DIGITAL
CONVERTER DRIVER CIRCUITS
The THS4500 family of devices is designed to drive
high-performance ADCs with extremely high linearity,
allowing for the maximum effective number of bits at the
output of the data converter. Two representative circuits
shown below highlight single-supply operation and split
supply operation. Specific feedback resistor, gain resistor,
and feedback capacitor values are not specified, as their
values depend on the frequency of interest. Information on
calculating these values can be found in the applications
material above.
CF
RS
VS
Rg
RT
Rf
5V
10 µF
1 µF
Rg
0.1 µF
+ −
VOCM
+
−
THS4503
−5 V
5V
Riso
Riso
IN ADS5410
12 Bit/80 MSps
IN
CM
10 µF 0.1 µF
0.1 µF
Rf
CF
Using the THS4503 With the ADS5410
Figure 101
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
CF
RS
VS
Rg
applicable to many different types of systems. The first
pole is set by the resistors and capacitors in the feedback
paths, and the second pole is set by the isolation resistors
and the capacitor across the outputs of the isolation
resistors.
Rf
5V
RT
10 µF
5V
0.1 µF
Riso
+ −
VOCM
+
−
1 µF
IN ADS5421
14 Bit/40 MSps
IN
CM
THS4501
CF1
Riso
Rg1
RS
Rg
Rf1
Rf
VS
CF
Riso
RT
+
−
0.1 µF
−
C
VO
+
Rg2
Riso
Using the THS4501 With the ADS5421
Rf2
Figure 102
CF2
FULLY DIFFERENTIAL LINE DRIVERS
The THS4500 family of amplifiers can be used as
high-frequency, high-swing differential line drivers. Their
high power supply voltage rating (16.5 V absolute
maximum) allows operation on a single 12-V or a single
15-V supply. The high supply voltage, coupled with the
ability to provide differential outputs enables the ability to
drive 26 VPP into reasonably heavy loads (250 Ω or
greater). The circuit in Figure 103 illustrates the THS4500
family of devices used as high speed line drivers. For line
driver applications, close attention must be paid to thermal
design constraints due to the typically high level of power
dissipation.
RS
VS
CG
Rg
RT
Riso
+
−
THS4500/2
− +
0.1 µF
Figure 104
Often times, filters like these are used to eliminate
broadband noise and out-of-band distortion products in
signal acquisition systems. It should be noted that the
increased load placed on the output of the amplifier by the
second low-pass filter has a detrimental effect on the
distortion performance. The preferred method of filtering
is using the feedback network, as the typically smaller
capacitances required at these points in the circuit do not
load the amplifier nearly as heavily in the pass-band.
Rf
15 V
VOCM
A Two-Pole, Low-Pass Filter Design Using a Fully
Differential Amplifier With Poles Located at:
P1 = (2πRfCF)−1 in Hz and P2 = (4πRisoC)−1 in Hz
RL
VDD
Riso
Rf
Rg
SETTING THE OUTPUT COMMON-MODE
VOLTAGE WITH THE VOCM INPUT
CS
CS
VOD = 26 VPP
CG
Fully Differential Line Driver With High Output Swing
Figure 103
FILTERING WITH FULLY DIFFERENTIAL
AMPLIFIERS
Similar to their single-ended counterparts, fully differential
amplifiers have the ability to couple filtering functionality
with voltage gain. Numerous filter topologies can be based
on fully differential amplifiers. Several of these are outlined
in A Differential Circuit Collection, (literature number
SLOA064) referenced at the end of this data sheet. The
circuit below depicts a simple two-pole low-pass filter
The output common-mode voltage pin provides a critical
function to the fully differential amplifier; it accepts an input
voltage and reproduces that input voltage as the output
common-mode voltage. In other words, the VOCM input
provides the ability to level-shift the outputs to any voltage
inside the output voltage swing of the amplifier.
A description of the input circuitry of the VOCM pin is shown
below to facilitate an easier understanding of the VOCM
interface requirements. The VOCM pin has two 50-kΩ
resistors between the power supply rails to set the default
output common-mode voltage to midrail. A voltage
applied to the VOCM pin alters the output common-mode
voltage as long as the source has the ability to provide
enough current to overdrive the two 50-kΩ resistors. This
phenomenon is depicted in the VOCM equivalent circuit
diagram. The table contains some representative
examples to aid in determining the current drive
requirement for the VOCM voltage source. This parameter
is especially important when using the reference voltage
25
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
of an analog-to-digital converter to drive VOCM. Output
current drive capabilities differ from part to part, so a
voltage buffer may be necessary in some applications.
I1 =
DC Current Path to Ground
Rg1
RS
VS+
VS
R = 50 kΩ
IIN
Rf1
5V
RT
VOCM = 2.5 V
IIN =
VOCM
VOCM
Rf1+ Rg1 + RS || RT
2 VOCM − VS+ − VS−
2.5-V DC
+ −
− +
RL
R
R = 50 kΩ
Rg2
Rf2
2.5-V DC
DC Current Path to Ground
VS−
Equivalent Input Circuit for VOCM
Figure 105
VOCM
I2 =
Rf2 + Rg2
Depiction of DC Power Dissipation Caused By
Output Level-Shifting in a DC-Coupled Circuit
Figure 106
By design, the input signal applied to the VOCM pin
propagates to the outputs as a common-mode signal. As
shown in the equivalent circuit diagram, the VOCM input
has a high impedance associated with it, dictated by the
two 50-kΩ resistors. While the high impedance allows for
relaxed drive requirements, it also allows the pin and any
associated printed-circuit board traces to act as an
antenna. For this reason, a decoupling capacitor is
recommended on this node for the sole purpose of filtering
any high frequency noise that could couple into the signal
path through the VOCM circuitry. A 0.1-µF or 1-µF
capacitance is a reasonable value for eliminating a great
deal of broadband interference, but additional, tuned
decoupling capacitors should be considered if a specific
source of electromagnetic or radio frequency interference
is present elsewhere in the system. Information on the ac
performance (bandwidth, slew rate) of the VOCM circuitry
is included in the specification table and graph section.
Since the VOCM pin provides the ability to set an output
common-mode voltage, the ability for increased power
dissipation exists. While this does not pose a performance
problem for the amplifier, it can cause additional power
dissipation of which the system designer should be aware.
The circuit shown in Figure 106 demonstrates an
example of this phenomenon. For a device operating on
a single 5-V supply with an input signal referenced around
ground and an output common-mode voltage of 2.5 V, a
dc potential exists between the outputs and the inputs of
the device. The amplifier sources current into the
feedback network in order to provide the circuit with the
proper operating point. While there are no serious effects
on the circuit performance, the extra power dissipation
may need to be included in the system’s power budget.
26
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY
The THS4500 family of fully differential amplifiers contains
devices that come with and without the power-down
option. Even-numbered devices have power-down
capability, which is described in detail here.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage (i.e. an internal pullup resistor is present), putting
the amplifier in the power-on mode of operation. To turn off
the amplifier in an effort to conserve power, the
power-down pin can be driven towards the negative rail.
The threshold voltages for power-on and power-down are
relative to the supply rails and given in the specification
tables. Above the enable threshold voltage, the device is
on. Below the disable threshold voltage, the device is off.
Behavior in between these threshold voltages is not
specified.
Note that this power-down functionality is just that; the
amplifier consumes less power in power-down mode. The
power-down mode is not intended to provide a
high-impedance output. In other words, the power-down
functionality is not intended to allow use as a 3-state bus
driver. When in power-down mode, the impedance looking
back into the output of the amplifier is dominated by the
feedback and gain setting resistors.
The time delays associated with turning the device on and
off are specified as the time it takes for the amplifier to
reach 50% of the nominal quiescent current. The time
delays are on the order of microseconds because the
amplifier moves in and out of the linear mode of operation
in these transitions.
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
POUT
(dBm)
1X
OIP3
The THS4500 family of devices features unprecedented
distortion performance for monolithic fully differential
amplifiers. This section focuses on the fundamentals of
distortion, circuit techniques for reducing nonlinearity,
and methods for equating distortion of fully differential
amplifiers to desired linearity specifications in RF receiver
chains.
PO
IMD3
Amplifiers are generally thought of as linear devices. In
other words, the output of an amplifier is a linearly scaled
version of the input signal applied to it. In reality, however,
amplifier transfer functions are nonlinear. Minimizing
amplifier nonlinearity is a primary design goal in many
applications.
Intercept points are specifications that have long been
used as key design criteria in the RF communications
world as a metric for the intermodulation distortion
performance of a device in the signal chain (e.g.,
amplifiers, mixers, etc.). Use of the intercept point, rather
than strictly the intermodulation distortion, allows for
simpler system-level calculations. Intercept points, like
noise figures, can be easily cascaded back and forth
through a signal chain to determine the overall receiver
chain’s intermodulation distortion performance. The
relationship between intermodulation distortion and
intercept point is depicted in Figure 107 and Figure 108.
Power
PO
PO
∆fc = fc − f1
∆fc = f2 − fc
IMD3 = PS − PO
PS
PS
3X
f1 fc
f2
fc + 3∆f
f − Frequency − MHz
Figure 107
PIN
(dBm)
PS
Figure 108
Due to the intercept point’s ease of use in system level
calculations for receiver chains, it has become the
specification of choice for guiding distortion-related design
decisions. Traditionally, these systems use primarily
class-A, single-ended RF amplifiers as gain blocks. These
RF amplifiers are typically designed to operate in a 50-Ω
environment, just like the rest of the receiver chain. Since
intercept points are given in dBm, this implies an
associated impedance (50 Ω).
However, with a fully differential amplifier, the output does
not require termination as an RF amplifier would. Because
closed-loop amplifiers deliver signals to their outputs
regardless of the impedance present, it is important to
comprehend this when evaluating the intercept point of a
fully differential amplifier. The THS4500 series of devices
yields optimum distortion performance when loaded with
200 Ω to 1 kΩ, very similar to the input impedance of an
analog-to-digital converter over its input frequency band.
As a result, terminating the input of the ADC to 50 Ω can
actually be detrimental to system performance.
This discontinuity between open-loop, class-A amplifiers
and closed-loop, class-AB amplifiers becomes apparent
when comparing the intercept points of the two types of
devices. Equation 10 gives the definition of an intercept
point, relative to the intermodulation distortion.
OIP 3 + P O )
fc − 3∆f
IIP3
ǒŤIMD2 ŤǓ where
ǒ
P O + 10 log
3
Ǔ
V 2Pdiff
2RL 0.001
(10)
(11)
NOTE: Po is the output power of a single tone, RL is the differential load
resistance, and VP(diff) is the differential peak voltage for a
single tone.
27
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
As can be seen in the equation, when a higher impedance
is used, the same level of intermodulation distortion
performance results in a lower intercept point. Therefore,
it is important to comprehend the impedance seen by the
output of the fully differential amplifier when selecting a
minimum intercept point. The graphic below shows the
relationship between the strict definition of an intercept
point with a normalized, or equivalent, intercept point for
the THS4502.
OIP 3 − Third-Order Output Intercept Point − dBm
THIRD-ORDER OUTPUT INTERCEPT POINT
vs
FREQUENCY
delivered to the amplifier by the source (NI) and input noise
power are used to calculate the noise factor and noise
figure as shown in equations 23 through 27.
Ni
eg
NA
Rf
Si
Ni
No
Rs
+
Rt
Normalized to 200 Ω
55
et
iii
45
eg
Rg
40
35
So
No
fully-diff
amp
−
ini
Normalized to 50 Ω
50
ef
en
es
60
Rf
ef
OIP3 RL= 800 Ω
30
Gain = 1
Rf = 392 Ω
VS = ± 5 V
Tone Spacing = 200 kHz
25
20
15
0
10 20 30 40 50 60 70 80 90 100
f − Frequency − MHz
Figure 110. Noise Sources in a Fully
Differential Amplifier Circuit
NA: Fully Differential Amplifier
Noise
Source Scale Factor
Figure 109
ȡR
ȧR ) R
Ȣ
g
Comparing specifications between different device types
becomes easier when a common impedance level is
assumed. For this reason, the intercept points on the
THS4500 family of devices are reported normalized to a
50-Ω load impedance.
(eni)2
Noise analysis in fully differential amplifiers is analogous
to noise analysis in single-ended amplifiers. The same
concepts apply. Below, a generic circuit diagram
consisting of a voltage source, a termination resistor, two
gain setting resistors, two feedback resistors, and a fully
differential amplifier is shown, including all the relevant
noise sources. From this circuit, the noise factor (F) and
noise figure (NF) are calculated. The figures indicate the
appropriate scaling factor for each of the noise sources in
two different cases. The first case includes the termination
resistor, and the second, simplified case assumes that the
voltage source is properly terminated by the gain-setting
resistors. With these scaling factors, the amplifier’s input
noise power (NA) can be calculated by summing each
individual noise source with its scaling factor. The noise
f
ȣ
ȧ
Ȥ
2
Rg
R sR t
g) ǒ
2 Rs)R tǓ
(12)
(ini)2
Rg2
(13)
(iii)2
Rg2
(14)
AN ANALYSIS OF NOISE IN FULLY
DIFFERENTIAL AMPLIFIERS
28
Rg
R
ȡ R2R)2R
ȣ
ȧR ) 2R R ȧ
Ȣ R )2R Ȥ
2
s
4kTRt
s
g
s
t
2
4kTRf
4kTRg
G
2
s
ǒ Ǔ
Rg
Rf
ȡ
ȧR
Ȣ
(15)
g
g
2
(16)
ȣ
ȧ
Ȥ
2
Rg
R sR t
g)
2ǒR s)RtǓ
(17)
Figure 111. Scaling Factors for Individual Noise
Sources Assuming a Finite Value Termination
Resistor
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
NA: Fully Differential Amplifier; termination = 2Rg
Noise
Source Scale Factor
ȡR )
ȧR R
Ȣ
ȣ
Rȧ
) Ȥ
f
Minimize the distance (< 0.25”) from the power supply
pins to high frequency 0.1-µF decoupling capacitors.
At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors. Larger
(6.8 µF or more) tantalum decoupling capacitors,
effective at lower frequency, should also be used on
the main supply pins. These may be placed somewhat
farther from the device and may be shared among
several devices in the same area of the PC board. The
primary goal is to minimize the impedance seen in the
differential-current return paths.
D
Careful selection and placement of external
components preserve
the
high
frequency
performance of the THS4500 family. Resistors should
be a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high frequency performance.
Again, keep their leads and PC board trace length as
short as possible. Never use wirewound type resistors
in a high frequency application. Since the output pin
and inverting input pins are the most sensitive to
parasitic capacitance, always position the feedback
and series output resistors, if any, as close as possible
to the inverting input pins and output pins. Other
network components, such as input termination
resistors, should be placed close to the gain-setting
resistors. Even with a low parasitic capacitance
shunting the external resistors, excessively high
resistor values can create significant time constants
that can degrade performance. Good axial metal-film
or surface-mount resistors have approximately 0.2 pF
in shunt with the resistor. For resistor values > 2.0 kΩ,
this parasitic capacitance can add a pole and/or a zero
below 400 MHz that can effect circuit operation. Keep
resistor values as low as possible, consistent with
load driving considerations.
D
Connections to other wideband devices on the board
may be made with short direct traces or through
onboard transmission lines. For short connections,
consider the trace and the input to the next device as
a lumped capacitive load. Relatively wide traces
(50 mils to 100 mils) should be used, preferably with
2
Rg2
(19)
(iii)2
Rg2
(20)
4kTRf
D
(18)
s
g
(ini)2
ǒ Ǔ
Rg
Rf
2
Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. To reduce
unwanted capacitance, a window around the signal
I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground
and power planes should be unbroken elsewhere on
the board.
2
Rg
g
(eni)2
D
2
(21)
ȡ R ȣ
ȧR ) R ȧ
Ȣ 2Ȥ
2
g
2
4kTRg
(22)
s
g
Figure 112. Scaling Factors for Individual Noise
Sources Asseming No Termination Resistance is
Used (e.g., RT is open)
ȡ 2R R ȣ
ȧ R )2R ȧ
N + 4kTR ȧ
R ȧ
ȧR )R2R)2R
ȧ
Ȣ
Ȥ
2
t
i
g
s
(23)
g
t
t
s
g
g
t
Figure 113. Input Noise With a Termination
Resistor
Ni + 4kTR s
ǒ
2R g
Rs ) 2Rg
Ǔ
2
(24)
Figure 114. Input Noise Assuming No
Termination Resistor
Noise Factor and Noise Figure Calculations
N A + SǒNoise Source
F+1)
Scale FactorǓ
NA
NI
NF + 10 log (F)
(25)
(26)
(27)
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier-like devices in the THS4500 family requires
careful attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
29
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ground and power planes opened up around them.
Estimate the total capacitive load and determine if
isolation resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need an RS
since the THS4500 family is nominally compensated
to operate with a 2-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded phase
margin). If a long trace is required, and the 6-dB signal
loss intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques).
A 50-Ω environment is normally not necessary
onboard, and in fact, a higher impedance environment
improves distortion as shown in the distortion versus
load plots. With a characteristic board trace
impedance defined based on board material and trace
dimensions, a matching series resistor into the trace
from the output of the THS4500 family is used as well
as a terminating shunt resistor at the input of the
destination device.
Remember also that the terminating impedance is the
parallel combination of the shunt resistor and the input
impedance of the destination device: this total
effective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is low, there is some signal
attenuation due to the voltage divider formed by the
series output into the terminating impedance.
D
Socketing a high speed part like the THS4500 family
is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the THS4500 family parts
directly onto the board.
PowerPAD DESIGN CONSIDERATIONS
The THS4500 family is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die
is mounted [see Figure 115(a) and Figure 115(b)]. This
arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see
30
Figure 115(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good thermal
path away from the thermal pad.
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either
a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in
combining the small area and ease of assembly of surface
mount with the, heretofore, awkward mechanical methods
of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 115. Views of Thermally Enhanced
Package
Although there are many ways to properly heatsink the
PowerPAD package, the following steps illustrate the
recommended approach.
0.205
0.060
0.017
Pin 1
0.013
0.030
0.075
0.025 0.094
0.010
vias
0.035
0.040
Top View
Figure 116. PowerPAD PCB Etch and Via Pattern
PowerPAD PCB LAYOUT CONSIDERATIONS
1.
Prepare the PCB with a top side etch pattern as shown
in Figure 116. There should be etch for the leads as
well as etch for the thermal pad.
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
Place five holes in the area of the thermal pad. These
holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a
problem during reflow.
3.
Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the THS4500
family IC. These additional vias may be larger than the
13-mil diameter vias directly under the thermal pad.
They can be larger because they are not in the thermal
pad area to be soldered so that wicking is not a
problem.
4.
Connect all holes to the internal ground plane.
5.
When connecting these holes to the ground plane, do
not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS4500
family PowerPAD package should make their
connection to the internal ground plane with a
complete connection around the entire circumference
of the plated-through hole.
6.
7.
8.
The top-side solder mask should leave the terminals
of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should
cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the
thermal pad area during the reflow process.
Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
With these preparatory steps in place, the IC is simply
placed in position and run through the solder reflow
operation as any standard surface-mount
component. This results in a part that is properly
installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer must
take care to ensure that the design does not violate the
absolute maximum junction temperature of the device.
Failure may result if the absolute maximum junction
temperature of 150°C is exceeded. For best performance,
design for a maximum junction temperature of 125°C.
Between 125°C and 150°C, damage does not occur, but
the performance of the amplifier begins to degrade.
The thermal characteristics of the device are dictated by
the package and the PC board. Maximum power
dissipation for a given package can be calculated using the
following formula.
P Dmax +
Tmax–T A
q JA
(28)
Where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
For systems where heat dissipation is more critical, the
THS4500 family of devices is offered in an 8-pin MSOP
with PowerPAD. The thermal coefficient for the MSOP
PowerPAD package is substantially improved over the
traditional SOIC. Maximum power dissipation levels are
depicted in the graph for the two packages. The data for
the DGN package assumes a board layout that follows the
PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application notes in the
Additional Reference Material section at the end of the
data sheet.
3.5
PD − Maximum Power Dissipation − W
2.
8-Pin DGN Package
3
2.5
2
8-Pin D Package
1.5
1
0.5
0
−40
−20
0
20
40
60
TA − Ambient Temperature − °C
80
θJA = 170°C/W for 8-Pin SOIC (D)
θJA = 58.4°C/W for 8-Pin MSOP (DGN)
ΤJ = 150°C, No Airflow
Figure 117. Maximum Power Dissipation vs
Ambient Temperature
When determining whether or not the device satisfies the
maximum power dissipation requirement, it is important to
not only consider quiescent power dissipation, but also
dynamic power dissipation. Often times, this is difficult to
quantify because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
31
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SLOS350D − APRIL 2002 − REVISED JANUARY 2004
DRIVING CAPACITIVE LOADS
High-speed amplifiers are typically not well-suited for
driving large capacitive loads. If necessary, however, the
load capacitance should be isolated by two isolation
resistors in series with the output. The requisite isolation
resistor size depends on the value of the capacitance, but
10 to 25 Ω is a good place to begin the optimization
process. Larger isolation resistors decrease the amount of
peaking in the frequency response induced by the
capacitive load, but this comes at the expense of larger
voltage drop across the resistors, increasing the output
swing requirements of the system.
EVALUATION FIXTURES, SPICE MODELS,
AND APPLICATIONS SUPPORT
Texas Instruments is committed to providing its customers
with the highest quality of applications support. To support
this goal, an evaluation board has been developed for the
THS4500 family of fully differential amplifiers. The
evaluation board can be obtained by ordering through the
Texas Instruments web site, www.ti.com, or through your
local Texas Instruments sales representative. Schematic
for the evaluation board is shown below with the default
component values. Unpopulated footprints are shown to
provide insight into design flexibility.
Rf
VS
VS
Rg
RS
C4
Riso
+ −
RT
−
C0805
R4
R0805
VS
CL
+
Riso
−VS
Riso = 10 − 25 Ω
Rf
Rg
J1
C1
R1
C0805
C2
R1206
C0805
R2
1
PD
U1
THS450X
R6
4
7
R0805
3
_
R0805
R0805
R3
8
+
2
5
6
VOCM
PwrPad
C5
C0805
C7
C0805
R0805
R7
J2
J3
J2
J3
C6
C0805
−VS
R5 R0805
C3
C0805
Use of Isolation Resistors With a Capacitive Load.
Figure 118
POWER SUPPLY DECOUPLING
TECHNIQUES AND RECOMMENDATIONS
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance (most
notably improved distortion performance). The following
guidelines ensure the highest level of performance.
1.
Place decoupling capacitors as close to the power
supply inputs as possible, with the goal of minimizing
the inductance of the path from ground to the power
supply.
2.
Placement priority should be as follows: smaller
capacitors should be closer to the device.
3.
Use of solid power and ground planes is
recommended to reduce the inductance along power
supply return current paths.
4.
Recommended values for power supply decoupling
include 10-µF and 0.1-µF capacitors for each supply.
A 1000-pF capacitor can be used across the supplies
as well for extremely high frequency return currents,
but often is not required.
32
J2
R8
R0805
J3
R9
R0805
R0805
R9
4
J4
3
5
R11
R1206
6
T1
1
Simplified Schematic of the Evaluation Board. Power
Supply Decoupling, VOCM, and Power Down Circuitry
Not Shown
Figure 119
Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and
inductance can have a major effect on circuit performance.
A SPICE model for the THS4500 family of devices is
available through either the Texas Instruments web site
(www.ti.com) or as one model on a disk from the Texas
Instruments
Product
Information
Center
(1−800−548−6132). The PIC is also available for design
assistance and detailed product information at this
number. These models do a good job of predicting
small-signal ac and transient performance under a wide
variety of operating conditions. They are not intended to
model the distortion characteristics of the amplifier, nor do
they attempt to distinguish between the package types in
their small-signal ac performance. Detailed information
about what is and is not modeled is contained in the model
file itself.
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ADDITIONAL REFERENCE MATERIAL
D
D
D
D
PowerPAD Made Easy, application brief, Texas Instruments Literature Number SLMA004.
D
Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments Literature Number
SLOA064.
D
Carter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, Texas Instruments Literature
Number SLOA072.
D
Karki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog Applications
Journal, July 2001.
PowerPAD Thermally Enhanced Package, technical brief, Texas Instruments Literature Number SLMA002.
Karki, James. Fully Differential Amplifiers. application report, Texas Instruments Literature Number SLOA054D.
Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High−Speed ADCs, and Differential
Transmission Lines. Texas Instruments Analog Applications Journal, February 2001.
33
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