TI TLC27L7IDRG4

  SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
D Trimmed Offset Voltage:
D, JG, OR P PACKAGE
(TOP VIEW)
TLC27L7 . . . 500 µV Max at 25°C,
VDD = 5 V
Input Offset Voltage Drift . . . Typically
0.1 µV/Month, Including the First 30 Days
Wide Range of Supply Voltages Over
Specified Temperature Range:
0°C to 70°C . . . 3 V to 16 V
−40°C to 85°C . . . 4 V to 16 V
−55°C to 125°C . . . 4 V to 16 V
Single-Supply Operation
Common-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix,
I-Suffix Types)
Ultra-Low Power . . . Typically 95 µW
at 25°C, VDD = 5 V
Output Voltage Range Includes Negative
Rail
High Input Impedance . . . 1012 Ω Typ
ESD-Protection Circuitry
Small-Outline Package Option Also
Available in Tape and Reel
Designed-In Latch-Up immunity
D
D
D
D
D
D
D
D
8
2
7
3
6
4
5
VDD
2OUT
2IN −
2IN +
FK PACKAGE
(TOP VIEW)
NC
1IN −
NC
1IN +
NC
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC
2OUT
NC
2IN −
NC
NC − No internal connection
DISTRIBUTION OF TLC27L7
INPUT OFFSET VOLTAGE
description
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
30
The TLC27L2 and TLC27L7 dual operational
amplifiers combine a wide range of input offset
voltage grades with low offset voltage drift, high
input impedance, extremely low power, and high
gain.
PACKAGE
VIOmax
AT 25°C
SMALL
OUTLINE
(D)
0°C
to
70°C
500 µV
2 mV
5 mV
10 mV
TLC27L7CD
TLC27L2BCD
TLC27L2ACD
TLC27L2CD
− 40°C
to
85°C
500 µV
2 mV
5 mV
10 mV
TLC27L7ID
TLC27L2BID
TLC27L2AID
TLC27L2ID
− 55°C
to
125°C
500 µV
10 mV
TLC27L7MD
TLC27L2MD
TLC27L2MDRG4
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
—
TLC27L7CP
TLC27L2BCP
TLC27L2ACP
TLC27L2CP
—
—
TLC27L7IP
TLC27L2BIP
TLC27L2AIP
TLC27L2IP
TLC27L7MFK
TLC27L2MFK
TLC27L7MJG
TLC27L2MJG
TLC27L7MP
TLC27L2MP
—
Percentage of Units − %
25
AVAILABLE OPTIONS
TA
1
NC
1OUT
NC
VDD
NC
D
1OUT
1IN −
1IN +
GND
NC
GND
NC
2IN +
NC
D
335 Units Tested From 2 Wafer Lots
VDD = 5 V
TA = 25°C
P Package
20
15
10
5
0
−800
−400
0
400
800
VIO − Input Offset Voltage − µV
The D package is available taped and reeled. Add R suffix to the device type
(e.g., TLC27L7CDR).
LinCMOS is a trademark of Texas Instruments.
Copyright  2005, Texas Instruments Incorporated
!"#
$%
$ !
! & ' $$ (
)% $
!
* $ #) #$
* ## !%
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
description (continued)
These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset voltage
stability far exceeding the stability available with conventional metal-gate processes.
The extremely high input impedance, low bias currents, and low power consumption make these cost-effective
devices ideal for high gain, low frequency, low power applications. Four offset voltage grades are available
(C-suffix and I-suffix types), ranging from the low-cost TLC27L2 (10 mV) to the high-precision TLC27L7
(500 µV). These advantages, in combination with good common-mode rejection and supply voltage rejection,
make these devices a good choice for new state-of-the-art designs as well as for upgrading existing designs.
In general, many features associated with bipolar technology are available in LinCMOS operational amplifiers,
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27L2 and
TLC27L7. The devices also exhibit low voltage single-supply operation and ultra-low power consumption,
making them ideally suited for remote and inaccessible battery-powered applications. The common-mode input
voltage range includes the negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up.
The TLC27L2 and TLC27L7 incorporate internal ESD-protection circuits that prevent functional failures at
voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in
handling these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-Suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from − 40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
equivalent schematic (each amplifier)
VDD
P3
P4
R6
R1
N5
R2
IN −
P5
P1
P6
P2
IN +
R5
C1
OUT
N3
N1
R3
N2
D1
N4
R4
D2
GND
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
N6
R7
N7
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Total current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN −.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70
70°C
C
POWER RATING
TA = 85
85°C
C
POWER RATING
TA = 125
125°C
C
POWER RATING
5.8 mW/°C
464 mW
377 mW
—
D
725 mW
FK
1375 mW
11 mW/°C
880 mW
715 mW
275 mW
JG
1050 mW
8.4 mW/°C
672 mW
546 mW
210 mW
P
1000 mW
8 mW/°C
640 mW
520 mW
—
recommended operating conditions
Supply voltage, VDD
Common-mode input voltage, VIC
VDD = 5 V
VDD = 10 V
Operating free-air temperature, TA
POST OFFICE BOX 655303
C SUFFIX
I SUFFIX
M SUFFIX
MIN
MAX
MIN
MAX
MIN
MAX
3
16
4
16
4
16
−0.2
3.5
−0.2
3.5
0
3.5
−0.2
8.5
−0.2
8.5
0
8.5
0
70
−40
85
−55
125
• DALLAS, TEXAS 75265
UNIT
V
V
°C
3
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC27L2C
TLC27L2AC
TLC27L2BC
TLC27L7C
MIN
TLC27L2C
VIO
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
VIC = 0,
RL = 1 MΩ
Full range
TLC27L2BC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
Full range
TLC27L7C
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
αVIO
IIO
Input offset current (see Note 4)
VO = 2.5 V,
VIC = 2.5 V
IIB
Input bias current (see Note 4)
VO = 2.5 V,
VIC = 2.5 V
VOH
VOL
AVD
CMRR
kSVR
IDD
Low-level output voltage
Large-signal differential voltage
amplification
Common-mode rejection ratio
VID = 100 mV,
RL = 1 MΩ
VID = − 100 mV,
VO = 0.25 V to 2 V,
IOL = 0
RL = 1 MΩ
VIC = VICRmin
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply current (two amplifiers)
VO = 2.5 V,
No load
VO = 1.4 V
VIC = 2.5 V,
10
0.9
204
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mV
2000
3000
25°C
170
Full range
500
µV
V
1500
25 C to
25°C
70°C
1.1
25°C
0.1
60
70°C
7
300
25°C
0.6
60
70°C
50
600
25°C
25
C
−0.2
to
4
Full range
−0.2
to
3.5
25°C
3.2
4.1
0°C
3
4.1
70°C
3
4.2
µV/°C
V/°C
−0.3
to
4.2
pA
pA
V
V
V
25°C
0
50
0°C
0
50
70°C
0
50
25°C
50
700
0°C
50
700
70°C
50
380
25°C
65
94
0°C
60
95
70°C
60
95
25°C
70
97
0°C
60
97
70°C
60
98
mV
V/mV
dB
dB
25°C
20
34
0°C
24
42
70°C
16
28
† Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
4
5
6.5
25°C
Common-mode input voltage range
(see Note 5)
High-level output voltage
MAX
1.1
12
25°C
VO = 1.4 V,
RS = 50 Ω,
Input offset voltage
TYP
Full range
TLC27L2AC
Average temperature coefficient of input
offset voltage
VICR
25°C
UNIT
µA
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC27L2C
TLC27L2AC
TLC27L2BC
TLC27L7C
MIN
VO = 1.4 V,
RS = 50 Ω,
TLC27L2C
VIO
VIC = 0,
RL = 1 MΩ
25°C
MAX
1.1
10
12
25°C
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
Full range
TLC27L2BC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
Full range
TLC27L7C
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
Full range
Input offset voltage
TYP
Full range
TLC27L2AC
UNIT
0.9
5
6.5
25°C
235
2000
3000
25°C
190
800
Average temperature coefficient of input
offset voltage
25°C
0.1
60
IIO
Input offset current (see Note 4)
VO = 5 V,
VIC = 5 V
70°C
8
300
25°C
0.7
60
IIB
Input bias current (see Note 4)
VO = 5 V,
VIC = 5 V
70°C
50
600
VICR
VOH
VOL
AVD
CMRR
kSVR
IDD
High-level output voltage
25°C to
70°C
Low-level output voltage
Large-signal differential voltage
amplification
Common-mode rejection ratio
VID = 100 mV,
RL = 1 MΩ
VID = − 100 mV,
IOL = 0
VO = 1 V to 6 V,
RL = 1 MΩ
VIC = VICRmin
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply current (two amplifiers)
VO = 5 V,
No load
VO = 1.4 V
VIC = 5 V,
µV
1900
αVIO
µV/°C
1
25°C
25
C
−0.2
to
9
Full range
−0.2
to
8.5
Common-mode input voltage range
(see Note 5)
mV
−0.3
to
9.2
pA
pA
V
V
25°C
8
8.9
0°C
7.8
8.9
70°C
7.8
8.9
V
25°C
0
50
0°C
0
50
70°C
0
50
25°C
50
860
0°C
50
1025
70°C
50
660
25°C
65
97
0°C
60
97
70°C
60
97
25°C
70
97
0°C
60
97
70°C
60
98
mV
V/mV
dB
dB
25°C
29
46
0°C
36
66
70°C
22
40
µA
† Full range is 0°C to 70°C.
NOTES: 4 The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5 This range also applies to each input individually.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC27L2I
TLC27L2AI
TLC27L2BI
TLC27L7I
MIN
VO = 1.4 V,
RS = 50 Ω,
TLC27L2I
VIO
VIC = 0,
RL = 1 MΩ
VIC = 0,
RL = 1 MΩ
Full range
TLC27L2BI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
Full range
TLC27L7I
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
αVIO
IIO
Input offset current (see Note 4)
VO = 2.5 V,
VIC = 2.5 V
IIB
Input bias current (see Note 4)
VO = 2.5 V,
VIC = 2.5 V
VOH
VOL
AVD
CMRR
kSVR
IDD
Low-level output voltage
Large-signal differential
voltage amplification
Common-mode rejection ratio
VID = 100 mV,
RL = 1 MΩ
VID = − 100 mV,
IOL = 0
VO = 0.25 V to 2 V,
RL = 1 MΩ
VIC = VICRmin
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply current (two amplifiers)
VO = 2.5 V,
No load
VO = 1.4 V
VIC = 2.5 V,
10
0.9
240
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mV
2000
3500
25°C
170
Full range
500
µV
V
2000
25 C to
25°C
85°C
1.1
25°C
0.1
60
85°C
24
1000
25°C
0.6
60
85°C
200
2000
25°C
25
C
−0.2
to
4
Full range
−0.2
to
3.5
25°C
3.2
4.1
−40°C
3
4.1
85°C
3
4.2
µV/°C
V/°C
−0.3
to
4.2
pA
pA
V
V
V
25°C
0
50
−40°C
0
50
85°C
0
50
25°C
50
480
−40°C
50
900
85°C
50
330
25°C
65
94
−40°C
60
95
85°C
60
95
25°C
70
97
−40°C
60
97
85°C
60
98
mV
V/mV
dB
dB
25°C
20
34
−40°C
31
54
85°C
15
26
† Full range is − 40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6
5
7
25°C
Common-mode input voltage range
(see Note 5)
High-level output voltage
MAX
1.1
13
25°C
VO = 1.4 V,
RS = 50 Ω,
Input offset voltage
TYP
Full range
TLC27L2AI
Average temperature coefficient of
input offset voltage
VICR
25°C
UNIT
µA
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC27L2I
TLC27L2AI
TLC27L2BI
TLC27L7I
MIN
TLC27L2I
VIO
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
VIC = 0,
RL = 1 MΩ
Full range
TLC27L2BI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
Full range
TLC27L7I
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
αVIO
IIO
Input offset current (see Note 4)
VO = 5 V,
VIC = 5 V
IIB
Input bias current (see Note 4)
VO = 5 V,
VIC = 5 V
VOH
VOL
AVD
CMRR
kSVR
IDD
Low-level output voltage
Large-signal differential voltage
amplification
Common-mode rejection ratio
RL = 1 MΩ
VID = − 100 mV,
VO = 1 V to 6 V,
IOL = 0
RL = 1 MΩ
VIC = VICRmin
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply current (two amplifiers)
VO = 5 V,
No load
VO = 1.4 V
VIC = 5 V,
5
mV
7
235
2000
3500
25°C
190
Full range
800
µV
V
2900
25 C to
25°C
85°C
VID = 100 mV,
10
0.9
25°C
µV/°C
V/°C
1
25°C
0.1
60
85°C
26
1000
25°C
0.7
60
85°C
220
2000
25°C
25
C
−0.2
to
9
Full range
−0.2
to
8.5
Common-mode input voltage range
(see Note 5)
High-level output voltage
MAX
1.1
13
25°C
VO = 1.4 V,
RS = 50 Ω,
Input offset voltage
TYP
Full range
TLC27L2AI
Average temperature coefficient of input
offset voltage
VICR
25°C
UNIT
−0.3
to
9.2
pA
pA
V
V
25°C
8
8.9
−40°C
7.8
8.9
85°C
7.8
8.9
V
25°C
0
50
−40°C
0
50
85°C
0
50
25°C
50
860
−40°C
50
1550
85°C
50
585
25°C
65
97
−40°C
60
97
85°C
60
98
25°C
70
97
−40°C
60
97
85°C
60
98
mV
V/mV
dB
dB
25°C
29
46
−40°C
49
86
85°C
20
36
µA
† Full range is − 40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC27L2M
TLC27L7M
MIN
VIO
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
Full range
TLC27L7M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
Full range
Input offset voltage
αVIO
Average temperature coefficient of
input offset voltage
IIO
Input offset current (see Note 4)
IIB
25°C
TLC27L2M
Input bias current (see Note 4)
VO = 2.5 V,
VO = 2.5 V,
VIC = 2.5 V
VIC = 2.5 V
VOL
AVD
CMRR
kSVR
IDD
Low-level output voltage
VID = 100 mV,
VID = − 100 mV,
Large-signal differential voltage
amplification
VO = 0.25 V to 2 V,
Common-mode rejection ratio
VIC = VICRmin
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply current (two amplifiers)
VO = 2.5 V,
No load
RL = 1 MΩ
IOL = 0
RL = 1 MΩ
VO = 1.4 V
VIC = 2.5 V,
10
170
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mV
µV
µV/°C
25°C
0.1
60
pA
125°C
1.4
15
nA
25°C
0.6
60
pA
125°C
9
35
nA
−0.3
to
4.2
25°C
0
to
4
0
to
3.5
3.2
−55°C
3
4.1
125°C
3
4.2
V
V
4.1
V
25°C
0
50
−55°C
0
50
125°C
0
50
25°C
50
500
−55°C
25
1000
125°C
25
200
25°C
65
94
−55°C
60
95
125°C
60
85
25°C
70
97
−55°C
60
97
125°C
60
98
mV
V/mV
dB
dB
25°C
20
34
−55°C
35
60
125°C
14
24
† Full range is − 55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
8
500
3750
1.4
Common-mode input voltage range
(see Note 5)
High-level output voltage
1.1
25 C to
25°C
125°C
Full range
VOH
MAX
12
25°C
25°C
25
C
VICR
UNIT
TYP
µA
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC27L2M
TLC27L7M
MIN
VIO
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
Full range
TLC27L7M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 1 MΩ
Full range
Input offset voltage
αVIO
Average temperature coefficient of
input offset voltage
IIO
Input offset current (see Note 4)
IIB
VICR
25°C
TLC27L2M
Input bias current (see Note 4)
VO = 5 V,
VIC = 5 V
VO = 5 V,
VIC = 5 V
VOL
AVD
CMRR
kSVR
IDD
Low-level output voltage
Large-signal differential voltage
amplification
Common-mode rejection ratio
VID = 100 mV,
RL = 1 MΩ
VID = − 100 mV,
IOL = 0
VO = 1 V to 6 V,
RL = 1 MΩ
VIC = VICRmin
Supply-voltage rejection ratio
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply current (two amplifiers)
VO = 5 V,
No load
VO = 1.4 V
VIC = 5 V,
1.1
10
190
800
4300
25 C to
25°C
125°C
25°C
mV
µV
µV/°C
1.4
0.1
60
pA
125°C
1.8
15
nA
25°C
0.7
60
pA
125°C
10
35
nA
25°C
25
C
0
to
9
Full range
0
to
8.5
Common-mode input voltage range
(see Note 5)
High-level output voltage
MAX
12
25°C
25°C
VOH
UNIT
TYP
−0.3
to
9.2
V
V
8
8.9
−55°C
7.8
8.8
125°C
7.8
9
V
25°C
0
50
−55°C
0
50
125°C
0
50
25°C
50
860
−55°C
25
1750
125°C
25
380
25°C
65
97
−55°C
60
97
125°C
60
91
25°C
70
97
−55°C
60
97
125°C
60
98
mV
V/mV
dB
dB
25°C
29
46
−55°C
56
96
125°C
18
30
µA
† Full range is − 55 °C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
operating characteristics, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC27L2C
TLC27L2AC
TLC27L2BC
TLC27L7C
MIN
VI(PP) = 1 V
SR
RL = 1 MΩ,
M ,
CL = 20 pF,
See Figure 1
Slew rate at unity gain
VI(PP) = 2.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
B1
φm
Unity-gain bandwidth
VI = 10 mV,
CL = 20 pF,
Phase margin
f = B1,
See Figure 3
TYP
25°C
0.03
0°C
0.04
70°C
0.03
25°C
0.03
0°C
0.03
70°C
0.02
25°C
68
25°C
5
0°C
6
70°C
4.5
25°C
85
0°C
100
70°C
65
25°C
34°
0°C
36°
70°C
30°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
kHz
operating characteristics, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC27L2C
TLC27L2AC
TLC27L2BC
TLC27L7C
MIN
VI(PP) = 1 V
SR
Slew rate at unity gain
RL = 1 MΩ,
M ,
CL = 20 pF,
See Figure 1
VI(PP) = 5.5 V
Vn
BOM
B1
φm
10
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 pF,
POST OFFICE BOX 655303
f = B1,
See Figure 3
• DALLAS, TEXAS 75265
TYP
25°C
0.05
0°C
0.05
70°C
0.04
25°C
0.04
0°C
0.05
70°C
0.04
25°C
68
25°C
1
0°C
1.3
70°C
0.9
25°C
110
0°C
125
70°C
90
25°C
38°
0°C
40°
70°C
34°
UNIT
MAX
V/
V/µss
nV/√Hz
kHz
kHz
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
operating characteristics, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC27L2I
TLC27L2AI
TLC27L2BI
TLC27L7I
MIN
VI(PP) = 1 V
SR
RL = 1 MΩ,
M ,
CL = 20 pF,
See Figure 1
Slew rate at unity gain
VI(PP) = 2.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
B1
φm
Unity-gain bandwidth
VI = 10 mV,
CL = 20 pF,
Phase margin
f = B1,
See Figure 3
TYP
25°C
0.03
−40°C
0.04
85°C
0.03
25°C
0.03
−40°C
0.04
85°C
0.02
25°C
68
25°C
5
−40°C
7
85°C
4
25°C
85
−40°C
130
85°C
55
25°C
34°
−40°C
38°
85°C
29°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
kHz
operating characteristics, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC27L2I
TLC27L2AI
TLC27L2BI
TLC27L7I
MIN
VI(PP) = 1 V
SR
Slew rate at unity gain
RL = 1 MΩ,
M ,
CL = 20 pF,
See Figure 1
VI(PP) = 5.5 V
Vn
BOM
B1
φm
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 pF,
POST OFFICE BOX 655303
f = B1,
See Figure 3
• DALLAS, TEXAS 75265
TYP
25°C
0.05
−40°C
0.06
85°C
0.03
25°C
0.04
−40°C
0.05
85°C
0.03
25°C
68
25°C
1
−40°C
1.4
85°C
0.8
25°C
110
−40°C
155
85°C
80
25°C
38°
−40°C
42°
85°C
32°
UNIT
MAX
V/
V/µss
nV/√Hz
kHz
kHz
11
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
operating characteristics, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC27L2M
TLC27L7M
MIN
VI(PP) = 1 V
SR
RL = 1 MΩ,
M ,
CL = 20 pF,
See Figure 1
Slew rate at unity gain
VI(PP) = 2.5 V
Vn
BOM
B1
φm
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
Unity-gain bandwidth
VI = 10 mV,
CL = 20 pF,
Phase margin
f = B1,
See Figure 3
TYP
25°C
0.03
−55°C
0.04
125°C
0.02
25°C
0.03
−55°C
0.04
125°C
0.02
25°C
68
25°C
5
−55°C
8
125°C
3
25°C
85
−55°C
140
125°C
45
25°C
34°
−55°C
39°
125°C
25°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
kHz
operating characteristics, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC27L2M
TLC27L7M
MIN
VI(PP) = 1 V
SR
Slew rate at unity gain
M ,
RL = 1 MΩ,
CL = 20 pF,
See Figure 1
VI(PP) = 5.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
BOM
Maximum output-swing bandwidth
VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 1
VI = 10 mV,
See Figure 3
CL = 20 pF,
B1
φm
12
Unity-gain bandwidth
Phase margin
VI = 10 mV,
CL = 20 pF,
POST OFFICE BOX 655303
f = B1,
See Figure 3
• DALLAS, TEXAS 75265
TYP
25°C
0.05
−55°C
0.06
125°C
0.03
25°C
0.04
−55°C
0.06
125°C
0.03
25°C
68
25°C
1
−55°C
1.5
125°C
0.7
25°C
110
−55°C
165
125°C
70
25°C
38°
−55°C
43°
125°C
29°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
kHz
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC27L2 and TLC27L7 are optimized for single-supply operation, circuit configurations used for
the various tests often present some inconvenience since the input signal, in many cases, must be offset from
ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to
the negative rail. A comparison of single-supply versus split-supply test circuits is shown in Figure 1. The use
of either circuit gives the same result.
VDD +
VDD
−
−
VO
VO
VI
+
CL
RL
+
VI
CL
RL
VDD −
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 1. Unity-Gain Amplifier
2 kΩ
2 kΩ
VDD +
VDD
−
20 Ω
−
VO
VO
+
1/2 VDD
+
20 Ω
20 Ω
20 Ω
VDD −
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 2. Noise-Test Circuit
10 kΩ
VDD
VDD +
100 Ω
−
100 Ω
VI
−
VI
10 kΩ
VO
VO
+
+
1/2 VDD
CL
CL
VDD −
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 3. Gain-of-100 Inverting Amplifier
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLC27L2 and TLC27L7 operational amplifiers, attempts to measure
the input bias current can result in erroneous readings. The bias current at normal room ambient temperature
is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are
offered to avoid erroneous measurements:
1.
Isolate the device from other potential leakage sources.Use a grounded shield around and between the
device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using
a picoammeter) with no device in the test socket. The actual input bias current can then be calculated
by subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires that a
device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not
feasible using this method.
8
5
V = VIC
1
4
Figure 4. Isolation Metal Around Device Inputs
(JG and P packages)
low-level output voltage
To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well
as the differential input voltage level. When attempting to correlate low-level output readings with those quoted
in the electrical specifications, these two conditions should be observed. If conditions other than these are to
be used, please refer to Figure 14 through Figure 19 in the Typical Characteristics of this data sheet.
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
14
POST OFFICE BOX 655303
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 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(see Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 100 kHz
(b) BOM > f > 100 kHz
(c) f = BOM
(d) f > BOM
Figure 5. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS high-volume, short-test-time
environment. Internal capacitances are inherently higher in CMOS devices and require longer test times than
their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and
lower temperatures.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
16
VIO
αVIO
Input offset voltage
Distribution
6, 7
Temperature coefficient of input offset voltage
Distribution
8, 9
VOH
High-level output voltage
vs High-level output current
vs Supply voltage
vs Free-air temperature
10, 11
12
13
VOL
Low-level output voltage
vs Differential input voltage
vs Free-air temperature
vs Low-level output current
14,16
15,17
18, 19
AVD
Large-signal differential voltage amplification
vs Supply voltage
vs Free-air temperature
vs Frequency
20
21
32, 33
IIB
IIO
Input bias current
vs Free-air temperature
22
Input offset current
vs Free-air temperature
22
VIC
Common-mode input voltage
vs Supply voltage
23
IDD
Supply current
vs Supply voltage
vs Free-air temperature
24
25
SR
Slew rate
vs Supply voltage
vs Free-air temperature
26
27
Normalized slew rate
vs Free-air temperature
28
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
29
B1
Unity-gain bandwidth
vs Free-air temperature
vs Supply voltage
30
31
φm
Phase margin
vs Supply voltage
vs Free-air temperature
vs Capacitive Load
34
35
36
Vn
Equivalent input noise voltage
vs Frequency
37
Phase shift
vs Frequency
32, 33
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC27L2
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC27L2
INPUT OFFSET VOLTAGE
70
70
905 Amplifiers Tested From 6 Wafer Lots
VDD = 5 V
TA = 25°C
P Package
60
Percentage of Units − %
Percentage of Units − %
60
905 Amplifiers Tested From 6 Wafer Lots
VDD = 10 V
TA = 25°C
P Package
50
40
30
20
50
40
30
20
10
10
0
0
−5
−4
−3 −2 −1 0
1
2
3
VIO − Input Offset Voltage − mV
4
−5
5
−4
Figure 6
70
356 Amplifiers Tested From 8 Wafer Lots
VDD = 5 V
TA = 25°C to 125°C
P Package
Outliers:
(1) 19.2 µV/°C
(1) 12.1 µV/°C
60
Percentage of Units − %
Percentage of Units − %
5
DISTRIBUTION OF TLC27LC AND TLC27L7
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
70
50
4
Figure 7
DISTRIBUTION OF TLC27LC AND TLC27L7
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
60
−3 −2 −1 0
1
2
3
VIO − Input Offset Voltage − mV
40
30
20
50
40
356 Amplifiers Tested From 8 Wafer Lots
VDD = 10 V
TA = 25°C to 125°C
P Package
Outliers:
(1) 18.7 µV/°C
(1) 11.6 µV/°C
30
20
10
10
0
2
4
6
8
−10 −8 −6 −4 −2 0
αVIO − Temperature Coefficient − µV/°C
10
0
−10 −8 −6 −4 −2 0
2
4
6
8
αVIO − Temperature Coefficient − µV/°C
10
Figure 9
Figure 8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS†
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
16
VOH
VOH − High-Level Output Voltage − V
VOH
VOH − High-Level Output Voltage − V
VID = 100 mV
TA = 25°C
4
VDD = 5 V
3
VDD = 4 V
ÁÁ
ÁÁ
ÁÁ
VDD = 3 V
2
0
0
VDD = 16 V
12
−2
−4
−6
−8
IOH − High-Level Output Current − mA
8
VDD = 10 V
6
4
2
0
− 10
0
− 5 − 10 − 15 − 20 − 25 − 30 − 35 − 40
IOH − High-Level Output Current − mA
Figure 11
Figure 10
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
VID = 100 mV
RL = 10 kΩ
TA = 25°C
14
12
10
ÁÁ
ÁÁ
ÁÁ
8
ÁÁ
ÁÁ
ÁÁ
6
4
2
0
0
2
ÁÁÁÁÁ
ÁÁÁÁÁ
VDD − 1.6
VOH
VOH − High-Level Output Voltage − V
VOH
VOH − High-Level Output Voltage − V
16
VID = 100 mV
TA = 25°C
10
ÁÁ
ÁÁ
ÁÁ
1
ÎÎÎÎÎ
ÎÎÎÎÎ
14
4
6
8
10
12
VDD − Supply Voltage − V
14
16
−1.7
VDD = 5 V
−1.8
IOH = − 5 mA
VID = 100 mA
−1.9
−2
VDD = 10 V
−2.1
−2.2
−2.3
−2.4
−75
−50
−25
0
20
50
75
100
TA − Free-Air Temperature − °C
Figure 13
Figure 12
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS†
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
700
500
VOL
VOL − Low-Level Output Voltage − mV
VOL
VOL − Low-Level Output Voltage − mV
VDD = 5 V
IOL = 5 mA
TA = 25°C
600
VID = − 100 mV
500
ÁÁ
ÁÁ
ÁÁ
ÁÁ
400
VID = − 1 V
300
0
0.5
1
1.5
2
2.5
3
3.3
VIC − Common-Mode Input Voltage − V
4
VDD = 10 V
IOL = 5 mA
TA = 25°C
450
400
VID = − 100 mV
VID = − 1 V
350
VID = − 2.5 V
300
250
0
2
4
6
8
1
3
5
7
9
VIC − Common-Mode Input Voltage − V
Figure 15
Figure 14
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
900
IOL = 5 mA
VIC = |VID/2|
TA = 25°C
VOL
VOL − Low-Level Output Voltage − mV
VOL
VOL − Low-Level Output Voltage − mV
800
700
600
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
500
VDD = 5 V
400
300
VDD = 10 V
ÁÁ
ÁÁ
200
100
−1
800
700
600
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
IOL = 5 mA
VID = − 1 V
VIC = 0.5 V
500
−2 −3 −4 −5 −6 −7 −8 −9 −10
VID − Differential Input Voltage − V
VDD = 5 V
ÎÎÎÎÎ
ÎÎÎÎÎ
400
VDD = 10 V
300
ÁÁÁ
ÁÁÁ
0
0
10
200
100
0
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
Figure 17
Figure 16
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS†
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL
VOL − Low-Level Output Voltage − V
0.9
0.8
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VDD = 5 V
0.7
VDD = 4 V
0.6
VDD = 3 V
0.5
ÁÁ
ÁÁ
ÁÁ
0.4
0.2
0.1
0
1
2
3
4
5
6
7
IOL − Low-Level Output Current − mA
VID = − 1 V
VIC = 0.5 V
TA = 25°C
2.5
2
1.5
1
0.5
0
8
0
5
10
15
20
25
IOL − Low-Level Output Current − mA
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
2000
2000
AVD
AVD − Large-Signal Differential
Voltage Amplification − V/mV
TA = − 55°C
1600
1400
TA = 0°C
1600
1400
ÎÎ
ÎÎ
ÎÎ
ÎÎÁÁ
ÁÁ
ÁÁ
1200
25°C
1000
70°C
800
85°C
600
400
125°C
200
0
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
16
RL = 1 MΩ
1800
−40°C
AVD
AVD − Large-Signal Differential
Voltage Amplification − V/mV
RL = 1 MΩ
1800
VDD = 10 V
1200
1000
800
600
VDD = 5 V
400
200
0
−75
−50
Figure 20
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 21
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
20
30
Figure 19
Figure 18
Á
Á
Á
VDD = 16 V
VDD = 10 V
ÁÁ
ÁÁ
ÁÁ
0.3
0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
3
VID = − 1 V
VIC = 0.5 V
TA = 25°C
VOL
VOL − Low-Level Output Voltage − V
1
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
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 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS†
COMMON-MODE
INPUT VOLTAGE POSITIVE LIMIT
vs
SUPPLY VOLTAGE
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
10000
16
VDD = 10 V
VIC = 5 V
See Note A
1000
100
ÎÎ
VI − Common-Mode Input Voltage − V
VIC
IIIB
I IO − Input Bias and Offset Currents − pA
IB and IIO
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
IIB
ÎÎ
IIO
10
1
0.1
25
45
65
85
105
TA − Free-Air Temperature − °C
125
TA = 25°C
14
12
10
8
6
ÁÁ
ÁÁ
4
2
0
0
2
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
4
6
8
10
12
VDD − Supply Voltage − V
14
16
Figure 23
Figure 22
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
90
60
TA = − 55°C
VO = VDD/2
No Load
80
VO = VDD/2
No Load
ÁÁ
ÁÁ
−40°C
60
50
0°C
40
25°C
30
70°C
20
125°C
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
40
VDD = 10 V
30
ÁÁ
ÁÁ
20
VDD = 5 V
10
10
0
IDD
mA
I DD − Supply Current − µ
A
IDD
mA
I DD − Supply Current − µ
A
50
70
16
0
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
Figure 25
Figure 24
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS†
SLEW RATE
vs
SUPPLY VOLTAGE
SLEW RATE
vs
FREE-AIR TEMPERATURE
0.07
0.07
AV = 1
VI(PP) = 1 V
RL =1 MΩ
CL = 20 pF
TA = 25°C
See Figure 1
0.05
0.06
SR − Slew Rate − V/sµ s
SR − Slew Rate − V/sµ s
0.06
0.04
0.03
0.03
0.01
0.01
2
4
6
8
10
12
VDD − Supply Voltage − V
14
0.00
−75
16
VDD = 10 V
VI(PP) = 1 V
0.04
0.02
0.00
VDD = 5 V
VI(PP) = 1 V
VDD = 5 V
VI(PP) = 2.5 V
−50
NORMALIZED SLEW RATE
vs
FREE-AIR TEMPERATURE
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
Normalized Slew Rate
1.2
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
1.1
1
AV = 1
VIPP = 1 V
RL =1 MΩ
CL = 20 pF
VDD = 5 V
ÁÁ
ÁÁ
ÁÁ
0.9
0.8
0.7
0.6
0.5
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
10
9
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
8
VDD = 10 V
7
6
5
TA = 125°C
TA = 25°C
TA = − 55°C
VDD = 5 V
4
3
RL = 1 MΩ
See Figure 1
2
1
0
0.1
Figure 28
1
10
f − Frequency − kHz
Figure 29
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
125
MAXIMUM-PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
1.4
VDD = 10 V
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 27
Figure 26
1.3
RL =1 MΩ
CL = 20 pF
AV = 1
See Figure 1
0.05
0.02
0
VDD = 10 V
VI(PP) = 5.5 V
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 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS†
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
150
140
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
B1
B1 − Unity-Gain Bandwidth − kHz
B1
B1 − Unity-Gain Bandwidth − kHz
130
VI = 10 mV
CL = 20 pF
TA = 25°C
See Figure 3
130
110
90
70
50
120
110
100
90
80
70
60
30
−75
50
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
0
125
2
4
6
8
10
12
VDD − Supply Voltage − V
14
16
Figure 31
Figure 30
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 7
VDD = 10 V
RL = 1 MΩ
TA = 25°C
ÁÁ
ÁÁ
ÁÁ
10 5
0°
10 4
30°
AVD
10 3
10 2
60°
ÎÎÎÎÎ
Phase Shift
AVD
AVD − Large-Signal Differential
Voltage Amplification
10 6
90°
Phase Shift
10 1
120°
1
0.1
1
150°
10
100
1k
10 k
f − Frequency − Hz
100 k
180°
1M
Figure 32
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS†
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 7
VDD = 10 V
RL = 1 MΩ
TA = 25°C
ÁÁ
ÁÁ
ÁÁ
10 5
0°
10 4
30°
AVD
10 3
60°
ÎÎÎÎÎ
ÎÎÎÎÎ
10 2
90°
Phase Shift
AVD
AVD − Large-Signal Differential
Voltage Amplification
10 6
Phase Shift
10 1
120°
1
150°
0.1
1
10
100
1k
10 k
f − Frequency − Hz
100 k
180°
1M
Figure 33
PHASE MARGIN
vs
SUPPLY VOLTAGE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
42°
40°
VI = 10 mV
CL = 20 pF
TA = 25°C
See Figure 3
Á
Á
36°
38°
φm
m − Phase Margin
φm
m − Phase Margin
40°
VDD = 5 mV
VI = 10 mV
CL = 20 pF
See Figure 3
32°
ÁÁ
ÁÁ
36°
34°
28°
24°
32°
30°
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
16
20°
−75
− 50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 34
Figure 35
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
24
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125
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
CAPACITIVE LOAD
37°
ÁÁ
ÁÁ
ÁÁ
ÁÁ
33°
31°
ÁÁ
ÁÁ
29°
27°
25°
0
10
20
30 40 50 60 70 80
CL − Capacitive Load − pF
90 100
VN
nV/HzHz
V n− Equivalent Input Noise Voltage − nV/
200
VDD = 5 mV
VI = 10 mV
TA = 25°C
See Figure 3
35°
φm
m − Phase Margin
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
VDD = 5 V
RS = 20 Ω
TA = 25°C
See Figure 2
175
150
125
100
75
50
25
0
1
Figure 36
10
100
f − Frequency − Hz
1000
Figure 37
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 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
APPLICATION INFORMATION
single-supply operation
While the TLC27L2 and TLC27L7 perform well using dual power supplies (also called balanced or split
supplies), the design is optimized for single-supply operation. This design includes an input common-mode
voltage range that encompasses ground as well as an output voltage range that pulls down to ground. The
supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly
available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is
recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC27L2 and TLC27L7 permits the use of very large resistive values to
implement the voltage divider, thus minimizing power consumption.
The TLC27L2 and TLC27L7 work well in conjunction with digital logic; however, when powering both linear
devices and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
VDD
R4
R1
R2
−
VI
VO
+
VREF
R3
V
REF
V
C
0.01 µF
O
+ V
+
R3
DD R1 ) R3
ǒVREF – VI Ǔ R4
R2
) V
Figure 38. Inverting Amplifier With Voltage Reference
−
VO
Logic
Logic
Logic
Power
Supply
+
(a) COMMON SUPPLY RAILS
−
+
VO
Logic
Logic
Logic
Power
Supply
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
Figure 39. Common Versus Separate Supply Rails
26
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REF
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
APPLICATION INFORMATION
input characteristics
The TLC27L2 and TLC27L7 are specified with a minimum and a maximum input voltage that, if exceeded at
either input, could cause the device to malfunction. Exceeding this specified range is a common problem,
especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper
range limit is specified at VDD −1 V at TA = 25°C and at VDD −1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC27L2 and TLC27L7
very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage
drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC27L2 and
TLC27L7 are well suited for low-level signal processing; however, leakage currents on printed circuit boards
and sockets can easily exceed bias current requirements and cause a degradation in device performance. It
is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC27L2 and TLC27L7 result in a low noise
current, which is insignificant in most applications. This feature makes the devices especially favorable over
bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater
noise currents.
VO
+
(b) INVERTING AMPLIFIER
VI
+
−
−
+
(a) NONINVERTING AMPLIFIER
VI
−
VI
VO
VO
(c) UNITY-GAIN AMPLIFIER
Figure 40. Guard-Ring Schemes
output characteristics
The output stage of the TLC27L2 and TLC27L7 is designed to sink and source relatively high amounts of current
(see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can
cause device damage under certain conditions. Output current capability increases with supply voltage.
All operating characteristics of the TLC27L2 and TLC27L7 were measured using a 20-pF load. The devices
drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole
occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many
cases, adding a small amount of resistance in series with the load capacitance alleviates the problem.
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 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
APPLICATION INFORMATION
output characteristics (continued)
(a) CL = 20 pF, RL = NO LOAD
(b) CL = 260 pF, RL = NO LOAD
2.5 V
−
VO
+
VI
TA = 25°C
f = 1 kHz
VI(PP) = 1 V
CL
−2.5 V
(d) TEST CIRCUIT
(c) CL = 310 pF, RL = NO LOAD
Figure 41. Effect of Capacitive Loads and Test Circuit
Although the TLC27L2 and TLC27L7 possess excellent high-level output voltage and current capability,
methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup
resistor (RP) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages
to the use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a
comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance
between approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With
very low values of RP, a voltage offset from 0 V at the output occurs. Second, pullup resistor RP acts as a
drain load to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not
supplying the output current.
28
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 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
APPLICATION INFORMATION
output characteristics (continued)
VDD
VI
+
RP
IP
C
VO
−
IF
R2
RL
−
IL
R1
VO
+
V –V
DD O
) I ) I
F
L
P
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
R
P
+
I
IP = Pullup current required
by the operational amplifier
(typically 500 µA)
Figure 42. Resistive Pullup to Increase VOH
Figure 43. Compensation for
Input Capacitance
feedback
Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
electrostatic discharge protection
The TLC27L2 and TLC27L7 incorporate an internal electrostatic discharge (ESD) protection circuit that
prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care
should be exercised, however, when handling these devices, as exposure to ESD may result in the degradation
of the device parametric performance. The protection circuit also causes the input bias currents to be
temperature dependent and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27L2 and
TLC27L7 inputs and outputs were designed to withstand −100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
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29
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
APPLICATION INFORMATION
1/2
TLC27L2
+
VO1
500 kΩ
−
5V
500 kΩ
+
VO2
−
1/2
TLC27L2
0.1 µF
500 kΩ
500 kΩ
Figure 44. Multivibrator
100 kΩ
VDD
100 kΩ
Set
+
−
Reset
100 kΩ
1/2
TLC27L2
33 kΩ
NOTE: VDD = 5 V to 16 V
Figure 45. Set /Reset Flip-Flop
30
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 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
APPLICATION INFORMATION
VDD
VI
1/2
TLC27L7
+
VO
−
90 kΩ
VDD
C
S1
SELECT:
AV
S1
10
X1
TLC4066
A
S2
100
B
1
9 kΩ
C
S2
1
X2
A
Analog
Switch
2
B
2
1 kΩ
NOTE: VDD = 5 V to 12 V
Figure 46. Amplifier With Digital Gain Selection
10 kΩ
VDD
20 kΩ
−
VI
VO
1/2
TLC27L2
100 kΩ
+
NOTE: VDD = 5 V to 16 V
Figure 47. Full-Wave Rectifier
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31
 SLOS052D − OCTOBER 1987 − REVISED OCTOBER 2005
APPLICATION INFORMATION
0.016 µF
5V
VI
10 kΩ
10 kΩ
+
VO
0.016 µF
−
1/2
TLC27L2
NOTE: Normalized to fc = 1 kHz and RL = 10 kΩ
Figure 48. Two-Pole Low-Pass Butterworth Filter
R2
100 kΩ
VDD
R1
10 kΩ
VIA
−
R1
10 kΩ
VIB
VO
+
1/2
TLC27L7
R2
100 kΩ
NOTE: VDD = 5 V to 16 V
V
+ R2 V – V
IA
O
R1 IB
ǒ
Ǔ
Figure 49. Difference Amplifier
32
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
5962-89494032A
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
5962-8949403PA
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
5962-89494042A
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
5962-8949404PA
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
TLC27L2ACD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2AC
TLC27L2ACDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2AC
TLC27L2ACDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2AC
TLC27L2ACDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2AC
TLC27L2ACP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27L2AC
TLC27L2ACPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27L2AC
TLC27L2ACPSLE
OBSOLETE
SO
PS
8
TBD
Call TI
Call TI
0 to 70
TLC27L2AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2AI
TLC27L2AIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2AI
TLC27L2AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2AI
TLC27L2AIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2AI
TLC27L2AIP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27L2AI
TLC27L2AIPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27L2AI
TLC27L2AMFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLC27L2AMJG
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
TLC27L2AMJGB
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC27L2BCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2BC
TLC27L2BCDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2BC
TLC27L2BCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2BC
TLC27L2BCDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2BC
TLC27L2BCP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27L2BC
TLC27L2BCPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27L2BC
TLC27L2BID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2BI
TLC27L2BIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2BI
TLC27L2BIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2BI
TLC27L2BIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2BI
TLC27L2BIP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27L2BI
TLC27L2BIPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27L2BI
TLC27L2CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2C
TLC27L2CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2C
TLC27L2CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2C
TLC27L2CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L2C
TLC27L2CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27L2CP
TLC27L2CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27L2CP
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC27L2CPSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27L2
TLC27L2CPSRG4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27L2
TLC27L2CPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27L2
TLC27L2CPWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27L2
TLC27L2CPWLE
OBSOLETE
TSSOP
PW
8
TBD
Call TI
Call TI
0 to 70
TLC27L2CPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27L2
TLC27L2CPWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27L2
TLC27L2ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2I
TLC27L2IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2I
TLC27L2IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2I
TLC27L2IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L2I
TLC27L2IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27L2IP
TLC27L2IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27L2IP
TLC27L2IPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Y27L2
TLC27L2IPWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Y27L2
TLC27L2IPWLE
OBSOLETE
TSSOP
PW
8
TBD
Call TI
Call TI
-40 to 85
TLC27L2IPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Y27L2I
TLC27L2IPWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Y27L2I
TLC27L2MD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
27L2M
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC27L2MDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
27L2M
TLC27L2MDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
27L2M
TLC27L2MDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
27L2M
TLC27L2MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLC27L2MJG
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
TLC27L2MJGB
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
TLC27L7CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L7C
TLC27L7CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L7C
TLC27L7CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L7C
TLC27L7CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
27L7C
TLC27L7CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27L7CP
TLC27L7CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC27L7CP
TLC27L7CPSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27L7
TLC27L7CPSRG4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P27L7
TLC27L7ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L7I
TLC27L7IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L7I
TLC27L7IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L7I
TLC27L7IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
27L7I
TLC27L7IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC27L7IP
Addendum-Page 4
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
TLC27L7IPE4
ACTIVE
PDIP
P
8
TLC27L7MFKB
OBSOLETE
LCCC
FK
TLC27L7MJG
OBSOLETE
CDIP
JG
TLC27L7MJGB
OBSOLETE
CDIP
JG
50
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
20
TBD
Call TI
Call TI
-55 to 125
8
TBD
Call TI
Call TI
-55 to 125
8
TBD
Call TI
Call TI
-55 to 125
TLC27L7IP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC27L2, TLC27L2M :
• Catalog: TLC27L2
Addendum-Page 5
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
• Military: TLC27L2M
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 6
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC27L2ACDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2BCDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2BIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2CPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TLC27L2IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2MDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L2MDRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L7CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC27L7CPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TLC27L7IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC27L2ACDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC27L2AIDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC27L2BCDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC27L2BIDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC27L2CDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC27L2CPSR
SO
PS
8
2000
367.0
367.0
38.0
TLC27L2IDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC27L2MDR
SOIC
D
8
2500
367.0
367.0
35.0
TLC27L2MDRG4
SOIC
D
8
2500
367.0
367.0
35.0
TLC27L7CDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC27L7CPSR
SO
PS
8
2000
367.0
367.0
38.0
TLC27L7IDR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
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