TLC555-Q1 LinCMOS™ TIMER www.ti.com SLFS078 – OCTOBER 2006 FEATURES • • • • • • Qualified for Automotive Applications Very Low Power Consumption – 1 mW Typ at VDD = 5 V Capable of Operation in Astable Mode CMOS Output Capable of Swinging Rail to Rail High Output-Current Capability – Sink 100 mA Typ – Source 10 mA Typ Output Fully Compatible With CMOS, TTL, and MOS • • • Low Supply Current Reduces Spikes During Output Transitions Single-Supply Operation From 2 V to 15 V Functionally Interchangeable With the NE555; Has Same Pinout D PACKAGE (TOP VIEW) GND TRIG OUT RESET 1 8 2 7 3 6 4 5 VDD DISCH THRES CONT DESCRIPTION/ORDERING INFORMATION The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage. Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering. While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555. The TLC555 is characterized for operation over the full automotive temperature range of –40°C to 125°C. ORDERING INFORMATION (1) TA –40°C to 125°C (1) (2) PACKAGE (2) VDD 5 V to 15 V SOIC – D Reel of 2500 ORDERABLE PART NUMBER TLC555QDRQ1 TOP-SIDE MARKING TLC555Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TLC555-Q1 LinCMOS™ TIMER www.ti.com SLFS078 – OCTOBER 2006 FUNCTION TABLE (1) RESET VOLTAGE (1) TRIGGER VOLTAGE (1) THRESHOLD VOLTAGE (1) OUTPUT DISCHARGE SWITCH <MIN Irrelevant Irrelevant L On >MAX <MIN Irrelevant H Off >MAX >MAX >MAX L On >MAX >MAX <MIN As previously established For conditions shown as MIN or MAX, use the appropriate value specified under electrical characteristics. FUNCTIONAL BLOCK DIAGRAM CONT 5 RESET 4 VDD 8 R THRES R1 6 3 R OUT 1 S R TRIG 2 R 7 DISCH 1 GND A. 2 RESET can override TRIG, which can override THRES. Submit Documentation Feedback TLC555-Q1 LinCMOS™ TIMER www.ti.com SLFS078 – OCTOBER 2006 EQUIVALENT SCHEMATIC CONT TRIG THRES RESET 39 5 COMPONENT COUNT Transistors Resistors Submit Documentation Feedback V DD OUT DISCH GND 3 TLC555-Q1 LinCMOS™ TIMER www.ti.com SLFS078 – OCTOBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN VDD Supply voltage (2) VI Input voltage range Any input –0.3 Sink current, discharge or output IO Source current, output MAX UNIT 18 V VDD V 150 mA 15 mA See Dissipation Rating Table Continuous total power dissipation TA Operating free-air temperature range –40 125 °C Tstg Storage temperature range –65 150 °C 260 °C 1000 V Lead temperature 1,6 mm (1/16 ch) from case for 10 s HBM (Human Body Model) ESD (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network GND. Dissipation Ratings PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 125°C POWER RATING D 725 mW 5.8 mW/°C 145 mW Recommended Operating Conditions MIN 4 VDD Supply voltage TA Operating free-air temperature Submit Documentation Feedback MAX UNIT 2 15 V –40 125 °C TLC555-Q1 LinCMOS™ TIMER www.ti.com SLFS078 – OCTOBER 2006 Electrical Characteristics VDD = 5 V, at specified free-air temperature (unless otherwise noted) TEST CONDITIONS PARAMETER VIT Threshold voltage IIT Threshold current VI(TRIG) Trigger voltage II(TRIG) Trigger current VI(RESET) Reset voltage II(RESET) TA (1) MIN TYP MAX 25°C 2.8 3.3 3.8 Full range 2.7 IOL = 10 mA High-level output voltage IOH = –1 mA IOL = 8 mA VOL Low-level output voltage IOL = 5 mA IOL = 3.2 mA IDD (1) (2) Supply current (2) 5000 1.36 1.26 1.66 10 MAX 5000 25°C 0.4 0.3 1.1 10 MAX 5000 MAX 66.7 25°C 0.14 Full range 0.1 MAX 120 25°C 4.1 Full range 4.1 Full range 25°C pA % 0.5 V nA V 0.4 0.3 0.45 0.08 0.3 170 350 Full range 25°C V 0.6 0.13 Full range 25°C 1.5 4.8 0.21 V pA 0.6 25°C 25°C 1.96 1.8 25°C V pA 2.06 25°C Full range Discharge switch off-state current VOH 10 MAX 25°C Control voltage (open circuit) as a percentage of supply voltage Discharge switch on-state voltage 25°C Full range Reset current 3.9 UNIT V 0.4 Full range 700 µA Full range TA is –40°C to 125°C. These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. Submit Documentation Feedback 5 TLC555-Q1 LinCMOS™ TIMER www.ti.com SLFS078 – OCTOBER 2006 Electrical Characteristics VDD = 15 V, at specified free-air temperature (unless otherwise noted) TEST CONDITIONS PARAMETER VIT Threshold voltage IIT Threshold current VI(TRIG) Trigger voltage II(TRIG) Trigger current VI(RESET) Reset voltage II(RESET) TA (1) MIN TYP MAX 25°C 9.45 10 10.55 Full range 9.35 IOL = 100 mA VOH High-level output voltage IOH = –5 mA IOH = –1 mA IOL = 100 mA VOL Low-level output voltage IOL = 50 mA IOL = 10 mA IDD (1) (2) 6 Supply current (2) 5000 4.65 4.55 5 10 MAX 5000 25°C 0.4 0.3 1.1 10 MAX 5000 MAX 66.7 25°C 0.77 Full range 0.1 MAX 120 25°C 12.5 Full range 12.5 25°C 13.5 Full range 13.5 25°C 14.2 Full range 14.2 1.28 1.7 V nA V 3.2 3.8 0.63 1 1.5 0.12 V 0.3 0.45 360 Full range Full range TA is –40°C to 125°C. These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. Submit Documentation Feedback % 14.9 Full range 25°C V pA 14.6 Full range 25°C 1.5 14.2 Full range 25°C V pA 1.8 25°C 25°C 5.35 1.8 25°C V pA 5.45 25°C Full range Discharge switch off-state current IOH = –10 mA 10 MAX 25°C Control voltage (open circuit) as a percentage of supply voltage Discharge switch on-state voltage 25°C Full range Reset current 10.65 UNIT 600 1000 µA TLC555-Q1 LinCMOS™ TIMER www.ti.com SLFS078 – OCTOBER 2006 Operating Characteristics VDD = 5 V, TA = 25°C (unless otherwise noted) PARAMETER TYP MAX Initial error of timing interval (1) VDD = 5 V to 15 V, CT = 0.1 µF, RA = RB = 1 kΩ to 100 kΩ (2) 1 3 Supply voltage sensitivity of timing interval VDD = 5 V to 15 V, CT = 0.1 µF, RA = RB = 1 kΩ to 100 kΩ (2) 0.1 0.5 %/V tr Output pulse rise time RL = 10 MΩ, CL = 10 pF 20 75 ns tf Output pulse fall time RL = 10 MΩ, CL = 10 pF 15 60 ns Maximum frequency in astable mode RA = 470 Ω, CT = 200 pF, RB = 200 Ω (2) fmax (1) (2) TEST CONDITIONS MIN 1.2 2.1 UNIT % MHz Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. RA, RB, and CT are as defined in Figure 1. Electrical Characteristics VDD = 5 V, TA = 25°C (unless otherwise noted) TEST CONDITIONS PARAMETER VIT Threshold voltage IIT Threshold current VI(TRIG) Trigger voltage II(TRIG) Trigger current TYP MAX 2.8 3.3 3.8 1.36 1.66 10 0.4 Reset current 0.14 Discharge switch off-state current VOH VOL IDD (1) High-level output voltage Low-level output voltage 1.5 4.1 V nA 4.8 V IOL = 8 mA 0.21 0.4 IOL = 5 mA 0.13 0.3 IOL = 3.2 mA 0.08 0.3 170 350 Supply current (1) V % 0.5 0.1 IOH = –1 mA V pA 66.7 IOL = 10 mA V pA 10 Control voltage (open circuit) as a percentage of supply voltage Discharge switch on-state voltage 1.1 UNIT pA 1.96 10 VI(RESET) Reset voltage II(RESET) MIN V µA These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG. Submit Documentation Feedback 7 TLC555-Q1 LinCMOS™ TIMER www.ti.com SLFS078 – OCTOBER 2006 TYPICAL CHARACTERISTICS DISCHARGE SWITCH ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE 100 Discharge Switch On-State Resistance − Ω 70 VDD = 2 V, IO = 1 mA 40 VDD = 5 V, IO = 10 mA 20 VDD = 15 V, IO = 100 mA 10 7 4 2 1 −75 − 50 − 25 0 25 50 75 100 125 TA − Free-Air Temperature − °C Figure 1. PROPAGATION DELAY TIMES TO DISCHARGE OUTPUT FROM TRIGGER AND THRESHOLD SHORTED TOGETHER vs SUPPLY VOLTAGE t PHL , t PLH − Propagation Delay Times − ns 600 IO(on) ≥ 1 mA CL ≈ 0 TA = 25°C 500 400 300 tPHL 200 100 tPLH (see Note A) 0 0 2 4 6 8 10 12 14 16 VDD − Supply Voltage − V A. 8 The effects of the load resistance on these values must be taken into account separately. Figure 2. Submit Documentation Feedback 18 20 TLC555-Q1 LinCMOS™ TIMER www.ti.com SLFS078 – OCTOBER 2006 APPLICATION INFORMATION 0.1 µF RA VDD 0.1 µF 4 7 5 CONT RESET 8 tPHL VDD RL 3 CT Output OUT THRES 2 2/3 VDD TLC555 DISCH 6 RB tc(L) tc(H) CL 1/3 VDD TRIG GND 1 CIRCUIT GND tPLH TRIGGER AND THRESHOLD VOLTAGE WAVEFORM Figure 3. Astable Operation Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor CT charges through RA and RB to the threshold voltage level (approximately 0.67 VDD) and then discharges through RB only to the value of the trigger voltage level (approximately 0.33 VDD). The output is high during the charging cycle (tc(H)) and low during the discharge cycle (tc(L)). The duty cycle is controlled by the values of RA, RB, and CT as shown in the following equations. t [ C (R ) R ) In 2 (In 2 + 0.693) c(H) T A B t [ C R In 2 c(L) T B Period + t ) t [ C (R ) 2R ) In 2 c(H) c(L) T A B t R c(L) B [ 1– Output driver duty cycle + t ) t R ) 2R c(H) c(L) A B t R c(H) B Output waveform duty cycle + [ t ) t R ) 2R c(H) c(L) A B The 0.1-µF capacitor at CONT in Figure 3 decreases the period by about 10%. The formulas shown above do not allow for any propagation delay times from the TRIG and THRES inputs to DISCH. These delay times add directly to the period and create differences between calculated and actual values that increase with frequency. In addition, the internal on-state resistance (ron) during discharge adds to RB to provide another source of timing error in the calculation when RB is very low or ron is very high. Submit Documentation Feedback 9 TLC555-Q1 LinCMOS™ TIMER www.ti.com SLFS078 – OCTOBER 2006 APPLICATION INFORMATION (continued) The following equations provide better agreement with measured values. t + C (R ) R ) In c(H) T A B t + C (R ) r on) In c(L) T B ƪ ǒ ƪ ǒ 3 –exp 3 –exp –t PLH C (R ) r on) T B –t PHL C (R ) R ) T A B Ǔƫ ) t Ǔƫ ) t PHL PLH These equations and those given previously are similar in that a time constant is multiplied by the logarithm of a number or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and In 3 at extremely high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic terms t t c(H) c(H) t )t t c(L) require that c(L) < 1 and can be substituted with good results. Duty cycles less than 50% c(H) possibly RA ≤ ron. These conditions can be difficult to obtain. In monostable applications, the trip point on TRIG can be set by a voltage applied to CONT. An input voltage between 10% and 80% of the supply voltage from a resistor divider with at least 500-µA bias provides good results. 10 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 16-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TLC555QDRQ1 ACTIVE SOIC D Pins Package Eco Plan (2) Qty 8 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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