Preliminary Datasheet TLE 6217 Smart Quad Channel Low-Side Switch Features Product Summary • • • • • • Shorted Circuit Protection Overtemperature Protection Overvoltage Protection Parallel Control of the Inputs (PWM Applications) Separate Diagnostic Pin for Each Channel Power - SO 20 - Package with integrated cooling area • Standby mode with low current consumption • µC compatible Input • Electrostatic Discharge (ESD) Protection Supply voltage Drain source voltage On resistance Output current VS VDS(AZ)max RON 1,2 RON 3,4 ID 1,2 ID 3,4 4.8 - 32 60 0.2 0.35 2x5 2x3 V V Ω Ω A A Application • • • • All kinds of resistive and inductive loads (relays, electromagnetic valves) µC compatible power switch for 12 and 24 V applications Solenoid control switch in automotive and industrial control systems Robotic Controls P-DSO-20-12 General description Quad channel Low-Side-Switch (2x5A/2x3A) in Smart Power Technology (SPT) with four separate inputs and four open drain DMOS output stages. The TLE 6217 GP is fully protected by embedded protection functions and designed for automotive and industrial applications. Each channel has its own status signal for diagnostic feedback. Therefore the TLE 6217 GP is particularly suitable for ABS or Powertrain Systems. Block Diagram STBY ENA VS GND normal function IN1 VBB SCB / overload IN2 as Ch. 1 IN3 as Ch. 1 IN4 as Ch. 1 overtemperature LOGIC open load/sh. to gnd Output Stage ST1 1 OUT1 4 4 ST2 ST3 as ST 1 ST4 as ST 1 Gate Control OUT4 as ST 1 GND V5 Page 1 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 V5 Page 2 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Pin Configuration (Top view) P - DSO - 20 - 12 Pin Description Pin Symbol Function 1 GND Ground 2 OUT1 Power Output channel 1 3 ST1 Status Output channel 1 4 IN4 Control Input channel 4 5 VS Supply Voltage 6 STBY Standby 7 IN3 Control Input channel 3 8 ST2 Status Output channel 2 9 OUT2 Power Output channel 2 10 GND Ground 11 GND Ground 12 OUT3 Power Output channel 3 13 ST3 Status Output channel 3 14 IN2 Control Input channel 2 15 GND Ground Logic 16 ENA Enable Input for all four channels 17 IN1 Control Input channel 1 18 ST4 Status Output channel 4 19 OUT4 Power Output channel 4 20 GND Ground Heat slug internally connected to ground pins V5 Page 3 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Detailed Block Diagram VS STBY ENA internal supply Overtemperature Channel 4 Overtemperature Channel 1 Open Load IN1 LOGIC Overload OUT1 ST1 Open Load IN4 LOGIC IPD Overload OUT4 ST4 Overtemperature Channel 3 Overtemperature Channel 2 IPD Open Load IN2 LOGIC Overload OUT2 ST2 Open Load IN3 LOGIC IPD Overload OUT3 ST3 IPD GND V5 Page 4 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Maximum Ratings for T j = – 40°C to 150°C The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Parameter Supply voltage Symbol VS Continuous drain source voltage (OUT1...OUT4) VDS Input voltage IN1 to IN4, ENA VIN , VENA - Input voltage STBY VSTBY - 0.3 ... + 40 Status output voltage VST - 0.3 ... + 32 V Operating temperature range Σt = 30 min Σt = 15 min Storage temperature range Tj Tj Tj Tstg 40 ... + 150 175 190 - 55 ... + 150 °C Output current per channel ID(lim) Output current at reversal supply ID 1,2 ID 3,4 Status output current IST Inductive load switch off energy (single pulse) Tj = 25°C Electrostatic Discharge Voltage (HBM) according to MIL STD 883D, method 3015.7 and EOS/ESD assn. Standard S5.1 – 1993 Output 1-4 Pins All other Pins Thermal resistance junction – case (die soldered on the frame) Values -0.3 ... + 40 Unit V 40 V 1.5... + 6 V - overload shutdown EAS A -4 -2 A - 5 ... + 5 mA 50 mJ 4000 2000 VESD VESD K/W RthJC Maximum operating lifetime (according to "Ambient thermal conditions") tb 2 10000 Ambient thermal conditions V5 V V TAmbient temperature range operating periods -40 °C 2% -20 °C 10 % 25 °C 24 % 60 °C 34 % 80 °C 24 % 100 °C 5% > 120 °C 1% Page 5 of 20 30. 07. 2002 h Preliminary Datasheet TLE 6217 Electrical Characteristics Parameter and Conditions VS = 4.8 to 18 V ; Tj = - 40 °C to + 150 °C (unless otherwise specified) Symbol Values min Unit typ max 1. Power Supply (VS) Supply current (Outputs ON) IS 8 mA Supply current (Outputs OFF) VENA = L, VSTBY = H IS 4 mA IS 10 Standby current VSTBY = L Operating voltage VS 4.8 32 µA V 2. Power Outputs ON state resistance Channel 1,2 ID = 1A; VS ≥ 9.5 V Tj = 25 ° C Tj = 150°C RDS(ON) ON state resistance Channel 3,4 ID = 1A; VS ≥ 9.5 V Tj = 25 ° C Tj = 150°C RDS(ON) ID ≥ 100 mA VDS(AZ) 45 IPD IDlk 10 Z-Diode clamping voltage (OUT1...4) Pull down current Output Leakage Current VSTBY = H, VIN = L VSTBY = L Tj = -40°C...150°C wafer test at 25°C Output turn on delay time 1 Output turn off delay time 1 Output on fall time 1 Output off rise time 1 Overload switch-off delay time 1 Output off status delay time 2 Failure extension Time for Status Report Input Suppression Time Open Load (off) filtering Time 2 ID = 1 A ID = 1 A ID = 1 A ID = 1 A Ω 0.2 0.5 Ω 0.35 0.75 20 60 V 50 µA 5 1 ton toff tfall trise tDSO tD tD-failure tD-IN tfOL(off) 0 0 3 3 20 500 500 500 10 5 10 10 10 1200 1200 1200 30 20 30 30 30 100 3000 3000 3000 100 µA µA µs 3. Digital Inputs (IN1, IN2, IN3, IN4, ENA) Input low voltage Input high voltage Input voltage hysteresis 2 Input pull down current Enable pull down current VIN = 5 V; VS ≥ 6.5 V VENA = 5 V; VS ≥ 6.5 V VINL - 0.3 1.0 V VINH 2.0 6.0 V VINHys 50 100 IIN 10 30 60 µA IENA 10 20 40 µA VSTL 0.5 V ISTH 2 µA mV 4. Digital Status Outputs (ST1 - ST4) Open Drain Output voltage low IST = 2 mA Leakage current high 1 2 See timing diagram, resistive load condition; VS ≥ 9 V This parameter will not be tested but assured by design V5 Page 6 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Electrical Characteristics Parameter and Conditions VS = 4.8 to 18 V ; Tj = – 40 °C to + 150 °C (unless otherwise specified) Symbol Values min Unit typ max 5. Standby Input (STBY) Input low voltage VSTBY 0 1 V Input high voltage VSTBY 3.5 VS V 300 µA 0.3* VS 0.33* VS 0.36* VS V Input current VSTBY = 18 V ISTBY 6. Diagnostic Functions Open load detection voltage VENA = X, VIN = L VS ≥ 6.5 V VDS(OL) Open load detection current channel 1,2 VENA = VIN = H VS ≥ 6.5 V ID(OL) 1,2 100 240 mA Open load detection current channel 3,4 VENA = VIN = H VS ≥ 6.5 V ID(OL) 3,4 100 240 mA Overload Current channel 1, 2 VS ≥ 6.5 V ID(lim) 1,2 5 7.5 A VS ≥ 6.5 V ID(lim) 3,4 3 5 A Tth Thys 170 Overload Current channel 3 , 4 Overtemperature shutdown threshold Hysteresis 2 Pulse Width for static diagnostic output 2 tIN 200 °C K 500 µs 10 This parameter will not be tested but assured by design V5 Page 7 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Application Description This IC is especially designed to drive inductive loads (relays, electromagnetic valves). Integrated clamp-diodes limit the output voltage when inductive loads are discharged. Four open-drain logic outputs indicate the status of the integrated circuit. The following conditions are monitored and signalled: - Overloading of output (also shorted load to supply) in active mode - Open and shorted load to ground in active and inactive mode - Overtemperature Circuit Description Input Circuits The control and enable inputs, both active high, consist of schmitt triggers with hysteresis. All inputs are provided with pull-down current sources. Not connected inputs are interpreted as low and the respective output stages are switched off. In standby mode (STBY = LOW) the current consumption is greatly reduced. The circuit is active when STBY = HIGH. If the standby function is not used, it is allowed to connect the standby pin directly to VS. Status Signals: The status signals are undefined for 2ms after a power up event or a STBY low to high transition. Output Stages The four power outputs consist of DMOS-power transistors with open drains. The output stages are short circuit protected throughout the operating range. Each output has it's own zenerclamp. This causes a voltage limitation at the power transistor when inductive loads are switched off. Parallel to the DMOS transistors there are internal pull down current sources. They are provided to detect an open load condition in the off state. They will be disconnected in the standby mode. Due to EMI measures there is an internal zenerclamp in parallel to the output stage. It gets active above 33V drain source voltage. This leads to an increasing leakage current up to 1 mA @ VDS = 40V. Protective Circuits The outputs are protected against current overload and overtemperature. If the output current increases above the overload detection threshold IQO for a longer time then tDSO or the temperature increases above Tth, then the power transistor is immediately switched off. It remains off until the control signal at the input is switched off and on again. Fault Detection The status outputs indicate the switching state of the output stage. Under normal conditions is: ST = low ⇒ Output off; ST = high ⇒ Output on. If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table. If current overload or overtemperature occurs for a longer time than tDSO, the fault condition is latched into an internal register and the output is shutdown. The reset is done by switching off the corresponding control input for a time longer than tD-IN. V5 Page 8 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Open load is detected for all four channels in on and off mode. In the on mode the load current is monitored. If it drops below the specified threshold value IQU then an open load condition is detected. In the off mode, the output voltage is monitored. An open load condition is detected when the output voltage of a given channel is below the threshold VDS(OL), which is typ. 33 % of the supply voltage VS. To prevent an open load diagnosis in case of transient Voltages on the outputs the open load detection in off mode uses a filter of typ. 30µs. Status output at pulse width operation If the input is operated with a pulsed signal, the status does not follow each single pulse of the input signal. An internal delay tD of typ. 1.2ms (min 500 µs) enables a continuous status output signal. See the timing diagrams on the following pages for further information. This internal status delay simplifies diagnostic software for pwm applications. Diagnostic Table In general the status follows the input signal in normal operating conditions. If any error is detected the status is inverted. Standby Input Enable Input Control Input Power Output Status Output STBY ENA IN Q ST Standby L X X off H Normal function H H H L H H X L H off off ON L L H Open load or short to ground H H H H L L H H L H L H off off off ON H H H L Overload or short to supply1) H H H off L 2) H H H→L off L H L X off L Overtemperature1) H H H off L reset latch 2) H H H→L off L H L X off L Operating Condition reset latch Note 1) : overload/short-to-supply/overtemperature - events shorter than min. time t DSO specified in 2.10 will not be latched and not reported at the status pin. V5 Page 9 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Note 2): to reset latched status-output in case of overload/short-to-supply/overtemperature the control input has to go low and stay low for longer than max. Input suppression time tD-IN specified in 2.13 of the characteristics Failure Situations and Status Report Logic Block Diagram Overtemperature 1.....overtemperature 0.....normal cond. Gate Driver 1... Output 0....Output On Off ENA 1....enabled 0... disabled Input 1....On 0... Off IN tDSO Delay D Delay 60µs S R SET CLR Q OUT 1,2ms typ. IN tD OUT 60µs typ. Q Delay 60µs tD t D-IN when overload occured EN Overload 0.....overload 1.....normal cond. Delay D OUT IN tfOL(off) HI Open load "off" 1.....open load 0.....normal cond. tD Filter 30µs Filter Status 0....High 1....Low EN IN Delay D OUT Delay D OUT t D-failure EN Open load "on" 0.....open load 1.... normal cond. IN tD-failure V5 Page 10 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Timing Diagrams Output Slope VIN VI NH V INL t VDS VS 85% t off ton 15% t tf tr V ST tD t Fig. 1 Overload Switch OFF Delay ID t ID(lim) DSO ID(OL) t VST t D-failure t Fig. 2 V5 Page 11 of 20 30. 07. 2002 V5 ST2 Page 12 of 20 IN1 IENA IIN4 IIN3 IIN2 IIN1 IST4 IST3 IST2 IST1 STBY ENA IN4 IN3 IN2 IN1 ST4 ST3 ST2 ST1 IVS GND TLE 6227 VS VS TLE 6217 GP VSTBY VENA ISTBY ENA VIN4 IN4 10k VIN3 IN3 VIN2 IN2 10k VST3 VST4 VIN1 ST4 10k ST3 VST1 VST2 ST1 10k VD = 5V OUT4 OUT3 OUT2 OUT1 ID4 ID3 ID2 ID1 R L4 OUT3 R L2 OUT2 RL1 OUT1 VDS(OUT4) VDS(OUT3) VDS(OUT2) VDS(OUT1) OUT4 R L3 Preliminary Datasheet TLE 6217 Test Circuit 30. 07. 2002 Preliminary Datasheet TLE 6217 +12V Application Circuit L4 L3 L2 ENA GND 6217 OUT3 OUT4 Enable Input Control Inputs Status Output 10k 10k 10k 10k VD = 5V C VS IN1 IN2 IN3 IN4 STBY ST1 OUT1 ST2 ST3 ST4 TLE OUT2 L1 The blocking capacitor C is recommended to avoid critical negative voltage spikes on VS in case of battery interruption during OFF-commutation. V5 Page 13 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Timing Diagrams of Diagnostic with Pulsed Input Signal Normal condition, resistive load, pulsed input signal V IN t IN ID V ST tD tD Fig. 3 Current Overload F current overload condition tINoff V IN I D(lim) ID V ST tD-IN t DSO t DSO tINoff < tD-IN : Input suppression time avoids a restart after overtemperature Fig. 4 V5 Page 14 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Diagnostic status output at different open load current conditions V IN I D(OL) ID t D-failure V ST tD Fig. 5 V IN tINoff I D(OL) ID tD-failure V ST tD tINOFF < tD leads to a static status signal Fig. 6 V IN tINoff I D(OL) ID V ST tD-failure tD tD-failure tINoff > tD : Intermittend status signal V5 tD-failure Fig. 7 Page 15 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Normal operation, followed by open load condition ~ 55V Open load voltage condition VDS 12V 33% VIN I D(OL) ID tfOL(off)- tD-failure VST tD-failure tD Fig. 8 Overtemperature Overtemperature VIN tINoff > tD-IN Reset of overload Flip Flop I D(OL) ID VST tD-failure tD-failure t DSO Fig. 9 V5 Page 16 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Ordering code Type Ordering Code Package TLE6217 G TLE6217 C on request on request P - DSO - 20 – 12 Bare dice on wafer Pad Assignment Out GT ST IN VR1 EN GN I IN T P _ Out GT ST y P G N P G N x center of P G N ST GT IN I V STB P G N IN Out V5 V ST GT Out Page 17 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Package dimensions All dimensions in mm 15.74 +/- 0. 1 13.7 -0.2 9 x 1.27 = 11.43 0.4 +0.13 1.27 1 5.9 +/-0.1 11 3.2 +/-0.1 20 0.25 M A 10 1 x 45° PIN 1 INDEX MARKING A 15.9 +/ -0.15 1.2 -0.3 1.3 0.1 8° 2.8 8° 8° 8° 6.3 1) 11 +/-0.15 14.2 +/ -0.3 V5 Page 18 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Revision List: 01.09.2001 01.10.2001 01.12.2001 30.04.2002 30.07.2002 V5 Target Datasheet First revision Second revision Third revision Preliminary Datasheet V1 V2 V3 V4 V5 Page 19 of 20 30. 07. 2002 Preliminary Datasheet TLE 6217 Published by Infineon Technologies AG, Bereichs Kommunikation St.-Martin-Strasse 76, D-81541 München © Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that lifesupport device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. V5 Page 20 of 20 30. 07. 2002