TI TLV2553-Q1

TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
12-BIT 200-KSPS 11-CHANNEL LOW-POWER SERIAL ADC
FEATURES
APPLICATIONS
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
12-Bit-Resolution Analog-to-Digital Converter
(ADC)
Up to 200-KSPS (150-KSPS for 3 V)
Throughput Over Operating Temperature
Range With 12-Bit Output Mode
11 Analog Input Channels
Three Built-In Self-Test Modes
Inherent Sample and Hold Function
Linearity Error of +1 LSB (Max)
On-Chip Conversion Clock
Unipolar or Bipolar Output Operation
Programmable Most Significant Bit (MSB) or
Least Significant Bit (LSB) First
Programmable Power Down
Programmable Output Data Length
SPI Compatible Serial Interface With I/O Clock
Frequencies up to 15 MHz (CPOL=0, CPHA=0)
Process Control
Portable Data Logging
Battery-Powered Instruments
Automotive
DW PACKAGE
(TOP VIEW)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
VCC
EOC
18 I/O CLOCK
17 DATA IN
16 DATA OUT
15 CS
14 REF+
13 REF–
12 AIN10
11 AIN9
1
20
2
19
3
4
5
6
7
8
9
10
DESCRIPTION\ORDERING INFORMATION
The TLV2553 is a 12-bit switched-capacitor successive-approximation analog-to-digital converter (ADC). The
ADC has three control inputs [chip select (CS), the input-output clock, and the address/control input (DATAIN)]
designed for communication with the serial port of a host processor or peripheral through a serial 3-state output.
In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel
multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages using configuration
register 1. The sample-and-hold function is automatic. At the end of conversion, when programmed as EOC, the
pin 19 output goes high to indicate that conversion is complete. The converter incorporated in the device features
differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog
circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full
operating temperature range.
The TLV2553I is characterized for operation from TA = –40°C to 85°C.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 85°C
(1)
(2)
SOP – DW
Reel of 2000
ORDERABLE PART NUMBER
TLV2553IDWRQ1
TOP-SIDE MARKING
TLV2553IQ1
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAM
VCC
20
REF +
14
REF −
13
3
AIN0 1
AIN1 2
AIN2 3
AIN3 4
AIN4 5
AIN5 6
AIN6 7
AIN7 8
AIN8 9
AIN9 11
AIN10 12
DATA IN
CS
I/O CLOCK
Self Test
14-Channel
Analog
Multiplexer
Low Power
12-Bit
SAR ADC
Sample
and Hold
4
Input Address
Register
18
19
Control Logic
and I/O
Counters
EOC
12
12
Output Data
Register
12-to-1
Data
Selector
and Driver
17
15
Reference CTRL
16 DATA
OUT
4
Internal OSC
10
GND
2
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
TERMINAL FUNCTIONS
TERMINAL
NAME
AIN0–AIN10
CS
DATA IN
NO.
I/O
DESCRIPTION
1–9, 11, 12
I
Analog input. These 11 analog-signal inputs are internally multiplexed.
15
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and
enables DATA OUT, DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and
I/O CLOCK within a setup time.
I
Serial data input. The 4-bit serial data can be used as address selects the desired analog input
channel or test voltage to be converted next, or a command to activate other other features.
The input data is presented with the MSB (D7) first and is shifted in on the first four rising
edges of the I/O CLOCK. After the four address/command bits are read into the command
register CMR, I/O CLOCK clocks the remaining four bits of configuration in.
17
DATA OUT
16
O
3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state
when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the
high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of
the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the
logic level corresponding to the next MSB/LSB, and the remaining bits are shifted out in order.
EOC
19
O
End-of-convertions status. Used to indicate the end of conversion (EOC) to the host processor.
EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and
remains low until the conversion is complete and the data is ready for transfer.
GND
10
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all
voltage measurements are with respect to GND.
I/O CLOCK
18
I
Input /output clock. I/O CLOCK receives the serial input and performs the following four
functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges
of I/O CLOCK with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected
multiplexer input begins charging the capacitor array and continues to do so until the last
falling edge of I/O CLOCK.
3. The remaining 11 bits of the previous conversion data are shifted out on DATA OUT.
Data changes on the falling edge of I/O CLOCK.
4. Control of the conversion is transferred to the internal state controller on the falling edge
of the last I/O CLOCK.
REF+
14
I/O
Positive reference voltage The upper reference voltage value (nominally VCC) is applied to
REF+. The maximum analog input voltage range is determined by the difference between the
voltage applied to terminals REF+ and REF–.
REF–
13
I/O
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to
REF–. This pin is connected to analog ground (GND of the ADC) when internal reference is
used.
VCC
20
Positive supply voltage
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
3
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
VCC
Supply voltage range (2)
VI
Input voltage range (any input)
–0.3 V to VCC + 0.3
VO
Output voltage range
–0.3 V to VCC + 0.3
Vref+
Positive reference voltage range
–0.3 V to VCC + 0.3
Vref–
Negative reference voltage range
–0.3 V to VCC + 0.3
II
Peak input current (any input)
–0.5 V to 6.5 V
±20 mA
Peak total input current (all inputs)
±30 mA
TJ
Operating virtual junction temperature range
–40°C to 150°C
TA
Operating free-air temperature range
–40°C to 85°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
(1)
(2)
260°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted).
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage
I/O CLOCK frequency
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
Aperature jitter
VCC = 4.5 V to 5.5 V
Analog input voltage (1)
VIH
High-level control input voltage
VIL
Low-level control input voltage
TA
Operating free-air temperature
(1)
4
MAX
5.5
16-bit I/O
0.01
15
12-bit I/O
0.01
15
18-bit I/O
0.01
15
VCC = 2.7 to 3.6 V
Tolerable clock jitter, I/O CLOCK
NOM
2.7
0.01
100
0
VCC = 3 V to 3.6 V
0
VCC = 2.7 V to 3 V
0
VCC = 4.5 V to 5.5 V
2
VCC = 2.7 V to 3.6 V
2.1
MHz
ns
ps
REF+ – REF–
V
V
VCC = 4.5 V to 5.5 V
0.8
VCC = 2.7 V to 3.6 V
0.6
–40
V
10
0.38
VCC = 4.5 V to 5.5 V
UNIT
85
V
°C
Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, when VCC = 5 V: VREF+ = 5 V, I/O CLOCK frequency = 15 MHz,
when VCC = 2.7 V: VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VCC = 4.5 V, IOH = –1.6 mA
VCC = 2.7 V, IOH = –0.2 mA
High-level output voltage
VOL
VCC = 4.5 V, IOH = –20 µA
VCC = 2.7 V, IOH = –20 µA
VCC = 4.5 V, IOL = –1.6 mA
VCC = 2.7 V, IOL = –0.8 mA
Low-level output voltage
VCC = 4.5 V, IOL = –20 µA
VCC = 2.7 V, IOL = –20 µA
MIN
0.4
30 pF
1
2.5
VO = 0 V, CS = VCC
–1
–2.5
CS = 0 V,
External reference
ICC(PD)
Power-down current
For all digital inputs, Software power down
0 ≤ VI ≤ 0.5 V or
VI ≥ VCC – 0.5 V,
Auto power down
I/O CLOCK = 0 V
IIH
High-level input current
IIL
Low-level input current
tconvert
Conversion time
(13.5 × (1/fOSC) + 25 ns)
VCC = 5 V
1.2
VCC = 2.7 V
0.9
Input impedance (2)
Ci
Input capacitance
(1)
(2)
Analog inputs
µA
mA
0.1
1
0.1
10
VI = VCC
0.005
2.5
µA
VI = 0 V
–0.005
–2.5
µA
Selected channel at VCC ,
Unselected channel at 0 V
1
Selected channel at 0 V,
Unselected channel at VCC
–1
µA
µA
VCC = 4.5 V to 5.5 V
3.27
VCC = 2.7 V to 3.6 V
2.56
MHz
VCC = 4.5 V to 5.5 V
4.15
VCC = 2.7 V to 3.6 V
5.54
Internal oscillator frequency voltage
Zi
V
0.1
VO = VCC, CS = VCC
Operating supply current
Internal oscillator frequency
V
VCC – 0.1
ICC
fOSC
UNIT
2.4
High-impedance off-state output current
Selected channel leakage current
MAX
30 pF
IOZ
Ilkg
TYP (1)
3.6
4.1
VCC = 4.5 V
500
VCC = 2.7 V
600
Analog inputs
45
55
Control inputs
5
15
µs
V
Ω
pF
All typical values are at VCC = 5 V, TA = 25°C.
The switch resistance is very nonlinear and varies with input voltage and supply voltage. This is the worst case.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
5
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
EXTERNAL REFERENCE SPECIFICATIONS (1)
PARAMETER
–0.1
0
0.1
VCC = 2.7 V to 3.6 V
–0.1
0
0.1
VCC = 4.5 V to 5.5 V
2
VCC
VCC = 2.7 V to 3.6 V
2
VCC
External reference input voltage difference VCC = 4.5 V to 5.5 V
(REF+ – REF–)
VCC = 2.7 V to 3.6 V
1.9
VCC
1.9
VCC
Reference input voltage, REF–
VREF+
Reference input voltage, REF+
External reference supply current
CS = 0 V
VCC = 5 V
ZREF
Reference input impedance
VCC = 2.7 V
(1)
(2)
MAX
VCC = 4.5 V to 5.5 V
VREF–
IREF
MIN TYP (2)
TEST CONDITIONS
VCC = 4.5 V to 5.5 V
0.94
VCC = 2.7 V to 3.6 V
0.62
Static
1
During sampling/conversion
6
Static
1
During sampling/conversion
6
UNIT
V
V
V
mA
MΩ
9
kΩ
MΩ
9
kΩ
Add a 0.1-µF capacitor between REF+ and REF– pins when external reference is used.
All typical values are at VCC = 5 V, TA = 25°C.
OPERATING CHARACTERISTICS
over recommended operating free-air temperature range, when VCC = 5 V: VREF+ = 5 V, I/O CLOCK frequency = 15 MHz,
when VCC = 2.7 V: VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(2)
MIN TYP (1)
MAX
UNIT
–1
1
LSB
–1
1
LSB
INL
Integral linearity error
DNL
Differential linearity error
EO
Offset error (3)
See
(4)
–2
2
mV
EG
Gain error (3)
See
(4)
–3
3
mV
ET
Total unadjusted error
(5)
Self-test output code (6) (see Table 2)
(1)
(2)
(3)
(4)
(5)
(6)
6
±1.5
Address data input = 1011
2048
Address data input = 1100
0
Address data input = 1101
4095
LSB
All typical values are at VCC = 5 V, TA = 25°C.
Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain
point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal
midstep value at the offset point.
Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
Total unadjusted error comprises linearity, zero-scale errors, and full-scale errors.
Both the input address and the output codes are expressed in positive logic.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
TIMING CHARACTERISTICS
over recommended operating free-air temperature range,
VREF+ = 5 V, I/O CLOCK frequency = 15 MHz, VCC = 5 V, Load = 25 pF (unless otherwise noted)
PARAMETER
tw1
Pulse duration I/O CLOCK high or low
tsu1
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 26)
th1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 26)
(1)
tsu2
Setup time CS low before first rising I/O CLOCK edge
th2
Hold time CS pulse duration high time (see Figure 27)
th3
(see Figure 27)
MIN
MAX
26.7
100000
UNIT
ns
12
ns
0
ns
25
ns
100
ns
Hold time CS low after last I/O CLOCK falling edge (see Figure 27)
0
ns
th4
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 28)
2
ns
th5
Hold time CS high after EOC rising edge when CS is toggled (see Figure 31)
0
ns
Load = 25 pF
28
Load = 10 pF
20
td1
Delay time CS falling edge to DATA OUT valid (MSB or LSB)
(see Figure 25)
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 25)
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 28)
td4
ns
10
ns
20
ns
Delay time last I/O CLOCK falling edge to EOC falling edge
55
ns
td5
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
1.5
µs
tt1
Transition time I/O CLOCK (1) (see Figure 28)
1
µs
tt2
Transition time DATA OUT (see Figure 28)
5
ns
tt3
Transition time EOC, CL = 7 pF (see Figure 30)
2.4
ns
tt4
Transition time DATA IN, CS
10
µs
tcycle
Total cycle time (sample, conversion and delays) (1)
(2)
µs
tsample
Channel acquisition time (sample) at 1 kΩ (1)
(see Figure 33 through Figure 38)
2
Source impedance = 25 Ω
600
Source impedance = 100 Ω
650
Source impedance = 500 Ω
700
Source impedance = 1 kΩ
(1)
(2)
ns
1000
I/O CLOCK period = 8 × [1/(I/O CLOCK frequency)] or 12 × [1/(I/O CLOCK frequency)] or 16 × [1/(I/O CLOCK frequency)], depending
on I/O format selected
tconvert(max) + I/O CLOCK period (8/12/16 CLKs)
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
7
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
TIMING CHARACTERISTICS
over recommended operating free-air temperature range,
VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz, VCC = 2.7 V, Load = 25 pF (unless otherwise noted)
MIN
MAX
tw1
Pulse duration I/O CLOCK high or low
PARAMETER
40
100000
tsu1
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 26)
22
ns
th1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 26)
0
ns
(1)
tsu2
Setup time CS low before first rising I/O CLOCK edge
th2
Hold time CS pulse duration high time (see Figure 27)
th3
(see Figure 27)
UNIT
ns
33
ns
100
ns
Hold time CS low after last I/O CLOCK falling edge (see Figure 27)
0
ns
th4
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 28)
2
ns
th5
Hold time CS high after EOC rising edge when CS is toggled (see Figure 31)
0
ns
Load = 25 pF
30
Load = 10 pF
22
td1
Delay time CS falling edge to DATA OUT valid (MSB or LSB)
(see Figure 25)
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 25)
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 28)
td4
ns
10
ns
33
ns
Delay time last I/O CLOCK falling edge to EOC falling edge
75
ns
td5
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
1.5
µs
tt1
Transition time I/O CLOCK (1) (see Figure 28)
1
µs
tt2
Transition time DATA OUT (see Figure 28)
5
ns
tt3
Transition time EOC, CL = 7 pF (see Figure 30)
4
ns
tt4
Transition time DATA IN, CS
10
µs
tcycle
Total cycle time (sample, conversion and delays) (1)
(2)
µs
tsample
Channel acquisition time (sample), at 1 kΩ (1)
(see Figure 33 through Figure 38)
2
Source impedance = 25 Ω
(1)
(2)
8
800
Source impedance = 100 Ω
850
Source impedance = 500 Ω
1000
Source impedance = 1 kΩ
1600
ns
I/O CLOCK period = 8 × [1/(I/O CLOCK frequency)] or 12 × [1/(I/O CLOCK frequency)] or 16 × [1/(I/O CLOCK frequency)], depending
on I/O format selected
tconvert(max) + I/O CLOCK period (8/12/16 CLKs)
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
ICC − Supply Current − mA
0.620
0.43
VCC = 3.3 V
VREF+ = 2.5 V
VREF− = 0 V
I/O CLOCK = 10 MHz
0.42
External Reference Current − mA
0.625
EXTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
0.615
0.610
0.605
0.600
0.595
0.590
0.585
0.580
−40
0.41
VCC = 3.3 V
VREF+ = 2.5 V
VREF− = 0 V
I/O CLOCK = 10 MHz
0.40
0.39
0.38
0.37
0.36
0.35
0.34
−25
−10
5
20
35
50
65
0.33
−40
80
−25
−10
5
Figure 1.
0.40
50
65
80
65
80
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
0.06
VCC = 3.3 V
VREF+ = 2.5 V
VREF− = 0 V
I/O CLOCK = 10 MHz
0.05
0.35
0.30
VCC = 3.3 V
VREF+ = 2.5 V
VREF− = 0 V
I/O CLOCK = 10 MHz
0.04
Current − µ A
Current − µ A
35
Figure 2.
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
0.45
20
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
0.25
0.20
0.15
0.03
0.02
0.10
0.01
0.05
0.00
−40
−25
−10
5
20
35
50
65
80
0.00
−40
TA − Free-Air Temperature − °C
Figure 3.
−25
−10
5
20
35
50
TA − Free-Air Temperature − °C
Figure 4.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
9
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.9
0.8
0.0
VCC = 2.7 V
VREF+ = 2.5 V
VREF− = 0 V
I/O CLOCK = 10 MHz
Minimum Differential Nonlinearity − LSB
Maximum Differential Nonlinearity − LSB
1.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−40
−25
−10
5
20
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
35
50
65
−0.1
VCC = 2.7 V
VREF+ = 2.5 V
VREF− = 0 V
I/O CLOCK = 10 MHz
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
−0.8
−40
80
−25
TA − Free-Air Temperature − °C
−10
5
Figure 5.
−0.1
Minimum Integral Nonlinearity − LSB
Maximum Integral Nonlinearity − LSB
65
80
0.0
VCC = 2.7 V
VREF+ = 2.5 V
VREF− = 0 V
I/O CLOCK = 10 MHz
0.6
0.5
0.4
0.3
0.2
0.1
−25
−10
5
20
35
50
65
80
VCC = 2.7 V
VREF+ = 2.5 V
VREF− = 0 V
I/O CLOCK = 10 MHz
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
−40
TA − Free-Air Temperature − °C
Figure 7.
10
50
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.8
0.0
−40
35
Figure 6.
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.7
20
TA − Free-Air Temperature − °C
−25
−10
5
20
35
50
65
80
TA − Free-Air Temperature − °C
Figure 8.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
TYPICAL CHARACTERISTICS (continued)
DNL − Differential Nonlinearity − LSB
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.5
0.4
VCC = 2.7 V, VREF+ = 2.5 V, VREF− = 0 V, I/O CLOCK = 10 MHz, TA = 25°C
0.3
0.2
0.1
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
1024
2048
3072
4096
Digital Output Code
Figure 9.
INL − Integral Nonlinearity − LSB
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.8
VCC = 2.7 V, VREF+ = 2.5 V, VREF− = 0 V, I/O CLOCK = 10 MHz, TA = 25°C
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
−0.8
0
1024
2048
3072
4096
Digital Output Code
Figure 10.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
11
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
GAIN ERROR
vs
FREE-AIR TEMPERATURE
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
0.6
1.4
1.2
EG − Gain Error − mV
EO − Offset Error − mV
0.5
0.4
0.3
0.2
1.0
0.8
0.6
0.4
0.1
0.0
−40
VCC = 3.3 V
VREF+ = 2.5 V
VREF− = 0 V
I/O CLOCK = 10 MHz
−25
−10
5
20
0.2
35
50
65
VCC = 3.3 V
VREF+ = 2.5 V
VREF− = 0 V
I/O CLOCK = 10 MHz
0.0
−40
80
−25
−10
Figure 11.
65
80
0.7
External Reference Current − mA
ICC − Supply Current − mA
50
0.8
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
0.94
0.92
0.90
0.88
0.86
0.6
0.5
0.4
0.3
0.2
0.1
−25
−10
5
20
35
50
65
80
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
0.0
−40
TA − Free-Air Temperature − °C
Figure 13.
12
35
EXTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
0.98
0.84
−40
20
Figure 12.
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.96
5
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
−25
−10
5
20
35
50
65
80
TA − Free-Air Temperature − °C
Figure 14.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
TYPICAL CHARACTERISTICS (continued)
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
0.14
0.45
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
0.40
0.35
0.12
Current − µ A
Current − µ A
0.10
0.30
0.25
0.20
0.08
0.06
0.15
0.04
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
0.10
0.02
0.05
0.00
−40
−25
−10
5
20
35
50
65
0.00
−40
80
−25
TA − Free-Air Temperature − °C
−10
Figure 15.
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
Minimum Differential Nonlinearity − LSB
Maximum Differential Nonlinearity − LSB
50
65
80
0.00
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−40
35
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1.0
0.8
20
Figure 16.
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.9
5
TA − Free-Air Temperature − °C
−25
−10
5
20
35
50
65
80
−0.05
−0.10
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
−0.15
−0.20
−0.25
−0.30
−0.35
−0.40
−0.45
−40
TA − Free-Air Temperature − °C
Figure 17.
−25
−10
5
20
35
50
65
80
TA − Free-Air Temperature − °C
Figure 18.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
13
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.90
0.86
−0.330
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
Minimum Integral Nonlinearity − LSB
Maximum Integral Nonlinearity − LSB
0.88
−0.329
0.84
0.82
0.80
0.78
0.76
0.74
−40
−25
−10
5
20
35
50
65
80
−0.331
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
−0.332
−0.333
−0.334
−0.335
−0.336
−0.337
−0.338
−40
−25
−10
5
20
35
50
65
80
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
Figure 19.
Figure 20.
DNL − Differential Nonlinearity − LSB
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.3
VCC = 5.5 V, VREF+ = 4.096 V, VREF− = 0 V, I/O CLOCK = 15 MHz, TA = 25°C
0.2
0.1
0.0
−0.1
−0.2
−0.3
0
1024
2048
3072
4096
Digital Output Code
Figure 21.
14
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
TYPICAL CHARACTERISTICS (continued)
INL − Integral Nonlinearity − LSB
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.8
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
VCC = 5.5 V, VREF+ = 4.096 V, VREF− = 0 V, I/O CLOCK = 15 MHz, TA = 25°C
−0.8
0
1024
2048
3072
4096
Digital Output Code
Figure 22.
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
0.00
EO − Offset Error − mV
−0.10
−0.1
−0.2
EG − Gain Error − mV
−0.05
0.0
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
−0.15
−0.20
−0.25
−0.30
−0.35
−0.3
−0.4
−0.5
−0.6
−0.7
−0.40
−0.8
−0.45
−0.9
−0.50
−40
−25
−10
5
20
35
50
65
80
VCC = 5.5 V
VREF+ = 4.096 V
VREF− = 0 V
I/O CLOCK = 15 MHz
−1.0
−40
TA − Free-Air Temperature − °C
Figure 23.
−25
−10
5
20
35
50
65
80
TA − Free-Air Temperature − °C
Figure 24.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
15
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
Parameter Measurement Information
VIH
CS
Data Valid
VIL
td1
VIH
DATA IN
td2
VIL
th1
VOH
Data Out
VOL
Figure 25. DATA OUT to Hi-Z Voltage Waveforms
VIH
VIL
CS
th2
th3
tsu2
tsu1
I/O
CLOCK
VIH
VIL
Figure 26. DATA IN and I/O CLOCK Voltage
tt1
tt1
VIH
VIL
I/O
CLOCK
I/O CLK Period
VIH
I/O
CLOCK
Last
Clock
td3
VIL
th4
VOH
Data Out
VOL
tt2
Figure 27. CS and I/O CLOCK Voltage Waveforms
I/O
CLOCK
Figure 28. I/O CLOCK and DATA OUT Voltage
Waveforms
VIH
Last
Clock
VIL
tt3
VOL
tconvert
td2
tt3
VOH
EOC
VOL
VOH
EOC
VOH
Data Out
tt3
MSB
Valid
Figure 29. I/O CLOCK and EOC Voltage Waveforms
th5
EOC
VIL
1
VOH
I/O
CLOCK
VOL
EOC
Figure 31. CS and EOC Waveforms
16
Figure 30. EOC and DATA OUT Voltage Waveforms
VIH
CS
VOL
VIH
VIL
VOH
VOL
Figure 32. I/O CLOCK and DATA OUT Voltage
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
Parameter Measurement Information (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
I/O
CLOCK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
DATA
OUT
3
2
4
5
6
7
8
9
10
11
12
D7
D6
Output Data
Format
D5
D4
D3
D2
D1
3
2
Hi−Z State
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
Channel
Address
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Previous Conversion Data
MSB
DATA
IN
Sample Cycle
LSB
MSB
D0
MSB−1 MSB−2
D7
D6
D5
A/D Conversion Interval
tCONV
EOC
Initialize
Initialize
Figure 33. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
I/O
CLOCK
DATA
OUT
DATA IN
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Sample Cycle
3
2
4
5
6
7
8
Previous Conversion Data
MSB
10
11
D6
D5
Output Data
Format
D4
D3
D2
D1
D0
12
1
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
Channel
Address
D7
9
LSB
Low Level
MSB
D7
2
3
MSB−1 MSB−2
D6
D5
A/D Conversion Interval
tCONV
EOC
Initialize
Initialize
NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 34. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
17
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
Parameter Measurement Information (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
2
Sample Cycle
3
4
5
7
6
I/O
CLOCK
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
DATA
OUT
DATA IN
Previous Conversion Data
8
1
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
2
3
4
5
6
7
Hi−Z State
MSB
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5
Channel
Address
D7
D6
D5
LSB+1
Output Data
Format
D4
D3
D2
D1
LSB
MSB
D0
D7
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
D6
D5
D4
D3
D2
D1
A/D Conversion Interval
tCONV
EOC
Initialize
Initialize
Figure 35. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
1
Access
Cycle
3
2
I/O
CLOCK
Sample Cycle
4
5
7
6
8
1
2
3
4
5
6
7
Previous Conversion Data
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
DATA
OUT
MSB
D7
DATA IN
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5
Channel
Address
D6
D5
LSB+1
Output Data
Format
D4
D3
D2
D1
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
LSB
Low Level
D0
MSB
D7
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
D6
D5
D4
D3
D2
D1
A/D Conversion Interval
tCONV
EOC
Initialize
Initialize
NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 36. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First
18
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
Parameter Measurement Information (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
1
Sample Cycle
3
2
4
I/O
CLOCK
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
DATA
OUT
MSB
DATA IN
D7
5
6
7
8
9
10
11
12
Pad
Zeros
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
D6
Output Data
Format
D5
D4
D3
D2
D1
1
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Previous Conversion Data
Channel
Address
16
Hi−Z State
LSB
MSB
D0
D7
A/D Conversion Interval
tCONV
EOC
Initialize
Initialize
Figure 37. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
1
2
3
Sample Cycle
4
I/O
CLOCK
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
DATA
OUT
MSB
DATA IN
D7
5
6
7
8
9
10
11
12
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9
D6
D5
Output Data
Format
D4
D3
D2
D1
1
Pad
Zeros
Previous Conversion Data
Channel
Address
16
LSB+1
LSB
Low Level
MSB
D0
D7
A/D Conversion Interval
tCONV
EOC
Initialize
Initialize
NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 38. Timing for 16-Clock Transfer Not Using CS With DATA OUT Set for MSB First
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
19
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
PRINCIPLES OF OPERATION
Detailed Description
Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA IN and
removes DATA OUT from the high-impedance state. The input data is an 8-bit data stream consisting of a 4-bit
address or command (D7–D4) and a 4-bit configuration data (D3–D0). Configuration register 1 (CFGR1), which
controls output data format configuration, consists of a 2-bit data length select (D3–D2), an output MSB or LSB
first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to any command (from DATA IN)
except for command 1111b. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to
the input data register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion result
from the output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles
long depending on the data-length selection in the input data register. Sampling of the analog input begins on the
fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK
sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.
Converter Operation
The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle, 2) the
sampling cycle, and 3) the conversion cycle. The first two are partially overlapped.
Data I/O Cycle
The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,
depending on the selected output data length. During the I/O cycle, the following two operations take place
simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided to
DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. DATA INPUT
is ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length of 8, 12,
or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising
edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling edge of
CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding
bit is clocked out on the falling edge of each succeeding I/O CLOCK.
Sampling Cycle
During the sampling cycle, one of the analog inputs is internally connected to the capacitor array of the converter
to store the analog input signal. The converter starts sampling the selected input immediately after the four
address/command bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge of
the I/O CLOCK depending on the data-length selection.
After the 8-bit data stream has been clocked in, DATA IN should be held at a fixed digital level until EOC goes
high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the influence
of external digital noise.
Conversion Cycle
A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external
digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by
an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns) to
start the OSC. During the conversion period, the device performs a successive-approximation conversion on the
analog input voltage.
EOC goes low at the start of the conversion cycle and goes high when the conversion is complete and the output
data register is latched. After EOC goes low, the analog input can be changed without affecting the conversion
result. Since the delay from the falling edge of the last I/O CLOCK to the falling edge of EOC is fixed, any
time-varying analog input signals can be digitized at a fixed rate without introducing systematic harmonic
distortion or noise due to timing uncertainty.
20
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
Power Up and Initialization
After power up, CS must be taken from high to low to begin an I/O cycle. The EOC pin is initially high, and the
configuration register is set to all zeroes. The contents of the output data register are random, and the first
conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low to
begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not
read accurately due to internal device settling.
Table 1. Operational Terminology
Current (N) I/O cycle
The entire I/O CLOCK sequence that transfers address and control data into the data register and
clocks the digital result from the previous conversion from DATA OUT
Current (N) conversion cycle
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle
is the last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded
into the output register when conversion is complete.
Current (N) conversion result
The current conversion result is serially shifted out on the next I/O cycle.
Previous (N – 1) conversion cycle
The conversion cycle just prior to the current I/O cycle
Next (N + 1) I/O cycle
The I/O period that follows the current conversion cycle
Example
In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the
next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this
corrupts the output data from the previous conversion. The current conversion is begun immediately after the
twelfth falling edge of the current I/O cycle.
Data Input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the input data byte with the MSB
first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data
input-register format).
Table 2. Command Set (CMR) and Configuration
SDI D[7:4]
(1)
COMMAND
BINARY
HEX
0000
0
SELECT analog input channel 0
0001
1
SELECT analog input channel 1
0010
2
SELECT analog input channel 2
0011
3
SELECT analog input channel 3
0100
4
SELECT analog input channel 4
0101
5
SELECT analog input channel 5
0110
6
SELECT analog input channel 6
0111
7
SELECT analog input channel 7
1000
8
SELECT analog input channel 8
1001
9
SELECT analog input channel 9
1010
A
SELECT analog input channel 10
1011
B
SELECT TEST,
Voltage = (VREF+ + VREF–)/2
1100
C
SELECT TEST, Voltage = REFM
1101
D
SELECT TEST, Voltage = REFP
1110
E
SW POWERDOWN (analog + reference)
1111
F
Reserved
CFGR1
SDI D[3:0]
CONFIGURATION
01: 8-bit output length
D[3:2]
X0: 12-bit output length (1)
11: 16-bit output length
D1
D0
0: MSB out first
1: LSB out first
0: Unipolar binary
1: Bipolar 2s complement
Select 12-bit output mode to achieve 200-KSPS sampling rate.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
21
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
Data Input – Address/Command Bits
The four MSBs (D7–D4) of the input data register are the address or command. These can be used to address
one of the 11 input channels, address one of three reference-test voltages, or activate software power-down
mode. All address/command bits affect the current conversion, which is the conversion that immediately follows
the current I/O cycle. They also have access to CFGR1 except for command 1111b, which is reserved.
Data Output Length
CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for
the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current
I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be
selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be
exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion result
are truncated and discarded. The current conversion is started immediately after the eighth falling edge of the
current I/O cycle.
Since the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there can
be a conflict with the previous cycle if the data-word length was changed. This may occur when the data format
is selected to be least significant bit first, since at the time the data length change becomes effective (six rising
edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation, when
different data lengths are required within an application and the data length is changed between two conversions,
no more than one conversion result can be corrupted and only when it is shifted out in LSB-first format.
LSB Out First
D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion
result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first
always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to
another, the current I/O cycle is never disrupted.
Bipolar Output Format
D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared to
0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an
input voltage equal to or less than VREF– is a code with all zeros (000...0) and the conversion result of an input
voltage equal to or greater than VREF+ is a code of all ones (111...1). The conversion result of (VREF+ + VREF–)/2 is
a code of a one followed by zeros (100...0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to or less than VREF– is a code of a one followed by zeros (100...0), and the conversion
of an input voltage equal to or greater than VREF+ is a code of a zero followed by all ones (011...1). The
conversion result of (VREF+ + VREF–)/2 is a code of all zeros (000...0). The MSB is interpreted as the sign bit. The
bipolar data format is related to the unipolar format in that the MSBs are always each other's complement.
22
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579 – APRIL 2009
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
Reference
An external reference can be used through two reference input pins, REF+ and REF–. The voltage levels applied
to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale
reading respectively. The values of REF+, REF–, and the analog input should not exceed the positive supply or
be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale
when the input signal is equal to or higher than REF+ and at zero when the input signal is equal to or lower than
REF–.
Analog
Supply
VCC
REF+
Sample
C1
0.1 µF
Decoupling Cap
Convert
∼50 pF
CDAC
REF−
GND
Figure 39. Reference Block
EOC Output
Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning
and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after
the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the
converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O
CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes
low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the
falling edge of CS.
Chip-Select Input (CS)
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
23
TLV2553-Q1
SLAS579 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its
output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is
inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next I/O cycle.
When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs
on DATA OUT on the rising edge of EOC. Note that the first cycle in the series still requires a transition CS from
high to low. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes low and the
serial output is forced low until EOC goes high again.
When CS is toggled between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On
each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in
the serial conversion result until the required number of bits has been output.
Power-Down Features
When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles, the
software power-down mode is selected. Software power down is activated on the falling edge of the fourth I/O
CLOCK pulse.
During software power-down, all internal circuitry is put in a low-current standby mode. No conversions is
performed. The internal output buffer keeps the previous conversion cycle data results, provided that all digital
inputs are held above VCC – 0.5 V or below 0.5 V. The I/O logic remains active so the current I/O cycle must be
completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle, the
converter normally begins in the power-down mode. The device remains in the software power-down mode until
a valid input address (other than command 1110b or 1111b) is clocked in. Upon completion of that I/O cycle, a
normal conversion is performed with the results being shifted out during the next I/O cycle.
The ADC also has an auto power-down mode. This is transparent to users. The ADC gets into auto power-down
within one I/O CLOCK cycle after the conversion is complete and resumes, with a small delay, after an active CS
is sent to the ADC. The resumption is fast enough to be used between cycles.
Analog MUX
The 11 analog inputs, 3 internal voltages, and power-down mode are selected by the input multiplexer according
to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce
input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on the falling
edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the
falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
24
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2553-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TLV2553IDWRQ1
ACTIVE
SOIC
DW
Pins Package Eco Plan (2)
Qty
20
2000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2553-Q1 :
• Catalog: TLV2553
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Communications and Telecom www.ti.com/communications
Amplifiers
amplifier.ti.com
Computers and Peripherals
www.ti.com/computers
Data Converters
dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
Energy and Lighting
www.ti.com/energy
DSP
dsp.ti.com
Industrial
www.ti.com/industrial
Clocks and Timers
www.ti.com/clocks
Medical
www.ti.com/medical
Interface
interface.ti.com
Security
www.ti.com/security
Logic
logic.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and
Automotive
www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
Wireless
www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions
www.ti.com/lprf
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated