TI TLV2556IPW

TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
12-BIT, 200-KSPS, 11 CHANNEL, LOW POWER, SERIAL ADC
WITH INTERNAL REFERENCE
FEATURES
D 12-Bit-Resolution A/D Converter
D Up to 200-KSPS (150-KSPS for 3 V)
D
D
D
D
D
D
D
D
D
D
D
D
Throughput Bit With 12-Output Mode Over
Operating Temperature Range
11 Analog Input Channels
3 Built-In Self-Test Modes
Programmable Reference (2.048/4.096 V
Internal, External)
Inherent Sample and Hold Function
Linearity Error . . . ± 1 LSB Max
On-Chip Conversion Clock
Programmable Conversion Status Output: INT
or EOC
Unipolar or Bipolar Output Operation
Programmable MSB or LSB First
Programmable Power Down
Programmable Output Data Length
SPI Compatible Serial Interface With I/O Clock
Frequencies up to 15 MHz (CPOL=0, CPHA=0)
In addition to the high-speed converter and versatile
control capability, the device has an on-chip 14-channel
multiplexer that can select any one of 11 inputs or any
one of three internal self-test voltages using
configuration register 1. The sample-and-hold function
is automatic. At the end of conversion, when
programmed as EOC, the pin 19 output goes high to
indicate that conversion is complete. If pin 19 is
programmed as INT, the signal goes low when the
conversion is complete. The converter incorporated in
the device features differential, high-impedance
reference inputs that facilitate ratiometric conversion,
scaling, and isolation of analog circuitry from logic and
supply noise. A switched-capacitor design allows lowerror conversion over the full operating temperature
range. An internal reference is available and its voltage
level is programmable via configuration register 2
(CFGR2).
The TLV2556I is characterized for operation from
TA = –40°C to 85°C. See available options table for
package options.
APPLICATIONS
D Industrial Process Control
D Portable Data Logging
D Battery Powered Instruments
D Automotive
DESCRIPTION
The TLV2556 is a 12-bit, switched-capacitor,
successive-approximation, analog-to-digital converter.
The ADC has three control inputs [chip select (CS), the
input-output clock, and the address/control input
(DATAIN)], designed for communication with the serial
port of a host processor or peripheral through a serial
3-state output.
PW AND DW PACKAGE
(TOP VIEW)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
INT/EOC
I/O CLOCK
DATA IN
DATA OUT
CS
REF +
REF –
AIN10
AIN9
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
TA
20-TSSOP (PW)
20-SOWB (DW)
TLV2556IPW
TLV2556IDW
– 40°C to 85°C
functional block diagram
VCC
20
3
AIN0 1
AIN1 2
AIN2 3
AIN3 4
AIN4 5
AIN5 6
AIN6 7
AIN7 8
AIN8 9
AIN9 11
AIN10 12
DATA IN
CS
I/O CLOCK
Self Test
14-Channel
Analog
Multiplexer
4.096/2.048 V
Internal Reference
Low Power
12-Bit
SAR ADC
Input Address
Register
18
Control Logic
and I/O
Counters
10
GND
2
19
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INT/EOC
12
Output Data
Register
12
12-to-1
Data
Selector
and Driver
17
15
REF –
13
Reference CTRL
Sample
and Hold
4
REF +
14
4
Internal
OSC
16
DATA
OUT
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AIN0 – AIN10
1 – 9,
11, 12
I
Analog input. These 11 analog-signal inputs are internally multiplexed.
CS
15
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT,
DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and I/O CLOCK within a setup time.
DATA IN
17
I
Serial data input. The 4-bit serial data can be used as address selects the desired analog input channel or
test voltage to be converted next, or a command to activate other other features. The input data is presented
with the MSB (D7) first and is shifted in on the first four rising edges of the I/O CLOCK. After the four
address/command bits are read into the command register CMR, I/O CLOCK clocks the remaining four bits
of configuration in.
DATA OUT
16
O
The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS
is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state
and is driven to the logic level corresponding to the MSB(most significant bit)/LSB(least significant bit) value
of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level
corresponding to the next MSB/LSB, and the remaining bits are shifted out in order.
INT/EOC
19
O
Status output, used to indicate the end of conversion (EOC) or an interrupt (INT) to host processor.
Programmed as INT (interrupt): INT goes from a high to a low logic level after the conversion is complete and
the data is ready for transfer. INT is cleared by a rising I/O CLOCK transition.
Programmed as EOC: EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK
and remains low until the conversion is complete and the data is ready for transfer.
GND
10
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage
measurements are with respect to GND.
I/O CLOCK
18
I
Input /output clock. I/O CLOCK receives the serial input and performs the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK
with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of I/O CLOCK.
3. The remaining 11 bits of the previous conversion data are shifted out on DATA OUT. Data changes on the
falling edge of I/O CLOCK.
4. Control of the conversion is transferred to the internal state controller on the falling edge of the last
I/O CLOCK.
REF +
14
I/O
Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The
maximum analog input voltage range is determined by the difference between the voltage applied to terminals
REF+ and REF–.
REF –
13
I/O
VCC
20
When the internal reference is used it is capable of driving a 10-kΩ, 10-pF load.
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF–. This
pin is connected to analog ground (GND of the ADC) when the internal reference is used.
Positive supply voltage
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3
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Positive reference voltage range, Vref + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Negative reference voltage range, Vref – . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Peak input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminal with REF – and GND wired together (unless otherwise noted).
recommended operating conditions
PARAMETERS
MIN
Supply voltage, VCC
SCLK frequency
Tolerable clock jitter, I/O CLOCK
Aperature jitter
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
NOM
MAX
UNIT
V
2.7
5.5
16-bit I/O
0.01
15
12-bit I/O
0.01
15
8-bit I/O
0.01
15
0.01
10
0.38
100
ns
ps
0
(REF+) – (REF–)
VCC = 3.0 V to 3.6 V
VCC = 2.7 V to 3.0 V
0
(REF+) – (REF–)
0
(REF+) – (REF–)
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
2.0
High level control input voltage,
High-level
voltage VIH
Low level control input voltage
Low-level
voltage, VIL
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
Analog in
input
ut voltage (see Note 2)
MHz
V
V
2.1
0.8
0.6
V
Operating free-air temperature, TA
TLV2556I
–40
85
°C
NOTE 2: Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
4
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
electrical characteristics over recommended operating free-air temperature range, VREF+ = 5 V,
SCLK frequency = 15 MHz when VCC = 5 V, VREF+ = 2.5 V, SCLK frequency = 10 MHz when
VCC = 2.7 V (unless otherwise noted)
PARAMETER
VOH
VOL
IOZ
ICC
TEST CONDITIONS
High level output voltage
High-level
Low level output voltage
Low-level
High impedance off
High-impedance
off-state
state output current
ICC(APD)
IIH
IIL
power down current
Auto power-down
High-level input current
2.4
VCC = 4.5 V, IOH = –20 µA
VCC = 2.7 V, IOH = –20 µA
30 pF
VCC –0.1
VCC = 5.5 V, IOL = 1.6 mA
VCC = 3.6 V, IOH = 0.8 mA
30 pF
0.4
VCC = 5.5 V, IOL = –20 µA
VCC = 3.6 V, IOH = –20 µA
30 pF
0.1
V
VO = VCC,
VO = 0 V,
CS at VCC
Ext.
Ext Ref
VCC = 5 V
VCC = 2.7 V
1.2
CS at 0 V
V,
3
Int.
Int Ref
VCC = 5 V
VCC = 2.7 V
CS at VCC
1
2.5
–1
–2.5
Selected channel leakage current
Ext. Ref
0.1
1
Int. Ref
0.1
1
For all digital inputs,
0 V ≤ VI ≤ 0.5 V or
VI ≥ VCC – 0.5 V,
SCLK = 0 V
Ext. Ref
0.1
10
µA
A
µA
Int. Ref
1800
0.005
2.5
µA
–0.005
–2.5
µA
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
tconv
Conversion time = 13
13.5
5 [f(OSC)] + 25 ns
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
Internal oscillator frequency switch over
voltage
Zi
Analog input MUX impedance‡
Ci
Input capacitance
1
µA
Selected channel at 0 V, Unselected channel
at VCC
Internal oscillator frequency
mA
2.4
For all digital inputs,
0 V ≤ VI ≤ 0.5 V or
VI ≥ VCC – 0.5 V,
SCLK = 0 V
f(OSC)
µA
A
0.9
Selected channel at VCC , Unselected
channel at 0 V
Ilkg
UNIT
V
VI = VCC
VI = 0 V
Low-level input current
MAX
30 pF
Operating supply current
down current
Software power
power-down
TYP†
VCC = 4.5 V, IOH = –1.6 mA
VCC = 2.7 V, IOH = –0.2 mA
CS at 0 V,
V
ICC(SPD)
MIN
–1
3.27
MHz
2.56
4.15
5.54
3.6
4.1
VCC = 4.5 V
VCC = 2.7 V
600
500
Analog inputs
45
55
Control inputs
5
15
µs
V
Ω
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The switch resistance is very nonlinear and varies with input voltage and supply voltage. This is the worst case.
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5
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
external reference specifications
MIN
TYP†
MAX
–0.1
0
0.1
Reference input voltage
voltage, REF
REF–
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
–0.1
0
0.1
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
2
Reference input voltage,
voltage REF+
REF
External reference in
input
ut voltage difference,
(REF+) – (REF–)
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
1.9
External reference supply current
CS at 0 V
PARAMETER
TEST CONDITIONS
2
1.9
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 5 V
Reference input impedance
V
VCC
VCC
V
1
1
During sampling/conversion
6
Static
1
During sampling/conversion
† All typical values are at VCC = 5 V, TA = 25°C.
NOTE: Add a 0.1-µF capacitor between REF+ and REF– pins when external reference is used.
V
VCC
VCC
0.7
Static
27V
VCC = 2.7
UNIT
mA
MΩ
9
kΩ
MΩ
6
9
kΩ
internal reference specifications
PARAMETER
Reference input voltage, REF–
IInternal
t
l reference
f
d
delta
lt voltage,
lt
(REF+) – (REF–)
Internal reference start-up
start up time
TEST CONDITIONS
TYP†
MAX
VCC = 2.7 V to 5.5 V,
VCC = 5.5 V,
REF– = Analog GND
Internal 4.096-Vref selected
3.95
4.065
4.25
VCC = 5.5 V,
VCC = 2.7 V,
Internal 2.048-Vref selected
1.95
2.019
2.1
Internal 2.048-Vref selected
1.95
2.019
2.1
VCC = 5 V
VCC = 2.7 V
0
UNIT
V
V
20
With 10
10-µF
F load
Internal reference temperature coefficient
VCC = 2.7 V to 5.5 V
† All typical values are at VCC = 5 V, TA = 25°C.
NOTE: When an internal reference is used, the following conditions are required:
a) Add 0.1-µF and 10-µF capacitors between REF+ and REF– pins.
b) REF– must be connected to analog GND (the ground pin of the ADC).
6
MIN
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20
±50
ms
PPM/°C
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
operating characteristics over recommended operating free-air temperature range, VREF+ = 5 V,
SCLK frequency = 15 MHz when VCC = 5 V, VREF+ =2.5 V, SCLK frequency = 10 MHz when VCC = 2.7 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
INL
Integral nonlinearity error (see Note 3)
–1
1
LSB
DNL
Differential nonlinearity error
–1
1
LSB
EO
Offset error (see Note 4)
See Note 2
–2
2
mV
EG
Gain error (see Note 4)
See Note 2
–3
ET
Total unadjusted error (see Note 5)
Address data input = 1011
Self-test
Self
test out
output
ut code (see Table 2 and Note 6)
3
±1.5
mV
LSB
2048
Address data input = 1100
0
Address data input = 1101
4095
† All typical values are at TA = 25°C.
NOTES: 2. Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than
the voltage applied to REF– convert as all zeros (000000000000).
3. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
4. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified
gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the
nominal midstep value at the offset point.
5. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
6. Both the input address and the output codes are expressed in positive logic.
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7
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
timing characteristics over recommended operating free-air temperature range, VREF+ = 5 V, SCLK
frequency = 15 MHz, VCC = 5 V, load = 25 pF (unless otherwise noted)
PARAMETER
MIN
tw1
Pulse duration I/O CLOCK high or low
tsu1
th1
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 38)
26.7
TYP
MAX
UNIT
100000
ns
12
ns
0
ns
Setup time CS low before 1st rising I/O CLOCK edge
(see Note 7 and Figure 39)
25
ns
th2
th3
Hold time CS pulse duration high time (see Figure 39)
100
ns
Hold time CS low after last I/O CLOCK falling edge (see Figure 39)
0
ns
th4
th5
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 40)
2
ns
Hold time CS high after EOC rising edge when CS is toggled (see Figure 43)
0
ns
th6
Hold time CS high after INT falling edge (see Figure 43)
0
ns
th7
Hold time I/O CLOCK low after EOC rising edge or INT falling edge when CS is
held low (see Figure 44)
10
ns
td1
Delay time CS falling edge to DATA OUT valid
(MSB or LSB) (see Figure 37)
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 37)
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 40)
td4
td5
Delay time last I/O CLOCK falling edge to EOC falling edge (see Figure 41)
55
ns
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
1.5
µs
td6
Delay time last I/O CLOCK falling edge to INT falling edge (see Figure 41)
MAX(tconv)
ns
td7
Delay time EOC rising edge or INT falling edge to DATA OUT valid: MSB or LSB
1st (see Figure 42)
4
ns
td9
Delay time I/O CLOCK high to INT rising edge when CS is held low
(see Figure 44)
28
ns
tsu2
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 38)
Load = 25 pF
28
Load = 10 pF
20
2
1
ns
10
ns
20
ns
tt1
tt2
Transition time I/O CLOCK (see Note 7 and Figure 40)
1
µs
Transition time DATA OUT (see Figure 40)
5
ns
tt3
tt4
Transition time INT/EOC, CL at 7 pF (see Figures 41 and 42)
2.4
ns
Transition time DATA IN, CS
10
µs
tcyc
Total cycle time (sample, conversion and delays) (see Note 7)
MAX(tconv) + I/O
period
(8/12/16 CLKs)
µs
tsample
Channel acquisition time (sam
(sample),
le), at 1 kΩ
(see Note 7)
Source impedance = 25 Ω
600
Source impedance = 100 Ω
650
Source impedance = 500 Ω
700
Source impedance = 1 K Ω
1000
ns
NOTE 7: I/O CLOCK period = 8 [1/(I/O CLOCK frequency)] or 12 [1/(I/O CLOCK frequency)] or 16 [1/(I/O CLOCK frequency)] depends
on I/O format selected.
8
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
timing characteristics over recommended operating free-air temperature range, VREF+ = 2.5 V, SCLK
frequency = 10 MHz, VCC = 2.7 V, load = 25 pF (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
100000
ns
tw1
tsu1
Pulse duration I/O CLOCK high or low
40
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 38)
22
ns
th1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 38)
0
ns
tsu2
Setup time CS low before 1st rising I/O CLOCK edge
(see Note 7 and Figure 39)
33
ns
th2
th3
Hold time CS pulse width high time (see Figure 39)
100
ns
Hold time CS low after last I/O CLOCK falling edge (see Figure 39)
0
ns
th4
th5
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 40)
2
ns
Hold time CS high after EOC rising edge when CS is toggled (see Figure 43)
0
ns
th6
Hold time CS high after INT falling edge (see Figure 43)
0
ns
th7
Hold time I/O CLOCK low after EOC rising edge or INT falling edge when CS is
held low (see Figure 44)
10
ns
td1
Delay time CS falling edge to DATA OUT valid
(MSB or LSB) (see Figure 37)
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 37)
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 40)
td4
td5
Delay time last I/O CLOCK falling edge to EOC falling edge (see Figure 41)
75
ns
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
1.5
µs
td6
Delay time last I/O CLOCK falling edge to INT falling edge (see Figure 41)
MAX(tconv)
ns
td7
Delay time EOC rising edge or INT falling edge to DATA OUT valid: MSB or LSB
1st (see Figure 42)
20
ns
td9
Delay time I/O CLOCK high to INT rising edge when CS is held low
(see Figure 44)
55
ns
tt1
tt2
Transition time I/O CLOCK (see Note 7 and Figure 40)
1
µs
Transition time DATA OUT (see Figure 40)
5
ns
tt3
tt4
Transition time INT/EOC, CL at 7 pF (see Figures 41 and 42)
4
ns
Transition time DATA IN, CS
10
µs
tcyc
Total cycle time (sample, conversion and delays) (see Note 7)
MAX(tconv) + I/O
period
(8/12/16 CLKs)
µs
tsample
Channel acquisition time (sam
(sample),
le), at 1 kΩ
(see Note 7)
Load = 25 pF
30
Load = 10 pF
22
2
Source impedance = 25 Ω
800
Source impedance = 100 Ω
850
Source impedance = 500 Ω
1000
Source impedance = 1K Ω
1600
ns
10
ns
33
ns
ns
NOTE 7: I/O CLOCK period = 8 [1/(I/O CLOCK frequency)] or 12 [1/(I/O CLOCK frequency)] or 16 [1/(I/O CLOCK frequency)] depends
on I/O format selected.
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9
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
I CC – Supply Current – mA
0.78
1100
VCC = 3.3 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
1050
Current – µ A
0.8
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
0.76
0.74
1000
VCC = 3.3 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
950
0.72
0.7
900
–40
25
85
TA – Free-Air Temperature – °C
–40
25
85
TA – Free-Air Temperature – °C
Figure 1
Figure 2
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
Current – µ A
0.2
1.15
VCC = 3.3 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
1.1
Current – mA
0.25
2-V INTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
0.15
0.1
1.05
VCC = 3.3 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
1
0.05
0.95
0
–40
–40
25
85
TA – Free-Air Temperature – °C
Figure 3
25
85
TA – Free-Air Temperature – °C
Figure 4
NOTE: All typical curves are with internal reference unless specified otherwise. Refer to the TLV2553 data sheet (SLAS354) for typical curves
using an external reference.
10
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.9
0.8
0.7
VCC = 2.7 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
0
Minimum Differential Nonlinearity – LSB
Maximum Differential Nonlinearity – LSB
1
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
VCC = 2.7 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1
–40
25
85
TA – Free-Air Temperature – °C
–40
25
85
TA – Free-Air Temperature – °C
Figure 5
Figure 6
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1
0
0.9
–0.1
Minimum Integral Nonlinearity – LSB
Maximum Integral Nonlinearity – LSB
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
VCC = 2.7 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
–0.2
–0.3
VCC = 2.7 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1
0
–40
25
TA – Free-Air Temperature – °C
85
–40
Figure 7
25
85
TA – Free-Air Temperature – °C
Figure 8
NOTE: All typical curves are with internal reference unless specified otherwise. Refer to the TLV2553 data sheet (SLAS354) for typical curves
using an external reference.
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11
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
DNL – Differential Nonlinearity Error – LSB
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 2.7 V, VREF+ = 2.048 V, VREF– = 0 V,
I/O CLOCK = 10 MHz, 150 KSPS, TA = 25°C
1
0.5
0
–0.5
–1
–1.5
0
1024
2048
3072
4096
Codes
INL – Integral Nonlinearity Error – LSB
Figure 9
INTEGRAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 2.7 V, VREF+ = 2.048 V, VREF– = 0 V,
I/O CLOCK = 10 MHz, 150 KSPS, TA = 25°C
1
0.5
0
–0.5
–1
–1.5
0
1024
2048
3072
4096
Codes
Figure 10
NOTE: All typical curves are with internal reference unless specified otherwise. Refer to the TLV2553 data sheet (SLAS354) for typical curves
using an external reference.
12
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
GAIN ERROR
vs
FREE-AIR TEMPERATURE
OFFSET ERROR
vs
FREE-AIR-TEMPERATURE
0.05
0
0.03
0.02
0.01
0
VCC = 3.3 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
–40
EO– Offset Error – mV
EG – Gain Error – mV
0.04
–0.05
VCC = 3.3 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 10 MHz
150 KSPS,
TA = 25°C
–0.1
–0.15
25
85
TA – Free-Air Temperature – °C
–40
25
85
TA – Free-Air Temperature – °C
Figure 11
Figure 12
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
0.99
0.97
1100
Current – µ A
I CC – Supply Current – mA
0.98
1120
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.96
0.95
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
1080
1060
1040
0.94
0.93
1020
–40
25
85
TA – Free-Air Temperature – °C
–40
Figure 13
25
85
TA – Free-Air Temperature – °C
Figure 14
NOTE: All typical curves are with internal reference unless specified otherwise. Refer to the TLV2553 data sheet (SLAS354) for typical curves
using an external reference.
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13
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
4-V INTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
1.55
0.5
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
1.5
1.45
Current – mA
Current – µ A
0.4
0.3
0.2
1.4
1.35
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
1.3
0.1
1.25
1.2
0
–40
–40
25
85
TA – Free-Air Temperature – °C
Figure 15
Figure 16
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.8
0.7
0
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.6
0.5
0.4
0.3
0.2
0.1
Minimum Differential Nonlinearity – LSB
Maximum Differential Nonlinearity – LSB
1
0.9
25
85
TA – Free-Air Temperature – °C
0
–0.1
–0.2
–0.3
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1
25
85
–40
TA – Free-Air Temperature – °C
–40
25
85
TA – Free-Air Temperature – °C
Figure 17
Figure 18
NOTE: All typical curves are with internal reference unless specified otherwise. Refer to the TLV2553 data sheet (SLAS354) for typical curves
using an external reference.
14
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1
0
0.9
–0.1
Minimum Integral Nonlinearity – LSB
Maximum Integral Nonlinearity – LSB
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.8
0.7
0.6
0.5
0.4
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.3
0.2
0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
0
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
–1
–40
25
85
–40
TA – Free-Air Temperature – °C
25
85
TA – Free-Air Temperature – °C
DNL – Differential Nonlinearity Error – LSB
Figure 19
Figure 20
DIFFERENTIAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 5.5 V, VREF+ = 4.096 V, VREF– = 0 V,
I/O CLOCK = 15 MHz, 200 KSPS, TA = 25°C
1
0.5
0
–0.5
–1
–1.5
0
1024
2048
3072
4096
Codes
Figure 21
NOTE: All typical curves are with internal reference unless specified otherwise. Refer to the TLV2553 data sheet (SLAS354) for typical curves
using an external reference.
www.ti.com
15
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
INL – Integral Nonlinearity Error – LSB
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 5.5 V, VREF+ = 4.096 V, VREF– = 0 V,
I/O CLOCK = 15 MHz, 200 KSPS, TA = 25°C
1
0.5
0
–0.5
–1
–1.5
0
1024
2048
3072
4096
Codes
Figure 22
OFFSET ERROR
vs
FREE-AIR-TEMPERATURE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
0
–0.4
0.15
EG – Gain Error – mV
EO – Offset Error – mV
–0.2
0.2
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
–0.6
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.1
0.05
0
–0.8
–40
–40
25
85
TA – Free-Air Temperature – °C
25
85
TA – Free-Air Temperature – °C
Figure 23
Figure 24
NOTE: All typical curves are with internal reference unless specified otherwise. Refer to the TLV2553 data sheet (SLAS354) for typical curves
using an external reference.
16
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.5
0.96
0.92
0.4
Current – µ A
I CC – Supply Current – mA
0.94
VCC = 5.5 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.9
0.88
VCC = 5.5 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0.3
0.2
0.86
0.1
0.84
0.82
0
–40
25
85
TA – Free-Air Temperature – °C
–40
25
TA – Free-Air Temperature – °C
Figure 25
Figure 26
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
2-V INTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
1010
1.25
VCC = 5.5 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
1.2
1.15
Current – mA
Current – µ A
1005
1000
995
85
VCC = 5.5 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
1.1
1.05
990
1
985
–40
0.95
25
85
TA – Free-Air Temperature – °C
–40
25
85
TA – Free-Air Temperature – °C
Figure 27
Figure 28
NOTE: All typical curves are with internal reference unless specified otherwise. Refer to the TLV2553 data sheet (SLAS354) for typical curves
using an external reference.
www.ti.com
17
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1
0
0.9
–0.1
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC = 5.5 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
Minimum Differential Nonlinearity – LSB
Maximum Differential Nonlinearity – LSB
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
–0.2
–0.3
VCC = 5.5 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1
–40
25
85
TA – Free-Air Temperature – °C
–40
25
85
TA – Free-Air Temperature – °C
Figure 29
Figure 30
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0
–0.1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
VCC = 5.5 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
Minimum Integral Nonlinearity – LSB
Maximum Integral Nonlinearity – LSB
1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1
0
–40
VCC = 5.5 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
25
85
TA – Free-Air Temperature – °C
Figure 31
–40
25
85
TA – Free-Air Temperature – °C
Figure 32
NOTE: All typical curves are with internal reference unless specified otherwise. Refer to the TLV2553 data sheet (SLAS354) for typical curves
using an external reference.
18
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
OFFSET ERROR
vs
FREE-AIR-TEMPERATURE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
0.4
0
0.3
EG – Gain Error – mV
EO – Offset Error – mV
–0.2
VCC = 5.5 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
–0.4
0.2
0.1
–0.6
–0.8
VCC = 5.5 V
VREF+ = 2.048 V
VREF– = 0 V
I/O CLOCK = 15 MHz
200 KSPS,
TA = 25°C
0
–40
25
85
TA – Free-Air Temperature – °C
–40
25
85
TA – Free-Air Temperature – °C
DNL – Differential Nonlinearity Error – LSB
Figure 33
Figure 34
DIFFERENTIAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 5.5 V, VREF+ = 2.048 V, VREF– = 0 V,
I/O CLOCK = 10 MHz, 200 KSPS, TA = 25°C
1
0.5
0
–0.5
–1
–1.5
0
1024
2048
3072
4096
Codes
Figure 35
NOTE: All typical curves are with internal reference unless specified otherwise. Refer to the TLV2553 data sheet (SLAS354) for typical curves
using an external reference.
www.ti.com
19
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
INL – Integral Nonlinearity Error – LSB
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
vs
CODES
1.5
VCC = 5.5 V, VREF+ = 2.048 V, VREF– = 0 V,
I/O CLOCK = 15 MHz, 200 KSPS, TA = 25°C
1
0.5
0
–0.5
–1
–1.5
0
1024
2048
3072
4096
Codes
Figure 36
NOTE: All typical curves are with internal reference unless specified otherwise. Refer to the TLV2553 data sheet (SLAS354) for typical curves
using an external reference.
PARAMETER MEASUREMENT INFORMATION
Data Valid
VIH
VIL
CS
td1
th1
td2
VOH
VOL
DATA
OUT
I/O CLOCK
Figure 37. DATA OUT to Hi-Z Voltage
Waveforms
VIH
VIL
th2
VIH
VIL
tt1
tt1
VIH
VIL
I/O CLOCK
I/O CLOCK Period
th3
tsu2
Last
Clock
Figure 39. CS and I/O CLOCK Voltage
Waveforms
20
tsu1
Figure 38. DATA IN and I/O CLOCK Voltage
CS
I/O CLOCK
VIH
VIL
DATA IN
td3
VIH
VIL
th4
DATA
OUT
tt2
VOH
VOL
Figure 40. I/O CLOCK and DATA OUT Voltage
Waveforms
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
I/O CLOCK
tt3
VIH
VIL
Last
Clock
tt3
tconv
td4
EOC
tt3
VOH
VOL
INT
VOH
VOL
DATA
OUT
td6
MSB
Valid
VIL
VIL
I/O CLOCK
th5
th7
VOH
EOC
EOC
VOH
td9
th6
INT
VOH
VOL
Figure 42. EOC and DATA OUT Voltage
Waveforms
Figure 41. I/O CLOCK and EOC Voltage
Waveforms
CS
VOH
VOL
td7
tt3
INT
VOH
VOL
EOC
VOL
INT
VOL
Figure 43. CS and EOC Voltage Waveforms
VOH
Figure 44. I/O CLOCK and EOC Voltage
Waveforms
timing information
First Cycle After Power-Up: Configure CFGR2
Configure CFGR1
1st Conversion Cycle
CS
1
Access Cycle
3
2
4
5
Data Cycle
7
6
8
9
10
11
12
16
1
I/O CLOCK
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Invalid Conversion Data
Hi–Z State
DATA OUT
Command 1111
DATA IN
CFGR2 Data
D3
D2
D1
D0
D7
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 45. Timing for CFGR2 Configuration
The host must configure CFGR2 before valid device conversions can begin. This can be accessed through
command 1111. This can be done using eight, twelve, or sixteen I/O CLOCK clocks. (A minimum of eight is
required to fully program CFGR2.)
After CFGR2 is configured, the following cycle configures CFGR1 and a valid sample/conversion is performed.
CS can be held low for each remaining cycle. First valid conversion output data is available on the third cycle
after power up.
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21
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
timing diagrams
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
3
2
Sample Cycle
4
I/O
CLOCK
5
6
7
8
9
10
11
12
Previous Conversion Data
DATA
OUT
MSB
ÎÎÎÎ
DATA
IN
D7
D6
Output Data
Format
D5
D4
D3
D2
D1
3
2
Hi–Z State
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9 LSB+1
Channel
Address
1
LSB
MSB
ÎÎÎÎÎÎÎÎÎÎÎÎ
D0
MSB–1 MSB–2
D7
D6
D5
A/D Conversion Interval
tconv
EOC
INT
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 46. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
3
2
Sample Cycle
4
5
6
7
8
9
10
11
12
1
I/O
CLOCK
2
3
Previous Conversion Data
DATA
OUT
MSB
ÎÎÎÎ
D7
DATA IN
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9 LSB+1
Channel
Address
D6
D5
Output Data
Format
D4
D3
D2
D1
LSB
Low Level
ÎÎÎÎÎÎÎÎÎÎÎÎ
D0
MSB
D7
MSB–1 MSB–2
D6
D5
A/D Conversion Interval
tconv
EOC
INT
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 47. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First
22
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
2
3
Sample Cycle
4
5
6
7
8
1
2
3
4
5
6
7
I/O
CLOCK
Previous Conversion Data
Hi–Z State
DATA
OUT
MSB
Channel
Address
ÎÎÎÎ
D7
DATA IN
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 LSB+1
D6
D5
LSB
Output Data
Format
D4
D3
D2
D1
D0
A/D Conversion Interval
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6
MSB
ÎÎÎÎÎÎÎÎ
D7
D6
D4
D5
D3
D2
D1
tconv
EOC
INT
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 48. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
1
Access
Cycle
3
2
I/O
CLOCK
Sample Cycle
4
5
6
7
8
1
2
3
4
5
6
7
Previous Conversion Data
DATA
OUT
MSB
ÎÎÎÎ
DATA IN
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 LSB+1
Channel
Address
D7
D6
D5
LSB
Output Data
Format
D4
D3
D2
D1
D0
A/D Conversion Interval
Low Level
MSB
ÎÎÎÎÎÎÎÎ
D7
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6
D6
D5
D4
D3
D2
D1
tconv
EOC
INT
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 49. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First
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23
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
1
Sample Cycle
3
2
4
I/O
CLOCK
5
6
7
8
9
10
11
12
Pad
Zeros
Previous Conversion Data
DATA
OUT
MSB
ÎÎÎÎ
DATA IN
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9 LSB+1
Channel
Address
D7
D6
Output Data
Format
D5
D4
D3
D2
16
1
Hi–Z State
LSB
MSB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
D1
D0
D7
A/D Conversion Interval
tconv
EOC
INT
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 50. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
1
2
3
Sample Cycle
4
I/O
CLOCK
5
6
7
8
9
10
11
12
MSB
ÎÎÎÎ
ÎÎÎÎ
DATA IN
D7
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9 LSB+1
Channel
Address
D6
D5
Output Data
Format
D4
D3
D2
D1
D0
1
Pad
Zeros
Previous Conversion Data
DATA
OUT
16
LSB
Low Level
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
D7
A/D Conversion Interval
tconv
EOC
INT
Initialize
Initialize
Figure 51. Timing for 16-Clock Transfer Not Using CS With DATA OUT Set for MSB First
24
MSB
www.ti.com
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Shift in New Multiplexer Address, Simultaneously
Shift Out Previous Conversion Result
CS
1
Access Cycle
3
4
2
Sample Cycle
5
7
6
8
9
10
11
16
12
1
I/O CLOCK
Previous Conversion Data
DATA OUT
DATA IN
MSB
Channel
Address
ÎÎÎ
Pad Zeros
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9 LSB+1
Output Data
Format
Hi–Z State
LSB
MSB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DATA IN Can be Tied or Held High
D7
A/D Conversion Interval
tconv
EOC Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 52. Timing for Default Mode Using CS: (16-Clock Transfer, MSB First, Ext. Ref,
Pin 19 = EOC, Input = AIN0)
Shift in New Multiplexer Address, Simultaneously
Shift Out Previous Conversion Result
CS
Access Cycle
1
2
3
Sample Cycle
4
5
6
7
8
9
10
11
12
16
1
I/O CLOCK
Previous Conversion Data
Pad Zeros
DATA OUT
MSB
ÎÎÎÎ
DATA IN
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9 LSB+1
Channel
Address
Output Data
Format
DATA IN Can be Tied or Held High
LSB
Low Level
MSB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
D7
A/D Conversion Interval
tconv
EOC
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 53. Timing for Default Mode Not Using CS: (16-Clock Transfer, MSB First Ext. Ref,
Pin 19 = EOC, Input = AIN0)
To remove the device from default mode, CFGR2–D0 must be reset to 0. Valid sample/convert cycles can
resume on the cycle following the CFGR2 configuration.
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25
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA IN and
removes DATA OUT from the high-impedance state. The input data is an 8-bit data stream consisting of a 4-bit
address or command (D7–D4) and a 4-bit configuration data (D3–D0). There are two sets of configuration
registers, configuration register 1 – CFGR1 and configuration register 2 – CFGR2. CFGR1, which controls
output data format configuration, consists of a 2-bit data length select (D3–D2), an output MSB or LSB first bit
(D1), and a unipolar or bipolar output select bit (D0) that are applied to any command (from DATA IN) except
for command 1111b. CFGR2, which provides configuration information other than data format, consists of a 2-bit
reference select (D3–D2), an EOC/INT program bit (D1), and a default mode select bit (D0) that are applied to
command 1111b. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the input
data register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the
output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles long
depending on the data-length selection in the input data register. Sampling of the analog input begins on the
fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK
sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low (if pin 19 = EOC) and begins
the conversion.
converter operation
The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle,
2) the sampling cycle and 3) the conversion cycle. The first two are partially overlapped.
data I/O cycle
The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,
depending on the selected output data length. During the I/O cycle, the following two operations take place
simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided
to DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. Data input
is ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length of 8, 12,
or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising
edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling edge of
CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding
bit is clocked out on the falling edge of each succeeding I/O CLOCK.
sampling period
During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after
the four address/command bits have been clocked into the input data register. Sampling starts on the fourth
falling edge of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth
falling edge of I/O CLOCK depending on the data-length selection.
After the 8-bit data stream has been clocked in, DATA IN should be held at a fixed digital level until EOC goes
high or INT goes low (indicating that the conversion is complete) to maximize the sampling accuracy and
minimize the influence of external digital noise.
26
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
conversion cycle
A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external
digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by
an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns)
to start the OSC. During the conversion period, the device performs a successive-approximation conversion
on the analog input voltage.
When programmed as EOC, pin 19 goes low at the start of the conversion cycle and goes high when the
conversion is complete and the output data register is latched. After EOC goes low, the analog input can be
changed without affecting the conversion result. Since the delay from the falling edge of the last I/O CLOCK to
the falling edge of EOC is fixed, any time-varying analog input signals can be digitized at a fixed rate without
introducing systematic harmonic distortion or noise due to timing uncertainty.
When programmed as INT, pin 19 goes low when the conversion is complete and the output data register is
latched. The next I/O CLOCK rising edge clears the INT output. The time from the last I/O CLOCK falling edge
to the falling INT edge is equivalent to the EOC delay mentioned above plus the maximum conversion time. INT
is cancelled by (or brought to high) by either the next CS falling edge or the next SCLK rising edge (when CS
is held low all of the time for multiple cycles). When CS is held low continuously (for multiple cycles) MSB output
occurs after the first rising edge of I/O CLOCK after EOC is inactive or the falling edge of INT.
power up and initialization
After power up, CS must be taken from high to low to begin an I/O cycle. INT/EOC pin is initially high, and both
configuration registers are set to all zeroes. The contents of the output data register are random, and the first
conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low
to begin the next I/O cycle. The first conversion after the device has returned from the power-down state may
not read accurately due to internal device settling.
Table 1. Operational Terminology
Current (N) I/O cycle
The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion from DATA OUT.
Current (N) conversion cycle
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the
last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the output register when conversion is complete.
Current (N) conversion result
The current conversion result is serially shifted out on the next I/O cycle.
Previous (N–1) conversion cycle
The conversion cycle just prior to the current I/O cycle
Next (N+1) I/O cycle
The I/O period that follows the current conversion cycle
Example:
In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the
next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this
corrupts the output data from the previous conversion. The current conversion is begun immediately after the
twelfth falling edge of the current I/O cycle.
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27
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
default mode
When the DATA IN pin is held high, the ADC goes into hardware default mode because the CFGR2 bits are all
programmed to the default values after 8 I/O CLOCKs. This means the ADC is programmed for an external
reference and pin 19 as EOC. In addition, channel AIN0 is selected. The first conversion is invalid therefore the
conversion result should be ignored. On the next cycle, AIN0 is sampled and converted. This mode of operation
is valid when CS is toggled or held low after the first cycle.
To remove the device from hardware default mode, CFGR2 bit D0 must be reset to 0. Once this is done, the
host must program CFGR1 on the next cycle and disregard the result from the current cycle’s conversion.
data input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the input data byte with the MSB
first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data
input-register format).
Table 2. Command Set (CMR) and Configuration
SDI D[7:4]
Binary,
HEX
COMMAND
0000b
0h
SELECT analog input channel 0
0001b
1h
SELECT analog input channel 1
0010b
2h
SELECT analog input channel 2
0011b
3h
SELECT analog input channel 3
0100b
4h
SELECT analog input channel 4
0101b
5h
SELECT analog input channel 5
0110b
6h
SELECT analog input channel 6
CFGR1
0111b
7h
SELECT analog input channel 7
1000b
8h
SELECT analog input channel 8
SDI
D[3:0]
1001b
9h
SELECT analog input channel 9
1010b
Ah
SELECT analog input channel 10
1011b
Bh
SELECT TEST,
D[3:2]
D1
Voltage = (VREF+ + VREF–)/2
D0
1100b
Ch
SELECT TEST, Voltage = REFM
1101b
Dh
SELECT TEST, Voltage = REFP
1110b
Eh
SW POWERDOWN (analog + reference)
1111b
Fh
ACCESS CFGR2
01: 8-bit output length
X0: 12-bit output length
11: 16-bit output length (default)
0: MSB out first (default)
1: LSB out first
0: Unipolar binary (default)
1: Bipolar 2s complement
CFGR2
SDI
D[3:0]
D[3:2]
D1
D0
28
CONFIGURATION
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CONFIGURATION
00:
01:
11:
0:
1:
0:
Internal 4.096 reference
Internal 2.048 reference
External reference (default)
Pin 19 output EOC (default)
Pin 19 output Int
Normal mode
(CFGR1 needs to be programmed)
1: Default mode enabled
(D[3:0] of CFGR1 and D[3:1] of
CFGR2 set to default)
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
data input—address/command bits
The four MSBs (D7–D4) of the input data register are the address or command. These bits can be used to
address one of the 11 input channels, select one of three reference-test voltages, activate the software
power-down mode, or access the second configuration register, CFGR2. All address/command bits affect the
current conversion, which is the conversion that immediately follows the current I/O cycle. They also allow
access to CFGR1 except for command 1111b, which allows access to CFGR2.
data output length
CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid
for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current
I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be
selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly
12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion
result are truncated and discarded. The current conversion is started immediately after the eighth falling edge
of the current I/O cycle.
Since the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there
can be a conflict with the previous cycle if the data-word length was changed. This may occur when the data
format is selected to be least significant bit first, since at the time the data length change becomes effective (six
rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation,
when different data lengths are required within an application and the data length is changed between two
conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first
format.
LSB out first
D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion
result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first
always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to
another, the current I/O cycle is never disrupted.
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29
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
bipolar output format
D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared
to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result
of an input voltage equal to or less than VREF– is a code with all zeros (000 . . . 0) and the conversion result of
an input voltage equal to or greater than VREF+ is a code of all ones (111 . . . 1). The conversion result of (VREF+
+ VREF–)/2 is a code of a one followed by zeros (100 ...0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to or less than VREF– is a code of a one followed by zeros (100 . . . 0), and the conversion
of an input voltage equal to or greater than VREF+ is a code of a zero followed by all ones
(011 . . . 1). The conversion result of (VREF+ + VREF–)/2 is a code of all zeros (000 . . . 0). The MSB is interpreted
as the sign bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other’s
complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
reference
The device has a built-in reference with a programmable level of 2.048 V or 4.096 V. If the internal reference
is used, REF+ is set to 2.048 V or 4.096 V and REF– is set to analog GND. An external reference can also be
used through two reference input pins, REF+ and REF–, if the reference source is programmed as external.
The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a
full-scale and zero-scale reading respectively. The values of REF+, REF–, and the analog input should not
exceed the positive supply or be lower than GND consistent with the specified absolute maximum ratings. The
digital output is at full scale when the input signal is equal to or higher than REF+ and at zero when the input
signal is equal to or lower than REF–.
30
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
Analog
Supply
VCC
Internal
Reference
S1
S2
S1, S2:
Closed = Internal Reference Used
Opened = External Reference Used
REF+
Sample
C1
0.1 µF
Decoupling Cap
C2
10 µF
Int Reference
Compensation Cap
C2 and Grounding REF– Are Required
When Either 4.096 V or 2.048 Internal
Reference Is Used
Convert
∼50 pF
CDAC
REF–
GND
Figure 54. Reference Block
INT/EOC output
Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning
and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after
the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the
converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O
CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes
low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the
falling edge of CS.
When programmed as INT, the output indicates that the conversion is completed and the output data is ready
to be read. In the reset state, INT is always high. INT is high during the sampling period and until the conversion
is complete. After the conversion is finished and the output data is latched, INT goes low and remains low until
it is cleared by the host. When CS is held low, the MSB (or LSB) of the conversion result is presented on DATA
OUT on the falling edge of INT. A rising I/O CLOCK edge clears the interrupt.
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31
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
chip-select input (CS)
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing
its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK
is inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next I/O cycle.
When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs
on DATA OUT on the rising edge of EOC or falling edge of INT. Note that the first cycle in the series still requires
a transition of CS from high to low. When a new conversion is started after the last falling edge of I/O CLOCK,
EOC goes low and the serial output is forced low until EOC goes high again.
When CS is toggled between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On
each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit
in the serial conversion result until the required number of bits has been output.
power-down features
When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles,
the software power-down mode is selected. Software power down is activated on the falling edge of the fourth
I/O CLOCK pulse.
During software power down, all internal circuitry is put in a low-current standby mode. The internal reference
(if being used) is powered down. No conversion is performed. The internal output buffer keeps the previous
conversion cycle data results provided that all digital inputs are held above VCC – 0.5 V or below 0.5 V. The I/O
logic remains active so the current I/O cycle must be completed even when the power-down mode is selected.
Upon power-on reset and before the first I/O cycle, the converter normally begins in the power-down mode. The
device remains in the software power-down mode until a valid input address (other than command 1110b) is
clocked in. Upon completion of that I/O cycle, a normal conversion is performed with the results being shifted
out during the next I/O cycle. If using the internal reference, care must be taken to allow the reference to power
on completely before a valid conversion can be performed. It requires 1 ms to resume from a software power
down.
The ADC also has an auto power-down mode. This is transparent to users. The ADC goes into auto power down
within 1 I/O CLOCK cycle after the conversion is complete and resumes, with a small delay after an active CS
is sent to the ADC. This mode keeps built-in reference so resumption is fast enough to be used between cycles.
analog MUX
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce
input-to-input noise rejection resulting from channel switching. Sampling of the analog inputs starts on the falling
edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the
falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
32
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0.050 (1,27)
0.016 (0,40)
0°–ā8°
A
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
PINS **
0.004 (0,10)
16
18
20
24
28
A MAX
0.410
(10,41)
0.462
(11,73)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.453
(11,51)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000 / E 08/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
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33
TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–ā8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
34
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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