TI TLV2553

TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
12-BIT, 200-KSPS, 11-CHANNEL, LOW-POWER, SERIAL ADC
FEATURES
D
D
D
D
D
D
D
D
D
D
D
D
12-Bit-Resolution A/D Converter
Up to 200 KSPS (150 KSPS for 3 V)
Throughput Over Operating Temperature
Range With 12-Bit Output Mode
11 Analog Input Channels
3 Built-In Self-Test Modes
Inherent Sample and Hold Function
Linearity Error . . . ± 1 LSB Max
On-Chip Conversion Clock
Unipolar or Bipolar Output Operation
Programmable MSB or LSB First
Programmable Power Down
Programmable Output Data Length
SPI Compatible Serial Interface With I/O Clock
Frequencies up to 15 MHz (CPOL=0, CPHA=0)
In addition to the high-speed converter and versatile
control capability, the device has an on-chip 14-channel
multiplexer that can select any one of 11 inputs or any
one of three internal self-test voltages using
configuration register 1. The sample-and-hold function
is automatic. At the end of conversion, when
programmed as EOC, the pin 19 output goes high to
indicate that conversion is complete. The converter
incorporated in the device features differential, highimpedance reference inputs that facilitate ratiometric
conversion, scaling, and isolation of analog circuitry
from logic and supply noise. A switched-capacitor
design allows low-error conversion over the full
operating temperature range.
The TLV2553I is characterized for operation from
TA = –40°C to 85°C. See available options table for
package options.
APPLICATIONS
D
D
D
D
Process Control
Portable Data Logging
Battery-Powered Instruments
Automotive
DESCRIPTION
The TLV2553 is a 12-bit, switched-capacitor,
successive-approximation, analog-to-digital converter.
The ADC has three control inputs [chip select (CS), the
input-output clock, and the address/control input
(DATAIN)], designed for communication with the serial
port of a host processor or peripheral through a serial
3-state output.
DW AND PW PACKAGE
(TOP VIEW)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
EOC
I/O CLOCK
DATA IN
DATA OUT
CS
REF +
REF –
AIN10
AIN9
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
TA
20-TSSOP (PW)
20-SOWB (DW)
TLV2553IPW
TLV2553IDW
– 40°C to 85°C
functional block diagram
VCC
20
REF +
14
REF –
13
3
AIN0 1
AIN1 2
AIN2 3
AIN3 4
AIN4 5
AIN5 6
AIN6 7
AIN7 8
AIN8 9
AIN9 11
AIN10 12
Self Test
14-Channel
Analog
Multiplexer
Low Power
12-Bit
SAR ADC
Sample
and Hold
4
Reference CTRL
Input Address
Register
19
12
Output Data
Register
12
12-to-1
Data
Selector
and Driver
DATA IN
CS
I/O CLOCK
17
15
18
Control Logic
and I/O
Counters
10
GND
2
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EOC
4
Internal OSC
16
DATA
OUT
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AIN0 – AIN10
1 – 9,
11, 12
I
Analog input. These 11 analog-signal inputs are internally multiplexed.
CS
15
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT,
DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and I/O CLOCK within a setup time.
DATA IN
17
I
Serial data input. The 4-bit serial data can be used as address selects the desired analog input channel or
test voltage to be converted next, or a command to activate other other features. The input data is presented
with the MSB (D7) first and is shifted in on the first four rising edges of the I/O CLOCK. After the four
address/command bits are read into the command register CMR, I/O CLOCK clocks the remaining four bits
of configuration in.
DATA OUT
16
O
The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS
is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state
and is driven to the logic level corresponding to the MSB(most significant bit)/LSB(least significant bit) value
of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level
corresponding to the next MSB/LSB, and the remaining bits are shifted out in order.
EOC
19
O
Status output, used to indicate the end of conversion (EOC) to the host processor.
EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until
the conversion is complete and the data is ready for transfer.
GND
10
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage
measurements are with respect to GND.
I/O CLOCK
18
I
Input /output clock. I/O CLOCK receives the serial input and performs the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK
with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of I/O CLOCK.
3. The remaining 11 bits of the previous conversion data are shifted out on DATA OUT. Data changes on the
falling edge of I/O CLOCK.
4. Control of the conversion is transferred to the internal state controller on the falling edge of the last
I/O CLOCK.
REF +
14
I/O
Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The
maximum analog input voltage range is determined by the difference between the voltage applied to terminals
REF+ and REF–.
REF –
13
I/O
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF–. This
pin is connected to analog ground (GND of the ADC) when internal reference is used.
VCC
20
Positive supply voltage
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3
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Positive reference voltage, Vref + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Negative reference voltage, Vref – . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Peak input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
Operating free-air temperature range, TA: I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminal with REF – and GND wired together (unless otherwise noted).
recommended operating conditions
PARAMETERS
MIN
Supply voltage, VCC
I/O CLOCK frequency
Tolerable clock jitter, I/O CLOCK
Aperature jitter
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
NOM
MAX
UNIT
V
2.7
5.5
16-bit I/O
0.01
15
12-bit I/O
0.01
15
8-bit I/O
0.01
15
0.01
10
0.38
100
(REF+) – (REF–)
VCC = 3.0 V to 3.6 V
VCC = 2.7 V to 3.0 V
0
(REF+ ) –(REF–)
0
(REF+) –(REF–)
High level control input voltage,
High-level
voltage VIH
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
2.0
Low level control input voltage
Low-level
voltage, VIL
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
Operating free-air temperature, TA
TLV2553I
V
V
2.1
0.8
0.6
–40
ns
ps
0
Analog input voltage (see Note 2)
MHz
85
V
°C
NOTE 2: Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
4
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
electrical characteristics over recommended operating free-air temperature range, VREF+ = 5 V,
I/O CLOCK frequency = 15 MHz when VCC = 5 V, VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz when
VCC = 2.7 V (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
High level output voltage
High-level
Low level output voltage
Low-level
MIN
TYP†
MAX
VCC = 4.5 V, IOH = –1.6 mA
VCC = 2.7 V, IOH = –0.2 mA
30 pF
2.4
VCC = 4.5 V, IOH = –20 µA
VCC = 2.7 V, IOH = –20 µA
30 pF
VCC –0.1
VCC = 5.5 V, IOL = 1.6 mA
VCC = 3.6 V, IOH = 0.8 mA
30 pF
0.4
VCC = 5.5 V, IOL = –20 µA
VCC = 3.6 V, IOH = –20 µA
30 pF
0.1
V
V
IOZ
High impedance off-state
High-impedance
off state output current
VO = VCC,
VO = 0 V,
CS at VCC
1
2.5
CS at VCC
–1
–2.5
ICC
Operating supply current
CS at 0 V,
V
Ext.
Ext Ref
ICC(PD)
Power-down current
For all digital inputs,
0 ≤ VI ≤ 0.5 V or
VI ≥ VCC – 0.5
0 5 V,
V
I/O CLOCK = 0 V
IIH
IIL
High-level input current
Ilkg
lk
Selected channel leakage current
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
tconvertt
Conversion time = 13.5X
13 5X [f(OSC)] + 25 ns
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
Internal oscillator frequency voltage
Ci
Input capacitance
0.9
Software power
down
0.1
Auto power down
Analog inputs
1
µA
mA
µA
µ
0.1
10
0.005
2.5
µA
–0.005
–2.5
µA
1
µA
Selected channel at 0 V, Unselected
channel at VCC
Internal oscillator frequency
Input impedance‡
1.2
Selected channel at VCC , Unselected
channel at 0 V
f(OSC)
Zi
VCC = 5 V
VCC = 2.7 V
VI = VCC
VI = 0 V
Low-level input current
UNIT
–1
3.27
MHz
2.56
4.15
5.54
3.6
4.1
VCC = 4.5 V
VCC = 2.7 V
500
600
Analog inputs
45
55
Control inputs
5
15
µs
V
Ω
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The switch resistance is very nonlinear and varies with input voltage and supply voltage. This is the worst case.
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5
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
external reference specifications
MIN
TYP†
MAX
voltage REF–
REF
Reference input voltage,
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
–0.1
0
0.1
–0.1
0
0.1
Reference input voltage,
voltage REF+
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
2
External reference input voltage
g difference,,
(REF+) – (REF–)
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
1.9
External reference supply current
CS at 0 V
PARAMETER
TEST CONDITIONS
2
1.9
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 5 V
Reference input impedance
7V
VCC = 2
2.7
During sampling/conversion
6
Static
1
During sampling/conversion
† All typical values are at TA = 25°C.
NOTE: Add a 0.1-µF capacitor between REF+ and REF– pins when external reference is used.
V
VCC
VCC
V
0.62
1
V
VCC
VCC
0.94
Static
UNIT
mA
MΩ
9
kΩ
MΩ
6
9
kΩ
operating characteristics over recommended operating free-air temperature range, VREF+ = 5 V,
I/O CLOCK frequency = 15 MHz when VCC = 5 V, VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz when
VCC = 2.7 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
INL
Integral linearity error (see Note 3)
–1
1
LSB
DNL
Differential linearity error
–1
1
LSB
EO
Offset error (see Note 4)
See Note 2
–2
2
mV
EG
Gain error (see Note 4)
See Note 2
–3
3
ET
Total unadjusted error (see Note 5)
±1.5
Address data input = 1011
Self-test output code (see Table 2 and Note 6)
mV
LSB
2048
Address data input = 1100
0
Address data input = 1101
4095
† All typical values are at TA = 25°C.
NOTES: 2. Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than
the voltage applied to REF– convert as all zeros (000000000000).
3. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
4. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified
gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the
nominal midstep value at the offset point.
5. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
6. Both the input address and the output codes are expressed in positive logic.
6
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
timing characteristics over recommended operating free-air temperature range, VREF+ = 5 V,
I/O CLOCK frequency = 15 MHz, VCC = 5 V, load = 25 pF (unless otherwise noted)
PARAMETER
MIN
tw1
tsu1
Pulse duration I/O CLOCK high or low
26.7
th1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 26)
tsu2
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 26)
TYP
MAX
UNIT
100000
ns
12
ns
0
ns
Setup time CS low before first rising I/O CLOCK edge
(see Note 7 and Figure 27)
25
ns
th2
th3
Hold time CS pulse duration high time (see Figure 27)
100
ns
Hold time CS low after last I/O CLOCK falling edge (see Figure 27)
0
ns
th4
th5
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 28)
2
ns
Hold time CS high after EOC rising edge when CS is toggled (see Figure 31)
0
ns
Load = 25 pF
28
ns
Load = 10 pF
20
ns
10
ns
td1
Delay
y time CS falling
g edge
g to DATA OUT valid
(MSB or LSB) (see Figure 25)
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 25)
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 28)
20
ns
td4
td5
Delay time Last I/O CLOCK falling edge to EOC falling edge
55
ns
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
1.5
µs
tt1
tt2
Transition time I/O CLOCK (see Note 7 and Figure 28)
1
µs
Transition time DATA OUT (see Figure 28)
5
ns
tt3
tt4
Transition time INT/EOC, CL at 7 pF (see Figure 30)
2.4
ns
Transition time DATA IN, CS
10
µs
tcycle
Total cycle time (sample, conversion and delays) (see Note 7)
MAX(tconvert) +
I/O period
(8/12/16 CLKs)
µs
tsample
l
Channel acquisition
q
time ((sample),
), at 1 kΩ
See Figures 33–38 and Note 7
2
Source impedance = 25 Ω
600
Source impedance = 100 Ω
650
Source impedance = 500 Ω
700
Source impedance = 1 kΩ
ns
1000
NOTE 7: I/O CLOCK period = 8X [1/(I/O CLOCK frequency)] or 12X [1/(I/O CLOCK frequency)] or 16X [1/(I/O CLOCK frequency)] depends on
I/O format selected.
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7
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
timing characteristics over recommended operating free-air temperature range, VREF+ = 2.5 V,
I/O CLOCK frequency = 10 MHz, VCC = 2.7 V, load = 25 pF (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
100000
ns
tw1
tsu1
Pulse duration I/O CLOCK high or low
40
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 26)
22
ns
th1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 26)
0
ns
tsu2
Setup time CS low before first rising I/O CLOCK edge
(see Note 7 and Figure 27)
33
ns
th2
th3
Hold time CS pulse duration high time (see Figure 27)
100
ns
Hold time CS low after last I/O CLOCK falling edge (see Figure 27)
0
ns
th4
th5
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 28)
2
ns
Hold time CS high after EOC rising edge when CS is toggled (see Figure 31)
0
ns
Load = 25 pF
30
ns
Load = 10 pF
22
ns
10
ns
td1
Delay
y time CS falling
g edge
g to DATA OUT valid
(MSB or LSB) (see Figure 25)
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 25)
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 28)
33
ns
td4
td5
Delay time Last I/O CLOCK falling edge to EOC falling edge
75
ns
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
1.5
µs
tt1
tt2
Transition time I/O CLOCK (see Note 7 and Figure 28)
1
µs
Transition time DATA OUT (see Figure 28)
5
ns
tt3
tt4
Transition time INT/EOC, CL at 7 pF (see Figure 30)
4
ns
Transition time DATA IN, CS
10
µs
tcycle
Total cycle time (sample, conversion and delays) (see Note 7)
MAX(tconvert) +
I/O period
(8/12/16 CLKs)
µs
tsample
l
Channel acquisition
q
time ((sample),
), at 1 kΩ
See Figures 33–38 and Note 7
2
Source impedance = 25 Ω
800
Source impedance = 100 Ω
850
Source impedance = 500 Ω
1000
Source impedance = 1 kΩ
1600
ns
NOTE 7: I/O CLOCK period = 8X [1/(I/O CLOCK frequency)] or 12X [1/(I/O CLOCK frequency)] or 16X [1/(I/O CLOCK frequency)] depends on
I/O format selected.
8
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
I CC – Supply Current – mA
0.620
0.615
0.43
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
0.42
External Reference Current – mA
0.625
EXTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
0.610
0.605
0.600
0.595
0.590
0.585
0.58
–40
0.41
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
0.40
0.39
0.38
0.37
0.36
0.35
0.34
–25
–10
5
20
35
50
65
0.33
–40
80
–25
–10
Figure 1
0.40
35
50
65
80
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
0.06
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
0.05
0.30
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
0.04
Current – µ A
Current – µ A
0.35
20
Figure 2
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
0.45
5
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
0.25
0.20
0.15
0.03
0.02
0.10
0.01
0.05
0.0
–40
–25
–10
5
20
35
50
65
0
–40
80
TA – Free-Air Temperature – °C
–25
–10
5
20
35
50
65
80
TA – Free-Air Temperature – °C
Figure 3
Figure 4
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9
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.9
0.8
–0.0
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–40
–25
–10
5
20
–0.1
Minimum Differential Nonlinearity – LSB
Maximum Differential Nonlinearity – LSB
1.0
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
35
50
65
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–40
80
–25
TA – Free-Air Temperature – °C
–10
Figure 5
–0.1
Minimum Integral Nonlinearity – LSB
Maximum Integral Nonlinearity – LSB
50
65
80
–0.0
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
0.6
0.5
0.4
0.3
0.2
0.1
–25
–10
5
20
35
50
65
80
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–40
TA – Free-Air Temperature – °C
–25
–10
5
20
35
50
65
TA – Free-Air Temperature – °C
Figure 7
10
35
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.8
0.0
–40
20
Figure 6
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.7
5
TA – Free-Air Temperature – °C
Figure 8
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
DNL – Differential Nonlinearity – LSB
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.5
VCC = 2.7 V, VREF+ = 2.5 V, VREF– = 0 V, I/O CLOCK = 10 MHz, TA = 25°C
0.4
0.3
0.2
0.1
–0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
1024
2048
3072
4096
Digital Output Code
Figure 9
INL – Integral Nonlinearity – LSB
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.8
VCC = 2.7 V, VREF+ = 2.5 V, VREF– = 0 V, I/O CLOCK = 10 MHz, TA = 25°C
0.6
0.4
0.2
–0.0
–0.2
–0.4
–0.6
–0.8
0
1024
2048
3072
4096
Digital Output Code
Figure 10
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11
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
GAIN ERROR
vs
FREE-AIR TEMPERATURE
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
1.4
0.6
1.2
EG – Gain Error – mV
EO – Offset Error – mV
0.5
0.4
0.3
0.2
1.0
0.8
0.6
0.4
0.1
0.0
–40
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
–25
–10
5
20
0.2
35
50
65
0.0
–40
80
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
–25
–10
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
65
80
0.7
External Reference Current – mA
I CC – Supply Current – mA
50
0.8
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
0.94
0.92
0.90
0.88
0.86
0.6
0.5
0.4
0.3
0.2
0.1
–25
–10
5
20
35
50
65
0
–40
80
TA – Free-Air Temperature – °C
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
–25
–10
5
20
35
50
65
TA – Free-Air Temperature – °C
Figure 13
12
35
EXTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
0.98
0.84
–40
20
Figure 12
Figure 11
0.96
5
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 14
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
0.14
0.45
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
0.40
0.35
0.12
Current – µ A
Current – µ A
0.10
0.30
0.25
0.20
0.08
0.06
0.15
0.04
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
0.10
0.02
0.05
0.0
–40
–25
–10
5
20
35
50
65
0
–40
80
–25
TA – Free-Air Temperature – °C
–10
Figure 15
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
Minimum Differential Nonlinearity – LSB
Maximum Differential Nonlinearity – LSB
50
65
80
–0.00
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–40
35
MINIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1.0
0.8
20
Figure 16
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.9
5
TA – Free-Air Temperature – °C
–25
–10
5
20
35
50
65
80
–0.05
–0.10
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
–40
TA – Free-Air Temperature – °C
–25
–10
5
20
35
50
65
80
TA – Free-Air Temperature – °C
Figure 17
Figure 18
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13
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
MAXIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
MINIMUM INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
0.90
–0.329
0.86
Minimum Integral Nonlinearity – LSB
Maximum Integral Nonlinearity – LSB
–0.330
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
0.88
0.84
0.82
0.80
0.78
0.76
0.74
–40
–25
–10
5
20
35
50
65
–0.331
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
–0.332
–0.333
–0.334
–0.335
–0.336
–0.337
–0.338
–40
80
–25
TA – Free-Air Temperature – °C
–10
5
20
35
Figure 19
Figure 20
DNL – Differential Nonlinearity – LSB
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.3
VCC = 5.5 V, VREF+ = 4.096 V, VREF– = 0 V, I/O CLOCK = 15 MHz, TA = 25°C
0.2
0.1
–0.0
–0.1
–0.2
–0.3
0
1024
2048
Digital Output Code
Figure 21
14
50
TA – Free-Air Temperature – °C
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3072
4096
65
80
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
TYPICAL CHARACTERISTICS
INL – Integral Nonlinearity – LSB
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.8
0.6
0.4
0.2
–0.0
–0.2
–0.4
–0.6
VCC = 5.5 V, VREF+ = 4.096 V, VREF– = 0 V, I/O CLOCK = 15 MHz, TA = 25°C
–0.8
0
1024
2048
3072
4096
Digital Output Code
Figure 22
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
–0.0
–0.00
EO – Offset Error – mV
–0.10
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
–0.1
–0.2
EG – Gain Error – mV
–0.05
–0.15
–0.20
–0.25
–0.30
–0.35
–0.3
–0.4
–0.5
–0.6
–0.7
–0.40
–0.8
–0.45
–0.9
–0.5
–40
–25
–10
5
20
35
50
65
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
–1
–40
80
TA – Free-Air Temperature – °C
–25
–10
5
20
35
50
65
80
TA – Free-Air Temperature – °C
Figure 23
Figure 24
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15
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
Data Valid
VIH
VIL
CS
td1
VIH
VIL
DATA IN
th1
td2
VOH
VOL
Data Out
I/O
CLOCK
Figure 25. DATA OUT to Hi-Z Voltage Waveforms
th2
VIH
VIL
Figure 26. DATA IN and I/O CLOCK Voltage
tt1
tt1
VIH
VIL
CS
tsu1
VIH
VIL
I/O
CLOCK
I/O CLK Period
th3
tsu2
I/O
CLOCK
td3
VIH
VIL
Last
Clock
th4
VOH
VOL
Data Out
tt2
Figure 27. CS and I/O CLOCK Voltage
Waveforms
I/O
CLOCK
Figure 28. I/O CLOCK and DATA OUT Voltage
Waveforms
tt3
VIH
VIL
Last
Clock
tconvert
VOH
td2
EOC
VOL
tt3
VOH
VOL
EOC
tt3
Data Out
MSB
Valid
Figure 30. EOC and DATA OUT Voltage
Waveforms
Figure 29. I/O CLOCK and EOC Voltage
Waveforms
1
CS
th5
EOC
VIH
VIL
I/O
CLOCK
VOH
VOL
EOC
VIH
VIL
VOH
VOL
Figure 32. I/O CLOCK and DATA OUT Voltage
Figure 31. CS and EOC Waveforms
16
VOH
VOL
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
timing diagrams
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
3
2
Sample Cycle
4
I/O
CLOCK
5
6
7
8
9
10
11
12
Previous Conversion Data
DATA
OUT
MSB
ÎÎÎ
DATA
IN
D7
D6
Output Data
Format
D5
D4
D3
D2
D1
LSB
MSB
MSB–1 MSB–2
ÎÎÎÎÎÎÎÎÎÎÎÎ
D0
3
2
Hi–Z State
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9 LSB+1
Channel
Address
1
D7
D6
D5
A/D Conversion Interval
tCONV
EOC
Initialize
Initialize
Figure 33. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
3
2
Sample Cycle
4
5
6
7
8
9
10
11
12
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9 LSB+1
LSB
1
I/O
CLOCK
2
3
Previous Conversion Data
DATA
OUT
DATA IN
ÎÎÎ
ÎÎÎ
MSB
Channel
Address
D7
D6
D5
Output Data
Format
D4
D3
D2
D1
D0
Low Level
MSB
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
D7
MSB–1 MSB–2
D6
D5
A/D Conversion Interval
tCONV
EOC
Initialize
Initialize
Figure 34. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
2
3
Sample Cycle
4
5
7
6
8
1
2
3
4
5
6
7
I/O
CLOCK
Previous Conversion Data
Hi–Z State
DATA
OUT
MSB
Channel
Address
ÎÎÎÎ
D7
DATA IN
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
D6
D5
LSB+1
LSB
Output Data
Format
D4
D3
D2
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6
MSB
ÎÎÎÎÎÎÎÎÎ
D1
D0
D7
D6
D4
D5
D3
D2
D1
A/D Conversion Interval
tCONV
EOC
Initialize
Initialize
Figure 35. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
1
Access
Cycle
3
2
I/O
CLOCK
Sample Cycle
4
5
7
6
8
1
2
3
4
5
6
7
Previous Conversion Data
DATA
OUT
MSB
ÎÎÎÎ
D7
DATA IN
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
Channel
Address
D6
D5
LSB+1
LSB
Output Data
Format
D4
D3
D2
D1
D0
A/D Conversion Interval
Low Level
MSB
ÎÎÎÎÎÎÎÎ
D7
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6
D6
D5
D4
D3
D2
D1
tCONV
EOC
Initialize
Initialize
Figure 36. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
18
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
1
Sample Cycle
3
2
4
I/O
CLOCK
5
6
7
8
9
10
11
12
Pad
Zeros
Previous Conversion Data
DATA
OUT
MSB
ÎÎÎÎ
DATA IN
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9
Channel
Address
D7
D6
Output Data
Format
D5
D4
D3
D2
D1
D0
16
LSB+1
1
Hi–Z State
LSB
MSB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
D7
A/D Conversion Interval
tCONV
EOC
Initialize
Initialize
Figure 37. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before responding to
control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
1
2
3
Sample Cycle
4
I/O
CLOCK
5
6
7
8
9
10
11
12
MSB
ÎÎÎÎ
ÎÎÎÎ
DATA IN
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6 MSB–7 MSB–8 MSB–9
Channel
Address
D7
D6
D5
Output Data
Format
D4
D3
D2
D1
D0
1
Pad
Zeros
Previous Conversion Data
DATA
OUT
16
LSB+1
LSB
Low Level
MSB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
D7
A/D Conversion Interval
tCONV
EOC
Initialize
Initialize
Figure 38. Timing for 16-Clock Transfer Not Using CS With DATA OUT Set for MSB First
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
detailed description
Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA IN and
removes DATA OUT from the high-impedance state. The input data is an 8–bit data stream consisting of a 4-bit
address or command (D7–D4) and a 4-bit configuration data (D3–D0). Configuration register 1, CFGR1, which
controls output data format configuration, consists of a 2-bit data length select (D3–D2), an output MSB or LSB
first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to any command (from DATA IN)
except for command 1111b. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data
to the input data register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion
result from the output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock
cycles long depending on the data-length selection in the input data register. Sampling of the analog input
begins on the fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the
I/O CLOCK sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the
conversion.
converter operation
The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle, 2)
the sampling cycle and 3) the conversion cycle. The first two are partially overlapped.
data I/O cycle
The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,
depending on the selected output data length. During the I/O cycle, the following two operations take place
simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided
to DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. DATA
INPUT is ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length
of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on
the rising edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling
edge of CS. This data is the result of the previous conversion period, and after the first output data bit, each
succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK.
sampling cycle
During the sampling cycle, one of the analog inputs is internally connected to the capacitor array of the converter
to store the analog input signal. The converter starts sampling the selected input immediately after the four
address/command bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge
of the I/O CLOCK depending on the data-length selection.
After the 8-bit data stream has been clocked in, DATA IN should be held at a fixed digital level until EOC goes
high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the influence
of external digital noise.
20
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
conversion cycle
A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external
digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by
an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns)
to start the OSC. During the conversion period, the device performs a successive-approximation conversion
on the analog input voltage.
EOC goes low at the start of the conversion cycle and goes high when the conversion is complete and the output
data register is latched. After EOC goes low, the analog input can be changed without affecting the conversion
result. Since the delay from the falling edge of the last I/O CLOCK to the falling edge of EOC is fixed, any
time-varying analog input signals can be digitized at a fixed rate without introducing systematic harmonic
distortion or noise due to timing uncertainty.
power up and initialization
After power up, CS must be taken from high to low to begin an I/O cycle. The EOC pin is initially high, and the
configuration register is set to all zeroes. The contents of the output data register are random, and the first
conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low
to begin the next I/O cycle. The first conversion after the device has returned from the power-down state may
not read accurately due to internal device settling.
Table 1. Operational Terminology
Current (N) I/O cycle
The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion from DATA OUT
Current (N) conversion cycle
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the
last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the output register when conversion is complete.
Current (N) conversion result
The current conversion result is serially shifted out on the next I/O cycle.
Previous (N–1) conversion cycle
The conversion cycle just prior to the current I/O cycle
Next (N+1) I/O cycle
The I/O period that follows the current conversion cycle
Example:
In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the
next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this
corrupts the output data from the previous conversion. The current conversion is begun immediately after the
twelfth falling edge of the current I/O cycle.
data input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the input data byte with the MSB
first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data
input-register format).
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
Table 2. Command Set (CMR) and Configuration
SDI D[7:4]
Binary,
HEX
COMMAND
0000b
0h
SELECT analog input channel 0
0001b
1h
SELECT analog input channel 1
CFGR1
0010b
2h
SELECT analog input channel 2
0011b
3h
SELECT analog input channel 3
SDI
D[3:0]
0100b
4h
SELECT analog input channel 4
D[3:2]
0101b
5h
SELECT analog input channel 5
0110b
6h
SELECT analog input channel 6
D1
0111b
7h
SELECT analog input channel 7
D0
1000b
8h
SELECT analog input channel 8
1001b
9h
SELECT analog input channel 9
1010b
Ah
SELECT analog input channel 10
1011b
Bh
SELECT TEST,
1100b
Ch
SELECT TEST, Voltage = REFM
1101b
Dh
SELECT TEST, Voltage = REFP
1110b
Eh
SW POWERDOWN (analog + reference)
1111b
Fh
Reserved
CONFIGURATION
01: 8-bit output length
X0: 12-bit output length (see Note)
11: 16-bit output length
0: MSB out first
1: LSB out first
0: Unipolar binary
1: Bipolar 2s complement
NOTE: Select 12-bit output mode to achieve 200 KSPS
sampling rate.
Voltage = (VREF+ + VREF–)/2
data input—address/command bits
The four MSBs (D7–D4) of the input data register are the address or command. These can be used to address
one of the 11 input channels, address one of three reference-test voltages, or activate software power-down
mode. All address/command bits affect the current conversion, which is the conversion that immediately follows
the current I/O cycle. They also have access to CFGR1 except for command 1111b, which is reserved.
data output length
CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid
for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current
I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be
selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly
12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
22
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
data output length (continued)
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion
result are truncated and discarded. The current conversion is started immediately after the eighth falling edge
of the current I/O cycle.
Since the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there
can be a conflict with the previous cycle if the data-word length was changed. This may occur when the data
format is selected to be least significant bit first, since at the time the data length change becomes effective (six
rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation,
when different data lengths are required within an application and the data length is changed between two
conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first
format.
LSB out first
D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion
result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first
always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to
another, the current I/O cycle is never disrupted.
bipolar output format
D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared
to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result
of an input voltage equal to or less than VREF– is a code with all zeros (000 . . . 0) and the conversion result of
an input voltage equal to or greater than VREF+ is a code of all ones (111 . . . 1). The conversion result of (VREF+
+ VREF–)/2 is a code of a one followed by zeros (100 ...0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to or less than VREF– is a code of a one followed by zeros (100 . . . 0), and the conversion
of an input voltage equal to or greater than VREF+ is a code of a zero followed by all ones
(011 . . . 1). The conversion result of (VREF+ + VREF–)/2 is a code of all zeros (000 . . . 0). The MSB is interpreted
as the sign bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other’s
complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
reference
An external reference can be used through two reference input pins, REF+ and REF–. The voltage levels
applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and
zero-scale reading respectively. The values of REF+, REF–, and the analog input should not exceed the positive
supply or be lower than GND consistent with the specified absolute maximum ratings. The digital output is at
full scale when the input signal is equal to or higher than REF+ and at zero when the input signal is equal to or
lower than REF–.
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23
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
Analog
Supply
VCC
REF+
Sample
C1
0.1 µF
Decoupling Cap
Convert
∼50 pF
CDAC
REF–
GND
Figure 39. Reference Block
EOC output
Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning
and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after
the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the
converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O
CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes
low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the
falling edge of CS.
chip-select input (CS)
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing
its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK
is inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
24
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
PRINCIPLES OF OPERATION
chip-select input (CS) (continued)
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next I/O cycle.
When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs
on DATA OUT on the rising edge of EOC. Note that the first cycle in the series still requires a transition CS from
high to low. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes low and the
serial output is forced low until EOC goes high again.
When CS is toggled between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On
each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit
in the serial conversion result until the required number of bits has been output.
power-down features
When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles,
the software power-down mode is selected. Software power down is activated on the falling edge of the fourth
I/O CLOCK pulse.
During software power-down, all internal circuitry is put in a low-current standby mode. No conversions is
performed. The internal output buffer keeps the previous conversion cycle data results, provided that all digital
inputs are held above VCC – 0.5 V or below 0.5 V. The I/O logic remains active so the current I/O cycle must be
completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle,
the converter normally begins in the power-down mode. The device remains in the software power-down mode
until a valid input address (other than command 1110b or 1111b) is clocked in. Upon completion of that I/O cycle,
a normal conversion is performed with the results being shifted out during the next I/O cycle.
The ADC also has an auto power-down mode. This is transparent to users. The ADC gets into auto power-down
within 1 I/O CLOCK cycle after the conversion is complete and resumes, with a small delay, after an active CS
is sent to the ADC. The resumption is fast enough to be used between cycles
analog MUX
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce
input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on the falling
edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the
falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
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25
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0.050 (1,27)
0.016 (0,40)
0°– 8°
A
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
PINS **
0.004 (0,10)
16
18
20
24
28
A MAX
0.410
(10,41)
0.462
(11,73)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.453
(11,51)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000 / E 08/01
NOTES: A.
B.
C.
D.
26
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
www.ti.com
27
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