晶揚科技股份有限公司 Taiwan Micropaq Corporation 承 認 書 SPECIFICATION FOR APPROVAL TM50S116T-7G 新竹縣新竹工業區文化路 4 號 No.4 Wenhua Rd. HsinChu Industrial Park HuKou , Taiwan, R.O.C. TEL：886-3-597-9402 ˙ FAX：886-3-597-0775 http://www.tmc.com.tw TMC SDRAM TM50S116T-7G Description The TM50S116T is organized as 2-bank x 524288-word x 16-bit(1Mx16), fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Features Package 400-mil 50-pin TSOP(II) JEDEC PC133/PC100 compatible Single 3.3V Power Supply LVTTL Signal Compatible Byte control(DQML and DQMU) Auto and Self Refresh 64ms refresh period (4K cycles) 11-Row x 8-Column organization 2-Bank operation controlled by BA0 Pin33 and 37 are “No Connected” Fully synchronous operation referenced to clock rising edge Programmable - CAS Latency (3 or 2 clocks) - Burst Length (1,2,4,8 & full page) - Burst type (Sequential & Interleave) Burst read/write and burst read/single write operations capability Frequency vs. AC Parameter Symbol Parameter - 6G - 7G - 75G Unit 6 7 7.5 ns tCK Min. clock cycle time @CL=3 fCK Max. operating frequency @CL=3 166 143 133 Mhz tAC Max. access time from clock @CL=3 5.0 5.4 5.4 ns trcd Min. row to column delay 18 18 20 ns For reference only. 2 TMC Rev:1.0 TMC TM50S116T-7G SDRAM Pin Description Pin Name CLK CKE /CS /RAS /CAS /WE DQ0~DQ15 For reference only. Function Master Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O 3 Pin Name DQML/DQMU A0-10 BA0 Function Output Disable(Write Mask) Address Input Bank Address Vdd VddQ Vss/VssQ NC Power Supply Power Supply for Output Ground No Connection TMC Rev:1.0 TMC TM50S116T-7G SDRAM Pin Function Pin Name System clock Pin Function CLK Active on the positive going edge to sample all inputs. /CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK,CKE and DQML/DQMU. CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0~A10 Address input Row/column addresses are multiplexed on the same pins. Row address:A0~A10, Column address:A0~A7 BA0 Bank address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with /RAS low. Enables rows access & pre-charge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. /WE Write enable Enables write operation and row pre-charge. Latches data in starting from /CAS,/WE active. DQMU/DQM Data I/O mask Makes data output Hi-Z, tSHZ after the clock and L masks the output. Blocks data input when (Byte controll) DQML/DQMU active. DQ0~15 Data input/output Data inputs/outputs are multiplexed on the same pins. Vdd/Vss Power supply/ground Power and ground for the input buffers and the core logic. VddQ/VssQ Data output power / Isolated power supply and ground for the output ground buffers to provide improved noise immunity. NC/RFU No connection / This pin is recommended to be left no connection reserved for future use on the device. For reference only. 4 TMC Rev:1.0 TMC TM50S116T-7G SDRAM Absolute maximum ratings Parameter Voltage on any pin relative to Vss Voltage supply relative to Vss(VssQ) Operating temperature Power dissipation Output Shorted current Symbol VIN, VOUT Vdd,VddQ Topr PD IOS Ratings -0.5 to 4.6 -0.5 to 4.6 0 to +70 1 50 Unit V V ℃ W mA DC OPERATING CONDITIONS Recommended operating conditions(Referenced to Vss=0V,TA=0℃ to 70℃) Parameter Power Supply Voltage Input Logic High Voltage Input Logic Low Voltage Output Logic High Voltage Output Logic Low Voltage Input/Output Leakage Current Symbol Min. Typ. Max. Unit Vdd, VddQ VIH VIL VOH VOL IIL, IOL 3.0 2.0 -0.3 2.4 -5 3.3 - 3.6 Vdd +0.3 0.8 0.4 5 V V V V V μA DC Characteristics (Recommended operating condition TA = 0℃ to 70℃, unless otherwise noted.) Parameter Operating Current (One bank active) Pre-charge Standby Current in Power Down Mode Pre-charge Standby Current in Non-Power Down Mode Symbol Limits -6G -7G -75G 95 85 85 Unit 2 mA ICC2P Burst length=1, CL=3, tRC = tRC(min), tCK = tCK(min) CKE=VIL(max), tCK = 15ns ICC2PS CKE & CLK=VIL(max) 2 ICC2N CKE>=VIH(min),/CS> = VIH (min) , tCK = 15ns CKE>=VIH(min),/CS> = VIH (min), CLK<= VIL(max) , CKE<=VIL(max), tCK =10ns 20 CKE & CLK<=VIL(max) 5 ICC1 ICC2NS Active Standby Current I P CC3 in Power Down Mode ICC3PS Active Standby Current ICC3N in Non-Power Down Mode ICC3NS Operating Current (Burst ICC4 mode) Auto Refresh Current ICC5 Self Refresh Current ICC6 For reference only. Test Conditions mA mA 20 7 mA /CS=CKE=VIH(min), 35 tCK =15ns /CS=CKE=VIH(min), 35 CLK= VIL(max ) BL=4,CL=3,All Banks Active 130 100 100 mA CBR Command cycling mA CKE<= 0.2V 5 150 130 130 2 TMC mA mA mA Rev:1.0 TMC TM50S116T-7G SDRAM AC Characteristics Recommended operating conditions(Vdd=VddQ=3.3V,Vss=0V,TA= 0 to 70℃) Parameter Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 tCK fCK tAC tCH tCL tIS tIH tT tRCD tRC tRAS tRP tRRD tREF -6G Min 6.0 Clock Cycle Time,CL=3 Clock Frequency,CL=3 Clock Access Time,CL=3 Clock High Pulse Width Clock Low Pulse Width Input Setup time(all inputs) Input Hold time(all inputs) Transition time of clock /RAS to /CAS delay Row Cycle time Row active time Pre-charge time Row active to active delay Refresh time For reference only. -7G Max Min 7.0 166 5.0 2.5 2.5 1.5 0.8 1.0 18 60 42 15 12 64 6 10 -75G Max Min 7.5 143 5.4 2.5 2.5 1.5 0.8 1.0 18 63 42 18 14 64 10 Unit Max 133 5.4 2.5 2.5 1.5 0.8 1.0 20 67 45 20 15 64 TMC 10 Rev:1.0 ns Mhz ns ns ns ns ns ns ns ns ns ns ns ms TMC For reference only. TM50S116T 7 SDRAM TMC Rev:1.0