TI TMS320C44

TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
D
D
D
D
D
D
D
D
D
D
D
D
D
Highest Performance Floating-Point Digital
Signal Processor (DSP)
– TMS320C44-60:
33-ns Instruction Cycle Time,
330 MOPS, 60 MFLOPS,
30 MIPS, 336M Bytes / s
– TMS320C44-50:
40-ns Instruction Cycle Time
Four Communication Ports
Six-Channel Direct Memory Address (DMA)
Coprocessor
Single-Cycle Conversion to and From
IEEE-754 Floating-Point Format
Single Cycle, 1/x, 1 / √x
Source-Code Compatible With ’320C3x and
’320C4x
Single-Cycle 40-Bit Floating-Point,
32-Bit Integer Multipliers
Twelve 40-Bit Registers, Eight Auxiliary
Registers, 14 Control Registers,
and Two Timers
IEEE-1149.1† (JTAG) Boundary-Scan
Compatible
Two Identical External Data and Address
Buses Supporting Shared Memory
Systems and High Data-Rate,
Single-Cycle Transfers
– High Port-Data Rate of 120M Bytes / s
(TMS320C44-60) (Each Bus)
– 128M-Byte Program / Data / Peripheral
Address Space
– Memory-Access Request for Fast,
Intelligent Bus Arbitration
– Separate Address-Bus, Data-Bus, and
Control-Enable Pins
– Four Sets of Memory-Control Signals
Support Different Speed Memories in
Hardware
304-Pin Plastic Quad Flatpack
(PDB Suffix)
Fabricated Using 0.72-µm Enhanced
Performance Implanted CMOS (EPIC)
Technology by Texas Instruments (TI)
Separate Internal Program-, Data-, and
DMA-Coprocessor Buses for Support of
Massive Concurrent I / O of Program and
Data, Thereby Maximizing Sustained CPU
Performance
PDB PACKAGE
( TOP VIEW )‡
304
229
1
228
76
153
77
152
‡ See Pin Assignments table and Pin Functions table for location
and description of all pins.
D
D
D
D
D
IDLE2 Clock-Stop Power-Down Mode
Communication-Port-Direction Pin
On-Chip Program Cache and
Dual-Access/ Single-Cycle RAM for
Increased Memory-Access Performance
– 512-Byte Instruction Cache
– 8K Bytes of Single-Cycle Dual-Access
Program or Data RAM
– ROM-Based Boot Loader Supports
Program Bootup Using 8-, 16-, or 32-Bit
Memories or One of the Communication
Ports
Software-Communication-Port Reset
NMI With Bus-Grant Feature
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture
EPIC and TI are trademarks of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
block diagram
Cache
(512 bytes)
32
RAM Block 0
(4K bytes)
32
32
RAM Block 1
(4K bytes)
32
32
ROM Block
(reserved)
32
32
32
Continued on next page
PDATA Bus
D31 – D0
A23 – A0
DE
AE
STAT3 – STAT0
LOCK
STRB0, STRB1
R / W0, R / W1
PAGE0, PAGE1
RDY0, RDY1
CE0, CE1
PADDR Bus
MUX
DDATA Bus
DADDR 1 Bus
DADDR 2 Bus
DMADATA Bus
DMAADDR Bus
32
32
32
32
32
IR
PC
MUX
X1
X2 / CLKIN
CPU1
ROMEN
CPU2
RESET
REG 1
REG1
IACK
H1
Controller
REG2
REG2
IIOF(3 – 0)
R
E
G
1
REG1
NMI
CPU1
RESETLOC0,
RESETLOC1
40
40
40
Multiplier
H3
ALU
CVSS
40
40
DVDD
DVSS
40
Extended
Precision
Registers
( R0 – R11)
40
32
IVSS
DVDD
DVDD
40
40
DISP, IR0, IR1
VDDL
VSSL
ARAU0
ARAU1
BK
VSUBS
32
32
32
32
32
Auxiliary
Registers
(AR0 – AR7)
32
32
2
40
32-Bit Barrel
Shifter
POST OFFICE BOX 1443
Other
Registers
(14)
• HOUSTON, TEXAS 77251–1443
32
32
32
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
PDATA Bus
PADDR Bus
DDATA Bus
MUX
Continued from previous page
block diagram (continued)
DADDR 1 Bus
DADDR 2 Bus
DMADATA Bus
LD31 – LD0
LA23 – LA0
LDE
LAE
LSTAT3 – LSTAT0
LLOCK
LSTRB0, LSTRB1
LR / W0, LR / W1
LPAGE0, LPAGE1
LRDY0, LRDY1
LCE0, LCE1
DMAADDR Bus
MUX
32
COM Port 1
Input
FIFO
PAU
Output
FIFO
Port-Control Registers
DMA Coprocessor
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel 4
DMA Channel 5
CREQ1
CACK1
CSTRB1
CRDY1
C1D7 – C1D0
CDIR1
COM Port 2
Four
Communication
Ports†
Peripheral Data Bus
COM Port 4
Six DMA Channels
Peripheral Address Bus
32
COM Port 5
Input
FIFO
PAU
Output
FIFO
Port-Control Registers
CREQ5
CACK5
CSTRB5
CRDY5
C5D7 – C5D0
CDIR5
Timer 0
Global-Control Register
Time-Period Register
Timer-Counter Register
TCLK0
Timer 1
Global-Control Register
Time-Period Register
Timer-Counter Register
TCLK1
Port Control
Global
Local
† Communication ports 0 and 3 are not connected.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
3
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
functions
This section lists signal descriptions for the ’320C44 device: each signal, number of pins, operating mode(s)
(that is, input, output, or high-impedance state as indicated by I, O, or Z, respectively ), and function. The signals
are grouped according to function.
Pin Functions
NO. OF
PINS
TYPE†
D31 – D0
32
I/O/Z
DE
1
I
A23 – A0
24
O/Z
AE
1
I
Address-bus-enable signal for the global-bus external interface
STAT3 – STAT0
4
O
Status signals for the global-bus external interface
LOCK
1
O
Lock signal for the global-bus external interface
STRB0‡
R / W0‡
1
O/Z
Access strobe 0 for the global-bus external interface
1
O/Z
Read / write signal for STRB0 accesses
PAGE0‡
RDY0‡
1
O/Z
Page signal for STRB0 accesses
1
I
Ready signal for STRB0 accesses
CE0‡
1
I
Control enable for the STRB0, PAGE0, and R / W0 signals
STRB1‡
R / W1‡
1
O/Z
Access strobe 1 for the global-bus external interface
1
O/Z
Read / write signal for STRB1 accesses
PAGE1‡
RDY1‡
1
O/Z
Page signal for STRB1 accesses
1
I
Ready signal for STRB1 accesses
CE1‡
1
I
SIGNAL NAME
DESCRIPTION
GLOBAL-BUS EXTERNAL INTERFACE (73 pins)
32-bit data port of the global-bus external interface
Data-bus-enable signal for the global-bus external interface
24-bit address port of the global-bus external interface
Control enable for the STRB1, PAGE1, and R / W1 signals
LOCAL-BUS EXTERNAL INTERFACE (73 pins)
LD31 – LD0
32
I/O/Z
32-bit data port of the local-bus external interface
LDE
1
I
LA23 – LA0
24
O/Z
Data-bus-enable signal for the local-bus external interface
LAE
1
I
Address-bus-enable signal for the local-bus external interface
LSTAT3 – LSTAT0
4
O
Status signals for the local-bus external interface
LLOCK
1
O
Lock signal for the local-bus external interface
LSTRB0‡
1
O/Z
Access strobe 0 for the local-bus external interface
LR / W0
1
O/Z
Read / write signal for LSTRB0 accesses
LPAGE0
1
O/Z
Page signal for LSTRB0 accesses
LRDY0
1
I
Ready signal for LSTRB0 accesses
LCE0
1
I
Control enable for the LSTRB0, LPAGE0, and LR / W0 signals
LSTRB1‡
1
O/Z
Access strobe 1 for the local-bus external interface
LR / W1
1
O/Z
Read / write signal for LSTRB1 accesses
LPAGE1
1
O/Z
Page signal for LSTRB1 accesses
LRDY1
1
I
Ready signal for LSTRB1 accesses
24-bit address port of the local-bus external interface
LCE1
1
I
Control enable for the LSTRB1, LPAGE1, and LR / W1 signals
† I = input, O = output, Z = high impedance
‡ The effective address range is defined by the local /global STRB ACTIVE bits in the memory interface-control registers.
4
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
Pin Functions (Continued)
NO. OF
PINS
TYPE†
C1D7 – C1D0
8
I/O
Communication port 1 data bus
CREQ1
1
I/O
Communication port 1 token-request signal
CACK1
1
I/O
Communication port 1 token-request-acknowledge signal
CSTRB1
1
I/O
Communication port 1 data-strobe signal
CRDY1
1
I/O
Communication port 1 data-ready signal
CDIR1
1
O
SIGNAL NAME
DESCRIPTION
COMMUNICATION PORT 1 INTERFACE (13 pins)
Communication port 1 direction signal
COMMUNICATION PORT 2 INTERFACE (13 pins)
C2D7 – C2D0
8
I/O
Communication port 2 data bus
CREQ2
1
I/O
Communication port 2 token-request signal
CACK2
1
I/O
Communication port 2 token-request-acknowledge signal
CSTRB2
1
I/O
Communication port 2 data-strobe signal
CRDY2
1
I/O
Communication port 2 data-ready signal
CDIR2
1
O
Communication port 2 direction signal
COMMUNICATION PORT 4 INTERFACE (13 pins)
C4D7 – C4D0
8
I/O
Communication port 4 data bus
CREQ4
1
I/O
Communication port 4 token-request signal
CACK4
1
I/O
Communication port 4 token-request-acknowledge signal
CSTRB4
1
I/O
Communication port 4 data-strobe signal
CRDY4
1
I/O
Communication port 4 data-ready signal
CDIR4
1
O
C5D7 – C5D0
8
I/O
Communication port 5 data bus
CREQ5
1
I/O
Communication port 5 token-request signal
CACK5
1
I/O
Communication port 5 token-request-acknowledge signal
CSTRB5
1
I/O
Communication port 5 data-strobe signal
CRDY5
1
I/O
Communication port 5 data-ready signal
CDIR5
1
O
IIOF3 – IIOF0
4
I/O
NMI
1
I
Nonmaskable interrupt. NMI is sensitive to a low-going edge.
IACK
1
O
Interrupt acknowledge
RESET
1
I
Reset signal
RESETLOC1
RESETLOC0
2
I
Reset-vector location
ROMEN
1
I
On-chip ROM enable (0 = disable, 1 = enable)
TCLK0
1
I/O
Timer 0
TCLK1
1
I/O
† I = input, O = output, Z = high impedance
Timer 1
Communication port 4 direction signal
COMMUNICATION PORT 5 INTERFACE (13 pins)
Communication port 5 direction signal
INTERRUPTS, I / O FLAGS, RESET, TIMER (12 pins)
Interrupt and I / O flags
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
Pin Functions (Continued)
NO. OF
PINS
TYPE†
X1
1
O
Crystal
X2 / CLKIN
1
I
Crystal /oscillator
H1
1
O
H1 clock
H3
1
O
H3 clock
CVSS
17
I
Ground
DVSS
17
I
Ground
IVSS
DVDD
6
I
Ground
22
I
VSUBS
1
I
5-VDC supply
Substrate (tie to ground)
VDDL
VSSL
4
I
4
I
5-VDC supply
Ground
TCK
1
I
IEEE 1149.1 test port clock
TDI
1
I
IEEE 1149.1 test port data in
TDO
1
O/Z
TMS
1
I
IEEE 1149.1 test port mode select
TRST
1
I
IEEE 1149.1 test port reset
EMU0
1
I/O
Emulation pin 0
EMU1
1
I/O
† I = input, O = output, Z = high impedance
Emulation pin 1
SIGNAL NAME
DESCRIPTION
CLOCK (4 pins)
POWER (71 pins)
EMULATION (7 pins)
6
IEEE 1149.1 test port data out
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
PDB Package Pin Assignments — Alphabetical Listing
PIN
NAME
PIN
PIN
NO.
NAME
NO.
A0
149
C2D7
A1
150
A2
A3
PIN
NAME
NO.
NAME
NO.
34
CVSS
134
D24
137
C4D0
87
CVSS
117
D25
138
151
C4D1
88
CVSS
102
D26
140
152
C4D2
90
CVSS
78
D27
141
A4
154
C4D3
92
CVSS
62
D28
142
A5
155
C4D4
94
CVSS
44
D29
143
A6
156
C4D5
97
CVSS
25
D30
144
A7
157
C4D6
99
CVSS
7
D31
145
A8
158
C4D7
100
CVSS
282
DE
89
A9
159
C5D0
37
CVSS
262
DVDD
139
A10
160
C5D1
39
CVSS
247
DVDD
124
A11
162
C5D2
41
CVSS
230
DVDD
109
A12
165
C5D3
42
CVSS
218
DVDD
96
A13
166
C5D4
45
CVSS
202
DVDD
83
A14
167
C5D5
46
CVSS
182
DVDD
67
A15
168
C5D6
47
CVSS
164
DVDD
51
A16
169
C5D7
48
D0
104
DVDD
40
A17
170
CACK1
13
D1
105
DVDD
28
A18
171
CACK2
21
D2
106
DVDD
17
A19
174
CACK4
73
D3
107
DVDD
302
A20
175
CACK5
50
D4
108
DVDD
288
A21
176
CDIR1
19
D5
110
DVDD
272
A22
177
CDIR2
18
D6
111
DVDD
256
A23
178
CDIR4
16
D7
112
DVDD
244
AE
57
CDIR5
15
D8
113
DVDD
236
C1D0
269
CE0
93
D9
114
DVDD
223
C1D1
271
CE1
101
D10
115
DVDD
207
C1D2
274
CRDY1
8
D11
118
DVDD
188
C1D3
276
CRDY2
23
D12
120
DVDD
172
C1D4
278
CRDY4
85
D13
122
DVDD
161
C1D5
280
CRDY5
53
D14
123
DVDD
153
C1D6
283
CREQ1
11
D15
125
DVSS
147
C1D7
286
CREQ2
20
D16
127
DVSS
133
C2D0
26
CREQ4
71
D17
128
DVSS
116
C2D1
27
CREQ5
49
D18
129
DVSS
103
C2D2
29
CSTRB1
14
D19
130
DVSS
79
C2D3
30
CSTRB2
22
D20
131
DVSS
63
C2D4
31
CSTRB4
84
D21
132
DVSS
43
C2D5
32
CSTRB5
52
D22
135
DVSS
24
C2D6
33
CVSS
148
D23
136
DVSS
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
PDB Package Pin Assignments — Alphabetical Listing (Continued)
PIN
8
PIN
PIN
NO.
NAME
NO.
DVSS
281
LA17
253
LD30
228
STAT0
68
DVSS
261
LA18
254
LD31
229
STAT1
66
DVSS
246
LA19
255
LDE
291
STAT2
64
DVSS
231
LA20
257
LLOCK
284
STAT3
61
DVSS
217
LA21
258
LOCK
95
STRB0
58
DVSS
201
LA22
259
LPAGE0
299
STRB1
69
DVSS
179
LA23
260
LPAGE1
294
TCK
86
DVSS
163
LAE
287
LRDY0
298
TCLK0
290
EMU0
75
LCE0
297
LRDY1
293
TCLK1
289
EMU1
74
LCE1
292
LR / W0
300
TDI
76
H1
266
LD0
183
LR / W1
295
TDO
80
H3
268
LD1
184
LSTAT0
279
TMS
82
IACK
270
LD2
185
LSTAT1
277
TRST
81
IIOF0
10
LD3
186
LSTAT2
275
38
IIOF1
9
LD4
187
LSTAT3
273
VDDL
VDDL
IIOF2
5
LD5
192
LSTRB0
301
4
LD6
194
LSTRB1
296
VDDL
VDDL
191
IIOF3
IVSS
IVSS
126
LD7
195
NC
1
LD8
196
NC
77
VSSL
VSSL
36
65
IVSS
IVSS
35
LD9
197
NC
173
LD10
200
NC
180
VSSL
VSSL
193
2
IVSS
IVSS
285
LD11
203
NC
181
VSUBS
146
209
LD12
204
NC
189
X1
264
LA0
232
LD13
205
NC
190
X2 / CLKIN
263
LA1
233
LD14
206
NC
198
LA2
234
LD15
208
NC
199
LA3
235
LD16
210
NC
214
LA4
237
LD17
211
NC
303
LA5
238
LD18
212
NC
304
LA6
239
LD19
213
NMI
3
LA7
240
LD20
215
PAGE0
60
LA8
241
LD21
216
PAGE1
72
LA9
242
LD22
219
RDY0
91
LA10
243
LD23
220
RDY1
98
LA11
245
LD24
221
RESET
54
LA12
248
LD25
222
RESETLOC0
55
LA13
249
LD26
224
RESETLOC1
56
LA14
250
LD27
225
ROMEN
12
LA15
251
LD28
226
R / W0
59
LA16
252
LD29
227
R / W1
70
POST OFFICE BOX 1443
NAME
PIN
NAME
• HOUSTON, TEXAS 77251–1443
NO.
NAME
NO.
121
267
119
265
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
PDB Package Pin Assignments — Numerical Listing
PIN
NO.
PIN
NAME
PIN
NO.
NAME
NO.
PIN
NAME
NO.
NAME
1
NC
41
C5D2
81
TRST
121
2
42
C5D3
82
TMS
122
3
IVSS
NMI
VDDL
D13
43
DVSS
83
DVDD
123
D14
4
IIOF3
44
CVSS
84
CSTRB4
124
DVDD
5
IIOF2
45
C5D4
85
CRDY4
125
D15
6
46
C5D5
86
TCK
126
7
DVSS
CVSS
47
C5D6
87
C4D0
127
IVSS
D16
8
CRDY1
48
C5D7
88
C4D1
128
D17
9
IIOF1
49
CREQ5
89
DE
129
D18
10
IIOF0
50
CACK5
90
C4D2
130
D19
11
CREQ1
51
DVDD
91
RDY0
131
D20
12
ROMEN
52
CSTRB5
92
C4D3
132
D21
13
CACK1
53
CRDY5
93
CE0
133
DVSS
14
CSTRB1
54
RESET
94
C4D4
134
CVSS
15
CDIR5
55
RESETLOC0
95
LOCK
135
D22
16
CDIR4
56
RESETLOC1
96
DVDD
136
D23
17
57
AE
97
C4D5
137
D24
18
DVDD
CDIR2
58
STRB0
98
RDY1
138
D25
19
CDIR1
59
R / W0
99
C4D6
139
DVDD
20
CREQ2
60
PAGE0
100
C4D7
140
D26
21
CACK2
61
STAT3
101
CE1
141
D27
22
CSTRB2
62
CVSS
102
CVSS
142
D28
23
CRDY2
63
DVSS
103
DVSS
143
D29
24
64
STAT2
104
D0
144
D30
25
DVSS
CVSS
65
105
D1
145
D31
26
C2D0
66
IVSS
STAT1
106
D2
146
VSUBS
27
C2D1
67
DVDD
107
D3
147
DVSS
28
DVDD
C2D2
68
STAT0
108
D4
148
CVSS
29
69
STRB1
109
DVDD
149
A0
30
C2D3
70
R / W1
110
D5
150
A1
31
C2D4
71
CREQ4
111
D6
151
A2
32
C2D5
72
PAGE1
112
D7
152
A3
33
C2D6
73
CACK4
113
D8
153
DVDD
34
C2D7
74
EMU1
114
D9
154
A4
35
75
EMU0
115
D10
155
A5
36
IVSS
VSSL
76
TDI
116
DVSS
156
A6
37
C5D0
77
NC
117
CVSS
157
A7
38
78
CVSS
118
D11
158
A8
39
VDDL
C5D1
79
DVSS
119
A9
DVDD
80
TDO
120
VSSL
D12
159
40
160
A10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
9
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
PDB Package Pin Assignments — Numerical Listing (Continued)
PIN
PIN
PIN
NAME
NO.
NAME
NO.
161
DVDD
A11
201
DVSS
241
LA8
281
DVSS
202
CVSS
242
LA9
282
CVSS
DVSS
CVSS
203
LD11
243
LA10
283
C1D6
164
204
LD12
244
DVDD
284
LLOCK
165
A12
205
LD13
245
LA11
285
166
A13
206
LD14
246
DVSS
286
IVSS
C1D7
167
A14
207
DVDD
247
CVSS
287
LAE
168
A15
208
LD15
248
LA12
288
DVDD
169
A16
209
249
LA13
289
TCLK1
170
A17
210
IVSS
LD16
250
LA14
290
TCLK0
171
A18
211
LD17
251
LA15
291
LDE
172
212
LD18
252
LA16
292
LCE1
173
DVDD
NC
213
LD19
253
LA17
293
LRDY1
174
A19
214
NC
254
LA18
294
LPAGE1
175
A20
215
LD20
255
LA19
295
LR / W1
176
A21
216
LD21
256
DVDD
296
LSTRB1
177
A22
217
DVSS
257
LA20
297
LCE0
178
A23
218
CVSS
258
LA21
298
LRDY0
179
DVSS
NC
219
LD22
259
LA22
299
LPAGE0
180
220
LD23
260
LA23
300
LR / W0
181
NC
221
LD24
261
DVSS
301
LSTRB0
182
222
LD25
262
CVSS
302
DVDD
183
CVSS
LD0
223
DVDD
263
X2 / CLKIN
303
NC
184
LD1
224
LD26
264
X1
304
NC
185
LD2
225
LD27
265
186
LD3
226
LD28
266
VSSL
H1
187
LD4
227
LD29
267
188
228
LD30
268
VDDL
H3
189
DVDD
NC
229
LD31
269
C1D0
190
NC
230
CVSS
270
IACK
191
VDDL
LD5
231
DVSS
271
C1D1
232
LA0
272
DVDD
233
LA1
273
LSTAT3
194
VSSL
LD6
234
LA2
274
C1D2
195
LD7
235
LA3
275
LSTAT2
196
LD8
236
DVDD
276
C1D3
197
LD9
237
LA4
277
LSTAT1
198
NC
238
LA5
278
C1D4
199
NC
239
LA6
279
LSTAT0
200
LD10
240
LA7
280
C1D5
162
163
192
193
10
PIN
NO.
POST OFFICE BOX 1443
NAME
• HOUSTON, TEXAS 77251–1443
NO.
NAME
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
memory map
Structure Depends Upon
Romen Bit
Figure 1 shows the memory map for the ’320C44. Refer to the TMS320C4x User’s Guide (literature number
SPRU063B) for a detailed description of this memory mapping.
00000 0000h
1M
Accessible Local Bus
(External)
Peripherals (Internal)
Boot-Loader ROM (Internal)
00000 0FFFh
00000 1000h
Reserved
0000F FFFFh
00010 0000h
Peripherals (Internal)
00010 00FFh
00010 0100h
1M
Reserved
Reserved
0001F FFFFh
00020 0000h
Reserved
Reserved
1M
1K RAM BLK 0 (Internal)
1K RAM BLK 1 (Internal)
0002F F7FFh
0002F F800h
1K RAM BLK 0 (Internal)
0002F FBFFh
0002F FC00h
1K RAM BLK 1 (Internal)
Structure Identical
0002F FFFFh
00030 0000h
13 M
Local Bus
(External)
Local Bus
(External)
000FF FFFFh
0100 0000h
2 G – 16 M
Local Bus
(alias region, see Figure 2)
Local Bus
(alias region, see Figure 2)
7FFF FFFFh
8000 0000h
16 M
Global Bus
(External)
Global Bus
(External)
80FF FFFh
8100 0000
2 G – 16 M
Global Bus
(alias region, see Figure 2)
Global Bus
(alias region, see Figure 2)
FFFF FFFFh
(a) INTERNAL ROM DISABLED
(ROMEN = 0)
(b) INTERNAL ROM ENABLED
(ROMEN = 1)
Microprocessor Mode
Microcomputer Mode
Figure 1. Memory Map for the ’320C44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
description
The TMS320C44 DSP is a 32-bit, floating-point processor manufactured in 0.72-µm double-level-metal CMOS
technology. The TMS320C44 is part of the TMS320C4x generation of DSPs from Texas Instruments. The
on-chip parallel-processing capabilities of the ’C44 make the immense floating-point performance required by
many applications achievable.
operation
The ’320C44 has four on-chip communication ports for processor-to-processor communication with no external
hardware and simple communication software. This allows connectivity with no external-glue logic. The
communication ports remove input / output bottlenecks, and the independent smart 6-channel DMA
coprocessor is able to handle the CPU input / output burden.
To fit the ’320C40 into a 304-pin PQFP package ( thermally enhanced plastic quad flatpack), two communication
ports are removed and the external local and global address buses are reduced to 24 address lines each. In
this case, both the bond pads and driver circuits are removed, decreasing die size and power consumption.
Otherwise, functionality remains the same as the rest of the ’320C4x family.
The communication-port token and data-strobe control lines are internally connected to avoid spurious data,
boot-up, and power consumption problems.
12
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
memory aliasing
The ’320C44 offers global and local addresses of A0 – A23 and LA0 – LA23, giving an external address reach
of (2 buses) × (2 24) = 225 words. Since the internal address span of the ’320C44 is 232 words, reading or writing
to memory outside of the base-address region causes memory aliasing. Figure 2 shows how the memory pages
overlap each other.
Local Bus
Global Bus
0x0000 0000
0x8000 0000
Base-Address
Region
Base-Address
Region
0x00FF FFFF
0x0100 0000
0x80FF FFFF
0x8100 0000
External Alias 1
External Alias 1
0x01FF FFFF
0x0200 0000
0x81FF FFFF
0x8200 0000
External Alias 2
External Alias 2
0x02FF FFFF
0x82FF FFFF
0x7F00 0000
0xFF00 0000
External Alias n
External Alias n
0x7FFFFFFF
0xFFFFFFFF
Figure 2. Memory Alias
central processing unit
The ’320C44 CPU is configured for high-speed internal parallelism for the highest sustained performance. The
key features of the CPU are:
D
D
D
D
D
Eight operations / cycle:
–
40- / 32-bit floating-point / integer multiply
–
40- / 32-bit floating-point / integer ALU operation
–
Two data accesses
–
Two address-register updates
Floating-point conversion
Divide and square-root support
’C3x and ’C4x assembly-language compatibility
Byte and halfword accessibility
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
13
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
DMA coprocessor
The DMA coprocessor allows concurrent I / O and CPU processing for the highest sustained CPU performance.
The key features of the DMA coprocessor are:
D
D
D
D
Link pointers to allow DMA channels to autoinitialize without CPU intervention
Parallel CPU operation and DMA transfers
Six DMA channels to support memory-to-memory data transfers
Split-mode operation which doubles the available channels to twelve when data transfers to and from a
communication port are required
communication ports
The ’320C44 contains four identical high-speed communication ports, each of which provides a
bidirectional-communication interface to other ’C4x devices and external peripherals. The key features of the
communication ports are:
D
D
D
D
D
Direct interprocessor communication and processor I / O
20M-byte / s bidirectional interface on each communication port for high-speed multiprocessor interface
Port direction pin (CDIR) to ease interfacing
Separate input and output 8-word-deep FIFO buffers for processor-to-processor communication and I / O
Automatic arbitration and handshaking for direct processor-to-processor connection
communication-port direction pin
A port-direction pin (CDIR1, CDIR2, CDIR4, CDIR5) is available for each ’C44 communication port. When the
communication port is in the output mode, CDIRx is driven low. When the communication port is in the input
mode, CDIRx is driven high. The truth table for two ’320C44 devices is shown in Table 1. Communication
port 1 of CPUA is connected to communication port 4 of CPUB.
Table 1. Truth Table for Two ’320C44 Devices
CDIR1
CDIR4
0
0
Token error
DESCRIPTION
0
1
CPUA is configured to transmit to CPUB.
1
0
CPUB is configured to transmit to CPUA .
1
1
Token exchange overlap, if > 1H then token error
communication-port-software reset
The input and output FIFO levels for a communication port can be flushed by writing at least two back-to-back
values to its communication-port software-reset address as specified in Table 2. This software reset flushes any
word or byte already present in the FIFOs, but it does not affect the status of the communication-port pins.
Table 2. Communication-Port Software-Reset Address
14
COMMUNICATION PORT
SOFTWARE-RESET ADDRESS
1
0x0100053
2
0x0100063
4
0x0100083
5
0x0100093
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
communication-port-software reset (continued)
When used in conjunction with the communication-port direction pins and NMI bus-grant, an effective method
of error detection and correction can be achieved. A subroutine showing how to reset communication port 1 is
given in Figure 3.
; –––––––––––––––––––––––––––––––––––––––––––––-–––;
; RESET1:Flushes FIFOs data for communication port 1;
; –––––––––––––––––––––––––––––––––––––––––––––-–––;
RESET1 push
AR0
; Save registers
push
R0
;
push
RC
;
ldhi
010h,AR0
; Set AR0 to base address of COM 1
or
050h,AR0
;
FLUSH: rpts
1
; Flush FIFO data with back-to-back write
sti
R0,*+AR0(3) ;
rpts
10
; Wait
nop
;
ldi
*+AR0(0),R0 ; Check for new data from other port
and
01FE0h,R0
;
bnz
FLUSH
;
pop
RC
; Restore registers
pop
R0
;
pop
AR0
;
rets
; Return
Figure 3. Example of Communication-Port-Software Reset
NMI with bus-grant feature
The ’320C44 devices have a software-configurable feature that allows forcing the internal-peripheral bus ready
when the NMI signal is asserted. The NMI bus-grant feature is enabled when bits 19 and 18 of the status register
(ST) are set to 10b. When enabled, a peripheral bus-grant signal is generated on the falling edge of NMI. If NMI
is asserted and this feature is not enabled, the CPU stalls on access to the peripheral bus if it is not ready. A
stall condition occurs when writing to a full output FIFO or reading an empty input FIFO. This feature is useful
in correcting communication-port errors when used in conjunction with the communication-port software-reset
feature.
IDLE2 clock-stop power-down mode
The ’320C44 has a clock-stop mode, or power-down mode (IDLE2) to achieve extremely low power
consumption. When an IDLE2 instruction is executed, the clocks are halted with H1 held high. ( Exiting IDLE2
requires asserting one of the IIOF3 – IIOF0 pins configured as an external interrupt.) A macro showing how to
generate the IDLE2 opcode is given in Figure 4. During this power-down mode:
D
D
D
No instructions are executed.
The CPU, peripherals, and internal memory retain their previous state.
The external-bus outputs are idle. The address lines remain in their previous state; the data lines are in the
high-impedance state; and the output-control signals are inactive.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
IDLE2 clock-stop power-down mode (continued)
; ––––––––––––––––––––––––––––––––––––––––––––-–-–;
; IDLE2: Macro to generate idle2 opcode
;
; –––––––––––––––––––––––––––––––––––––––––––––-––;
IDLE2
.macro
.word
06000001h
.endm
Figure 4. Example Software Subroutine Using IDLE2
IDLE2 is exited when one of the five external interrupts (NMI and IIOF3 – IIOF0) is asserted low for at least four
input clocks (two H1 cycles). The clocks then start after a delay of two input clocks (one H1 cycle). The clocks
can start in the opposite phase; that is, H1 can be high when H3 was high before the clocks were stopped.
However, the H1 and H3 clocks remain 180 degrees out of phase with each other.
During IDLE2 operation, an external interrupt can be recognized and serviced by the CPU if it is enabled before
entering IDLE2 and asserted for at least two H1 cycles. For the processor to recognize only one interrupt, the
interrupt pin must be configured for edge-trigger mode or asserted less than three cycles in level-trigger mode.
Any external interrupt pin can wake up the device from IDLE2, but for the CPU to recognize that interrupt, it must
also be enabled. If an interrupt is recognized and executed by the CPU, the instruction following the IDLE2
instruction is not executed until after a return opcode is executed.
When the device is in emulation mode, the CPU executes an IDLE2 instruction as if it were an IDLE instruction.
The clocks continue to run for correct operation of the emulator.
boot-loader mode selection
Table 3. Boot-Loader Mode Selection Using Pins IIOF3 – IIOF0
EXTERNAL PIN
IIOF2
IIOF1
IIOF0
1
1
0
1
Load source program from address 0030 0000h
1
0
1
1
Load source program from address 4000 0000h (see Note 1)
1
0
0
1
Load source program from address 80 0000h
0
1
1
1
Load source program from address 8000 0000h (see Note 2)
0
1
0
1
Load source program from address 8040 0000h (see Note 3)
0
0
1
1
Load source program from address 8080 0000h (see Note 4)
0
0
0
1
Reserved (boot-loader program terminates)
1
1
1
Load source program from communication port
1
NOTES: 1.
2.
3.
4.
16
SOURCE PROGRAM LOCATION
IIOF3
This selection cause the ’C44 to drive 0 in the 24 external local address pins and activates the LSTRB0 signal.
This selection cause the ’C44 to drive 0 in the 24 external global address pins ando activates the STRB0 signal.
This selection cause the ’C44 to drive 0x40 0000 in the 24 external global address pins and activates the STRB0 signal.
This selection cause the ’C44 to drive 0x80 0000 in the 24 external global address pins and to activate the STRB0 signal.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
development tools
A key aspect to a parallel-processing implementation is the development tools available. The ’C44 is supported
by a host of parallel-processing tools for developing and simulating code easily and for debugging
parallel-processing systems. The code-generation tools include:
D
D
D
D
An optimizing ANSI C compiler with a runtime-support library that supports use of communication ports and
DMA
Third party support for C, C++, and Ada compilers
Several operating systems available for parallel-processing support as well as DMA and
communication-port drivers
Assembler and linker with support for mapping program and data to parallel processors
The simulation tools include a TI software-simulator with a high-level-language debugger interface for
simulating a single processor. The hardware development and verification tools consist of the XDS510
( parallel-processor in-circuit emulator and high-level-language debugger ).
silicon revision identification
DSP
TMS320C44PDB
EAXXX
YYYYY
1991 TI TAIWAN
Device Type
Revision Number and Package Data Code
E XXXXX
: Silicon rev 1.X
EA XXXXX
: Silicon rev 2.X
Lot Number (May or may not exist)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
17
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 5: All voltage values are with respect to VSS.
recommended operating conditions
VDD
VIH
Supply voltage (DDVDD, etc.)
High-level input voltage
MIN
TYP‡
4.75
5
UNIT
X2 / CLKIN
2.6
CSTRB and CRDY pins
2.4
5.25
VDD + 0.3§
VDD + 0.3§
2
VDD + 0.3§
All other pins
VIL
IOH
MAX
– 0.3§
Low-level input voltage
High-level output current
IOL
Low-level output current
TC
Operating case temperature
‡ All typical values are at VDD = 5 V, TA (air temperature)= 25°C.
§ This parameter is characterized but not tested.
V
V
0.8
V
– 300
µA
2
mA
85
°C
0
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
TEST CONDITIONS¶
PARAMETER
VOH
High-level output voltage
VDD = MIN,
IOH = MAX
VOL
Low-level output voltage
VDD = MIN,
IOL = MAX
IZ
High-impedance current
VDD = MAX
Input current
Inputs with internal pullups
(see Note 6)
VI = VSS to VDD
All others
ICC
CI
Supply
y current
TA = 25 °C,
VDD = MAX,
fx = MAX (see Note 7)
TYP#
2.4
3
0.3
X2 / CLKIN only
II
MIN
MAX
V
0.6
V
– 20
20
µA
–30
30
– 400
20
– 10
10
’320C44-40
’320C44-50
350
850
’320C44-60
350
950
µA
mA
15||
Input capacitance
UNIT
pF
Co
Output capacitance
15||
pF
¶ For conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions.
# All typical values are at VDD = 3.3 V, TA (air temperature) = 25°C.
|| This parameter is specified by design but not tested.
NOTES: 6. Pins with internal pullup devices: TDI, TCK, TMS. Pin with internal pulldown device: TRST.
7. fx is the input clock frequency. The maximum value (max) for the ’320C44-40, ’320C44-50, and ’320C44-60 is 40, 50 and 60 MHz,
respectively.
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
VLoad
CT
Output
Under
Test
IOH
Where: IOL
=
=
IOH
VLOAD =
=
CT
2 mA (all outputs)
300 µA (all outputs)
2.15 V
80 pF typical load-circuit capacitance
Figure 5. Test Load Circuit
signal transition levels
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Output transition times are specified as follows:
D
D
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at
which the output is said to be high is 2 V.
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be
no longer high is 2 V and the level at which the output is said to be low is 1 V.
2.4 V
2V
1V
0.6 V
Figure 6. TTL-Level Outputs
Transition times for TTL-compatible inputs are specified as follows:
D
D
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.92 V (10%) and the level at which the input is said to be high is 1.88 V (90%).
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
1.88 V (90%) and the level at which the input is said to be low is 0.92 V (10%).
2V
1.88 V (90%)
0.92 V (10%)
0.8 V
Figure 7. TTL-Level Inputs
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, pin names that have both global and local applications are generally represented with (L)
immediately preceding the basic signal name (for example, (L)RDY represents both the global term RDY and
local term LRDY). Other pin names and related terminology have been abbreviated as follows, unless otherwise
noted:
20
A
(L)A23 – (L)A0 or (L)Ax
IACK
IACK
AE
(L)AE
IF
IIOF(3 – 0) or IIOFx
ASYNCH
Asynchronous reset signals in the
high-impedance state
IIOF
IIOF(3 – 0) or IIOFx
BYTE
Byte transfer
LOCK
(L)LOCK
CA
CACK(1,2,4,5) or CACKx
P
CD
C(1,2,4,5)D7 – C(1,2,4,5)D0 or CxDx
PAGE
tc(H)
(L)PAGE0 and (L)PAGE1 or (L)PAGEx
CDIR
CDIR(1,2,4,5) or CDIRx
RDY
(L)RDY0, (L)RDY1, or (L)RDYx
CE
(L)CE0, (L)CE1, or (L)CEx
RESET
RESET
CI
CLKIN
RW
(L)R / W0, (L)R / W1, or (L)R / Wx
COMM
Asynchronous reset signals
S
(L)STRB0, (L)STRB1, or (L)STRBx
CONTROL
Control signals
ST
(L)STAT3 – (L)STAT0 or (L)STATx
CRQ
CREQ(1,2,4,5) or CREQx
TCK
TCK
CRDY
CRDY(1,2,4,5) or CRDYx
TCLK
TCLK0, TCLK1, or TCLKx
CS
CSTRB(1,2,4,5) or CSTRBx
TDO
TDO
D
(L)D31 – (L)D0 or (L)Dx
TMS
TMS / TDI
DE
(L)DE
WORD
32-bit word transfer
H
H1, H3
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing for X2/CLKIN, H1, H3 (see Figure 8 and Figure 9)
TMS320C44- 50
NO
NO.
1
2
3
4
5
6
7
8
9
9.1
MIN
tf(CI)
tw(CIL)
Fall time, CLKIN
Pulse duration, CLKIN low, tc(CI) = MIN
7
tw(CIH)
tr(CI)
Pulse duration, CLKIN high, tc(CI) = MIN
7
tc(CI)
tf(H)
Cycle time, CLKIN
tw(HL)
tw(HH)
Pulse duration, H1 and H3 low
tr(H)
td(HL - HH)
Rise time, H1 and H3
MAX
5†
TMS320C44- 60
MIN
5
242.5
Fall time, H1 and H3
Pulse duration, H1 and H3 high
tc(CI) + 6
tc(CI) + 6
10
tc(H)
† This value is specified by design but not tested.
‡ Maximum cycle time is not limited during IDLE2 operation.
ns
ns
16.67
242.5
ns
3
ns
tc(CI) – 6
tc(CI) – 6
tc(CI) + 6
tc(CI) + 6
4
Delay time from H1 low to H3 high or from H3 low to H1 high
Cycle time, H1 and H3‡
ns
5†
3
tc(CI) – 6
tc(CI) – 6
UNIT
ns
5
5†
Rise time, CLKIN
20
MAX
5†
ns
ns
4
ns
–1
4
–1
4
ns
40
485
33.3
485
ns
5
4
1
X2 / CLKIN
3
2
Figure 8. X2 / CLKIN Timing
10
6
9
H1
8
7
9.1
9.1
H3
8
9
6
7
10
Figure 9. H1 and H3 Timings
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (see Note 8, Figure 10, and
Figure 11)
TMS320C44- 50
NO
NO.
1
2
3
4
5
6
7
8
8.1
9
10
11
MAX
9
TMS320C44- 60
UNIT
MIN
0†
MAX
8
ns
8
ns
9
0†
0†
8
ns
9
0†
8
ns
td(H1L - SL)
td(H1L - SH)
Delay time, H1 low to (L)STRBx low
td(H1H - RWL)
td(H1L - A)
Delay time, H1 high to (L)R / Wx low
0†
0†
Delay time, H1 low to (L)Ax valid
0†
tsu(D-H1L)R
th(H1L-D)R
Setup time, (L)Dx valid before H1 low (read)
10
9
ns
Setup time, (L)RDYx valid before H1 low
0
†
18
ns
tsu(RDY-H1L)
th(H1L-RDY)
0
20‡
0
0
ns
td(H1L - ST)
td(H1H-RWH)W
Delay time, H1 low to (L)STAT3 – (L)STAT0 valid
tv(H1L-D)W
th(H1H-D)W
Valid time, (L)Dx after H1 low (write)
Delay time, H1 low to (L)STRBx high
Hold time, (L)Dx after H1 low (read)
Hold time, (L)RDYx after H1 low
Delay time, H1 high to (L)R / Wx high (write)
Hold time, (L)Dx after H1 high (write)
8
0†
9
0
td(H1H - A)
Delay time, H1 high to address valid on back-to-back write cycles
† This value is specified by design but not tested.
‡ If this setup time is not met, the read / write operation is not assured.
NOTE 8: For consecutive reads, (L)R / Wx stays high and (L)STRBx stays low.
POST OFFICE BOX 1443
9
0†
16
12
22
MIN
0†
• HOUSTON, TEXAS 77251–1443
ns
8
ns
8
ns
13
ns
0
9
ns
8
ns
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (continued)
H3
H1
1
2
(L)STRBx
(L)R / Wx
5
4
3
(L)Ax
6
(L)Dx
8
7
(L)RDYx
8.1
(L)STATx
Figure 10. Memory-Read-Cycle Timing [(L)STRBx = 0]
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (continued)
H3
H1
1
2
(L)STRBx
3
9
(L)R / Wx
12
4
(L)Ax
10
11
(L)Dx
8
(L)RDYx
7
(L)STATx
Figure 11. Memory-Write-Cycle Timing [(L)STRBx = 0]
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
(L)DE-, (L)AE-, and (L)CEx-enable timing (see Figure 12)
TMS320C44- 50
NO
NO.
TMS320C44- 60
MIN
MAX
MIN
MAX
UNIT
1
td(DEH - DZ)
Delay time, (L)DE high to (L)D0 – (L)D31 in the high-impedance
state
0†
15‡
0†
15‡
ns
2
td(DEL - DV)
Delay time, (L)DE low to (L)D0 – (L)D31 valid
0†
21
0†
16
ns
3
td(AEH - AZ)
Delay time, (L)AE high to (L)A0 – (L)A23 in the high-impedance
state
0†
15‡
0†
15‡
ns
4
td(AEL - AV)
Delay time, (L)AE low to (L)A0 – (L)A23 valid
0†
18
0†
16
ns
5
td(CEH - RWZ)
Delay time, (L)CEx high to (L)R / W0, (L)R / W1 in the
high-impedance state
0†
15‡
0†
15‡
ns
6
td(CEL - RWV)
Delay time, (L)CEx low to (L)R / W0, (L)R / W1 valid
0†
21
0†
16
ns
7
td(CEH - SZ)
Delay time, (L)CEx high to (L)STRB0, (L)STRB1 in the
high-impedance state
0†
15‡
0†
15‡
ns
8
td(CEL - SV)
Delay time, (L)CEx low to (L)STRB0, (L)STRB1 valid
0†
21
0†
16
ns
td(CEH - PAGEZ)
Delay time, (L)CEx high to (L)PAGE0, (L)PAGE1 in the
high-impedance state
0†
15‡
0†
15‡
ns
0†
21
0†
16
ns
9
10 td(CEL - PAGEV) Delay time, (L)CEx low to (L)PAGE0, (L)PAGE1 valid
† This value is specified by design but not tested.
‡ This value is characterized but not tested.
(L)DE
2
1
Hi-Z
(L)Dx
(L)AE
4
3
Hi-Z
(L)Ax
(L)CEx
6
5
Hi-Z
(L)R / Wx
7
8
Hi-Z
(L)STRBx
9
10
Hi-Z
(L)PAGEx
Figure 12. (L)DE -, (L)AE -, and (L)CEx-Enable Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing for (L)LOCK when executing LDFI or LDII (see Figure 13)
TMS320C44- 50
NO
NO.
1
MIN
td(H1L - LOCKL)
Delay time, H1 low to (L)LOCK low
MAX
8
LDFI or LDII
External Access
H3
H1
(L)STRBx
(L)R / Wx
(L)Ax
(L)Dx
(L)RDYx
1
(L)LOCK
Figure 13. Timing for (L)LOCK When Executing LDFI or LDII
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44- 60
MIN
MAX
8
UNIT
ns
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing for (L)LOCK when executing STFI or STII (see Figure 14)
TMS320C44- 50
NO
NO.
1
MIN
td(H1L - LOCKH)
Delay time, H1 low to (L)LOCK high
MAX
8
TMS320C44- 60
MIN
MAX
8
UNIT
ns
STFI or STII
External Access
H3
H1
(L)STRBx
(L)R / Wx
(L)Ax
(L)Dx
(L)RDYx
1
(L)LOCK
Figure 14. Timing for (L)LOCK When Executing STFI or STII
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing for (L)LOCK when executing SIGI (see Figure 15)
TMS320C44- 50
NO
NO.
1
2
MIN
td(H1L - LOCKL)
td(H1L - LOCKH)
TMS320C44- 60
MIN
MAX
Delay time, H1 low to (L)LOCK low
8
8
Delay time, H1 low to (L)LOCK high
8
8
H3
H1
1
2
(L)LOCK
(L)R / Wx
(L)Ax
(L)Dx
(L)RDYx
(L)STATx
Figure 15. Timing for (L)LOCK When Executing SIGI
28
MAX
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
UNIT
ns
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing for (L)PAGE0, (L)PAGE1 during memory access to a different page (see Figure 16)
TMS320C44- 50
NO
NO.
1
2
td(H1L - PAGEH)
td(H1L - PAGEL)
TMS320C44- 60
UNIT
MIN
MAX
MIN
MAX
Delay time, H1 low to (L)PAGEx high for access to different page
0
9
0
8
ns
Delay time, H1 low to (L)PAGEx low for access to different page
0
9
0
8
ns
H1
(L)R / Wx
(L)STRBx
(L)RDYx
1
2
1
2
(L)PAGEx
(L)Dx
(L)Ax
(L)STATx
(L)STRB1 write to a different page
(L)STRB1 read from a different page
Figure 16. (L)PAGE0, (L)PAGE1 Timing Cycle, Memory Access to a Different Page
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
29
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing for the IIOFx when configured as an output (see Figure 17)
TMS320C44- 50
NO
NO.
1
MIN
tv(H1L - IIOF)
H1 low to IIOFx valid
Fetch Load
Instruction
MAX
TMS320C44- 60
MIN
MAX
14
Decode
Read
14
Execute
H3
H1
FLAGx (IIF Register)
1 or 0
1
IIOFx Pins
Figure 17. Timing for the IIOFx When Configured as an Output
30
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
UNIT
ns
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing of IIOFx changing from output to input mode (see Figure 18)
TMS320C44- 50
NO
NO.
1
2
MIN
th(H1L - IIOF)
tsu(IIOF-H1L)
Hold time, IIOFx after H1 low
Setup time, IIOFx before H1 low
3
th(H1L-IIOF)
Hold time, IIOFx after H1 low
† This value is specified by design but not tested.
Buffers Go
From Output
to Input
Execute
Load of IIF
Register
MAX
14†
TMS320C44- 60
MIN
MAX
14†
UNIT
ns
11
11
ns
0
0
ns
Synchronizer
Delay
Value on IIOF
Seen in IIF
H3
H1
2
3
TYPEx
(IIF Register)
1
IIOFx
Output
FLAGx
(IIF Register)
Data
Sampled
Data
Seen
Figure 18. Change of IIOFx From Output to Input Mode
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
31
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing of IIOFx changing from input to output mode (see Figure 19)
TMS320C44- 50
NO
NO.
1
MIN
td(H1L - IFIO)
MAX
Delay time, H1 low to IIOFx switching from input to output
TMS320C44- 60
MIN
MAX
14
14
TMS320C44- 50
TMS320C44- 60
UNIT
ns
Execution of
Load of IIF
Register
H3
H1
TYPEx
(IIF Register)
1
IIOFx
Figure 19. Change of IIOFx From Input to Output Mode
RESET timing (see Figure 20)
NO
NO.
1
MAX
MIN
MAX
11
11
ns
2
tc(CI)
10
2
10
ns
Setup time for RESET before CLKIN low
2.1
tsu(RESET-C1L)
td(CIH - H1H)
Delay time, CLKIN high to H1 high
2
tc(CI)
10
2.2
td(CIH - H1L)
Delay time, CLKIN high to H1 low
2
10
tsu(RESETH - H1L)
Setup time for RESET high before H1 low and after ten H1
clock cycles
3
4.1
UNIT
MIN
13
13
ns
ns
td(CIH - H3L)
td(CIH - H3H)
Delay time, CLKIN high to H3 low
2
10
2
10
ns
Delay time, CLKIN high to H3 high
2
10
13†
9†
ns
Delay time, H1 high to (L)Dx in the high-impedance state
10
13†
9†
2
td(H1H - DZ)
td(H3H - AZ)
Delay time, H3 high to control signals high [low for (L)PAGE]
9†
9†
9†
9†
ns
8
td(H3H - CONTROLH)
td(H1H - IACKH)
9
td(RESETL - ASYNCH)
Delay time, RESET low to asynchronous reset signals in the
high-impedance state
21†
21†
ns
10
td(RESETH - COMMH)
Delay time, RESET high to asynchronous reset signals high
15†
15†
ns
11
td(H1H-CDIRL)
td(H1H-CDIRH)
Delay time,
9
9
ns
12
Delay time,
† This value is characterized but not tested.
9
9
ns
4.2
5
6
7
32
Delay time, H3 high to (L)Ax in the high-impedance state
Delay time, H1 high to IACK high
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ns
ns
ns
CLKIN
RESET
(see Notes A and B)
1
2.2
2.1
3
H1
5
4.1
H3
Ten H1 Clock Cycles
(L)Dx
(see Note C)
6
7
Control Signals
(see Note D)
7
(L)PAGEx
(see Note D)
8
IACK
Asynchronous Reset
Signals (see Note E)
Asynchronous Reset
Signals (see Note A)
9
10
9
11
CDIRx
(see Note F)
12
CDIRy
(see Note F)
Figure 20. RESET Timing
33
TMS320C44
DIGITAL SIGNAL PROCESSOR
NOTES: A. Asynchronous reset signals that go to a high logic level after RESET returns to a high state include CREQy, CACKx, CSTRBx, and CRDYy
(where x = 1 or 2 and y = 4 or 5).
B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise,
an additional delay of one clock cycle can occur.
C. For this diagram, (L)Dx includes D31 – D0, LD31 – LD0, and CxD7 – CxD0; (L)Ax includes LA(23 – 0) and A(23 – 0).
D. Control signals LSTRB0, LSTRB1, STRB0, STRB1, (L)STAT3 – (L)STAT0, (L)LOCK, (L)R/W0, and (L)R/W1 go high while (L)PAGE0 and (L)PAGE1 go low.
E. Asynchronous reset signals that go into the high-impedance state after RESET goes low include TCLK0, TCLK1, IIOF3 – IIOF0, and the communication-port control
signals CREQx, CACKy, CSTRBy, and CRDYx (where x = 1 or 2, and y = 4 or 5). At reset, ports 1 and 2 become outputs, and ports 4 and 5 become inputs.
F. x = 1 or 2 and y = 4 or 5
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Control Signals
4.2
(L)Ax
see Note C)
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing for IIOFx interrupt response [P = tc(H)] (see Notes 9 and 10 and Figure 21)
TMS320C44- 50
NO
NO.
1
2
tsu(IIOF-H1L )
Setup time, IIOFx before H1 low
tw(INT )
Pulse duration, to assure one interrupt seen
(see Note 11)
MIN
11†
TYP
P
1.5P
MAX
< 2P‡
TMS320C44 - 60
MIN
11†
TYP
P
1.5P
MAX
UNIT
ns
< 2P‡
ns
† If this timing is not met, the interrupt is recognized in the next cycle.
‡ This value only applies to level-triggered interrupts and is specified by design but not tested.
NOTES: 9. IIOFx is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle can occur.
10. Edge-triggered interrupts require a setup of time (1) and a minimum duration of P. No maximum duration limit exists.
11. Level-triggered interrupts require interrupt-pulse duration of at least 1P wide (P = one H1 period) to assure it will be seen. It must
be less than 2P wide to assure it will be responded to only once. Recommended pulse duration is 1.5P.
Reset or
Interrupt
Vector Read
Fetch First
Instruction of
Service
Routine
H3
H1
IIOFx
1
(see Note A)
First
Instruction
Address
2
FLAGx
(IIF Register)
Address
Vector
Address
Data
NOTE A: The ’C44 can accept an interrupt from the same source every two H1 clock cycles.
Figure 21. IIOFx Interrupt-Response Timing [P = tc(H)]
34
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing for IACK (see Note 12 and Figure 22)
TMS320C44 - 50
NO
NO.
1
2
MIN
MAX
TMS320C44 - 60
MIN
MAX
UNIT
td(H1L - IACKL)
Delay time, H1 low to IACK low
9
7
ns
td(H1L - IACKH)
Delay time, H1 low to IACK high during first cycle of IACK instruction
data read
9
7
ns
NOTE 12: The IACK output is active for the entire duration of the bus cycle and is, therefore, extended if the bus cycle utilizes wait states.
Fetch IACK
Instruction
Decode IACK
Instruction
IACK Data
Read
Execute IACK
Instruction
H3
H1
1
2
IACK
Address
Data
Figure 22. IACK Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
35
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
communication-port word-transfer-cycle timing† [P = tc(H)] (see Note 13 and Figure 23)
NO
NO.
1
2
TMS320C44 - 50
TMS320C44 - 60
MIN
MIN
MAX
MAX
UNIT
tc(WORD)‡§
Cycle time, word transfer (4 bytes = 1 word)
1.5P + 7
2.5P + 170
1.5P + 7
2.5P + 170
ns
td(CRDYL-CSL)W‡
Delay time, CRDYx low to CSTRBx low between
back-to-back write cycles
1.5P + 7
2.5P + 28
1.5P + 7
2.5P + 28
ns
† For these timing values, it is assumed that the ’C4x receiving data is ready to receive data. Line propagation delay is not considered.
‡ This value is characterized but not tested.
§ tc(WORD) max = 2.5P + 28 ns + the maximum summed values of 4 × td(CSL-CRDYL)R, 3 × td(CRDYL-CSH), 3 × td(CSH-CRDYH)R, and
3 × td(CRDYH-CSL)W as seen in Figure 24. This timing assumes two ’C4xs are connected.
NOTE 13: These timings apply only to two communicating ’C4xs. When a non-’C4x device communicates with a ’C44, timings can be longer. No
restriction exists in this case on how slow the transfer could be except when using early silicon (C40 PG 1.x or 2.x). Refer to the CSTRB
width restriction section of the TMS320C4x User’s Guide (literature number SPRU063B).
CREQx
CACKx
1
CSTRBx
CxDx
B0
B1
B2
B3
Undef.
B0¶
2
CRDYx
= When signal is an input (clear = when signal is an output).
¶ Begins byte 0 of the next word.
NOTE A: For correct operation during token exchange, the two communicating ’C4xs must have CLKIN frequencies within a factor of 2 of each
other (in other words, at most, one of the ’C4xs can be twice as fast as the other).
Figure 23. Communication-Port Word-Transfer-Cycle Timing [P = tc(H)]
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
communication-port byte-cycle timing (write and read) (see Note 14 and Figure 24)
TMS320C44 - 50
NO
NO.
1
tsu(CD-CSL)W
td(CRDYL - CSH)W
Setup time, CxDx valid before CSTRBx low (write)
2
3
th(CRDYL - CD)W
Hold time, CxDx after CRDYx low (write)
4
td(CRDYH - CSL)W
Delay time, CRDYx high to CSTRBx low for subsequent bytes
(write)
5
tc(BYTE)‡
td(CSL - CRDYL)R
Cycle time, byte transfer
tsu(CSL - CD)R
th(CRDYL - CD)R
Setup time, CxDx valid after CSTRBx low (read)
6
7
8
Delay time, CRDYx low to CSTRBx high (write)
TMS320C44 - 60
MIN
MAX
MIN
MAX
2
0†
12
2
0†
12
2
0†
Hold time, CxDx valid after CRDYx low (read)
9
12
ns
44§
ns
10
ns
0†
10
ns
ns
0†
12
44§
Delay time, CSTRBx low to CRDYx low (read)
ns
2
0†
UNIT
0
0
ns
2
0†
2
0†
ns
td(CSH - CRDYH)R Delay time, CSTRBx high to CRDYx high (read)
10
10
ns
† This value is specified by design but not tested.
‡ tc(BYTE) max = summed maximum values of td(CRDY-CSH), td(CSL-CRDYL)R, td(CSH-CRDYH)R, and td(CRDYH-CSL)W. This assumes
two ’C4xs are connected.
§ This value is characterized but not tested.
NOTE 14: Communication port timing does not include line length delay.
CREQx
CACKx
5
7
5
CSTRBx
1
2
9
CxDx
Valid
Data
3
8
6
CRDYx
4
(a) WRITE TIMING
(b) READ TIMING
= When signal is an input (clear = when signal is an output).
Figure 24. Communication-Port Byte-Cycle Timing (Write and Read)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
37
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing for communication-token transfer sequence, input to an output port [P = tc(H)]
(see Figure 25)†
NO.
1‡
MAX
UNIT
0.5P+ 6
MIN
1.5P + 22
ns
Delay time, CACKx low to start of CREQx going high for token-request
acknowledge
P+5
2P + 22
ns
td(CRQH - CRQ)T
Delay time, start of CREQx going high to CREQx change from output to an input
0.5P – 5
0.5P + 13
ns
4
td(CRQH - CA)T
Delay time, start of CREQx going high to CACKx change from an input- to an
output-level high
0.5P – 5
0.5P + 13
ns
4.1
td(CRQH - CD)T
Delay time, start of CREQx going high to CxDx change from input-driven to
output-driven
0.5P – 5
0.5P + 13
ns
4.2
td(CRQH - CRDY)T
Delay time, start of CREQx going high to CRDYx change from an output to an
input
0.5P – 5
0.5P + 13
ns
5
td(CRQH - CSL)T
Delay time, start of CREQx going high to CSTRBx low for start of word-transfer
out
1.5P – 8
1.5P + 9
ns
6
td(CRDYL - CSL)T
td(CRQH - CDIRL)
Delay time, CRDYx low at end of word-input to CSTRBx low for word-output
3.5P + 12
5.5P + 48
ns
Delay time, CREQx high to CDIRx low, change from input to output
0.5P – 5
0.5P + 13
td(CAL - CS)T
Delay time, CACKx low to CSTRBx change from input to a high-level output
2‡
td(CAL - CRQH)T
3
7
ns
† These values are characterized but not tested.
‡ These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal
pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the
maximum delay occurs when the input condition occurs just after H1 falling.
CDIRx
7
3
CREQx
2
4
CACKx
5
1
CSTRBx
4.1
Valid Data Out
CxDx
6
CRDYx
4.2
= When signal is an input (clear = when signal is an output).
NOTE A: Before the token exchange, CREQx and CRDYx are output signals asserted by the ’320C44 receiving data. CACKx, CSTRBx, and
CxD7 – CxD0 are input signals asserted by the device sending data to the ’C44; these are asynchronous with respect to the H1 clock
of the receiving ’320C44. After token exchange, CACKx, CSTRBx, and CxD7 – CxD0 become output signals, and CREQx and CRDYx
become inputs.
Figure 25. Communication-Token Transfer Sequence, Input to an Output Port [P = tc(H)]
38
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timing for communication-token transfer sequence, output to an input port [P = tc(H)]
(see Figure 26)†
NO.
1‡
td(CRQL - CAL)T
2‡
td(CRDYL - CAL)T
td(CAL - CD)I
3
MIN
MAX
UNIT
Delay time, CREQx low to start of CACKx going low for
token-request-acknowledge
P+5
2P + 22
ns
Delay time, CRDYx low at end of word-transfer out to start of CACKx going low
P+6
2P + 27
ns
Delay time, start of CACKx going low to CxDx change from outputs to inputs
0.5P – 8
0.5P + 8
ns
Delay time, start of CACKx going low to CRDYx change from an input to output,
high level
0.5P – 8
0.5P + 8
ns
4
td(CAL - CRDY)T
5‡
6‡
td(CRQH - CRQ)T
td(CRQH - CA)T
Delay time, CREQx high to CREQx change from an input to output, high level
4
22
ns
Delay time, CREQx high to CACKx change from output to an input
4
22
ns
7‡
8‡
td(CRQH - CS)T
td(CRQH - CRQL)T
Delay time, CREQx high to CSTRBx change from output to an input
4
22
ns
P–4
2P + 8
ns
Delay time, CREQx high to CREQx low for the next token-request
9
td(CAL - CDIRH)
Delay time, CACKx low to CDIRx high, change from output to input
0.5P – 8 0.5P + 10
ns
† These values are characterized but not tested.
‡ These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal
pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the
maximum delay occurs when the input condition occurs just after H1 falling.
CDIRx
9
8
CREQx
1
5
CACKx
6
CSTRBx
3
7
CxDx
Valid Data
Valid Data
4
CRDYx
2
= When signal is an input (clear = when signal is an output).
NOTE A: Before the token exchange, CACKx, CSTRBx, and CxD7 – CxD0 are asserted by the ’C44 sending data. CREQx and CRDYx are
input signals asserted by the ’C44 receiving data and are asynchronous with respect to the H1 clock of the sending ’C44. After token
exchange, CREQx and CRDYx become outputs, and CSTRBx, CACKx, and CxD7 – CxD0 become inputs.
Figure 26. Communication-Token Transfer Sequence, Output to an Input Port [P = tc(H)]
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
39
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
timer-pin timing (see Note 15 and Figure 27)
NO.
1
2
MIN
tsu(TCLK-H1L)
th(H1L-TCLK)
Setup time, TCLKx before H1 low
MAX
10
Hold time, TCLKx after H1 low
ns
0
3
td(H1H-TCLK) Delay time, TCLKx valid after H1 high
NOTE 15: Period and polarity are specified by contents of internal control registers.
UNIT
ns
13
ns
H3
H1
2
3
1
3
TCLKx
Figure 27. Timer-Pin Timing Cycle
timing for IEEE-1149.1 test access port (see Figure 28)
TMS320C44 - 50
NO
NO.
1
MIN
MIN
MAX
UNIT
tsu(TMS - TCKH)
th(TCKH-TMS)
Setup time, TMS / TDI to TCK high
10
10
ns
2
Hold time, TMS / TDI from TCK high
5
5
ns
3
td(TCKL - TDOV)
Delay time, TCK low to TDO valid
0
TCK
1
TMS/TDI
3
2
TDO
Figure 28. IEEE-1149.1 Test Access Port Timings
40
MAX
TMS320C44 - 60
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
0
12
ns
TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
MECHANICAL DATA
PDB (S-PQFP-G304)
PLASTIC QUAD FLATPACK (DIE-DOWN)
228
153
229
152
Heat slug
0,27
0,17
0,08 M
0,50
0,13 NOM
304
77
1
76
37,50 TYP
40,20
SQ
39,80
42,80
SQ
42,40
Gage Plane
0,25
0,25 MIN
4,00
3,60
0°– 7°
0,75
0,50
Seating Plane
0,08
4,50 MAX
4040148 / B 10/94
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Thermally enhanced molded plastic package with a heat slug (HSL)
Falls within JEDEC MO-143
Thermal Resistance Characteristics
Parameter
°C / W
Air Flow LFPM
Parameter
°C / W
Air Flow LFPM
RΘJC
RΘJA
0.8
N /A
12.1
250
16.0
0
RΘJA
RΘJA
10.0
500
RΘJA
14.2
100
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
41
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated