TI TPA6012A4PWPR

TPA6012A4
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SLOS636 – OCTOBER 2009
3-W STEREO AUDIO POWER AMPLIFIER
WITH ADVANCED DC VOLUME CONTROL
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FEATURES
1
•
2
•
•
•
•
•
DESCRIPTION
Advanced 32 Steps DC Volume Control
– Steps From –40 dB to 18 dB
– Fade Mode
– –85-dB Mute Mode
3 W Into 3-Ω Speakers
Differential Inputs
Headphone Mode
Pin-to-Pin Compatible With TPA6011A4 and
TPA6013A4
24-Pin PowerPAD™ Package (PWP)
The TPA6012A4 is a stereo audio power amplifier
that drives 3 W/channel of continuous RMS power
into a 3-Ω load. Advanced dc volume control
minimizes external components and allows BTL
(speaker) volume control and SE (headphone)
volume control. LCD monitors and notebook benefit
from the integrated feature set that minimizes
external components without sacrificing functionality.
To simplify design, the speaker volume level is
adjusted by applying a dc voltage to the VOLUME
terminal. To ensure a smooth transition between
active and shutdown modes, a fade mode ramps the
volume up and down.
APPLICATIONS
•
•
•
LCD Monitors
Notebook PC
All-in-One PC
The 24-pin PowerPAD™ package (PWP) enchances
thermal performance.
APPLICATION CIRCUIT
DC VOLUME CONTROL
GAIN (BTL)
vs
VOLUME VOLTAGE
Right
Speaker
1
ROUT+
PGND
SE/BTL
2
23
Right Positive C
Differential i
Input Signal
0.47 mF
5
Right Negative C
Differential i
Input Signal
0.47 mF
6
RIN+
VOLUME
RIN–
AGND
BYPASS
8
Left Positive C
0.47 mF
Differential i
Input Signal
VDD
9
0.47 mF
21
−10
In From DAC
or
Potentiometer
(DC Voltage)
−20
18
C(BYP)
0.47 mF
FADE
16
15
1 kW
System Control
LIN+
NC
11
12
PVDD
LOUT−
LOUT+
PGND
−40
−60
−70
LIN–
SHUTDOWN
−30
−50
17
Headphones
0.47 mF
0.47 mF
0
1 kW
PVDD
VDD
Volume Up
Volume Down
10
VDD
7
Power Supply
20
100 kW
3
Left Negative C
Differential i
Input Signal
CO
330 mF
ROUT−
0.47 mF
Power Supply
100 kW
Gain − dB
CS
10 mF
VDD
24
−90
CO
330 mF
0.0
4, 10, 19, 20, 22
14
13
VDD = 5.0 V
BTL Output
RL = No Load
−80
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Volume [Pin 21] − V
Left
Speaker
S001
Figure 1. Application Circuit and DC Volume Control
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPA6012A4
SLOS636 – OCTOBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS
PACKAGE
TA
24-PIN TSSOP (PWP)
–40°C to 85°C
TPA6012A4PWP
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VSS
Supply voltage, VDD, PVDD
–0.3 V to 6 V
VI
Input voltage, RIN+, RIN–, LIN+,LIN–
–0.3 V to VDD+0.3 V
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Operating junction temperature range
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 85°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE (1)
(1)
2
PACKAGE
TA = 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PWP
2.7 mW
21.8 mW/°C
1.7 W
1.4 W
All characterization is done using an external heatsink with θSA= 25°C/W. The resulting derating factor
is 22.2 mW/°C.
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SLOS636 – OCTOBER 2009
RECOMMENDED OPERATING CONDITIONS
VSS
MIN
MAX
4
5.5
Supply voltage, VDD, PVDD
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
SE/BTL, FADE
UNIT
V
0.8 x VDD
V
2
V
SHUTDOWN
SE/BTL, FADE
0.6 x VDD
SHUTDOWN
V
0.8
V
85
°C
TYP
MAX
UNIT
–40
ELECTRICAL CHARACTERISTICS
TA = 25°C, VDD = PVDD = 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2
30
mV
VDD = 5.5 V, Gain = 18 dB, SE/BTL = 0 V
2.6
50
mV
Power supply rejection ratio
VDD = PVDD = 4 V to 5.5 V, Gain = 0 dB
–80
| IIH |
High-level input current (SE/BTL, FADE,
SHUTDOWN, VOLUME)
VDD = PVDD = 5.5 V,
VI = VDD = PVDD
1
µA
| IIL |
Low-level input current (SE/BTL, FADE,
SHUTDOWN, VOLUME)
VDD = PVDD = 5 V, VI = 0 V
1
µA
| VOO |
Output offset voltage (measured differentially)
PSRR
IDD
Supply current, no load
VDD = 5.5 V, Gain = 0 dB, SE/BTL = 0 V
dB
VDD = PVDD = 5 V, SE/BTL = 0 V,
SHUTDOWN = 2 V
6.7
9
VDD = PVDD = 5 V, SE/BTL = 5 V,
SHUTDOWN = 2 V
4.5
6
mA
IDD
Supply current, max power into a 3-Ω load
VDD = 5 V = PVDD, SE/BTL = 0 V,
SHUTDOWN = 2 V, RL = 3 Ω,
PO = 2 W, stereo
1.5
IDD(SD)
Supply current, shutdown mode
SHUTDOWN = 0 V
10
ARMS
25
µA
OPERATING CHARACTERISTICS
TA = 25°C, VDD = PVDD = 5 V, RL = 3 Ω, Gain = 6 dB, Stereo (unless otherwise noted)
PARAMETER
PO
THD+N
Output power
Total harmonic distortion + noise
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THD = 1%, f = 1 kHz, RL = 16 Ω (SE)
195
mW
THD = 10%, f = 1 kHz, RL = 16 Ω (SE)
235
mW
THD = 1%, f = 1 kHz, RL = 3 Ω (BTL)
2.0
THD = 10%, f = 1 kHz, VDD = 5.5 V, RL =3 Ω (BTL)
3.2
PO = 0.9 W, RL = 8 Ω (BTL), f = 20 Hz to 20 kHz
<0.1%
PO = 0.1 W, RL = 16 Ω (SE), f = 20 Hz to 20 kHz
0.03%
W
High-level output voltage
RL = 8 Ω, Measured between output and VDD = 5.5 V
700
mV
VOL
Low-level output voltage
RL = 8 Ω, Measured between output and GND,
VDD = 5.5 V
400
mV
V(Bypass)
Bypass voltage (Nominally VDD/2)
Measured at pin 17, No load, VDD = 5.5 V
VOH
Supply ripple rejection ratio
f = 1 kHz, Gain = 0 dB, C(BYP) = 1 µF
Crosstalk
ZI
Noise output voltage
f = 20 Hz to 20 kHz, Gain = 0 dB,
C(BYP) = 1 µF
Input impedance (see Figure 20)
VOLUME = 5 V
2.65
2.75
2.85
V
BTL (4Ω)
–66
dB
SE (32Ω)
–60
dB
BTL
110
dB
SE
102
dB
BTL
36
µVRMS
12
kΩ
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SLOS636 – OCTOBER 2009
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PWP Package
(Top View)
PGND
ROUT−
PVDD
1
24
2
23
3
22
NC
RIN+
RIN–
VDD
4
21
LIN–
LIN+
NC
PVDD
LOUT−
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
ROUT+
SE/BTL
NC
VOLUME
NC
NC
AGND
BYPASS
FADE
SHUTDOWN
LOUT+
PGND
P0110-02
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BYPASS
17
I
Tap to voltage divider for internal mid-supply bias generator used for analog reference
FADE
16
I
Places the amplifier in fade mode if a logic low is placed on this terminal; normal operation if a logic high is
placed on this terminal.
AGND
18
–
Analog power supply ground
LIN-
8
I
Left channel negative input for fully differential input.
LIN+
9
I
Left channel positive input for fully differential input.
LOUT–
12
O
Left channel negative audio output
LOUT+
14
O
Left channel positive audio output.
NC
4,
10,
19,
20,
22
–
No connection
PGND
1, 13
–
Power ground
PVDD
3, 11
–
Supply voltage terminal for power stage
RIN+
5
I
Right channel positive input for fully differential input.
RIN–
6
I
Right channel negative input for fully differential input.
ROUT–
2
O
Right channel negative audio output
ROUT+
24
O
Right channel positive audio output
SE/BTL
23
I
Output control. When this terminal is high, SE outputs are selected. When this terminal is low, BTL outputs
are selected.
SHUTDOWN
15
I
Places the amplifier in shutdown mode if a TTL logic low is placed on this terminal
VDD
7
–
Supply voltage terminal
DC VOLUME
21
I
Terminal for dc volume control. DC voltage range is 0 to VDD.
4
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SLOS636 – OCTOBER 2009
FUNCTIONAL BLOCK DIAGRAM
RIN+
_
_
+
ROUT+
+
RIN-
BYP
+
_
BYP
_
+
BYP
SE/BTL
ROUTEN
SE/BTL
Output
Control
VOLUME
FADE
PVDD
PGND
VDD
Power
Management
32-Step
Volume
Control
BYPASS
SHUTDOWN
AGND
LIN_
_
+
LOUT-
+
LIN+
BYP
+
_
BYP
_
+
BYP
LOUT+
EN
SE/BTL
NOTE: All resistor wipers are adjusted with 32 step volume control.
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Table 1. DC Volume Control (BTL Mode, VDD = 5 V) (1)
VOLUME (PIN 21)
(1)
(2)
6
FROM (V)
TO (V)
GAIN OF AMPLIFIER
(Typ) (2)
0.00
0.26
–85
0.33
0.37
–40
0.44
0.48
–34
0.56
0.59
–31
0.67
0.70
–28
0.78
0.82
–25
0.89
0.93
–22
1.01
1.04
–19
1.12
1.16
–16
1.23
1.27
–13
1.35
1.38
–10
1.46
1.49
–7
1.57
1.60
–4
1.68
1.72
–2
1.79
1.83
0
1.91
1.94
2
2.02
2.06
4
2.13
2.17
6
2.25
2.28
8
2.36
2.39
10
2.47
2.50
11
2.58
2.61
12
2.70
2.73
13
2.81
2.83
14
2.92
2.95
14.5
3.04
3.06
15
3.15
3.17
15.5
3.26
3.29
16
3.38
3.40
16.5
3.49
3.51
17
3.60
3.63
17.5
3.71
5.00
18
For other values of VDD, scale the voltage values in the table by a factor of VDD/5.
Tested in production.
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Table 2. DC Volume Control (SE Mode, VDD = 5 V) (1)
VOLUME (PIN 21)
(1)
(2)
FROM (V)
TO (V)
GAIN OF AMPLIFIER
(Typ)
0.00
0.26
–85
0.33
0.37
–46
0.44
0.48
–40
0.56
0.59
–37
0.67
0.70
–34
0.78
0.82
–31
0.89
0.93
–28
1.01
1.04
–25
1.12
1.16
–22
1.23
1.27
–19
1.35
1.38
–16
1.46
1.49
–13
1.57
1.60
–10
1.68
1.72
–8
1.79
1.83
–6 (2)
1.91
1.94
–4
2.02
2.06
-2
2.13
2.17
0 (2)
2.25
2.28
2
2.36
2.39
4
2.47
2.50
5
2.58
2.61
6 (2)
2.70
2.73
7
2.81
2.83
8
2.92
2.95
8.5
3.04
3.06
9
3.15
3.17
9.5
3.26
3.29
10
3.38
3.40
10.5
3.49
3.51
11
3.60
3.63
11.5
3.71
5.00
12
For other values of VDD, scale the voltage values in the table by a factor of VDD/5.
Tested in production. Remaining gain steps are specified by design.
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TYPICAL CHARACTERISTICS
Test conditions (unless otherwise noted) for typical operating performance:
VDD = 5.0 V, CIN = 1 µF, CBYPASS = 1 µF, TA = 27°C, SHUTDOWN = VDD
Table of Graphs
Gain (BTL)
vs Volume voltage
THD+N
Total harmonic distortion plus noise (BTL)
THD+N
Total harmonic distortion plus noise (SE)
Figure 1
vs Frequency
Figure 2, Figure 3, Figure 4
vs Output power
Figure 7, Figure 8, Figure 9
vs Frequency
Figure 5, Figure 6
vs Output power
Figure 10
vs Output voltage
Figure 11
PD
Total power dissipation (BTL)
vs Total output power
Figure 12
PD
Total power dissipation (SE)
vs Total output power
Figure 13
Crosstalk (BTL)
vs Frequency
Figure 14
vs Frequency
Figure 15
Power supply rejection ratio (BTL)
vs Frequency
Figure 16
PSRR
Power supply rejection ratio (SE)
vs Frequency
Figure 17
IDD
Supply current (BTL)
vs Total output power
Figure 18
IDD
Supply current (SE)
vs Total output power
Figure 19
Input impedance
vs Gain
Figure 20
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
10
10
PO = 500 mW
PO = 1 W
PO = 1.5 W
VDD = 5.0 V
RL = 3 Ω
BTL Output
Gain = 6 dB
1
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10k
20k
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
Crosstalk (SE)
PSRR
1
0.1
0.01
0.001
20
Figure 2.
8
PO = 250 mW
PO = 1 W
PO = 1.5 W
VDD = 5.0 V
RL = 4 Ω
BTL Output
Gain = 6 dB
100
1k
f − Frequency − Hz
10k
20k
Figure 3.
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TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
FREQUENCY
10
10
0.1
0.01
0.001
100
1k
f − Frequency − Hz
10k
20k
VDD = 5.0 V
RL = 32 Ω
SE Output
Gain = 0 dB
1
Po = 10 mW
Po = 40 mW
Po = 80 mW
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
10k
Figure 4.
Figure 5.
TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
10
100
VO = 500 mVRMS
VO = 1.0 VRMS
VO = 1.75 VRMS
VDD = 5.0 V
RL = 10 kΩ
SE Output
Gain = 0 dB
1
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
20
0.1
0.01
0.001
20
THD+N − Total Harmonic Distortion + Noise − %
PO = 250 mW
PO = 500 mW
PO = 900 mW
VDD = 5.0 V
RL = 8 Ω
BTL Output
Gain = 6 dB
1
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
FREQUENCY
100
1k
f − Frequency − Hz
10k
20k
RL = 3 Ω
BTL Output
Gain = 6 dB
VDD = 4.5 V
VDD = 5.0 V
VDD = 5.5 V
10
1
0.1
0.01
1m
10m
100m
1
4
Figure 6.
Figure 7.
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
OUTPUT POWER
100
100
RL = 4 Ω
BTL Output
Gain = 6 dB
VDD = 4.5 V
VDD = 5.0 V
VDD = 5.5 V
10
1
0.1
0.01
1m
10m
100m
20k
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
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1
3
RL = 8 Ω
BTL Output
Gain = 6 dB
VDD = 4.5 V
VDD = 5.0 V
VDD = 5.5 V
10
1
0.1
0.01
1m
10m
100m
PO − Output Power − W
PO − Output Power − W
Figure 8.
Figure 9.
1
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100
TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
OUTPUT VOLTAGE
RL = 16 Ω
RL = 32 Ω
VDD = 5.0 V
SE Output
Gain = 0 dB
10
1
0.1
0.01
100u
1m
10m
100m
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
TOTAL HARMONIC DISTORTION + NOISE (SE)
vs
OUTPUT POWER
300m
100
10
VDD = 5.0 V
RL = 10 kΩ
SE Output
Gain = 0 dB
1
0.1
0.01
0.001
0.0
500.0m
Figure 11.
TOTAL POWER DISSIPATION (BTL)
vs
TOTAL OUTPUT POWER
TOTAL POWER DISSIPATION (SE)
vs
TOTAL OUTPUT POWER
3.5
3.0
2.5
2.0
1.5
1.0
RL = 3 Ω
RL = 4 Ω
RL = 8 Ω
0.0
0.0
PD − Total Power Dissipation − W
PD − Total Power Dissipation − W
2.0
200m
VDD = 5.0 V
BTL Output
Gain = 6 dB
0.5
VDD = 5.0 V
SE Output
Gain = 0 dB
175m
150m
125m
100m
75m
50m
RL = 16 Ω
RL = 32 Ω
25m
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
5.0
100m
200m
0
Figure 12.
Figure 13.
CROSSTALK (BTL)
vs
FREQUENCY
CROSSTALK (SE)
vs
FREQUENCY
0
RL = 4 Ω
PO = 1 W
BTL Output
Gain = 6 dB
−20
300m
400m
500m
PO − Total Output Power − W
PO − Total Output Power − W
RL = 32 Ω
PO = 50 mW
SE Output
Gain = 0 dB
−20
−40
Crosstalk − dB
−40
Crosstalk − dB
1.5
Figure 10.
4.0
−60
−80
−60
−80
−100
−100
−120
−120
−140
−140
20
100
1k
f − Frequency − Hz
10k
20k
20
Figure 14.
10
1.0
VO − Output Voltage − VRMS
PO − Output Power − W
100
1k
f − Frequency − Hz
10k
20k
Figure 15.
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POWER SUPPLY REJECTION RATIO (BTL)
vs
FREQUENCY
POWER SUPPLY REJECTION RATIO (SE)
vs
FREQUENCY
0
VDD = 5.0 V
RL = 4 Ω
BTL Output
Supply Ripple = 0.2 Vpp Sine Wave
−20
Gain = 6 dB
Gain = 18 dB
PSRR − Power Supply Rejection Ratio − dB
PSRR − Power Supply Rejection Ratio − dB
0
−40
−60
−20
Gain = 0 dB
Gain = 12 dB
−40
−60
−80
−80
20
100
1k
f − Frequency − Hz
10k
20k
20
1.6
1k
f − Frequency − Hz
Figure 17.
SUPPLY CURRENT (BTL)
vs
TOTAL OUTPUT POWER
SUPPLY CURRENT (SE)
vs
TOTAL OUTPUT POWER
10k
20k
125m
VDD = 5.0 V
BTL Output
Gain = 6 dB
VDD = 5.0 V
SE Output
Gain = 0 dB
100m
IDD − Supply Current − A
1.4
1.2
1.0
0.8
0.6
0.4
75m
50m
25m
RL = 3 Ω
RL = 4 Ω
RL = 8 Ω
0.2
0.0
0.0
100
Figure 16.
1.8
IDD − Supply Current − A
VDD = 5.0 V
RL = 32 Ω
SE Output
Supply Ripple = 0.2 Vpp Sine Wave
RL = 16 Ω
RL = 32 Ω
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
100m
PO − Total Output Power − W
200m
300m
400m
500m
PO − Total Output Power − W
Figure 18.
Figure 19.
INPUT IMPEDANCE
vs
GAIN
120k
Differential
Single−Ended
Input Impedance − Ω
100k
80k
60k
40k
20k
VDD = 5.0 V
RL = No Load
0
−40 −35 −30 −25 −20 −15 −10 −5
Gain − dB
0
5
10
15
20
Figure 20.
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APPLICATION INFORMATION
SELECTION OF COMPONENTS
Figure 21 and Figure 22 are schematic diagrams of typical LCD monitor application circuits.
Right
Speaker
ROUT+
1
2
23
100 kW
3
Power Supply
1 kW
PVDD
21
Right
Audio Source
Ci
Ci
0.47 mF
0.47 mF
5
6
RIN+
RIN–
VOLUME
AGND
C(BYP)
0.47 mF
7
Ci
In From DAC
or
Potentiometer
(DC Voltage)
18
VDD
0.47 mF
100 kW
ROUT–
0.47 mF
10 mF
CO
330 mF
PGND
SE/BTL
CS
VDD
24
8
VDD
BYPASS
LIN–
FADE
0.47 mF
Headphones
17
16
CO
1 kW
330 mF
Left
Audio Source
Ci
0.47 mF
9
15
LIN+
VDD
Power Supply
11
12
0.47 mF
A.
PVDD
LOUT-
System
SHUTDOWN
Control
4, 19, 20, 22
NC
LOUT+
PGND
14
13
Left
Speaker
A 0.47-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise
signals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Figure 21. Typical TPA6012A4 Application Circuit Using Single-Ended Inputs
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Right
Speaker
ROUT+
1
PGND
SE/BTL
2
CS
Right Negative
Differential Input Signal
100 kW
ROUT–
100 kW
3
Power Supply
CO
330 mF
23
0.47 mF
10 mF
Right Positive
Differential Input Signal
VDD
24
Ci
0.47 mF
5
Ci
0.47 mF
6
1 kW
PVDD
RIN+
RIN–
VOLUME
AGND
21
In From DAC
or
Potentiometer
(DC Voltage)
18
C(BYP)
VDD
0.47 mF
7
VDD
BYPASS
Headphones
17
0.47 mF
Left Negative
Differential Input Signal
Ci
Left Positive
Differential Input Signal
Ci
0.47 mF
8
16
LIN–
1 kW
CO
0.47 mF
9
15
LIN+
VDD
Power Supply
0.47 mF
SHUTDOWN
NC
11
12
A.
FADE
PVDD
LOUT–
LOUT+
PGND
System
Control
4, 10, 19, 20, 22
330 mF
14
Left
Speaker
13
A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noise
signals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Figure 22. Typical TPA6012A4 Application Circuit Using Differential Inputs
SE/BTL OPERATION
The ability of the TPA6012A4 to easily switch between BTL and SE modes is one of its most important cost
saving features. This feature eliminates the requirement for an additional headphone amplifier in applications
where internal stereo speakers are driven in BTL mode but external headphone or speakers must be
accommodated. Internal to the TPA6012A4, two separate amplifiers drive OUT+ and OUT–. The SE/BTL input
controls the operation of the follower amplifier that drives LOUT– and ROUT–. When SE/BTL is held low, the
amplifier is on and the TPA6012A4 is in the BTL mode. When SE/BTL is held high, the OUT– amplifiers are in a
high output impedance state, which configures the TPA6012A4 as an SE driver from LOUT+ and ROUT+. IDD is
reduced by approximately one-third in SE mode. Control of the SE/BTL input can be from a logic-level CMOS
source or, more typically, from a resistor divider network as shown in Figure 23. The trip level for the SE/BTL
input can be found in the recommended operating conditions table.
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RIN+
_
_
+
ROUT+
24
+
Bypass
6
RIN–
Bypass
VDD
+
_
_
ROUT–
2
+
Bypass
100 kW
CO
330 mF
1 kW
EN
SE/BTL
23
100 kW
LOUT+
Figure 23. TPA6012A4 Resistor Divider Network Circuit
Using a 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is inserted. When
closed the 100-kΩ/1-kΩ divider pulls the SE/BTL input low. When a plug is inserted, the 1-kΩ resistor is
disconnected and the SE/BTL input is pulled high. When the input goes high, the OUT– amplifier is shut down
causing the speaker to mute (open-circuits the speaker). The OUT+ amplifier then drives through the output
capacitor, Co, into the headphone jack.
SHUTDOWN MODES
The TPA6012A4 employs a shutdown mode of operation designed to reduce supply current (IDD) to the absolute
minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held
high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute
and the amplifier to enter a low-current state, IDD = 20 µA. SHUTDOWN should never be left unconnected
because amplifier operation would be unpredictable.
Table 3. SE/BTL and Shutdown Functions
INPUTS
(1)
AMPLIFIER STATE
SE/BTL
(1)
SHUTDOWN
OUTPUT
X
Low
Mute
Low
High
BTL
High
High
SE
Inputs should never be left unconnected.
FADE OPERATION
For design flexibility, a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdown
mode and conversely ramp the gain down when going into shutdown. This mode provides a smooth transition
between the active and shutdown states and virtually eliminates any pops or clicks on the outputs.
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When the FADE input is a logic low, the device is placed into fade-on mode. A logic high on this pin places the
amplifier in the fade-off mode. The voltage trip levels for a logic low (VIL) or logic high (VIH) can be found in the
recommended operating conditions table.
When a logic low is applied to the FADE pin and a logic low is then applied on the SHUTDOWN pin, the channel
gain steps down from gain step to gain step at a rate of two clock cycles per step. With a nominal internal clock
frequency of 58 Hz, this equates to 34 ms (1/29 Hz) per step. The gain steps down until the lowest gain step is
reached. The time it takes to reach this step depends on the gain setting prior to placing the device in shutdown.
For example, if the amplifier is in the highest gain mode of 18 dB, the time it takes to ramp down the channel
gain is 1.05 seconds. This number is calculated by taking the number of steps to reach the lowest gain from the
highest gain, or 31 steps, and multiplying by the time per step, or 34 ms.
After the channel gain is stepped down to the lowest gain, the amplifier begins discharging the bypass capacitor
from the nominal voltage of VDD/2 to ground. This time is dependent on the value of the bypass capacitor. For a
0.47-µF capacitor that is used in the application diagram in Figure 21, the time is approximately 500 ms. This
time scales linearly with the value of bypass capacitor. For example, if a 1-µF capacitor is used for bypass, the
time period to discharge the capacitor to ground is twice that of the 0.47-µF capacitor, or 1 second. Figure 22
below is a waveform captured at the output during the shutdown sequence when the part is in fade-on mode.
The gain is set to the highest level and the output is at VDD when the amplifier is shut down.
When a logic high is placed on the SHUTDOWN pin and the FADE pin is still held low, the device begins the
start-up process. The bypass capacitor will begin charging. Once the bypass voltage reaches the final value of
VDD/2, the gain increases from the lowest gain level to the gain level set by the dc voltage applied to the
VOLUME pin.
In the fade-off mode, the output of the amplifier immediately drops to VDD/2 and the bypass capacitor begins a
smooth discharge to ground. When shutdown is released, the bypass capacitor charges up to VDD/2 and the
channel gain returns immediately to the value on the VOLUME terminal. Figure 23 below is a waveform captured
at the output during the shutdown sequence when the part is in the fade-off mode. The gain is set to the highest
level, and the output is at VDD when the amplifier is shut down.
The power-up sequence is different from the shutdown sequence and the voltage on the FADE pin does not
change the power-up sequence. Upon a power-up condition, the TPA6012A4 begins in the lowest gain setting
and steps up every 2 clock cycles until the final value is reached as determined by the dc voltage applied to the
VOLUME pin.
Device Shutdown
Device Shutdown
ROUT+
ROUT+
Figure 24. Shutdown Sequence in the Fade-on
Mode
Figure 25. Shutdown Sequence in the Fade-off
Mode
VOLUME OPERATION
The VOLUME pin controls the BTL volume when driving speakers, and the SE volume when driving
headphones. This pin is controlled with a dc voltage, which should not exceed VDD.
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The output volume increases in discrete steps as the dc voltage increases and decreases in discrete steps as
the dc voltage decreases. There are a total of 32 discrete gain steps of the amplifier and range from –85 dB to
18 dB for BTL operation and –85 dB to 12 dB for SE operation.
Table 1 and Table 2 show a range of voltages for each gain step. There is a gap in the voltage between each
gain step. This gap represents the hysteresis about each trip point in the internal comparator. The hysteresis
ensures that the gain control is monotonic and does not oscillate from one gain step to another. If a
potentiometer is used to adjust the voltage on the control terminals, the gain increases as the potentiometer is
turned in one direction and decreases as it is turned back the other direction. The trip point, where the gain
actually changes, is different depending on whether the voltage is increased or decreased as a result of the
hysteresis about each trip point. The gaps in Table 1 and Table 2 can also be thought of as indeterminate states
where the gain could be in the next higher gain step or the lower gain step depending on the direction the
voltage is changing. If using a DAC to control the volume, set the voltage in the middle of each range to ensure
that the desired gain is achieved.
A pictorial representation of the typical volume control can be found in Figure 26. The graph focuses on three
gain steps with the trip points defined in Table 1 for BTL gain. The dotted line represents the hysteresis about
each gain step.
BTL Gain - dB
14
13
12
2.61
2.70
2.73
2.81
Voltage on VOLUME Pin - V
Figure 26. DC Volume Control Operation
INPUT RESISTANCE
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB
or cutoff frequency also changes by over six times.
Rf
C
Input Signal
IN
Ri
Figure 27. Resistor on Input for Cut-Off Frequency
The input resistance at each gain setting is given in Figure 20.
The –3-dB frequency can be calculated using Equation 1.
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ƒ*3 dB +
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1
2p CR
i
(1)
INPUT CAPACITOR, CI
In the typical application an input capacitor CI is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier RI form a
high-pass filter with the corner frequency determined in Equation 2.
−3 dB
fc(highpass) +
1
2 p Ri C i
fc
(2)
The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit.
Consider the example where RI is 70 kΩ and the specification calls for a flat-bass response down to 40 Hz.
Equation 2 is reconfigured as Equation 3.
1
C +
i
2 p R fc
i
(3)
In this example, CI is 56.8 nF, so one would likely choose a value in the range of 56 nF to 1 µF. A further
consideration for this capacitor is the leakage path from the input source through the input network CI and the
feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that
reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or
ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications as the dc level there is held at VDD/2, which is likely higher
than the source dc level. Note that it is important to confirm the capacitor polarity in the application.
POWER SUPPLY DECOUPLING, C(S)
The TPA6012A4 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents
oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by
using two capacitors of different types that target different types of noise on the power supply leads. For higher
frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic
capacitor, typically 0.1 µF placed as close as possible to the device VDD lead, works best. For filtering
lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio
power amplifier is recommended.
MIDRAIL BYPASS CAPACITOR, C(BYP)
The midrail bypass capacitor C(BYP) is the most critical capacitor and serves several important functions. During
start-up or recovery from shutdown mode, C(BYP) determines the rate at which the amplifier starts up. The second
function is to reduce noise produced by the power supply caused by coupling into the output drive signal. This
noise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR and
THD+N.
Bypass capacitor C(BYP) values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended for
the best THD and noise performance. For the best pop performance, choose a value for C(BYP) that is equal to or
greater than the value chosen for CI. This ensures that the input capacitors are charged up to the midrail voltage
before C(BYP) is fully charged to the midrail voltage.
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OUTPUT COUPLING CAPACITOR, C(C)
In the typical single-supply SE configuration, an output coupling capacitor C(C) is required to block the dc bias at
the output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, the
output coupling capacitor and impedance of the load form a high-pass filter governed by Equation 4.
−3 dB
fc(high) +
1
2 p RL C (C)
fc
(4)
The main disadvantage, from a performance standpoint, is the load impedances are typically small, which drives
the low-frequency corner higher, degrading the bass response. Large values of C(C) are required to pass low
frequencies into the load. Consider the example where a C(C) of 330 µF is chosen and loads vary from 4 Ω, 8 Ω,
32 Ω , 10 kΩ, and 47 kΩ. Table 4 summarizes the frequency response characteristics of each configuration.
Table 4. Common Load Impedances vs Low Frequency
Output Characteristics in SE Mode
C(C)
LOWEST
FREQUENCY
4Ω
330 µF
120 Hz
8Ω
330 µF
60 Hz
RL
32 Ω
330 µF
15 Hz
10,000 Ω
330 µF
0.05 Hz
47,000 Ω
330 µF
0.01 Hz
As Table 4 indicates, most of the bass response is attenuated into a 4-Ω load, an 8-Ω load is adequate,
headphone response is good, and drive into line level inputs (a home stereo for example) is exceptional.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance, the more the real capacitor behaves like an ideal capacitor.
BRIDGE-TIED LOAD vs SINGLE-ENDED LOAD
Figure 28 shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA6012A4 BTL amplifier
consists of two Class-AB amplifiers driving both ends of the load. There are several potential benefits to this
differential drive configuration, but, initially consider power to the load. The differential drive to the speaker
means that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the
voltage swing on the load as compared to a ground referenced load. Plugging 2 x VO(PP) into the power equation,
where voltage is squared, yields 4x the output power from the same supply rail and load impedance (see
Equation 5).
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V(rms) +
Power +
V O(PP)
2 Ǹ2
V(rms)
2
RL
(5)
VDD
VO(PP)
RL
2x VO(PP)
VDD
-VO(PP)
Figure 28. Bridge-Tied Load Configuration
In a typical computer sound channel operating at 5 V, bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power that is a 6-dB improvement, which
is loudness that can be heard. In addition to increased power there are frequency response concerns. Consider
the single-supply SE configuration shown in Figure 29. A coupling capacitor is required to block the dc offset
voltage from reaching the load. These capacitors can be quite large (approximately 33 µF to 1000 µF), so they
tend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting
low-frequency performance of the system. This frequency limiting effect is due to the high-pass filter network
created with the speaker impedance and the coupling capacitance and is calculated with Equation 6.
f(c) +
1
2 p RL C C
(6)
For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
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VDD
-3 dB
VO(PP)
C(C)
RL
VO(PP)
fc
Figure 29. Single-Ended Configuration and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces 4x the output power of the SE
configuration. Internal dissipation versus output power is discussed further in the crest factor and thermal
considerations section.
SINGLE-ENDED OPERATION
In SE mode (see Figure 29), the load is driven from the primary amplifier output for each channel (OUT+).
The amplifier switches single-ended operation when the SE/BTL terminal is held high. This puts the negative
outputs in a high-impedance state, and effectively reduces the amplifier's gain by 6 dB.
BTL AMPLIFIER EFFICIENCY
Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output
stage transistors. There are two components of the internal voltage drop. One is the headroom or dc voltage
drop that varies inversely to output power. The second component is due to the sinewave nature of the output.
The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The
internal voltage drop multiplied by the RMS value of the supply current (IDDrms) determines the internal power
dissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power
supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the
load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 30).
IDD
VO
IDD(avg)
V(LRMS)
Figure 30. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are very
different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified
shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different.
Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which
supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.
The following equations are the basis for calculating amplifier efficiency.
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PL
P SUP
Efficiency of a BTL amplifier +
Where:
2
PL
V rms 2
V
V
+ L
, and VLRMS + P , therefore, P L + P
Ǹ2
RL
2RL
and P SUP + VDD I DDavg
I DDavg + 1
p
and
ŕ
p
0
VP
1
sin(t) dt + p
RL
p
VP
[cos(t)] 0 + 2V P
RL
p RL
Therefore,
P SUP +
2 VDD V P
p RL
(7)
substituting PL and PSUP into Equation 7,
2
Efficiency of a BTL amplifier +
VP
2 RL
2 V DD VP
p RL
+
p VP
4 V DD
Where:
VP +
Ǹ2 PL R L
Therefore,
h BTL +
p
Ǹ2 PL R L
4 V DD
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
(8)
Table 5 employs Equation 8 to calculate efficiencies for four different output power levels. Note that the efficiency
of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in
a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full
output power is less than in the half power range. Calculating the efficiency for a specific system is the key to
proper power supply design. For a stereo 1-W audio system with 8-Ω loads and a 5-V supply, we get an
efficiency of 0.628. Total output power is 2-W. Thus the maximum draw on the power supply is almost 3.25 W.
Table 5. Efficiency vs Output Power in 5-V, 8-Ω BTL Systems
OUTPUT POWER
(W)
EFFICIENCY
(%)
PEAK VOLTAGE
(V)
INTERNAL DISSIPATION
(W)
0.25
31.4
2.00
0.55
0.50
44.4
2.83
0.62
1.00
62.8
4.00
0.59
1.25
(1)
70.2
4.47
(1)
0.53
High peak voltages cause the THD to increase.
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A final point to remember about Class-AB amplifiers (either SE or BTL) is how to manipulate the terms in the
efficiency equation to utmost advantage when possible. Note that in equation 8, VDD is in the denominator. This
indicates that as VDD goes down, efficiency goes up.
CREST FACTOR AND THERMAL CONSIDERATIONS
Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operating
conditions. A typical music CD requires 12 dB to 15 dB of dynamic range, or headroom above the average power
output, to pass the loudest portions of the signal without distortion. In other words, music typically has a crest
factor between 12 dB and 15 dB. When determining the optimal ambient operating temperature, the internal
dissipated power at the average output power level must be used. From the data sheet graph (Figure 5.), one
can see that when the TPA6012A4 is operating from a 5-V supply into a 4-Ω speaker at 1% THD, that output
power is 1.5-W so maximum instantaneous output power is 3-W. Use equation 9 to convert watts to dB.
PW
3 W = 5 dB
PdB = 10Log
= 10Log
1W
Pref
(9)
Subtracting the headroom restriction to obtain the average listening level without distortion yields:
5 dB - 15 dB = –10 dB
(15-dB crest factor)
5 dB - 12 dB = –7 dB
(12-dB crest factor)
5 dB - 9 dB = –4 dB
(9-dB crest factor)
5 dB - 6 dB = -1 dB
(6-dB crest factor)
5 dB - 3 dB = 2 dB
(3-dB crest factor)
To convert dB back into watts use equation 10.
PdB/10
PW = 10
x Pref
(10)
= 48 mW
(18-dB crest factor)
= 95 mW
(15-dB crest factor)
= 190 mW
(12-dB crest factor)
= 380 mW
(9-dB crest factor)
= 750 mW
(6-dB crest factor)
= 1500 mW
(3-dB crest factor)
This is valuable information to consider when attempting to estimate the heat dissipation requirements for the
amplifier system. Comparing the worst case, which is 1.5 W of continuous power output with a 3-dB crest factor,
against 12-dB and 15-dB applications significantly affects maximum ambient temperature ratings for the system.
Using the power dissipation curves for a 5-V, 4-Ω system, the internal dissipation in the TPA6012A4 and
maximum ambient temperatures is shown in Table 6.
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Table 6. TPA6012A4 Power Rating, 5-V, 4-Ω Stereo
(1)
PEAK OUTPUT POWER
(W)
AVERAGE OUTPUT POWER
POWER DISSIPATION
(W/Channel)
MAXIMUM AMBIENT
TEMPERATURE
3
1500 mW (3 dB)
1.26
37°C
3
750 mW (6 dB)
1.20
42°C
3
380 mW (9 dB)
1.00
59°C
3
190 mW (12 dB)
0.79
79°C
3
95 mW (15 dB)
0.60
96°C (1)
3
48 mW (18 dB)
0.44
110°C (1)
Package limited to 85°C ambient.
Table 7. TPA6012A4 Power Rating, 5-V, 8-Ω Stereo
(1)
PEAK OUTPUT POWER
(W)
AVERAGE OUTPUT POWER
POWER DISSIPATION
(W/Channel)
MAXIMUM AMBIENT
TEMPERATURE
2.2
1100 mW (3-dB crest factor)
0.57
99°C (1)
2.2
876 mW (4-dB crest factor)
0.61
95°C (1)
2.2
440 mW (7-dB crest factor)
0.62
95°C (1)
2.2
220 mW (10-dB crest factor)
0.53
103°C (1)
Package limited to 85°C ambient.
The maximum dissipated power (PD(max)) is reached at a much lower output power level for an 8-Ω load than for
a 4-Ω load. As a result, this simple formula for calculating PD(max) may be used for an 8-Ω application.
2V2
P D(max) +
DD
p 2R L
(11)
However, in the case of a 4-Ω load, the PD(max) occurs at a point well above the normal operating power level.
The amplifier may therefore be operated at a higher ambient temperature than required by the PD(max) formula for
a 4-Ω load.
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the N package with an external heatsink is shown in the dissipation rating table. Use Equation 12 to convert
this to θJA..
1
1
o
= 45 C/W
=
qJA =
0.0222
Derating Factor
(12)
To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are per
channel, so the dissipated power needs to be doubled for two channel operation. Given θJA, the maximum
allowable junction temperature, and the total internal dissipation, the maximum ambient temperature can be
calculated using Equation 13. The maximum recommended junction temperature for the TPA6012A4 is 150°C.
The internal dissipation figures are taken from the Power Dissipation vs Output Power graphs.
TA Max = TJ Max - qJA PD
o
= 150 - 45 (0.6 x 2) = 96 C(15-dB crest factor)
(13)
NOTE
Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor per
channel.
Table 6 and Table 7 show that some applications require no airflow to keep junction temperatures in the
specified range. The TPA6012A4 is designed with thermal protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to the IC. Table 6 and Table 7 were calculated for maximum
listening volume without distortion. When the output level is reduced the numbers in the table change
significantly. Also, using 8-Ω speakers increases the thermal performance by increasing amplifier efficiency.
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPA6012A4
23
PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPA6012A4PWP
ACTIVE
HTSSOP
PWP
24
TPA6012A4PWPR
ACTIVE
HTSSOP
PWP
24
60
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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