TPIC6596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS096 – APRIL 2000 D D D D D D D D Low rDS(on) . . . 1.3 Ω Typ Avalanche Energy . . . 75 mJ Eight Power DMOS Transistor Outputs of 250-mA Continuous Current 1.5-A Pulsed Current Per Output Output Clamp Voltage at 45 V Enhanced Cascading for Multiple Stages All Registers Cleared With Single Input Low Power Consumption DW OR N PACKAGE (TOP VIEW) PGND VCC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 SRCLR G PGND description The TPIC6596 is a monolithic, high-voltage, highcurrent power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 PGND LGND SER OUT DRAIN7 DRAIN6 DRAIN5 DRAIN4 SRCK RCK PGND logic symbol† G RCK SRCLR SRCK 9 EN3 12 8 13 C2 R SRG8 C1 4 3 This device contains an 8-bit serial-in, parallel-out DRAIN0 2 1D SER IN 5 shift register that feeds an 8-bit D-type storage DRAIN1 6 register. Data transfers through both the shift and DRAIN2 storage registers on the rising edge of the 7 DRAIN3 shift-register clock (SRCK) and the register clock 14 DRAIN4 (RCK) respectively. The storage register transfers 15 data to the output buffer when shift-register clear DRAIN5 16 (SRCLR) is high. When SRCLR is low, all DRAIN6 17 registers in the device are cleared. When output DRAIN7 2 enable (G) is held high, all data in the output 18 SER OUT buffers is held low and all drain outputs are off. When G is held low, data from the storage register † This symbol is in accordance with ANSI/IEEE Std 91-1984 is transparent to the output buffers. The serial and IEC Publication 617-12. output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. Outputs are low-side, open-drain DMOS transistors with output ratings of 45 V and 250-mA continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS-transistor outputs have sink current capability. Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1, 10, 11, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between the logic and load circuits. The TPIC6596 is characterized for operation over the operating case temperature range of – 40°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 1 TPIC6596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS096 – APRIL 2000 logic diagram (positive logic) G RCK SRCLR 9 12 4 8 D SRCK SER IN 13 C1 D C2 CLR CLR 5 3 D C1 D C2 CLR CLR D C1 D C2 CLR CLR D D C1 C2 CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR 6 7 14 15 16 17 1, 10, 11, 20 D C1 18 CLR 2 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 SER OUT DRAIN0 DRAIN1 DRAIN2 DRAIN3 DRAIN4 DRAIN5 DRAIN6 DRAIN7 PGND TPIC6596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS096 – APRIL 2000 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 45 V Input 25 V 12 V 12 V PGND LGND LGND absolute maximum ratings over recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 V Continuous source-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Pulsed source-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Pulsed drain current, each output, all outputs on, IDn, TA = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 750 mA Continuous drain current, each output, all outputs on, IDn, TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA Peak drain current single output, IDM,TA = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mJ Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to LGND and PGND. 2. Each power DMOS source is internally connected to PGND. 3. Pulse duration ≤ 100 µs, duty cycle ≤ 2 % 4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 100 mH, IAS = 1 A (see Figure 4). DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 125°C POWER RATING DW 1125 mW 9.0 mW/°C 225 mW N 1150 mW 9.2 mW/°C 230 mW POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 3 TPIC6596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS096 – APRIL 2000 recommended operating conditions over recommended operating temperature range (unless otherwise noted) Logic supply voltage, VCC High-level input voltage, VIH MIN MAX 4.5 5.5 UNIT V 0.85 VCC Low-level input voltage, VIL V 0.15 VCC Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) – 1.8 1.5 V A Setup time, SER IN high before SRCK↑, tsu (see Figure 2) 10 ns Hold time, SER IN high after SRCK↑, th (see Figure 2) 10 ns Pulse duration, tw (see Figure 2) 20 Operating case temperature, TC – 40 ns °C 125 NOTES: 3. Pulse duration ≤ 100 µs, duty cycle ≤ 2% 5. Technique should limit TJ – TC to 10°C maximum. electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted) PARAMETER V(BR)DSX VSD Drain-source breakdown voltage TEST CONDITIONS Source-drain diode forward voltage ID = 1 mA IF = 250 mA, VOH High-level output voltage, g g , SER OUT IOH = – 20 mA, VCC = 4.5 V IOH = – 4 mA, VCC = 4.5 V VOL Low-level output voltage, g , SER OUT IOH = 20 mA, VCC = 4.5 V IOH = 4 mA, VCC = 4.5 V VDS = 15 V V(hys) IIH Input hysteresis IIL ICCL Low-level input current ICC(FRQ) Logic supply current frequency IN Nominal current IDSX Off state drain current Off-state rDS(on) Static drain-source on-state resistance NOTES: 3. 5. 6. 7. High-level input current Logic supply current VCC = 5.5 V, VCC = 5.5 V, See Note 3 MAX 0.85 4.4 4.49 4.1 4.3 TC = 125°C VCC = 4.5 V TC = 125°C, 1 See Notes 5 and 6 and Figures 9 and 10 V V 0.002 0.1 0.2 0.4 1.3 See Notes 5, 6, and 7 UNIT V V V 1 µA –1 µA 15 100 µA 0.6 5 mA VI = VCC VI = 0 VDS(on) = 0.5 V, IN = ID, TC = 85°C VDS = 40 V ID = 250 mA, VCC = 4.5 V ID = 500 mA, TYP 45 IO = 0, All inputs low fSRCK = 5 MHz, IO = 0, CL = 30 pF, See Figures 1, 2, and 6 VDS = 40 V, ID = 250 mA, MIN 250 mA 0.05 1 0.15 5 1.3 2 2 3.2 µA Ω VCC = 4.5 V 1.3 2 Pulse duration ≤ 100 µs, duty cycle ≤ 2% Technique should limit TJ – TC to 10°C maximum. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85°C. 4 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 TPIC6596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS096 – APRIL 2000 switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output from G tr tf Rise time, drain output Propagation delay time, high-to-low-level output from G MIN TYP CL = 30 pF,, ID = 250 mA,, See Figures 1, 2, and 11 Fall time, drain output tpd Propagation delay time, SRCK↓ to SER OUT CL = 30 pF, See Figure 2 f(SRCK) Serial clock frequency CL = 30 pF, See Note 8 ta trr Reverse-recovery-current rise time ID = 250 mA, ID = 250 mA, UNIT ns 200 ns 230 ns 170 ns 50 ns 5 IF = 250 mA,, di/dt = 20 A/µs, µ , See Notes 5 and 6 and Figure 3 Reverse-recovery time MAX 650 100 MHz ns 300 NOTES: 5. Technique should limit TJ – TC to 10°C maximum. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second stage. The clock period allows SRCK → SER OUT propagation delay and setup time plus some timing margin. thermal resistance PARAMETER RθJA TEST CONDITIONS Thermal resistance, resistance junction-to-ambient junction to ambient DW package MIN 111 All 8 outputs with equal power N package MAX 108 UNIT °C/W PARAMETER MEASUREMENT INFORMATION 24 V 5V 7 2 8 SRCLR 12 9 DRAIN SER IN 4 3 2 1 0 4 –7, 14 –17 5V G Output G 0V 5V 0V 5V SER IN CL = 30 pF (see Note B) RCK RCK 0V 5V SRCLR 0V LGND PGND 19 5V 0V RL = 95 Ω DUT 3 5 ID VCC 13 SRCK Word Generator (see Note A) 6 SRCK 1, 10, 11, 20 24 V DRAIN1 0.5 V VOLTAGE WAVEFORMS TEST CIRCUIT Figure 1. Resistive Load Operation POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 5 TPIC6596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS096 – APRIL 2000 PARAMETER MEASUREMENT INFORMATION 5V G 5V 50% 50% 0V 24 V tPLH tPHL 2 8 13 Word Generator (see Note A) 3 12 9 V SRCLR CC SRCK ID 4 –7, 14 –17 DUT Output RL = 95 Ω 90% 10% 10% tr Output CL = 30 pF (see Note B) RCK G LGND PGND 19 0.5 V tf SWITCHING TIMES DRAIN SER IN 24 V 90% 5V 0V tsu 1, 10, 11, 20 TEST CIRCUIT 50% SRCK th 5V SER IN 50% 50% 0V tw INPUT SETUP AND HOLD WAVEFORMS SRCK 50% 50% tpd SER OUT 50% tpd 50% SER OUT PROPAGATION DELAY WAVEFORM Figure 2. Test Circuit, Switching Times, and Voltage Waveforms NOTES: A. Outputs DRAIN 1, 2, 5, and 6 low (PGND), all other DRAIN outputs are at 24 V. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. 6 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 TPIC6596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS096 – APRIL 2000 PARAMETER MEASUREMENT INFORMATION TP K DRAIN 0.25 A 2500 µF 250 V Circuit Under Test di/dt = 20 A/µs + 25 V L = 1 mH IF (see Note B) IF – 0 TP A 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note A) ta 50 Ω trr CURRENT WAVEFORM TEST CIRCUIT NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.25 A, where t1 = 10 µs, t2 = 7 µs, and t3 = 3 µs. B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode 5V 15 V tw 2 8 13 Word Generator (see Note A) 3 SRCK DRAIN RCK See Note B 4 –7, 14 –17 ID VDS G LGND PGND 19 0V IAS = 1 A 100 mH SER IN tav 5V Input ID DUT 12 9 0.11 Ω V SRCLR CC 1, 10, 11, 20 SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT V(BR)DSX = 45 V MIN VDS VOLTAGE AND CURRENT WAVEFORMS NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. Input pulse duration, tw, is increased until peak current IAS = 1 A. Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 75 mJ, where tav = avalanche time. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 7 TPIC6596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS096 – APRIL 2000 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 3.5 10 3 I CC – Supply Current – mA IAS – Peak Avalanche Current – A TJS = 25°C 4 2 1 0.4 VCC = 5 V TJS = – 40°C to 125°C 2.5 2 1.5 1 0.5 0.2 0.1 0.1 0.2 0.4 1 2 4 0 0.1 10 1 Figure 5 MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 2 VCC = 5 V TA = 25°C d = tw/tperiod = 1 ms/tperiod VCC = 5 V 700 600 500 TA = 25°C 300 TA = 100°C 200 TA = 125°C 0 I D – Maximum Peak Drain Current of Each Output – A I D – Maximum Continuous Drain Current of Each Output – mA 800 100 100 Figure 6 MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 400 10 f – Frequency – MHz tav – Time Duration of Avalanche – ms 1.5 d = 5% 1 d = 50% d = 10% 0.5 d = 80% 0 0 1 2 3 4 5 6 7 8 N – Number of Outputs Conducting Simultaneously 0 1 2 3 4 5 6 7 8 N – Number of Outputs Conducting Simultaneously Figure 7 8 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Figure 8 • DALLAS, TEXAS 75265 TPIC6596 POWER LOGIC 8-BIT SHIFT REGISTER SLIS096 – APRIL 2000 TYPICAL CHARACTERISTICS r DS(on) – Static Drain-Source On-State Resistance – Ω r DS(on) – Static Drain-Source On-State Resistance – Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 4 3.5 VCC = 5 V See Note A 3 TC = 125°C 2.5 2 TC = 25°C 1.5 1 TC = – 40°C 0.5 0 0.25 0.5 0.75 1 1.25 1.5 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE 3 ID = 250 mA See Note A TC = 125°C 2.5 2 TC = 25°C 1.5 1 TC = – 40°C 0.5 0 3 4 5 6 7 VCC – Logic Supply Voltage – V ID – Drain Current – A Figure 10 Figure 9 SWITCHING TIME vs FREE-AIR TEMPERATURE 700 tr t – Switching Time – ns 600 tPLH ID = 250 mA See Note A 500 tf 400 300 200 tPHL 100 – 50 0 50 100 150 TA – Free-Air Temperature – °C Figure 11 NOTE A: Technique should limit TJ – TC to 10°C maximum. POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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