TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com 2A Dual Channel Synchronous Step-Down Switcher with Integrated FET ( SWIFT™) Check for Samples: TPS54295 FEATURES APPLICATIONS • • 1 2 • • • • • • • • • • • • • • D-CAP2™ Control Mode – Fast Transient Response – No External Parts Required For Loop Compensation – Compatible with Ceramic Output Capacitors Wide Input Voltage Range : 4.5 V to 18 V Output Voltage Range : 0.76V to 7.0V Highly Efficient Integrated FETs Optimized for Low Duty Cycle Applications – 150 mΩ (High Side) and 100 mΩ (Low Side) High Initial Reference Accuracy Low-Side rDS(on) Loss-Less Current Sensing Adjustable Soft Start Non-Sinking Pre-Biased Soft Start 700 kHz Switching Frequency Cycle-by-Cycle Over-Current Limit Control OCL/OVP/UVP/UVLO/TSD Protections Adaptive Gate Drivers with Integrated Boost PMOS Switch OCP Constant Due To Thermally Compensated rDS(on) with 4000ppm/℃ 16-Pin HTSSOP Auto-Skip Eco-mode™ for High Efficiency at Light Load Point-of-Load Regulation in Low Power Systems for Wide Range of Applications – Digital TV Power Supply – Networking Home Terminal – Digital Set Top Box (STB) – DVD Player/Recorder – Gaming Consoles and Other DESCRIPTION The TPS54295 is a dual, adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54295 enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, and low standby current solution. The main control loops of the TPS54295 use the D-CAP2™ mode control which provides a very fast transient response with no external compensation components. The adaptive on-time control supports seamless transition between PWM mode at higher load conditions and Eco-mode™ operation at light loads. Eco-mode™ allows the TPS54295 to maintain high efficiency during lighter load conditions. The TPS54295 is able to adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR, ceramic capacitors. The device provides convenient and efficient operation with input voltages from 4.5V to 18V. The TPS54295 is available in a 4.4mm×5.0mm 16 pin TSSOP (PWP) package, and is specified for an ambient temperature range from –40°C to 85°C. Input Voltage VO2 = 1.5 V (50 mV/div) 1 VIN1 2 VBST1 3 SW1 C11 VO1 L11 VIN2 16 C32 C31 VO2 C22 4 PGND 5 PGND1 EN1 TPS54295 HTSSOP16 PGND2 13 EN2 PGND 12 C41 R21 L12 SW2 14 C21 R11 C12 VBST2 15 Iout (1 A/div) C42 6 SS1 SS2 11 7 VFB1 VFB2 10 SGND SGND C5 8 GND VREG5 SGND 9 PGND R12 R22 t - Time - 100 ms/div SGND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SWIFT, D-CAP2, Eco-mode, Eco-Mode are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA PACKAGE –40℃ to 85℃ PWP (1) ORDERING PART NUMBER PINS TPS54295PWPR 16 TPS54295PWP OUTPUT SUPPLY ECO PLAN Tape-and-Reel Green (RoHS and no Sb/Br) Tube For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE Input voltage range VIN1, VIN2, EN1, EN2 –0.3 to 20 VBST1, VBST2 –0.3 to 26 VBST1, VBST2 (10ns transient) –0.3 to 28 VBST1–SW1 , VBST2–SW2 –0.3 to 6.5 VFB1, VFB2 –0.3 to 6.5 SW1, SW2 (10ns transient) Electrostatic discharge V –2 to 20 SW1, SW2 Output voltage range UNIT –3 to 22 VREG5, SS1, SS2 –0.3 to 6.5 PGND1, PGND2 –0.3 to 0.3 Human Body Model (HBM) 2 Charged Device Model (CDM) V kV 500 V TA Operating ambient temperature range –40 to 85 °C TSTG Storage temperature range –55 to 150 °C TJ Junction temperature range –40 to 150 °C (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to IC GND terminal. THERMAL INFORMATION THERMAL METRIC (1) TPS54295 PWP (16) PINS θJA Junction-to-ambient thermal resistance 47.5 θJCtop Junction-to-case (top) thermal resistance 27.1 θJB Junction-to-board thermal resistance 20.8 ψJT Junction-to-top characterization parameter 1.0 ψJB Junction-to-board characterization parameter 20.6 θJCbot Junction-to-case (bottom) thermal resistance 2.7 (1) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VALUES Supply input voltage range Input voltage range VIN1, VIN2 MAX UNIT 4.5 18 VBST1, VBST2 –0.1 24 VBST1, VBST2 (10ns transient) –0.1 27 VBST1–SW1, VBST2–SW2 –0.1 5.7 VFB1, VFB2 –0.1 5.7 EN1, EN2 –0.1 18 SW1, SW2 –1.0 V 18 –3 21 VREG5, SS1, SS2 –0.1 5.7 PGND1, PGND2 –0.1 0.1 VO1, VO2 0.76 7.0 SW1, SW2 (10ns transient) Output voltage range MIN V V TA Operating free-air temperature –40 85 °C TJ Operating Junction Temperature –40 150 °C ELECTRICAL CHARACTERISTICS (1) over recommended free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IIN VIN supply current TA = 25°C, EN1 = EN2 = 5 V, VFB1 = VFB2 = 0.8 V 1300 2000 µA IVINSDN VIN shutdown current TA = 25°C, EN1 = EN2 = 0 V 80 150 µA 765 773 mV 115 ppm/℃ 0.35 µA FEEDBACK VOLTAGE VVFBTHLx VFBx threshold voltage TA = 25°C, CH1 = 3.3 V, CH2 = 1.5 V TCVFBx Temperature coefficient On the basis of 25°C (2) –115 758 IVFBx VFBx Input Current VFBx = 0.8 V, TA = 25°C –0.35 0.2 VREG5 OUTPUT VVREG5 VREG5 output voltage TA = 25°C, 6 V < VIN1 < 18 V, IVREG = 5 mA 5.5 V IVREG5 Output current VIN1 = 6 V, VREG5 = 4.0 V, TA = 25°C (2) 75 mA High side switch resistance TA = 25℃, VBSTx-SWx = 5.5 V 150 mΩ 100 mΩ MOSFETs rDS(on)H rDS(on)L Low side switch resistance TA = 25℃ (2) (2) ON-TIME TIMER CONTROL TON1 SW1 On Time SW1 = 12 V, VO1 = 1.2 V 165 ns TON2 SW2 On Time SW2 = 12 V, VO2 = 1.2 V 165 ns (2) 220 ns 220 ns TOFF1 SW1 Min off time TA = 25℃, VFB1 = 0.7 V TOFF2 SW2 Min off time TA = 25℃, VFB2 = 0.7 V (2) ISSC SSx charge current VSSx = 0.5 V, TA = 25℃ TCISSC ISSC temperature coefficient On the basis of 25°C (2) ISSD SSx discharge current VSSx = 0.5 V SOFT START (1) (2) –8.4 –8.0 –4 3 7 –7.6 µA 3 nA/°C 10 mA x means either 1 or 2, e.g. VFBx means VFB1 or VFB2. Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 3 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT UVLO VUVREG5 VREG5 UVLO threshold VREG5 rising 3.83 Hysteresis V 0.6 LOGIC THRESHOLDs VENxH ENx H-level threshold voltage VENxL ENx L-level threshold voltage RENx_IN ENx input resistance 2.0 V 0.4 V ENx = 12V 225 450 900 kΩ LOUT = 2.2 µH (3) 2.7 3.9 4.5 A 115% 120% 125% CURRENT LIMITs IOCL Current limit OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION (UVP, OVP) VOVP Output OVP trip threshold TOVPDEL Output OVP prop delay VUVP Output UVP trip threshold TUVPDEL Output UVP delay time TUVPEN Output UVP enable delay measured on VFBx measured on VFBx 63% 3 10 68% 73% 1.5 UVP enable delay / softstart time x 1.4 x 1.7 µs ms x 2.0 THERMAL SHUTDOWN TSD (3) 4 Thermal shutdown threshold Shutdown temperature (3) Hysteresis (3) 155 25 °C Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com DEVICE INFORMATION HTSSOP PACKAGE (TOP VIEW) 1 VIN1 2 VBST1 3 SW1 4 PGND1 TPS54295 5 EN1 HTSSOP16 6 SS1 7 VFB1 8 GND VIN2 16 VBST2 15 SW 2 14 PGND 2 13 EN2 12 SS2 11 VFB2 10 VREG5 9 PowerPAD PIN FUNCTIONS (1) PIN NAME I/O DESCRIPTION NUMBER VIN1, VIN2 1, 16 I Power inputs and connects to both high side NFET drains. Supply Input for 5.5V linear regulator. VBST1, VBST2 2, 15 I Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between VBSTx and SWx pins. An internal diode is connected between VREG5 and VBSTx SW1, SW2 3, 14 I/O Switch node connections for both the high-side NFETs and low–side NFETs. Input of current comparator. PGND1, PGND2 4, 13 I/O Ground returns for low-side MOSFETs. Input of current comparator. EN1, EN2 5, 12 I Enable. Pull High to enable according converter. SS1, SS2 6, 11 O Soft-Start Programming Pin. Connect Capacitor from SSx pin to GND to program Soft-Start time. VFB1, VFB2 D-CAP2 feedback inputs. Connect to output voltage with resistor divider. 7, 10 I GND 8 I/O Signal GND. Connect sensitive SSx and VFBx returens to GND at a single point. VREG5 9 O Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least 1.0 µF. VREG5 is active when VIN1 is added. Back side I/O Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND. Exposed Thermal Pad (1) x means either 1 or 2, e.g. VFBx means VFB1 or VFB2. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 5 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM VIN1 VIN1 - 32 VBST1 UV1 UV 0.1uF OV1 OV +20 Ref1 SS1 SW1 VO1 PGND1 Err Comp PGND1 VFB1 Ref_OCL PGND1 SW1 OCP1 EN1 EN2 EN Logic SW1 ZC1 EN Logic VIN1 VREG5 GND CH1 Min- off timer 5VREG 1.0 uF CH2 Min- off timer SS1 SS1 SS2 SoftStart SS2 CSS1 CSS2 UV1 UV2 OV1 OV2 UVLO TSD -32 UV Ref1 Ref2 REF UVLO Protection Logic VIN2 VIN2 VBST2 UV2 0.1uF +20 Ref2 SS2 OV VO2 OV2 SW2 Err Comp PGND2 PGND2 VFB2 Ref_OCL PGND2 SW2 OCP2 6 SW2 ZC2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com OVERVIEW The TPS54295 is a 2A/2A dual synchronous step-down (buck) converter with two integrated N-channel MOSFETs for each channel. It operates using D-CAP2™ control mode. The fast transient response of D-CAP2™ control reduces the required output capacitance to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types. DETAILED DESCRIPTION PWM Operation The main control loop of the TPS54295 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ control mode. D-CAP2™ control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off when the internal timer expires. This timer is set by the converter’s input voltage, VINx, and the output voltage, VOx, to maintain a pseudo-fixed frequency over the input voltage range hence it is called adaptive on-time control. The timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage. An internal ramp is added to the reference voltage to simulate output voltage ripple, eliminating the need for ESR induced output ripple from D-CAP™ control. PWM Frequency and Adaptive On-Time Control TPS54295 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54295 runs with a pseudo-fixed frequency of 700 kHz by using the input voltage and output voltage to set the on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage, therefore, when the duty ratio is VOx/VIN, the frequency is constant. Auto-Skip Eco-Mode™ Control The TPS54295 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current decreases from heavy load condition, the inductor current also reduces and eventually comes to the point where its ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when zero inductor current is detected. As the load current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost half as it was in the continuous conduction mode because it takes longer to discharge the output capacitor with smaller load current to the nominal output voltage. The transition point to the light load operation IOx(LL) current can be estimated with Equation 1 with 700-kHz used as fSW. (VINx - VOx ) ´ VOx 1 ´ IOx(LL) = 2 ´ L1x ´ fSW VINx (1) Soft Start and Pre-Biased Soft Start The soft start time is adjustable. When the ENx pin becomes high, 8-µA current begins charging the capacitor which is connected from the SSx pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 2. VFBx voltage is 0.765-V and SSx pin source current is 8-µA. C4x(nF) ´ VFBx(V) C4x(nF) ´ 0.765 V TSS (ms) = = ISS (m A) 8 mA (2) The TPS54295 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than internal feedback voltage VFBx), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx) starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 7 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com Over-Current Protection The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detection control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SWx and PGNDx pins. This voltage is proportional to the switch current and the on-resistance of the FET. To improve the measurement accuracy, the voltage sensing is temperature compensated. During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VINx, VOx, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current IOx. If the sensed voltage on the low-side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is monitored in the same manner. Following are some important considerations for this type of over-current protection. The load current is one half of the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. When the over current condition is removed, the output voltage returns to the regulated value. This protection is non-latching. Over/Under Voltage Protection TPS54295 monitors the resistor divided feedback voltage to detect over and under voltage. If the feedback voltage is higher than 120% of the reference voltage, the OVP comparator output goes high and the circuit latches both the high-side MOSFET driver and the low-side MOSFET driver off. When the feedback voltage is lower than 68% of the reference voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 1.5ms, TPS54295 latches OFF both the high-side MOSFET and the low-side MOSFET drivers. This function is enabled approximately 1.7 times the softstart time after power-on. The OVP and UVP latch off is reset when EN is toggled. UVLO Protection Under-voltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower than the UVLO threshold, the TPS54295 shuts down. As soon as the voltage increases above the UVLO threshold, the converter starts again. Thermal Shutdown TPS54295 monitors its temperature. If the temperature exceeds the threshold value (typically 155°C), the device shuts down. When the temperature falls below the threshold, the IC starts again. When VIN1 starts up and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is lower than 155°C. As long as VIN1 rises, TJ must be kept below 110°C. 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). 200 VIN1 = VIN2 = 12V EN1 = EN2 = ON Ivccsdn - Shutdown Current - mA 180 160 140 120 100 80 60 40 20 0 -50 0 50 100 150 TJ - Junction Temperature - °C Figure 2. Input Shutdown Current vs Junction Temperature 100 3.4 90 3.38 80 3.36 VO - Output Voltage - V EN Input Current - mA Figure 1. Input Current vs Junction Temperature 70 60 50 40 30 3.34 VI = 12 V VI = 18 V 3.32 3.3 3.28 3.26 VI = 5 V 20 3.24 10 3.22 0 3.2 0 5 10 EN Input Voltage - V 15 20 0 Figure 3. EN Current vs EN Voltage (VEN=12V) 0.4 0.6 0.8 1 1.2 1.4 IO - Output Current - A 1.6 1.8 2 Figure 4. VO1=3.3V Output Voltage vs Output Current 1.55 3.4 1.54 3.38 1.53 3.36 VI = 18 V VI = 12 V 1.52 VO - Output Voltage - V VO - Output Voltage - V 0.2 1.51 1.5 1.49 VI = 5 V 1.48 3.34 Io1 = 1 A 3.32 3.3 3.28 Io1 = 10 mA 3.26 1.47 3.24 1.46 3.22 3.2 1.45 IO - Output Current - A 8 10 12 VI - Input Voltage - V Figure 5. VO2=1.5V Output Voltage vs Output Current Figure 6. VO1=3.3V Output Voltage vs Input Voltage 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 2 4 6 14 16 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 20 9 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). 1.55 1.54 Vo1(50 mV/div) VO - Output Voltage - V 1.53 Io2 = 1 A 1.52 1.51 1.5 IO1(1 A/div) Io2 = 10 m A 1.49 1.48 1.47 1.46 1.45 0 2 4 6 8 10 12 VI - Input Voltage - V 14 16 18 20 t - Time - 100 ms/div Figure 7. VO2=1.5V Output Voltage vs Input Voltage Figure 8. VO1=3.3V, 0A to 2A Load Transient Response EN1 (10 V/div) Vo2(50 mV/div) VO1(1 V/div) IO2(1 A/div) SS1 (2 V/div) CSSx = 0.01µF t - Time - 100 ms/div t - Time - 400 ms/div Figure 9. VO2=1.5V, 0A to 2A Load Transient Response Figure 10. VO1=3.3V, SoftStart 100 90 EN2 (10 V/div) VI = 12 V Efficiency - % 80 VO2(0.5 V/div) VI = 18 V VI = 5 V 70 60 50 SS2 (2 V/div) CSS2 = 0.01µF 40 0 0.5 t - Time - 400 ms/div Figure 11. VO2=1.5V, SoftStart 10 1 IO - Output Current - A 1.5 2 Figure 12. VO1=3.3V, Efficiency vs Output Current Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). 100 100 VI = 18 V 90 VI = 12 V 90 80 VI = 5 V 70 Efficiency - % Efficiency - % 80 60 50 40 VI = 12 V VI = 18 V VI = 5 V 70 60 30 20 50 10 40 0 0.001 0.01 IO - Output Current - A 0.1 0 Figure 13. VO1=3.3V, Efficiency vs Output Current 1.5 2 900 90 850 fsw - Switching Frequency - kHz VI = 18 V 80 VI = 12 V 70 Efficiency - % 1 IO - Output Current - A Figure 14. VO1=1.5V, Efficiency vs Output Current 100 60 VI = 5 V 50 40 30 20 750 700 650 600 550 500 450 0 0.001 400 0.01 IO - Output Current - A 0 0.1 900 800 800 fsw - Switching Frequency - kHz 1000 850 700 IO2 = 1 A 650 600 550 500 450 5 10 VI - Input Voltage - V 15 20 Figure 16. VO1=3.3V, SW-frequency vs Input Voltage 900 750 IO1=1 A 800 10 Figure 15. VO2=1.5V, Efficiency vs Output Current fsw - Switching Frequency - kHz 0.5 VI = 12 V 700 600 500 400 300 200 100 400 0 5 10 VI - Input Voltage - V 15 20 Figure 17. VO2=1.5V, SW-frequency vs Input Voltage 0 0.01 0.1 1 IO - Output Current - A 10 Figure 18. VO1=3.3V, SW-frequency vs Output Current Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 11 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). 800 VI = 12 V Vo1 = 3.3 V (10 mV/div) fsw - Switching Frequency - kHz 700 600 500 400 SW1 (5 V/div) 300 200 100 0 0.01 0.1 1 IO - Output Current - A 10 t - Time - 400 ns/div Figure 19. VO2=1.5V, SW-frequency vs Output Current Figure 20. VO1=3.3V, VO1 Ripple Voltage (IO1=2A) VIN1 = 12 V (50 mV/div) Vo2 = 1.5 V (10 mV/div) SW2 (5 V/div) SW1 (5 V/div) t - Time - 400 ns/div t - Time - 400 ns/div Figure 21. VO2=1.5V, Ripple Voltage (IO2=2A) Figure 22. VIN1 Input Voltage Ripple (IO1=2A) VIN2 = 12 V (50 mV/div) SW2 (5 V/div) t - Time - 400 ns/div Figure 23. VIN2 Input Voltage Ripple (IO2=2A) 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com DESIGN GUIDE Step By Step Design Procedure To • • • begin the design process, you must know a few application parameters: Input voltage range Output voltage Output current In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated switching frequency of 700 kHz is used. VINx 12V ± 10% C11 10 mF VO1 1.05 V L11 1.5 mH C31 0.1 mF C21 22 mF x2 1 VIN1 2 VBST1 3 4 VIN2 VBST2 15 PGND C12 10 mF SW2 14 TPS54295 HTSSOP16 VO2 1.8 V C22 22 mF x2 PGND2 13 PGND 5 EN1 EN2 12 6 SS1 SS2 11 7 VFB1 VFB2 10 8 GND VREG5 9 C41 R11 8.25 kW L12 1.5 mH C32 0.1 mF SW1 PGND1 16 C42 SGND SGND R21 22.1 kW C5 1uF R12 30.1 kW R22 22.1 kW PGND SGND SGND Figure 24. Schematic Diagram for the Design Example Output Voltage Resistors Selection The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use 1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOx. To improve the efficiency at very light loads consider using larger value resistors, but too high resistance values will be more susceptible to noise and voltage errors due to the VFBx input current will be more noticeable. æ R1x ö VOx = 0.765 V ´ ç 1+ ÷ è R2x ø (3) Output Filter Selection The output filter used with the TPS54295 is an LC circuit. This LC filter has double pole at: 1 FP = 2p L1x ´ C1x Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 (4) 13 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS545295. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 4 is located below the high frequency zero but close enough that the phase boost provided by the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 1. Table 1. Recommended Component Values OUTPUT VOLTAGE (V) R1x (kΩ) R2x (kΩ) L1x (µH) C2x (µF) 1 6.81 22.1 Cffx (pF) 1.0-1.5 22 - 68 1.05 8.25 22.1 1.0-1.5 22 - 68 1.2 12.7 22.1 1.0-1.5 22 - 68 1.5 21.5 22.1 1.5 22 - 68 1.8 30.1 22.1 5 - 22 1.5 22 - 68 2.5 49.9 22.1 5 - 22 2.2 22 - 68 3.3 73.2 22.1 5 - 22 2.2 22 - 68 5 124 22.1 5 - 22 3.3 22 - 68 For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward capacitor (Cff) in parallel with R1. The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5, Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. For the calculations, use 700 kHz as the switching frequency, fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS current of Equation 7. VINx(MAX) - VOx VOx ´ ΔIL1x = VINx(MAX) L1x ´ fSW (5) IL1xpeak = IOx ΔI + L1x 2 IL1x(RMS) = IOx 2 + (6) 1 DIL1x 2 12 (7) For the above design example, the calculated peak current is 2.46 A and the calculated RMS current is 2.02 A for VO1. The inductor used is a TDK CLF7045-1R5N with a rated current of 7.3A based on the inductance change and of 4.9A based on the temperature rise. The capacitor value and ESR determines the amount of output voltage ripple. The TPS54295 is intended for use with ceramic or other low ESR capacitors. The recommended value range is from 22µF to 68µF. Use Equation 8 to determine the required RMS current rating for the output capacitor(s). VOx ´ (VINx - VOx ) IC2x(RMS) = 12 ´ VINx ´ L1x ´ fSW (8) For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current is 0.19A and each output capacitor is rated for 4A. Input Capacitor Selection The TPS54295 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor of or above 10µF is recommended for the decoupling capacitor. Additionally, 0.1 µF ceramic capacitors from pin 1 and Pin 16 to ground are recommended to improve the stability and reduce the SWx node overshoots. The capacitors voltage rating needs to be greater than the maximum input voltage. 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com Bootstrap Capacitor Selection A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is recommended to use ceramic capacitors with a dielectric of X5R or better. VREG5 Capacitor Selection A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is recommended to use a ceramic capacitor with a dielectric of X5R or better. Thermal Information This 16-pin PWP package incorporates an exposed thermal pad. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB is used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities, refer to the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004. The exposed thermal pad dimensions for this package are shown in the following illustration. Figure 25. Thermal Pad Dimensions Layout Considerations 1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal pad. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. 3. Keep analog and non-switching components away from switching components. 4. Make a single point connection from the signal ground to power ground. 5. Do not allow switching currents to flow under the device. 6. Keep the pattern lines for VINx and PGNDx broad. 7. Exposed pad of device must be soldered to PGND. 8. VREG5 capacitor should be placed near the device, and connected to GND. 9. Output capacitors should be connected with a broad pattern to the PGND. 10. Voltage feedback loops should be as short as possible, and preferably with ground shields. 11. Kelvin connections should be brought from the output to the feedback pin of the device. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 15 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com 12. Providing sufficient vias is preferable for VIN, SW and PGND connections. 13. PCB pattern for VIN, SW, and PGND should be as broad as possible. 14. VIN Capacitor should be placed as near as possible to the device. VIN2 VIN HIGH FREQUENCY BYPASS CAPACITOR ～0.1µF VIN1 1 16 VIN2 VBST 1 2 15 VBST2 SW 1 3 14 SW2 4 13 PGND 2 EN1 5 12 EN2 SS1 6 11 SS2 VFB1 7 10 VFB2 GND 8 9 PGND 1 Symmetrical Layout for CH1 and CH2 VIN INPUT BYPASS CAPACITOR 10µF x2 Switching noise flows through IC and CIN . It avoids the thermal Pad. OUTPUT FILTER CAPACITOR VO2 OUTPUT INDUCTOR Recommend to keep distance more than 3-4mm. (to avoid noise scattering, especially GND plane.) TO ENABLE CONTROL Keep distance more than 1 inch VREG 5 POWER GND To feedback resisters Feedback resisters BIAS CAP GND PLANE 2,3 or bottom layer Via to GND Plane - Blue parts can be placed on the bottom side - Connect the SWx pins through another layer with the indcutor (yellow line) Figure 26. TPS54295 Layout 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 TPS54295 SLVSB01B – OCTOBER 2011 – REVISED DECEMBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers of current version may differ from previous versions. Changes from Original (October 2011) to Revision A Page • Added indication for not production tested parameters. ....................................................................................................... 3 • Added indication for not production tested parameters. ....................................................................................................... 4 • Added Over/Under Voltage Protection Description .............................................................................................................. 8 Changes from Revision A (October 2011) to Revision B Page • Deleted MIN and MAX values from VVREG5 specification ...................................................................................................... 3 • Deleted Line and Load regulation specs from VREG5 specification ....................................................................................... 3 • Added "Ensured by design. Not production tested" annotation to specifications for MOSFETs, ON-TIME TIMER CONTROl, and SOFT START. ............................................................................................................................................. 3 • Deleted MIN and MAX values from VUVREG5 specification .................................................................................................... 4 • Added "VIN = 12 V, TA = 25°C (unless otherwise noted)" to Typical Characteristics conditions statement. ....................... 9 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS54295 17 PACKAGE OPTION ADDENDUM www.ti.com 29-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS54295PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS54295PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54295PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 16 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54295PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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