TPS53014 www.ti.com SLVSBF1 – MAY 2012 Single Synchronous Step-down Controller for Low Voltage Power Rails Check for Samples: TPS53014 FEATURES 1 • 2 • • • • • • • • • D-CAP2™ Mode Control – Fast Transient Response – No External Parts Required For Loop Compensation – Compatible with Ceramic Output Capacitors High Initial Reference Accuracy (±1%) Wide Input Voltage Range: 4.5 V to 28 V Output Voltage Range: 0.77 V to 7.0 V Low-Side RDS(on) Loss-Less Current Sensing Adjustable Soft Start Non-Sinking Pre-Biased Soft Start 500 kHz Switching Frequency Cycle-By-Cycle Over Current Limiting Control Auto-Skip Eco-ModeTM for High Efficiency at Light load • • • • OCL/OVP/UVP/UVLO/TSD Protections Adaptive Gate Drivers with Integrated Boost PMOS Switch Thermally Compensated OCP, 4000 ppm/°C 10 pin VSSOP APPLICATIONS • Point-of-Load Regulation in Low Power Systems for Wide Range of Applications – Digital TV Power Supply – Networking Home Terminal – Digital Set Top Box (STB) – DVD Player / Recorder – Gaming Consoles and Other DESCRIPTION The TPS53014 is a single, adaptive on-time D-CAP2™ mode synchronous buck controller. The TPS53014 enables system designers to complete the suite of various end equipment's power bus regulators with cost effective low external component count and low standby current solution. The main control loop for the TPS53014 uses the D-CAP2™ mode control which provides a very fast transient response with no external compensation components. The Adaptive on-time control supports seamless transition between PWM mode at higher load condition and Eco-mode™ operation at light load. Eco-mode™ allows the TPS53014 to maintain high efficiency during lighter load conditions. The TPS53014 is also able to adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP and ultra-low ESR ceramic capacitors. The device provides convenient and efficient operation with input voltages from 4.5 V to 28 V and output voltage from 0.77 V to 7.0 V. The TPS53014 is available in the 3.0mm x 3.0 mm 10-pin VSSOP (DGS) package, and is specified for an ambient temperature range of –40°C to 85°C. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP2, Eco-mode, Eco-Mode are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS53014 SLVSBF1 – MAY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TYPICAL APPLICATION CIRCUITS VIN TPS53014 VBST 10 DRVH 9 SW 8 EN DRVL 7 VIN PGND 6 1 VFB 2 SS 3 VREG5 EN 4 VIN 5 VOUT ORDERING INFORMATION TA PACKAGE (1) –40°C to 85°C VSSOP (1) ORDERING PART NUMBER TPS53014DGSR PINS 10 TPS53014DGS (1) OUTPUT SUPPLY ECO PLAN Tape-and-Reel Green (RoHS & no Sb/Br) Tube For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS Operating under free-air temperature range (unless otherwise noted) (1) VALUE Input voltage range Output voltage range VIN, EN –0.3 to 30 VBST –0.3 to 36 VBST - SW –0.3 to 6 VFB –0.3 to 6 SW –0.3 to 30 SW (10 nsec transient) –3.0 to 30 DRVH –2 to 36 DRVH - SW –0.3 to 6 DRVL, VREG5, SS –0.3 to 6 PGND UNIT V V –0.3 to 0.3 TA Operating ambient temperature range –40 to 85 °C TSTG Storage temperature range –55 to 150 °C TJ Junction temperature range –40 to 150 °C (1) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 TPS53014 www.ti.com SLVSBF1 – MAY 2012 THERMAL INFORMATION TPS53014 THERMAL METRIC (1) θJA Junction-to-ambient thermal resistance 172.2 θJCtop Junction-to-case (top) thermal resistance 44.0 θJB Junction-to-board thermal resistance 93.0 ψJT Junction-to-top characterization parameter 1.6 ψJB Junction-to-board characterization parameter 91.4 θJCbot Junction-to-case (bottom) thermal resistance n/a (1) UNITS DGS (10 PINS) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS Supply input voltage range Input voltage range Output Voltage range MIN MAX 4.5 28 VBST –0.1 33.5 VBST - SW –0.1 5.5 VFB –0.1 5.5 EN –0.1 28 SW –1.0 28 DRVH –1.0 33.5 DRVH - SW –0.1 5.5 DRVL, VREG5, SS –0.1 5.5 PGND –0.1 0.1 VIN UNIT V V V TA Operating free-air temperature –40 85 °C TJ Operating junction temperature –40 125 °C ELECTRICAL CHARACTERISTICS over recommended free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IIN VIN Supply current IVINSDN VIN Shutdown current VIN current, TA = 25°C, EN = 5V, VVFB = 0.8V, VSW = 0 V 660 VIN current, TA = 25°C, No Load , VEN = 0V, VREG5 = OFF 6.0 μA μA VFB VOLTAGE and DISCHARGE RESISTANCE VVFBTHL VFB Threshold voltage TA = 25°C , VOUT = 1.05 V TCVFB VFB Temperature coefficient Relative to TA = 25°C (1) 765.3 -140 IVFB VFB Input current VFB = 0.8V, TA = 25°C -150 773.0 -10 780.7 mV 140 ppm/°C 100 nA VREG5 OUTPUT VVREG5 VREG5 Output voltage TA=25°C, 6 V < VIN < 28 V, IVREG5 = 5 mA 5.1 V IVREG5 Output current VIN = 5.5V, VVREG5 = 4.0V, TA = 25°C 120 mA OUTPUT: N-CHANNEL MOSFET GATE DRIVERS RDRVH DRVH resistance RDRVL DRVL resistance TD Dead time (1) Source, IDRVH = –50mA, TA = 25°C 3.2 4.7 Sink, IDRVH = 50mA, TA = 25°C 1.4 2.4 Source, IDRVL = –50mA, TA = 25°C 6.9 8.2 Sink, IDRVL = 50mA, TA = 25°C 0.8 1.7 DRVH-low to DRVL-on (1) 15 (1) 20 DRVL-low to DRVH-on Ω Ω ns Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 3 TPS53014 SLVSBF1 – MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT 0.1 0.2 V -7.36 -6.4 -5.44 μA 4.5 5.0 INTERNAL BOOST DIODE VFBST Forward voltage VVREG5-VBST, IF = 10mA, TA = 25°C SOFT START Issc SS Charge current VSS = 0V , TA = 25°C Issd SS Discharge current VSS = 0.5V , TA = 25°C TCISSC ISSC Temperature coefficient Relative to TA = 25°C -4.5 mA 4.5 nA/°C UVLO VUVVREG5 VREG5 UVLO threshold VREG5 Rising 4.0 Hysteresis 0.3 V LOGIC THRESHOLD VENH EN H-level threshold voltage VENL EN L-level threshold voltage REN EN pin resistance to GND 1.6 VEN = 12 V 225 14.3 V 0.5 V 450 900 kΩ 15 15.8 CURRENT SENSE ITRIP TRIP Source current VDRVL = 0.1V, TA = 25°C TCVTRIP VTRIP Temperature coefficient Relative to TA = 25°C VOCL Current limit threshold 4000 μA ppm/°C RTRIP = 75kΩ, TA = 25°C 234 336 424 RTRIP = 27kΩ, TA = 25°C 121 174 220 RTRIP = 6.8kΩ, TA = 25°C 35 50 63 mV ON-TIME TIMER CONTROL TON On time VOUT = 1.05 V (2) 250 ns TOFF(MIN) Minimum off time VIN = 4.5 V, VVFB = 0.7 V, TA = 25°C 230 ns OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP Output OVP trip threshold TOVPDEL Output OVP propagation delay VUVP Output UVP trip threshold TUVPDEL Output UVP delay TUVPEN Output UVP enable delay OVP detect voltage 115 120 UVP detect voltage 63 68 125 % 10 μs 73 1 UVP enable delay / soft start time X1.4 X1.7 % ms X2.0 THERMAL SHUTDOWN TSDN (2) 4 Thermal shutdown threshold Shutdown temperature (2) Hysteresis (2) 150 °C 25 Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 TPS53014 www.ti.com SLVSBF1 – MAY 2012 PIN FUNCTIONS PIN NAME I/O DESCRIPTION VSSOP-10 VFB 1 I D-CAP2 feedback input. Connect to output voltage with resistor divider. SS 2 O Soft start programming pin. Connect capacitor from SS pin to GND to program soft start time. VREG5 3 O Output of 5-V linear regulator and supply for MOSFET driver. Bypass to GND with a minimum 4.7-μF high quality ceramic capacitor. VREG5 is active when EN is asserted high. EN 4 I Enable. Pull High to enable converter. VIN 5 I Supply Input for 5-V linear regulator. Bypass to GND with a minimum 0.1-μF high quality ceramic capacitor. PGND 6 I System ground. DRVL 7 O Low-side N-Channel MOSFET gate driver output. PGND referenced driver switches between PGND(OFF) and VREG5(ON). SW 8 I/O Switch node connections for both the high-side driver and over current comparator. DRVH 9 O High-side N-channel MOSFET gate driver output. SW referenced driver switches between SW(OFF) and VBST(ON). VBST 10 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from VBST to SW. An internal diode is connected between VREG5 and VBST 10 PIN VSSOP (TOP VIEW) TPS53014 VBST 10 DRVH 9 SW 8 EN DRVL 7 VIN PGND 6 1 VFB 2 SS 3 VREG5 4 5 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 5 TPS53014 SLVSBF1 – MAY 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM VREG5 TPS53014 -32% + + VFB +20% - REF SS + + - 1 VBST VIN 10 UV DRVH CONTROL LOGIC OV 9 SW XCON VOUT 8 VREG5 DRVL 7 1 SHOT PGND 6 10µA PGND 6.4µA SGND OCL SS 2 + ADC SW VIN 5 SGND EN EN 4 EN LOGIC UV OV UVLO TSD VIN VREG5 SS LOGIC 3 VREG5 REF REF UVLO PGND PROTECTION LOGIC OVERVIEW The TPS53014 is single synchronous step-down (buck) controller. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the required amount of output capacitance to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types. DETAILED DESCRIPTION PWM OPERATION The main control loop of the TPS53014 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ control mode. D-CAP2™ control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. this MOSFET is turned off when the internal timer expires. This timer is set by the converter input voltage VIN, and the output voltage VO, to maintain a pseudofixed frequency over the input voltage range, hence it is called adaptive on-time control. The timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control. 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 TPS53014 www.ti.com SLVSBF1 – MAY 2012 AUTO-SKIP Eco-Mode™ CONTROL The TPS53014 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to point where its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost half as is was in the continuous conduction mode because it takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. The transition point to the light load operation IOX(LL) current can be calculated in Equation 1 with 500kHz used as fsw. (V -V )×VOUT 1 IOUT(LL) = × IN OUT 2×L×fSW VIN (1) DRIVERS TPS53014 contains two high-current resistive MOSFET gate drivers. The low-side driver is a PGND referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET whose source is connected to PGND. The high-side driver is a floating SW referenced, VBST powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the VBST voltage during the high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current equal to Gate Charge (Qg @ Vgs = 5V) times Switching frequency (fsw). To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF between each driver transition. During this time the inductor current is carried by one of the MOSFETs body diodes. 5-VOLT REGULATOR The TPS53014 has an internal 5V Low-Dropout (LDO) Regulator to provide a regulated voltage for all both drivers and the ICs internal logic. A high-quality 4.7µF or greater ceramic capacitor from VREG5 to GND is required to stabilize the internal regulator. SOFT START AND PRE-BIASED SOFT START The soft start function is adjustable. When the EN pin becomes high, 6.4-µA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 2. VFB voltage is 0.773 V and SS pin source current is 6.4-µA. t SS (ms) = CSS (nF) x VFB(V) I (mA) SS = CSS (nF) x 0.773 V 6.4mA (2) The TPS53014 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than internal feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VO) starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 7 TPS53014 SLVSBF1 – MAY 2012 www.ti.com OVER CURRENT PROTECTION TPS53014 has a cycle-by-cycle over current limit feature. The over current limits the inductor valley current by monitoring the voltage drop across the low-side MOSFET RDS(on) during the low-side driver on-time. If the inductor current is larger than the over current limit (OCL), the TPS53014 delays the start of the next switching cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(on) current sensing is used to provide an accuracy and cost effective solution without external devices. To program the OCL, a resister should be connected between DRVL and PGND. The recommended values are given inTable 1. Table 1. OCL Resistor Values Resister Value ( kΩ) Vtrip (V) 6.8 0.050 11 0.087 18 0.125 27 0.174 39 0.224 56 0.274 75 0.336 IOCL is determined by Equation 3. æ (V -V ) V ö V IOCL = ç IN OUT × OUT ÷ + TRIP ç 2×L×f VIN ÷ø RDS(ON) SW è (3) The trip voltage is set between 0.05V to 0.336V over all operational temperature, including the 4000ppm/°C temperature slope compensation for the temperature dependency of the RDS(on). If the load current exceeds the over-current limit, the voltage will begin to drop. If the over-current conditions continues the output voltage will fall below the under voltage protection threshold and the TPS53014 will shut down. OVER/UNDER VOLTAGE PROTECTION TPS53014 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage is higher than 120% of the reference voltage, the OVP comparator output goes high and the circuit latches the high-side MOSFET driver OFF and the low-side MOSFET driver ON. When the feedback voltage is lower than 68% of the reference voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 1ms, TPS53014 latches OFF both top and bottom MOSFET drivers. This function is enabled approximately 1.7 x Tss after power-on. The OVP and UVP latch off is reset when EN goes low. UVLO PROTECTION TPS53014 has under voltage lock out protection (UVLO) that monitors the voltage of VREG5 pin. When the VREG5 voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF. The UVLO is non-latch protection. THERMAL SHUTDOWN TPS53014 monitors its temperature. If the temperature exceeds the threshold value (typically 150°C), the device shuts off. When the temperature falls below the threshold, the IC starts again. When VIN starts up and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is kept lower than 150°C. As long as VIN rises, TJ must be kept less than 110°C. 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 TPS53014 www.ti.com SLVSBF1 – MAY 2012 TYPICAL CHARACTERISTICS VIN = 12 V, TA= 25 °C (unless otherwise noted) VIN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 1200 12 1000 10 Supply Current−Shutdown Current (µA) Supply Current (µA) VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE 800 600 400 200 8 6 4 2 VIN = 12 V 0 −50 0 50 100 Junction Temperature (°C) VIN = 12 V 0 −50 150 0 50 100 Junction Temperature (°C) 150 G001 G002 Figure 1. Figure 2. EN INPUT CURRENT VS EN INPUT VOLTAGE SWITCHING FREQUENCY vs JUNCTION TEMPERATURE 600 80 70 500 Switching Frequency (kHz) EN Input Current (µA) 60 50 40 30 400 300 200 20 100 VOUT = 1.05 V VOUT = 1.8 V VOUT = 3.3 V 10 IOUT = 3 A VIN = 12 V 0 0 5 10 15 20 EN Input Voltage (V) 25 30 0 −50 0 50 100 Junction Temperature (°C) G003 Figure 3. 150 G004 Figure 4. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 9 TPS53014 SLVSBF1 – MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) VIN = 12 V, TA= 25 °C (unless otherwise noted) SWITCHING FREQUENCY vs INPUT VOLTAGE VFB VOLTAGE vs INPUT VOLTAGE 600 0.800 0.795 0.790 0.785 400 VFB Voltage (V) Switching Frequency (kHz) 500 300 200 0.775 0.770 0.765 0.760 100 VOUT = 1.05 V VOUT = 1.8 V VOUT = 3.3 V IOUT = 3 A 0 0.780 0 5 10 15 20 Input Voltage (V) 25 0.755 0.750 30 IOUT = 50 mA IOUT = 2 A 0 5 10 15 20 Input Voltage (V) 25 30 G006 Figure 6. VFB VOLTAGE vs AMBIENT TEMPERATURE LOAD REGULATION 0.800 1.10 0.795 1.09 0.790 1.08 0.785 1.07 Output Voltage (V) VFB Voltage (V) G005 Figure 5. 0.780 0.775 0.770 1.06 1.05 1.04 0.765 1.03 0.760 1.02 0.755 0.750 −50 0 50 100 Ambient Temperature (°C) VIN = 5 V VIN = 12 V VIN = 28 V 1.01 IOUT = 50 mA IOUT = 2 A 150 1.00 0.0 1.0 2.0 3.0 4.0 5.0 Output Current (A) G007 Figure 7. 10 6.0 7.0 8.0 G008 Figure 8. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 TPS53014 www.ti.com SLVSBF1 – MAY 2012 TYPICAL CHARACTERISTICS (continued) VIN = 12 V, TA= 25 °C (unless otherwise noted) LINE REGULATION TRANSIENT RESPONSE 1.10 1.09 VO (50 mV/div ac coupled) 1.08 Output Voltage (V) 1.07 1.06 1.05 IOUT (5 A/div) 1.04 1.03 1.02 1.01 1.00 Slew Rate (0.3 A/µsec) IOUT = 50 mA IOUT = 2 A 0 5 10 15 20 Input Voltage (V) 25 Time Scale (100 µsec/div) 30 G009 Figure 9. Figure 10. START UP WAVEFORMS EFFICIENCY 100 EN (10 V/div) 90 80 VREG5 (5 V/div) SS (2 V/div) 70 Efficiency (%) VO (500 mV/div) 60 50 40 30 20 VOUT = 1.05 V VOUT = 1.8 V VOUT = 3.3 V 10 Time (1 msec/div) VIN = 12 V 0 0.0 1.0 2.0 3.0 4.0 5.0 Output Current (A) 6.0 7.0 8.0 G012 Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 11 TPS53014 SLVSBF1 – MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) VIN = 12 V, TA= 25 °C (unless otherwise noted) LIGHT LOAD EFFICIENCY OUTPUT VOLTAGE RIPPLE, IOUT = 8 A 100 90 VO = 1.05 V VO (20 mV/div ac coupled) 80 Efficiency (%) 70 60 50 SW (5 V/div) 40 30 20 VOUT = 1.05 V VOUT = 1.8 V VOUT = 3.3 V 10 VIN = 12 V 0 0.001 0.01 0.1 Output Current (A) 1 Time (1 µsec/div) 10 G013 Figure 13. Figure 14. OUTPUT VOLTAGE RIPPLE, IOUT = 50 mA INPUT VOLTAGE RIPPLE, IOUT = 8 A VO = 1.05 V VO (20 mV/div ac coupled) SW (5 V/div) VO = 1.05 V SW (5 V/div) Time (1 µsec/div) Time (10 µsec/div) Figure 15. 12 VIN (50 mV/div ac coupled) Figure 16. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 TPS53014 www.ti.com SLVSBF1 – MAY 2012 TYPICAL CHARACTERISTICS (continued) VIN = 12 V, TA= 25 °C (unless otherwise noted) INPUT VOLTAGE RIPPLE, IOUT = 50 mA VO = 1.05 V VIN (10 mV/div ac coupled) SW (5 V/div) Time (10 µsec/div) Figure 17. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 13 TPS53014 SLVSBF1 – MAY 2012 www.ti.com APPLICATION INFORMATION APPLICATION SCHEMATIC A typical application schematic is shown in Figure 18. VIN R1 3.96k R2 10.0k C1 0.01µF C2 4.7µF SGND VIN EN 1 TPS53014 VBST VFB 2 SS 3 VREG5 4 5 C3 10µF C5 10µF 10 DRVH 9 SW 8 EN DRVL 7 VIN PGND 6 Q1 CSD17307Q5A L1 1.5µH C4 0.1µF VOUT Q2 CSD17510Q5A R3 C6 22µF C7 22µF C8 22µF PGND PGND Figure 18. Application Schematic COMPONENT SELECTION INDUCTOR The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load. Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation. Equation 4 can be used to calculate te value for LOUT. VIN(MAX) -VOUT V L OUT = × OUT IL(RIPPLE) ×fSW VIN(MAX) (4) The inductors current ratings needs to support both the RMS (thermal) current and the peak (saturation) current. The RMS and peak inductor current can be estimated as follows: VIN(MAX) -VOUT V IL(RIPPLE) = × OUT LOUT ×fSW VIN(MAX) (5) V IL(PEAK) = TRIP +IL(RIPPLE) RDS(ON) (6) IL(RMS) = IOUT 2 + 1 ×IL(RIPPLE)2 12 (7) Note: The calculation above shall serve as a general reference. To further improve transient response, the output inductance could be reduced further. This needs to be considered along with the selection of the output capacitor. OUTPUT CAPACITOR The capacitor value and ESR determines the amount of output voltage ripple and load transient response. Ceramic output capacitors with X5R dielectric or better are recommended . IL(RIPPLE) 1 COUT = × 8×VOUT(RIPPLE) fSW (8) 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 TPS53014 www.ti.com COUT = SLVSBF1 – MAY 2012 ΔILOAD2 ×L OUT 2×VOUT ×ΔVOS (9) 2 COUT = ΔILOAD ×L OUT 2×K×ΔVUS (10) Where: K= (VIN -VOUT )× • • • TON TON -TOFF(MIN) (11) ΔVOS = The allowable amount of overshoot voltage in load transition ΔVUS = The allowable amount of undershoot voltage in load transition TOFF(MIN) = Minimum off time Select the capacitance value greater than the largest value calculated from Equation 8, Equation 9 and Equation 10. The minimum recommended output capacitance is 44 μF. INPUT CAPACITOR The TPS53014 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The capacitor voltage rating needs to be greater than the maximum input voltage. BOOTSTRAP CAPACITOR The TPS53014 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The capacitor voltage rating should be greater than 10 V. VREG5 CAPACITOR The TPS53014 requires that the VREG5 regulator is bypassed. A minimum 4.7-μF high-quality ceramic capacitor must be connected between the VREG5 and PGND for proper operation. The capacitor voltage rating should be greater than 10 V. CHOOSE OUTPUT VOLTAGE RESISTORS The output voltage is set with a resistor divider from output voltage node to the VFB pin. It is recommended to use 1% tolerance or better resistors. Select R2 between 10 kΩ and 100 kΩ and use Equation 12 to calculate R1. æV ö R1 = ç OUT -1÷ ×R2 è VVFB ø (12) spacer LAYOUT SUGGESTIONS • • • • • • Keep the input switching current loop as small as possible. Place the input capacitor close to the top switching FET. The output current loop should also be kept as small as possible. Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback pin (VFB) of the device. Keep analog and non-switching components away from switching components. Make a single point connection from the signal ground to power ground. Do not allow switching current to flow under the device. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :TPS53014 15 PACKAGE OPTION ADDENDUM www.ti.com 5-Jun-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS53014DGS ACTIVE MSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR TPS53014DGSR ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS53014DGSR Package Package Pins Type Drawing MSOP DGS 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53014DGSR MSOP DGS 10 2500 366.0 364.0 50.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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