TPS61165 www.ti.com SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 High Brightness White LED Driver in 2mm x 2mm QFN and SOT-23 Packages Check for Samples: TPS61165 FEATURES The default white LED current is set with the external sensor resistor Rset, and the feedback voltage is regulated to 200mV, as shown in the typical application. During the operation, the LED current can be controlled using the 1 wire digital interface ( Easyscale™ protocol) through the CTRL pin. Alternatively, a pulse width modulation (PWM) signal can be applied to the CTRL pin through which the duty cycle determines the feedback reference voltage. In either digital or PWM mode, the TPS61165 does not burst the LED current; therefore, it does not generate audible noises on the output capacitor. For maximum protection, the device features integrated open LED protection that disables the TPS61165 to prevent the output from exceeding the absolute maximum ratings during open LED conditions. 1 • • • • 2 • • • • 3-V to 18-V Input Voltage Range 38-V Open LED Protection for 10 LEDs 200-mV Reference Voltage With 2% Accuracy 1.2-A Switch FET With 1.2-MHz Switching Frequency Flexible 1 Wire Digital and PWM Brightness Control Built-in Soft Start Up to 90% Efficiency 2mm × 2mm × 0.8mm 6-pin QFN Package With Thermal Pad, and SOT-23 Package APPLICATIONS • • High Brightness LED Lighting White LED Backlighting for Media Form Factor Display The TPS61165 is available in a space -saving 2mm x 2mm OFN package with thermal pad, and SOT-23 package DESCRIPTION With a 40-V rated integrated switch FET, the TPS61165 is a boost converter that drives up to 10 LEDs in series. The boost converter runs at a 1.2-MHz fixed switching frequency with 1.2-A switch current limit, and allows for the use of a high brightness LED in general lighting. L1 10 mH VIN 5V C1 4.7 mF TPS61165 ON/OFF DIMMING CONTROL VIN SW CTRL FB COMP GND D1 C2 1 mF 350 mA 220 nF Rset 0.57 W L 1 : TOKO #A 915 _Y-100M C1 : Murata GRM 188R61A475 K C2 : Murata GRM 188R61E105K D1 : ONsemi MBR0540T1 LED : OSRAM LW-W 5SM Figure 1. Typical Application 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Easyscale is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2010, Texas Instruments Incorporated TPS61165 SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA OPEN LED PROTECTION –40°C to 85°C (1) (2) 38 V (typical) PACKAGE (2) PACKAGE MARKING TPS61165DRV CCQ TPS61165DBV DAK For the most current package and ordering information, see the TI Web site at www.ti.com. The DRV package is available in tape and reel. Add R suffix (TPS61165DRVR) to order quantities of 3000 parts per reel or add T suffix (TPS61165DRVT) to order 250 parts per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply Voltages on VIN (1) (2) Voltages on CTRL (2) VI Voltage on FB and COMP (2) Voltage on SW (2) VALUE UNIT –0.3 to 20 V –0.3 to 20 V –0.3 to 3 V –0.3 to 40 V PD Continuous Power Dissipation TJ Operating Junction Temperature Range –40 to 150 °C TSTG Storage Temperature Range –65 to 150 °C (1) (2) See the Dissipation Ratings Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. DISSIPATION RATINGS BOARD PACKAGE (1) (2) RqJC RqJA DERATING FACTOR ABOVE TA = 25C TA < 25°C TA = 70°C TA = 85°C Low-K DRV (1) 20°C/W 140°C/W 7.1mW/°C 715mW 395mW 285mW High-K DRV (2) 20°C/W 65°C/W 15.4mW/°C 1540mW 845mW 615mW High-K DBV (2) n/a 210°C/W 4.7mW/°C 470mW 258mW 188mW The JEDEC low-K (1s) board used to derive this data was a 3in x 3in, two-layer board with 2-ounce copper traces on top of the board. The JEDEC high-K (2s2p) board used to derive this data was a 3in x 3in, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT VI Input voltage range, VIN VO Output voltage range L Inductor (1) fdim CIN CO Output capacitor 1 10 mF TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C (1) 2 3 18 V VIN 38 V 10 22 mH PWM dimming frequency 5 100 kHz Input capacitor 1 mF These values are recommended values that have been successfully tested in several applications. Other values may be acceptable in other applications but should be fully tested by the user. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 TPS61165 www.ti.com SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 ELECTRICAL CHARACTERISTICS VIN = 3.6 V, CTRL = VIN, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VI Input voltage range, VIN IQ Operating quiescent current into VIN Device PWM switching no load 3 ISD Shutdown current CRTL=GND, VIN = 4.2 V UVLO Under-voltage lockout threshold VIN falling Vhys Under-voltage lockout hysterisis 2.2 18 V 2.3 mA 1 mA 2.5 V 70 mV ENABLE AND REFERENCE CONTROL V(CTRLh) CTRL logic high voltage VIN = 3 V to 18 V V(CTRLl) CTRL logic low voltage VIN = 3 V to 18 V 1.2 R(CTRL) CTRL pull down resistor toff CTRL pulse width to shutdown CTRL high to low 2.5 ms tes_det Easy Scale detection time (1) CTRL pin low 260 ms tes_delay Easy Scale detection delay 100 ms tes_win Easy Scale detection window time 1 ms 400 Measured from CTRL high V 0.4 800 V 1600 kΩ VOLTAGE AND CURRENT CONTROL VREF Voltage feedback regulation voltage 196 200 204 V(REF_PWM) Voltage feedback regulation voltage under brightness control VFB = 50 mV 47 50 53 VFB = 20 mV 17 20 23 IFB Voltage feedback input bias current VFB = 200 mV fS Oscillator frequency Dmax Maximum duty cycle tmin_on Minimum on pulse width Isink Comp pin sink current Isource Comp pin source current Gea Error amplifier transconductance Rea Error amplifier output resistance fea Error amplifier crossover frequency VFB = 100 mV mV mV 2 1.0 1.2 90% 93% 1.5 mA MHz 40 ns 100 mA 100 240 320 mA 400 umho 6 MΩ 5 pF connected to COMP 500 kHz VIN = 3.6 V 0.3 POWER SWITCH RDS(ON) ILN_NFET N-channel MOSFET on-resistance VIN = 3.0 V N-channel leakage current VSW = 35 V, TA = 25°C ILIM N-Channel MOSFET current limit D = Dmax ILIM_Start Start up current limit D = Dmax tHalf_LIM Time step for half current limit Vovp Open LED protection threshold Measured on the SW pin Open LED protection threshold on FB Measured on the FB pin, percentage of Vref, Vref = 200 mV and 20 mV 0.6 0.7 Ω 1 mA 1.44 A OC and OLP V(FB_OVP) tREF 0.96 0.7 VREF ramp up time A 5 37 38 ms 39 V 50% VREF filter time constant tstep 1.2 Each step, Measured as number of cycles of the 1.2 MHz clock 180 ms 213 ms EasyScale TIMING tstart Start time of program stream tEOS End time of program stream 2 360 ms tH_LB High time low bit Logic 0 2 180 ms tL_LB Low time low bit Logic 0 2 × tH_LB 360 ms (1) 2 ms To select EasyScale™ mode, the CTRL pin has to be low for more than tes_det during tes_win. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 3 TPS61165 SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 3.6 V, CTRL = VIN, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tH_HB High time high bit Logic 1 2 × tL_HB 360 ms tL_HB Low time high bit Logic 1 2 180 ms VACKNL Acknowledge output voltage low Open drain, Rpullup =15 kΩ to VIN tvalACKN Acknowledge valid time See tACKN Duration of acknowledge condition See 0.4 V (2) 2 ms (2) 512 ms THERMAL SHUTDOWN Tshutdown Thermal shutdown threshold Thysteresis Thermal shutdown threshold hysteresis (2) 160 °C 15 °C Acknowledge condition active 0, this condition will only be applied in case the RFA bit is set. Open drain output, line must be pulled high by the host with resistor load. DEVICE INFORMATION TOP VIEW FB TOP VIEW VIN Thermal Pad COMP VIN 1 6 FB CTRL 2 5 COMP CTRL SW 3 GND SW 4 GND 6-PIN SOT-23 6-PIN 2mm x 2mm x 0.8mm QFN PIN FUNCTIONS PIN DRV NO. DBV NO. I/O VIN 6 1 I The input supply pin for the IC. Connect VIN to a supply voltage between 3V and 18V. SW 4 3 I This is the switching node of the IC. Connect the switched side of the inductor to SW. This pin is also used to sense the output voltage for open LED protection. GND 3 4 O Ground FB 1 6 I Feedback pin for current. Connect the sense resistor from FB to GND. COMP 2 5 O Output of the transconductance error amplifier. Connect an external capacitor to this pin to compensate the regulator. CTRL 5 2 I Control pin of the boost regulator. It is a multi-functional pin which can be used for enable control, PWM and digital dimming. NAME Thermal Pad 4 DESCRIPTION The thermal pad should be soldered to the analog ground plane. If possible, use thermal via to connect to ground plane for ideal power dissipation. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 TPS61165 www.ti.com SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 FUNCTIONAL BLOCK DIAGRAM C2 D1 1 Rset 4 FB L1 SW Reference Control Error Amplifer OLP Vin 6 COMP 2 C1 PWM Control C3 5 CTRL Soft Start-up Ramp Generator + Current Sensor Oscillator GND 3 TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE Efficiency 3 LEDs (VOUT = 12V); VIN = 3, 5, 8.5V; L = 10 mH Figure 2 Efficiency 6 LEDs (VOUT = 24V); VIN = 5, 8.5, 12V; L = 10 mH Figure 3 Current limit TA = 25°C Figure 4 Current limit Figure 5 Easyscale step Figure 6 PWM dimming linearity VIN = 3.6 V; PWM Freq = 10 kHz and 32 kHz Figure 7 Output ripple at PWM dimming 3 LEDs; VIN = 5 V; ILOAD = 350 mA; PWM 32 kHz Figure 8 Switching waveform 3 LEDs; VIN = 5 V; ILOAD = 3500 mA; L = 10 mH Figure 9 Start-up 3 LEDs; VIN = 5 V; ILOAD = 350 mA; L = 10 mH Figure 10 Open LED protection 8 LEDs; VIN = 3.6 V; ILOAD = 20 mA Figure 11 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 5 TPS61165 SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 www.ti.com EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 VIN = 8.5 V 3 LEDs ( VOUT = 12 V ) VIN = 12 V 6 LEDs ( VOUT = 24 V ) 90 90 VIN = 8.5 V VIN = 5 V VIN = 5 V VIN = 3 V Efficiency - % Efficiency - % 80 70 70 60 60 50 50 40 40 0 50 100 150 200 Output Current - mA 250 0 300 250 SWITCH CURRENT LIMIT vs DUTY CYCLE SWITCH CURRENT LIMIT vs TEMPERATURE 1600 1500 1500 1400 1400 1300 1200 1100 1000 900 300 1300 1200 1100 1000 900 30 40 50 60 Duty Cycle - % 70 80 90 800 -40 -20 Figure 4. 6 100 150 200 Output Current - mA Figure 3. 1600 800 20 50 Figure 2. Switch Current Limit - mA Switch Current Limit - A 80 0 20 40 60 80 Temperature - °C 100 120 140 Figure 5. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 TPS61165 www.ti.com SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 FB VOLTAGE vs EASYSCALE STEP FB VOLTAGE vs PWM DUTY CYCLE 200 200 PWM 10 kHz, 32 kHz 180 160 160 FB Voltage - mV FB Voltage - mV 140 120 100 80 120 80 60 40 40 20 0 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Easy Scale Step 0 20 40 60 PWM Duty Cycle - % Figure 6. Figure 7. OUTPUT RIPPLE at PWM DIMMING SWITCHING WAVEFORM PWM 5 V/div 80 100 SW 5 V/div VOUT 50 mV/div AC VOUT 200 mV/div AC IL 500 mA/div ILED 200 mA/div t - 20 ms/div t - 400 ns/div Figure 8. Figure 9. START-UP OPEN LED PROTECTION CTRL 5 V/div OPEN LED 5 V/div FB 200 mV/div VOUT 5 V/div VOUT 10 V/div IL 200 mA/div COMP 500 mV/div IL 500 mA/div t - 100 ms/div t - 2 ms/div Figure 10. Figure 11. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 7 TPS61165 SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 www.ti.com DETAILED DESCRIPTION OPERATION The TPS61165 is a high efficiency, high output voltage boost converter in small package size, The device is ideal for driving up to 10 white LED in series. The serial LED connection provides even illumination by sourcing the same output current through all LEDs, eliminating the need for expensive factory calibration. The device integrates 40V/1.2A switch FET and operates in pulse width modulation (PWM) with 1.2MHz fixed switching frequency. For operation see the block diagram. The duty cycle of the converter is set by the error amplifier output and the current signal applied to the PWM control comparator. The control architecture is based on traditional current-mode control; therefore, a slope compensation is added to the current signal to allow stable operation for duty cycles larger than 40%. The feedback loop regulates the FB pin to a low reference voltage (200mV typical), reducing the power dissipation in the current sense resistor. SOFT START-UP Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device is enabled, the voltage at FB pin ramps up to the reference voltage in 32 steps, each step takes 213ms. This ensures that the output voltage rises slowly to reduce the input current. Additionally, for the first 5msec after the COMP voltage ramps, the current limit of the switch is set to half of the normal current limit spec. During this period, the input current is kept below 700mA (typical). These two features ensure smooth start-up and minimize the inrush current. See the start-up waveform of a typical example (Figure 10). OPEN LED PROTECTION Open LED protection circuitry prevents IC damage as the result of white LED disconnection. The TPS61165 monitors the voltage at the SW pin and FB pin during each switching cycle. The circuitry turns off the switch FET and shuts down the IC as soon as the SW voltage exceeds the Vovp threshold, and the FB voltage is less than half of regulation voltage for 8 clock cycles. As a result, the output voltage falls to the level of the input supply. The device remains in shutdown mode until it is enabled by toggling the CTRL pin logic. To allow the use of inexpensive low-voltage output capacitor, the TPS61165 has different open lamp protection thresholds to prevent the internal 40V FET from breaking down. The threshold is set at 38V. SHUTDOWN The TPS61165 enters shutdown mode when the CTRL voltage is logic low for more than 2.5ms. During shutdown, the input supply current for the device is less than 1mA (max). Although the internal FET does not switch in shutdown, there is still a DC current path between the input and the LEDs through the inductor and Schottky diode. The minimum forward voltage of the LED array must exceed the maximum input voltage to ensure that the LEDs remain off in shutdown. CURRENT PROGRAM The FB voltage is regulated by a low 0.2V reference voltage. The LED current is programmed externally using a current-sense resistor in series with the LED string. The value of the RSET is calculated using Equation 1 . V I LED + FB RSET (1) Where: ILED = output current of LEDs VFB = regulated voltage of FB RSET = current sense resistor The output current tolerance depends on the FB accuracy and the current sensor resistor accuracy. 8 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 TPS61165 www.ti.com SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 LED BRIGTHNESS DIMMING MODE SELECTION The CTRL pin is used for the control input for both dimming modes, PWM dimming and the 1 wire dimming. The dimming mode for the TPS61165 is selected each time the device is enabled. The default dimming mode is PWM dimming. To enter 1 wire mode, the following digital pattern on the CTRL pin must be recognized by the IC every time the IC starts from the shutdown mode. 1. Pull CTRL pin high to enable the TPS61165, and to start the 1 wire detection window. 2. After the EasyScale detection delay (tes_delay, 100ms) expires, drive CTRL low for more than the EasyScale detection time (tes_detect, 260ms). 3. The CTRL pin has to be low for more than EasyScale detection time before the EasyScale detection window (tes_win, 1msec) expires. EasyScale detection window starts from the first CTRL pin low to high transition. The IC immediately enters the 1 wire mode once the above 3 conditions are met. the EasyScale communication can start before the detection window expires. Once the dimming mode is programmed, it can not be changed without another start up. This means the IC needs to be shutdown by pulling the CTRL low for 2.5ms and restarts. See the Dimming Mode Detection and Soft Start (see Figure 12) for a graphical explanation. Insert battery PWM signal high CTRL low PWM mode Startup delay FB ramp Shutdown delay 200mV x duty cycle FB t Insert battery Enter ES mode Enter ES mode Timing window Programming code Programming code high CTRL low ES detect time ES mode ES detect delay Shutdown delay IC Shutdown Programmed value (if not programmed, 200mV default ) FB FB ramp FB ramp Startup delay 50mV Startup delay 50mV Figure 12. Dimming Mode Detection and Soft Start PWM Brightness Dimming PWM BRIGHTNESS DIMMING When the CTRL pin is constantly high, the FB voltage is regulated to 200mV typically. However, the CTRL pin allows a PWM signal to reduce this regulation voltage; therefore, it achieves LED brightness dimming. The relationship between the duty cycle and FB voltage is given by Equation 2: V FB + Duty 200 mV (2) Where: Duty = duty cycle of the PWM signal 200 mV = internal reference voltage As shown in Figure 13, the IC chops up the internal 200mV reference voltage at the duty cycle of the PWM signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the error amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for brightness dimming, only the WLED DC current is modulated, which is often referred as analog dimming. This eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and duty cycle of PWM control. Unlike other scheme which filters the PWM signal for analog dimming, TPS61165 regulation voltage is independent of the PWM logic voltage level which often has large variations. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 9 TPS61165 SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 www.ti.com For optimum performance, use the PWM dimming frequency in the range of 5kHz to 100kHz. The requirement of minimum dimming frequency comes from the EasyScale detection delay and detection time specification in the dimming mode selection. Since the CTRL pin is logic only pin, adding external RC filter applied to the pin does not work. To use lower PWM dimming, add external RC network connected to the FB pin as shown in the additional typical application, Figure 17. VBG 200 mV CTRL FB Error Amplifer Figure 13. Block Diagram of Programmable FB Voltage Using PWM Signal DIGITAL 1 WIRE BRIGHTNESS DIMMING The CTRL pin features a simple digital interface to allow digital brightness control. The digital dimming can save the processor power and battery life as it does not require a PWM signal all the time, and the processor can enter idle mode if available. The TPS61165 adopts the EasyScale™ protocol for the digital dimming, which can program the FB voltage to any of the 32 steps with single command. The step increment increases with the voltage to produce pseudo logarithmic curve for the brightness step. See Table 1 for the FB pin voltage steps. The default step is full scale when the device is first enabled (VFB = 200 mV). The programmed reference voltage is stored in an internal register. A power reset clears the register value and reset it to default. EasyScale™: 1 WIRE DIGITAL DIMMING EasyScale is a simple but flexible one pin interface to configure the FB voltage. The interface is based on a master-slave structure, where the master is typically a microcontroller or application processor. Figure 14 and Table 2 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte. The device specific address byte is fixed to 72 hex. The data byte consists of five bits for information, two address bits, and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale compared with other on pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to 160kBit/sec. Table 1. Selectable FB Voltage 10 FB voltage (mV) D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 5 0 0 0 0 1 2 8 0 0 0 1 0 3 11 0 0 0 1 1 4 14 0 0 1 0 0 5 17 0 0 1 0 1 6 20 0 0 1 1 0 7 23 0 0 1 1 1 8 26 0 1 0 0 0 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 TPS61165 www.ti.com SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 Table 1. Selectable FB Voltage (continued) FB voltage (mV) D4 D3 D2 D1 D0 9 29 0 1 0 0 1 10 32 0 1 0 1 0 11 35 0 1 0 1 1 12 38 0 1 1 0 0 13 44 0 1 1 0 1 14 50 0 1 1 1 0 15 56 0 1 1 1 1 16 62 1 0 0 0 0 17 68 1 0 0 0 1 18 74 1 0 0 1 0 19 80 1 0 0 1 1 20 86 1 0 1 0 0 21 92 1 0 1 0 1 22 98 1 0 1 1 0 23 104 1 0 1 1 1 24 116 1 1 0 0 0 25 128 1 1 0 0 1 26 140 1 1 0 1 0 27 152 1 1 0 1 1 28 164 1 1 1 0 0 29 176 1 1 1 0 1 30 188 1 1 1 1 0 31 200 1 1 1 1 1 DATA IN DATABYTE Device Address Start Start DA7 DA6 DA5 DA4 DA3 DA2 DA1 0 1 1 1 0 0 1 DA0 EOS Start RFA 0 A1 A0 D4 D3 D2 D1 D0 EOS DATA OUT ACK Figure 14. EasyScale™ Protocol Overview Table 2. EasyScale™ Bit Description BYTE Device Address Byte 72 hex BIT NUMBER NAME TRANSMISSION DIRECTION 7 DA7 0 MSB device address 6 DA6 1 5 DA5 1 4 DA4 3 DA3 2 DA2 0 1 DA1 1 0 DA0 0 LSB device address IN DESCRIPTION 1 0 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 11 TPS61165 SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 www.ti.com Table 2. EasyScale™ Bit Description (continued) BYTE Data byte BIT NUMBER TRANSMISSION DIRECTION NAME 7 (MSB) RFA 6 A1 0 Address bit 1 5 A0 0 Address bit 0 4 D4 3 D3 2 D2 Data bit 2 1 D1 Data bit 1 0 (LSB) D0 Data bit 0 DESCRIPTION Request for acknowledge. If high, acknowledge is applied by device Data bit 4 IN ACK Data bit 3 Acknowledge condition active 0, this condition will only be applied in case RFA bit is set. Open drain output, Line needs to be pulled high by the host with a pullup resistor. This feature can only be used if the master has an open drain output stage. In case of a push pull output stage Acknowledge condition may not be requested! OUT Easy Scale Timing, without acknowledge RFA = 0 t Start DATA IN t Start Address Byte DATA Byte Static High Static High DA7 0 DA0 0 D0 1 RFA 0 TEOS TEOS Easy Scale Timing, with acknowledge RFA = 1 t Start DATA IN t Start Address Byte DATA Byte Static High Static High DA7 0 DA0 0 TEOS RFA 1 D0 1 Controller needs to Pullup Data Line via a resistor to detect ACKN DATA OUT tLow Low Bit (Logic 0) t High tLOW t valACK ACKN t ACKN Acknowledge true, Data Line pulled down by device Acknowledge false, no pull down tHigh High Bit (Logic 1) Figure 15. EasyScale™— Bit Coding 12 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 TPS61165 www.ti.com SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 All bits are transmitted MSB first and LSB last. Figure 15 shows the protocol without acknowledge request (Bit RFA = 0), Figure 15 with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address byte and data byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least tstart (2ms) before the bit transmission starts with the falling edge. If the CTRL pin is already at a high level, no start condition is needed prior to the device address byte. The transmission of each byte is closed with an End of Stream condition for at least tEOS (2ms). The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and tHIGH. It can be simplified to: High Bit: tHIGH > tLOW, but with tHIGH at least 2x tLOW, see Figure 15. Low Bit: tHIGH < tLOW, but with tLOW at least 2x tHIGH, see Figure 15. The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on the relation between tHIGH and tLOW, the logic 0 or 1 is detected. The acknowledge condition is only applied if: • Acknowledge is requested by a set RFA bit. • The transmitted device address matches with the device address of the device. • 16 bits is received correctly. If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time tACKN, which is 512ms maximum then the Acknowledge condition is valid after an internal delay time tvalACK. This means that the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master controller keeps the line low in this period. The master device can detect the acknowledge condition with its input by releasing the CTRL pin after tvalACK and read back a logic 0. The CTRL pin can be used again after the acknowledge condition ends. Note that the acknowledge condition may only be requested if the master device has an open drain output. For a push-pull output stage, the use a series resistor in the CRTL line to limit the current to 500mA is recommended to for such cases as: • accidentally requested acknowledge, or • to protect the internal ACKN-MOSFET. UNDERVOLTAGE LOCKOUT An undervoltage lockout prevents operation of the device at input voltages below typical 2.2V. When the input voltage is below the undervoltage threshold, the device is shutdown and the internal switch FET is turned off. If the input voltage rises by undervoltage lockout hysteresis, the IC restarts. THERMAL SHUTDOWN An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded. The device is released from shutdown automatically when the junction temperature decreases by 15°C. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 13 TPS61165 SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 www.ti.com APPLICATION INFORMATION MAXIMUM OUTPUT CURRENT The overcurrent limit in a boost converter limits the maximum input current and thus maximum input power for a given input voltage. Maximum output power is less than maximum input power due to power conversion losses. Therefore, the current limit setting, input voltage, output voltage and efficiency can all change maximum current output. The current limit clamps the peak inductor current; therefore, the ripple has to be subtracted to derive maximum DC current. The ripple current is a function of switching frequency, inductor value and duty cycle. The following equations take into account of all the above factors for maximum output current calculation. 1 IP = é 1 1 ù + )ú êL ´ Fs ´ ( Vout + Vf - Vin Vin û ë (3) Where: Ip = inductor peak to peak ripple L = inductor value Vf = Schottky diode forward voltage Fs = switching frequency Vout = output voltage of the boost converter. It is equal to the sum of VFB and the voltage drop across LEDs. I out_max + Vin ǒI lim * I Pń2Ǔ h Vout (4) where Iout_max = Maximum output current of the boost converter Ilim = over current limit h = efficiency For instance, when VIN is 3V, 8 LEDs output equivalent to VOUT of 26V, the inductor is 22mH, the Schottky forward voltage is 0.2V; and then the maximum output current is 110mA in typical condition. When VIN is 5V, 10 LEDs output equivalent to VOUT of 32V, the inductor is 22mH, the Schottky forward voltage is 0.2V; and then the maximum output current is 150mA in typical condition. INDUCTOR SELECTION The selection of the inductor affects steady state operation as well as transient behavior and loop stability. These factors make it the most important component in power regulator design. There are three important inductor specifications, inductor value, DC resistance and saturation current. Considering inductor value alone is not enough. The inductor value determines the inductor ripple current. Choose an inductor that can handle the necessary peak current without saturating, according to half of the peak-to-peak ripple current given by Equation 3, pause the inductor DC current given by: I in_DC + Vout Iout Vin h (5) Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation level, its inductance can decrease 20% to 35% from the 0A value depending on how the inductor vendor defines saturation current. Using an inductor with a smaller inductance value forces discontinuous PWM when the inductor current ramps down to zero before the end of each switching cycle. This reduces the boost converter’s maximum output current, causes large input voltage ripple and reduces efficiency. Large inductance value provides much more output current and higher conversion efficiency. For these reasons, a 10mH to 22mH inductor value range is recommended. A 22mH inductor optimized the efficiency for most application while maintaining low inductor peak to peak ripple. Table 3 lists the recommended inductor for the TPS61165. When recommending inductor value, the factory has considered –40% and +20% tolerance from its nominal value. 14 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 TPS61165 www.ti.com SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 TPS61165 has built-in slope compensation to avoid sub-harmonic oscillation associated with current mode control. If the inductor value is lower than 10mH, the slope compensation may not be adequate, and the loop can be unstable. Therefore, customers need to verify the inductor in their application if it is different from the recommended values. Table 3. Recommended Inductors for TPS61165 PART NUMBER L (mH) DCR MAX (mΩ) SATURATION CURRENT (A) SIZE (L × W × H mm) VENDOR A915_Y-100M 10 90 1.3 5.2×5.2×3.0 TOKO VLCF5020T-100M1R1-1 10 237 1.1 5×5×2.0 TDK CDRH4D22/HP 10 144 1.2 5×5×2.4 Sumida LQH43PN100MR0 10 247 0.84 4.5×3.2×2.0 Murata SCHOTTKY DIODE SELECTION The high switching frequency of the TPS61165 demands a high-speed rectification for optimum efficiency. Ensure that the diode’s average and peak current rating exceeds the average output current and peak inductor current. In addition, the diode’s reverse breakdown voltage must exceed the open LED protection voltage. The ONSemi MBR0540 and the ZETEX ZHCS400 are recommended for TPS61165. COMPENSATION CAPACITOR SELECTION The compensation capacitor C3 (see the block diagram), connected from COMP pin to GND, is used to stabilize the feedback loop of the TPS61165. Use 220nF ceramic capacitor for C3. INPUT AND OUTPUT CAPACITOR SELECTION The output capacitor is mainly selected to meet the requirements for the output ripple and loop stability. This ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by: C out + ǒV out * V inǓ Iout Vout Fs V ripple (6) where, Vripple = peak-to-peak output ripple. The additional output ripple component caused by ESR is calculated using: V ripple_ESR + I out RESR (7) Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or electrolytic capacitors are used. Care must be taken when evaluating a ceramic capacitors derating under dc bias, aging and AC signal. For example, larger form factor capacitors (in 1206 size) have a self resonant frequencies in the range of the switching frequency. So the effective capacitance is significantly lower. The DC bias can also significantly reduce capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore, leave the margin on the voltage rating to ensure adequate capacitance at the required output voltage. The capacitor in the range of 1mF to 4.7mF is recommended for input side. The output requires a capacitor in the range of 1mF to 10mF. The output capacitor affects the loop stability of the boost regulator. If the output capacitor is below the range, the boost regulator can potentially become unstable. The popular vendors for high value ceramic capacitors are: TDK (http://www.component.tdk.com/components.php) Murata (http://www.murata.com/cap/index.html) Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 15 TPS61165 SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 www.ti.com LAYOUT CONSIDERATIONS As for all switching power supplies, especially those high frequency and high current ones, layout is an important design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems. To reduce switching losses, the SW pin rise and fall times are made as short as possible. To prevent radiation of high frequency resonance problems, proper layout of the high frequency switching path is essential. Minimize the length and area of all traces connected to the SW pin and always use a ground plane under the switching regulator to minimize inter-plane coupling. The loop including the PWM switch, Schottky diode, and output capacitor, contains high current rising and falling in nanosecond and should be kept as short as possible. The input capacitor needs not only to be close to the VIN pin, but also to the GND pin in order to reduce the IC supply ripple. Figure 16 shows a sample layout. C1 Rset Vin LEDs Out Vin FB L1 CTRL COMP CTRL GND SW C3 C2 Minimize the area of this trace GND Place enough VIAs around thermal pad to enhance thermal performance LEDs IN Figure 16. Layout Recommendation THERMAL CONSIDERATIONS The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation of the TPS61165. Calculate the maximum allowable dissipation, PD(max), and keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is determined using Equation 8: P D(max) + 125°C * T A RqJA (8) where, TA is the maximum ambient temperature for the application. RqJA is the thermal resistance junction-to-ambient given in Power Dissipation Table. The TPS61165 comes in a thermally enhanced QFN package. This package includes a thermal pad that improves the thermal capabilities of the package. The RqJA of the QFN package greatly depends on the PCB layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using thermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON PCB Attachment application report (SLUA271). 16 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 TPS61165 www.ti.com SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 ADDITIONAL TYPICAL APPLICATIONS L1 10 mH VIN 5V D1 C2 1 mF C1 4.7 mF TPS 61165 VIN ON/OFF SW CTRL FB 10 kW GND COMP 80 kW C3 220 nF Rset 0.64 W 100 kW L 1 : TOKO #A 915 _Y-100M C1 : Murata GRM188R61A475K C2 : Murata GRM188R61E105K D1 : ONsemi MBR 0540 T1 LED : OSRAM LW -W 5SM 0.1 mF PWM Signal: 1.8V ; 200 Hz LED current =1.8V x (1-d) / (8x Rset) Figure 17. Drive 3 High Brightness LEDs With External PWM Dimming Network L1 10 mH VIN 3 V to 6 V D1 3s9p 27LEDs C1 4.7 mF C2 1 mF TPS61165 VIN ON /OFF DIMMING CONTROL SW CTRL FB COMP GND C3 220 nF L1: C1: C2: D1: Rset 1.1 W TOKO # A915_ Y-100 M Murata GRM188 R61A475 K Murata GRM188 R61E105 K ONsemi MBR0540T 1 Figure 18. Drive 27 LEDs for Media Form Factor Display Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 17 TPS61165 SLVS790A – NOVEMBER 2007 – REVISED MAY 2010 www.ti.com L1 10 mH VIN 12 V C1 4.7 mF D1 C2 1 mF TPS 61165 ON/OFF DIMMING CONTROL VIN SW CTRL FB COMP GND 350 mA C3 220 nF Rset 0.57 W L1: TOKO #A915_Y-100M C1: Murata GRM188R61A475K C2: Murata GRM188R61E105K D1: ONsemi MBR0540T1 LED: OSRAM LW-W5SM Figure 19. Drive 6 High Brightness LEDs C1 4.7 mF C4 1 mF L1 10 mH VIN 9V to 15V L2 10 mH TPS 61165 VIN ON/OFF DIMMING CONTROL D1 VOUT= 12 V C2 1 mF SW 180 mA CTRL FB COMP GND C3 220 nF Rset 1.1 W L1, L2: TOKO #A915_Y-100M C1: Murata GRM188 R61A475K C2: Murata GRM188 R61E105K C4: Murata GRM188 R61H105K D1: ONsemi MBR0540T1 *L1,L2 can be replaced by 1:1 transformer Figure 20. Drive 4 High Brightness LED With SEPIC Topology Spacer REVISION HISTORY Changes from Original (November 2007) to Revision A Page • Added "and SOT-23 Package" to the Title, the last Features item, and the last paragraph of the Description ................... 1 • Added the DBV package to the Ordering Information table ................................................................................................. 2 • Changed the Dissipation Rating Table to include the DBV package ................................................................................... 2 • Added 6-pin SOT-23 pinout to the Device Information section ............................................................................................ 4 • Changed two values in the last paragraph of the MAXIMUM OUTPUT CURRENT section - From: 65mA To: 110mA in typical condition, and From: 85mA To: 150mA in typical condition ................................................................................ 14 18 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61165 PACKAGE OPTION ADDENDUM www.ti.com 8-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS61165DBVR PREVIEW SOT-23 DBV 6 3000 TBD Call TI Call TI TPS61165DBVT PREVIEW SOT-23 DBV 6 250 TBD Call TI Call TI TPS61165DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61165DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61165DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS61165DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS61165DRVR SON DRV 6 3000 330.0 12.4 2.2 2.2 1.1 8.0 12.0 Q2 TPS61165DRVT SON DRV 6 250 180.0 12.4 2.2 2.2 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS61165DRVR SON DRV 6 3000 346.0 346.0 29.0 TPS61165DRVT SON DRV 6 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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